Commit | Line | Data |
---|---|---|
b9164398 | 1 | /* |
e0614bf7 ZZ |
2 | * drivers/amlogic/amports/vvp9.c |
3 | * | |
4 | * Copyright (C) 2015 Amlogic, Inc. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | */ | |
5b851ff9 | 17 | #define DEBUG |
b9164398 NQ |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/types.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/semaphore.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/timer.h> | |
26 | #include <linux/kfifo.h> | |
27 | #include <linux/kthread.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/amlogic/media/vfm/vframe.h> | |
31 | #include <linux/amlogic/media/utils/amstream.h> | |
32 | #include <linux/amlogic/media/utils/vformat.h> | |
33 | #include <linux/amlogic/media/frame_sync/ptsserv.h> | |
34 | #include <linux/amlogic/media/canvas/canvas.h> | |
35 | #include <linux/amlogic/media/vfm/vframe_provider.h> | |
36 | #include <linux/amlogic/media/vfm/vframe_receiver.h> | |
37 | #include <linux/dma-mapping.h> | |
38 | #include <linux/dma-contiguous.h> | |
39 | #include <linux/slab.h> | |
8f657ce9 | 40 | #include <linux/amlogic/tee.h> |
b9164398 NQ |
41 | #include "../../../stream_input/amports/amports_priv.h" |
42 | #include <linux/amlogic/media/codec_mm/codec_mm.h> | |
43 | #include "../utils/decoder_mmu_box.h" | |
44 | #include "../utils/decoder_bmmu_box.h" | |
45 | ||
46 | #define MEM_NAME "codec_vp9" | |
47 | /* #include <mach/am_regs.h> */ | |
48 | #include <linux/amlogic/media/utils/vdec_reg.h> | |
49 | #include "../utils/vdec.h" | |
50 | #include "../utils/amvdec.h" | |
187af067 | 51 | #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC |
52 | #include "../utils/vdec_profile.h" | |
53 | #endif | |
b9164398 NQ |
54 | |
55 | #include <linux/amlogic/media/video_sink/video.h> | |
fe96802b NQ |
56 | #include <linux/amlogic/media/codec_mm/configs.h> |
57 | #include "../utils/config_parser.h" | |
6fff1c64 | 58 | #include "../utils/firmware.h" |
63e810c0 | 59 | #include "../../../common/chips/decoder_cpu_ver_info.h" |
2cd6815e | 60 | #include "../../../amvdec_ports/vdec_drv_base.h" |
b9164398 | 61 | |
a093654a TG |
62 | |
63 | ||
b9164398 | 64 | #define MIX_STREAM_SUPPORT |
b9164398 NQ |
65 | |
66 | #include "vvp9.h" | |
a6c89e96 | 67 | |
b7706e1e | 68 | |
a6c89e96 NQ |
69 | /*#define SUPPORT_FB_DECODING*/ |
70 | /*#define FB_DECODING_TEST_SCHEDULE*/ | |
b7706e1e | 71 | |
a6c89e96 NQ |
72 | |
73 | #define HW_MASK_FRONT 0x1 | |
74 | #define HW_MASK_BACK 0x2 | |
75 | ||
b9164398 NQ |
76 | #define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442 |
77 | #define VP9D_MPP_REFINFO_DATA 0x3443 | |
78 | #define VP9D_MPP_REF_SCALE_ENBL 0x3441 | |
79 | #define HEVC_MPRED_CTRL4 0x324c | |
80 | #define HEVC_CM_HEADER_START_ADDR 0x3628 | |
81 | #define HEVC_DBLK_CFGB 0x350b | |
82 | #define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464 | |
83 | #define HEVC_SAO_MMU_VH1_ADDR 0x363b | |
84 | #define HEVC_SAO_MMU_VH0_ADDR 0x363a | |
b9164398 | 85 | |
ac678990 NQ |
86 | #define HEVC_MV_INFO 0x310d |
87 | #define HEVC_QP_INFO 0x3137 | |
88 | #define HEVC_SKIP_INFO 0x3136 | |
89 | ||
b9164398 NQ |
90 | #define VP9_10B_DEC_IDLE 0 |
91 | #define VP9_10B_DEC_FRAME_HEADER 1 | |
92 | #define VP9_10B_DEC_SLICE_SEGMENT 2 | |
93 | #define VP9_10B_DECODE_SLICE 5 | |
94 | #define VP9_10B_DISCARD_NAL 6 | |
95 | #define VP9_DUMP_LMEM 7 | |
96 | #define HEVC_DECPIC_DATA_DONE 0xa | |
97 | #define HEVC_DECPIC_DATA_ERROR 0xb | |
98 | #define HEVC_NAL_DECODE_DONE 0xe | |
99 | #define HEVC_DECODE_BUFEMPTY 0x20 | |
100 | #define HEVC_DECODE_TIMEOUT 0x21 | |
101 | #define HEVC_SEARCH_BUFEMPTY 0x22 | |
fe96802b | 102 | #define HEVC_DECODE_OVER_SIZE 0x23 |
a6c89e96 | 103 | #define HEVC_S2_DECODING_DONE 0x50 |
b9164398 NQ |
104 | #define VP9_HEAD_PARSER_DONE 0xf0 |
105 | #define VP9_HEAD_SEARCH_DONE 0xf1 | |
106 | #define VP9_EOS 0xf2 | |
107 | #define HEVC_ACTION_DONE 0xff | |
108 | ||
b9164398 NQ |
109 | #define VF_POOL_SIZE 32 |
110 | ||
111 | #undef pr_info | |
112 | #define pr_info printk | |
113 | ||
a6c89e96 NQ |
114 | #define DECODE_MODE_SINGLE ((0x80 << 24) | 0) |
115 | #define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1) | |
116 | #define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2) | |
187af067 | 117 | #define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3) |
0eb79ad7 | 118 | #define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4) |
c23e8aee HZ |
119 | |
120 | #define VP9_TRIGGER_FRAME_DONE 0x100 | |
121 | #define VP9_TRIGGER_FRAME_ENABLE 0x200 | |
122 | ||
fe96802b | 123 | #define MV_MEM_UNIT 0x240 |
b9164398 | 124 | /*--------------------------------------------------- |
e0614bf7 ZZ |
125 | * Include "parser_cmd.h" |
126 | *--------------------------------------------------- | |
127 | */ | |
b9164398 NQ |
128 | #define PARSER_CMD_SKIP_CFG_0 0x0000090b |
129 | ||
130 | #define PARSER_CMD_SKIP_CFG_1 0x1b14140f | |
131 | ||
132 | #define PARSER_CMD_SKIP_CFG_2 0x001b1910 | |
133 | ||
134 | #define PARSER_CMD_NUMBER 37 | |
135 | ||
b9164398 NQ |
136 | /*#define HEVC_PIC_STRUCT_SUPPORT*/ |
137 | /* to remove, fix build error */ | |
138 | ||
139 | /*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/ | |
140 | ||
141 | #define MULTI_INSTANCE_SUPPORT | |
142 | #define SUPPORT_10BIT | |
143 | /* #define ERROR_HANDLE_DEBUG */ | |
b9164398 NQ |
144 | |
145 | #ifndef STAT_KTHREAD | |
146 | #define STAT_KTHREAD 0x40 | |
147 | #endif | |
148 | ||
149 | #ifdef MULTI_INSTANCE_SUPPORT | |
a674e3cd | 150 | #define MAX_DECODE_INSTANCE_NUM 9 |
b9164398 | 151 | #define MULTI_DRIVER_NAME "ammvdec_vp9" |
fe96802b NQ |
152 | |
153 | static unsigned int max_decode_instance_num | |
154 | = MAX_DECODE_INSTANCE_NUM; | |
155 | static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM]; | |
156 | static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM]; | |
157 | static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM]; | |
158 | static unsigned int run_count[MAX_DECODE_INSTANCE_NUM]; | |
159 | static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM]; | |
160 | static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM]; | |
161 | ||
162 | static u32 decode_timeout_val = 200; | |
163 | static int start_decode_buf_level = 0x8000; | |
b7706e1e | 164 | static u32 work_buf_size; |
b9164398 | 165 | |
fe96802b NQ |
166 | static u32 mv_buf_margin; |
167 | ||
168 | /* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */ | |
a6c89e96 NQ |
169 | /* double_write_mode: 0, no double write |
170 | 1, 1:1 ratio | |
171 | 2, (1/4):(1/4) ratio | |
172 | 4, (1/2):(1/2) ratio | |
173 | 0x10, double write only | |
fe96802b NQ |
174 | */ |
175 | static u32 double_write_mode; | |
176 | ||
b9164398 NQ |
177 | #define DRIVER_NAME "amvdec_vp9" |
178 | #define MODULE_NAME "amvdec_vp9" | |
fe96802b NQ |
179 | #define DRIVER_HEADER_NAME "amvdec_vp9_header" |
180 | ||
b9164398 NQ |
181 | |
182 | #define PUT_INTERVAL (HZ/100) | |
183 | #define ERROR_SYSTEM_RESET_COUNT 200 | |
184 | ||
185 | #define PTS_NORMAL 0 | |
186 | #define PTS_NONE_REF_USE_DURATION 1 | |
187 | ||
188 | #define PTS_MODE_SWITCHING_THRESHOLD 3 | |
189 | #define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3 | |
190 | ||
191 | #define DUR2PTS(x) ((x)*90/96) | |
192 | ||
193 | struct VP9Decoder_s; | |
194 | static int vvp9_vf_states(struct vframe_states *states, void *); | |
195 | static struct vframe_s *vvp9_vf_peek(void *); | |
196 | static struct vframe_s *vvp9_vf_get(void *); | |
197 | static void vvp9_vf_put(struct vframe_s *, void *); | |
198 | static int vvp9_event_cb(int type, void *data, void *private_data); | |
199 | ||
200 | static int vvp9_stop(struct VP9Decoder_s *pbi); | |
c23e8aee HZ |
201 | #ifdef MULTI_INSTANCE_SUPPORT |
202 | static s32 vvp9_init(struct vdec_s *vdec); | |
203 | #else | |
b9164398 | 204 | static s32 vvp9_init(struct VP9Decoder_s *pbi); |
c23e8aee | 205 | #endif |
a6c89e96 | 206 | static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask); |
b9164398 NQ |
207 | static int vvp9_local_init(struct VP9Decoder_s *pbi); |
208 | static void vvp9_put_timer_func(unsigned long arg); | |
fe96802b NQ |
209 | static void dump_data(struct VP9Decoder_s *pbi, int size); |
210 | static unsigned char get_data_check_sum | |
211 | (struct VP9Decoder_s *pbi, int size); | |
212 | static void dump_pic_list(struct VP9Decoder_s *pbi); | |
b9164398 NQ |
213 | static int vp9_alloc_mmu( |
214 | struct VP9Decoder_s *pbi, | |
215 | int cur_buf_idx, | |
216 | int pic_width, | |
217 | int pic_height, | |
218 | unsigned short bit_depth, | |
219 | unsigned int *mmu_index_adr); | |
b7706e1e | 220 | |
b9164398 NQ |
221 | |
222 | static const char vvp9_dec_id[] = "vvp9-dev"; | |
223 | ||
224 | #define PROVIDER_NAME "decoder.vp9" | |
225 | #define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9" | |
226 | ||
227 | static const struct vframe_operations_s vvp9_vf_provider = { | |
228 | .peek = vvp9_vf_peek, | |
229 | .get = vvp9_vf_get, | |
230 | .put = vvp9_vf_put, | |
231 | .event_cb = vvp9_event_cb, | |
232 | .vf_states = vvp9_vf_states, | |
233 | }; | |
234 | ||
235 | static struct vframe_provider_s vvp9_vf_prov; | |
236 | ||
237 | static u32 bit_depth_luma; | |
238 | static u32 bit_depth_chroma; | |
239 | static u32 frame_width; | |
240 | static u32 frame_height; | |
241 | static u32 video_signal_type; | |
976f3376 | 242 | |
b9164398 NQ |
243 | static u32 on_no_keyframe_skiped; |
244 | ||
b9164398 NQ |
245 | #define PROB_SIZE (496 * 2 * 4) |
246 | #define PROB_BUF_SIZE (0x5000) | |
247 | #define COUNT_BUF_SIZE (0x300 * 4 * 4) | |
248 | /*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/ | |
249 | #define MAX_FRAME_4K_NUM 0x1200 | |
e0e39311 | 250 | #define MAX_FRAME_8K_NUM 0x4800 |
b9164398 | 251 | |
a6c89e96 NQ |
252 | #define HEVC_ASSIST_MMU_MAP_ADDR 0x3009 |
253 | ||
254 | #ifdef SUPPORT_FB_DECODING | |
255 | /* register define */ | |
256 | #define HEVC_ASSIST_HED_FB_W_CTL 0x3006 | |
257 | #define HEVC_ASSIST_HED_FB_R_CTL 0x3007 | |
258 | #define HEVC_ASSIST_HED_FB_ADDR 0x3008 | |
259 | #define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a | |
260 | #define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b | |
261 | ||
262 | ||
263 | #define MAX_STAGE_PAGE_NUM 0x1200 | |
264 | #define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4) | |
265 | #endif | |
b9164398 NQ |
266 | static inline int div_r32(int64_t m, int n) |
267 | { | |
268 | /* | |
e0614bf7 ZZ |
269 | *return (int)(m/n) |
270 | */ | |
b9164398 | 271 | #ifndef CONFIG_ARM64 |
ddcb7dca LC |
272 | int64_t qu = 0; |
273 | qu = div_s64(m, n); | |
274 | return (int)qu; | |
b9164398 NQ |
275 | #else |
276 | return (int)(m/n); | |
277 | #endif | |
278 | } | |
279 | ||
280 | /*USE_BUF_BLOCK*/ | |
281 | struct BUF_s { | |
282 | int index; | |
283 | unsigned int alloc_flag; | |
284 | /*buffer */ | |
285 | unsigned int cma_page_count; | |
286 | unsigned long alloc_addr; | |
287 | unsigned long start_adr; | |
288 | unsigned int size; | |
289 | ||
290 | unsigned int free_start_adr; | |
2cd6815e | 291 | ulong v4l_ref_buf_addr; |
b9164398 NQ |
292 | } /*BUF_t */; |
293 | ||
fe96802b NQ |
294 | struct MVBUF_s { |
295 | unsigned long start_adr; | |
296 | unsigned int size; | |
297 | int used_flag; | |
298 | } /*MVBUF_t */; | |
b9164398 NQ |
299 | |
300 | /* #undef BUFMGR_ONLY to enable hardware configuration */ | |
301 | ||
302 | /*#define TEST_WR_PTR_INC*/ | |
df841122 | 303 | /*#define WR_PTR_INC_NUM 128*/ |
304 | #define WR_PTR_INC_NUM 1 | |
b9164398 NQ |
305 | |
306 | #define SIMULATION | |
307 | #define DOS_PROJECT | |
308 | #undef MEMORY_MAP_IN_REAL_CHIP | |
309 | ||
310 | /*#undef DOS_PROJECT*/ | |
311 | /*#define MEMORY_MAP_IN_REAL_CHIP*/ | |
312 | ||
313 | /*#define BUFFER_MGR_ONLY*/ | |
314 | /*#define CONFIG_HEVC_CLK_FORCED_ON*/ | |
315 | /*#define ENABLE_SWAP_TEST*/ | |
316 | #define MCRCC_ENABLE | |
317 | ||
b9164398 NQ |
318 | #define VP9_LPF_LVL_UPDATE |
319 | /*#define DBG_LF_PRINT*/ | |
320 | ||
321 | #ifdef VP9_10B_NV21 | |
322 | #else | |
323 | #define LOSLESS_COMPRESS_MODE | |
324 | #endif | |
325 | ||
326 | #define DOUBLE_WRITE_YSTART_TEMP 0x02000000 | |
327 | #define DOUBLE_WRITE_CSTART_TEMP 0x02900000 | |
328 | ||
329 | ||
330 | ||
331 | typedef unsigned int u32; | |
332 | typedef unsigned short u16; | |
333 | ||
334 | #define VP9_DEBUG_BUFMGR 0x01 | |
335 | #define VP9_DEBUG_BUFMGR_MORE 0x02 | |
fe96802b NQ |
336 | #define VP9_DEBUG_BUFMGR_DETAIL 0x04 |
337 | #define VP9_DEBUG_OUT_PTS 0x10 | |
b9164398 | 338 | #define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100 |
fe96802b | 339 | #define VP9_DEBUG_MERGE 0x200 |
b9164398 | 340 | #define VP9_DEBUG_DBG_LF_PRINT 0x400 |
fe96802b | 341 | #define VP9_DEBUG_REG 0x800 |
a6c89e96 NQ |
342 | #define VP9_DEBUG_2_STAGE 0x1000 |
343 | #define VP9_DEBUG_2_STAGE_MORE 0x2000 | |
ac678990 | 344 | #define VP9_DEBUG_QOS_INFO 0x4000 |
b9164398 NQ |
345 | #define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000 |
346 | #define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000 | |
347 | #define VP9_DEBUG_DUMP_PIC_LIST 0x40000 | |
348 | #define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000 | |
a6c89e96 | 349 | #define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000 |
b9164398 | 350 | #define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000 |
fe96802b NQ |
351 | #define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000 |
352 | #define VP9_DEBUG_DUMP_DATA 0x800000 | |
c23e8aee HZ |
353 | #define VP9_DEBUG_CACHE 0x1000000 |
354 | #define VP9_DEBUG_CACHE_HIT_RATE 0x2000000 | |
355 | #define IGNORE_PARAM_FROM_CONFIG 0x8000000 | |
b9164398 | 356 | #ifdef MULTI_INSTANCE_SUPPORT |
9495ddb6 NQ |
357 | #define PRINT_FLAG_ERROR 0x0 |
358 | #define PRINT_FLAG_V4L_DETAIL 0x10000000 | |
359 | #define PRINT_FLAG_VDEC_STATUS 0x20000000 | |
360 | #define PRINT_FLAG_VDEC_DETAIL 0x40000000 | |
361 | #define PRINT_FLAG_VDEC_DATA 0x80000000 | |
b9164398 NQ |
362 | #endif |
363 | ||
364 | static u32 debug; | |
d481db31 | 365 | static bool is_reset; |
fe96802b NQ |
366 | /*for debug*/ |
367 | /* | |
368 | udebug_flag: | |
369 | bit 0, enable ucode print | |
370 | bit 1, enable ucode detail print | |
371 | bit [31:16] not 0, pos to dump lmem | |
372 | bit 2, pop bits to lmem | |
373 | bit [11:8], pre-pop bits for alignment (when bit 2 is 1) | |
374 | */ | |
375 | static u32 udebug_flag; | |
376 | /* | |
377 | when udebug_flag[1:0] is not 0 | |
378 | udebug_pause_pos not 0, | |
379 | pause position | |
380 | */ | |
381 | static u32 udebug_pause_pos; | |
382 | /* | |
383 | when udebug_flag[1:0] is not 0 | |
384 | and udebug_pause_pos is not 0, | |
385 | pause only when DEBUG_REG2 is equal to this val | |
386 | */ | |
387 | static u32 udebug_pause_val; | |
388 | ||
389 | static u32 udebug_pause_decode_idx; | |
390 | ||
b9164398 NQ |
391 | #define DEBUG_REG |
392 | #ifdef DEBUG_REG | |
e0614bf7 | 393 | void WRITE_VREG_DBG2(unsigned int adr, unsigned int val) |
b9164398 NQ |
394 | { |
395 | if (debug & VP9_DEBUG_REG) | |
396 | pr_info("%s(%x, %x)\n", __func__, adr, val); | |
397 | if (adr != 0) | |
398 | WRITE_VREG(adr, val); | |
399 | } | |
400 | ||
401 | #undef WRITE_VREG | |
402 | #define WRITE_VREG WRITE_VREG_DBG2 | |
403 | #endif | |
404 | ||
c20e6c85 | 405 | #define FRAME_CNT_WINDOW_SIZE 59 |
406 | #define RATE_CORRECTION_THRESHOLD 5 | |
b9164398 | 407 | /************************************************** |
a6c89e96 NQ |
408 | |
409 | VP9 buffer management start | |
410 | ||
411 | ***************************************************/ | |
b7706e1e | 412 | |
b9164398 | 413 | #define MMU_COMPRESS_HEADER_SIZE 0x48000 |
df841122 | 414 | #define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4) |
e0e39311 | 415 | #define MAX_SIZE_8K (8192 * 4608) |
416 | #define MAX_SIZE_4K (4096 * 2304) | |
417 | #define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K) | |
b9164398 NQ |
418 | |
419 | #define INVALID_IDX -1 /* Invalid buffer index.*/ | |
420 | ||
421 | #define RPM_BEGIN 0x200 | |
422 | #define RPM_END 0x280 | |
423 | ||
424 | union param_u { | |
425 | struct { | |
426 | unsigned short data[RPM_END - RPM_BEGIN]; | |
427 | } l; | |
428 | struct { | |
429 | /* from ucode lmem, do not change this struct */ | |
430 | unsigned short profile; | |
431 | unsigned short show_existing_frame; | |
432 | unsigned short frame_to_show_idx; | |
433 | unsigned short frame_type; /*1 bit*/ | |
434 | unsigned short show_frame; /*1 bit*/ | |
435 | unsigned short error_resilient_mode; /*1 bit*/ | |
436 | unsigned short intra_only; /*1 bit*/ | |
437 | unsigned short display_size_present; /*1 bit*/ | |
438 | unsigned short reset_frame_context; | |
439 | unsigned short refresh_frame_flags; | |
440 | unsigned short width; | |
441 | unsigned short height; | |
442 | unsigned short display_width; | |
443 | unsigned short display_height; | |
444 | /* | |
e0614bf7 ZZ |
445 | *bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit)) |
446 | *bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit)) | |
447 | *bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit)) | |
448 | */ | |
b9164398 NQ |
449 | unsigned short ref_info; |
450 | /* | |
e0614bf7 ZZ |
451 | *bit[2]: same_frame_size0 |
452 | *bit[1]: same_frame_size1 | |
453 | *bit[0]: same_frame_size2 | |
454 | */ | |
b9164398 NQ |
455 | unsigned short same_frame_size; |
456 | ||
457 | unsigned short mode_ref_delta_enabled; | |
458 | unsigned short ref_deltas[4]; | |
459 | unsigned short mode_deltas[2]; | |
460 | unsigned short filter_level; | |
461 | unsigned short sharpness_level; | |
462 | unsigned short bit_depth; | |
463 | unsigned short seg_quant_info[8]; | |
464 | unsigned short seg_enabled; | |
465 | unsigned short seg_abs_delta; | |
466 | /* bit 15: feature enabled; bit 8, sign; bit[5:0], data */ | |
467 | unsigned short seg_lf_info[8]; | |
468 | } p; | |
469 | }; | |
470 | ||
471 | ||
472 | struct vpx_codec_frame_buffer_s { | |
473 | uint8_t *data; /**< Pointer to the data buffer */ | |
474 | size_t size; /**< Size of data in bytes */ | |
475 | void *priv; /**< Frame's private data */ | |
476 | }; | |
477 | ||
478 | enum vpx_color_space_t { | |
479 | VPX_CS_UNKNOWN = 0, /**< Unknown */ | |
480 | VPX_CS_BT_601 = 1, /**< BT.601 */ | |
481 | VPX_CS_BT_709 = 2, /**< BT.709 */ | |
482 | VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */ | |
483 | VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */ | |
484 | VPX_CS_BT_2020 = 5, /**< BT.2020 */ | |
485 | VPX_CS_RESERVED = 6, /**< Reserved */ | |
486 | VPX_CS_SRGB = 7 /**< sRGB */ | |
487 | }; /**< alias for enum vpx_color_space */ | |
488 | ||
489 | enum vpx_bit_depth_t { | |
490 | VPX_BITS_8 = 8, /**< 8 bits */ | |
491 | VPX_BITS_10 = 10, /**< 10 bits */ | |
492 | VPX_BITS_12 = 12, /**< 12 bits */ | |
493 | }; | |
494 | ||
495 | #define MAX_SLICE_NUM 1024 | |
496 | struct PIC_BUFFER_CONFIG_s { | |
497 | int index; | |
498 | int BUF_index; | |
fe96802b | 499 | int mv_buf_index; |
b9164398 NQ |
500 | int comp_body_size; |
501 | int buf_size; | |
502 | int vf_ref; | |
503 | int y_canvas_index; | |
504 | int uv_canvas_index; | |
505 | #ifdef MULTI_INSTANCE_SUPPORT | |
506 | struct canvas_config_s canvas_config[2]; | |
507 | #endif | |
508 | int decode_idx; | |
509 | int slice_type; | |
b9164398 | 510 | int stream_offset; |
fe96802b NQ |
511 | u32 pts; |
512 | u64 pts64; | |
b9164398 NQ |
513 | uint8_t error_mark; |
514 | /**/ | |
515 | int slice_idx; | |
516 | /*buffer*/ | |
b9164398 | 517 | unsigned long header_adr; |
b9164398 | 518 | unsigned long mpred_mv_wr_start_addr; |
b7706e1e | 519 | /*unsigned long mc_y_adr; |
520 | *unsigned long mc_u_v_adr; | |
521 | */ | |
b9164398 NQ |
522 | unsigned int dw_y_adr; |
523 | unsigned int dw_u_v_adr; | |
524 | int mc_canvas_y; | |
525 | int mc_canvas_u_v; | |
526 | ||
527 | int lcu_total; | |
528 | /**/ | |
529 | int y_width; | |
530 | int y_height; | |
531 | int y_crop_width; | |
532 | int y_crop_height; | |
533 | int y_stride; | |
534 | ||
535 | int uv_width; | |
536 | int uv_height; | |
537 | int uv_crop_width; | |
538 | int uv_crop_height; | |
539 | int uv_stride; | |
540 | ||
541 | int alpha_width; | |
542 | int alpha_height; | |
543 | int alpha_stride; | |
544 | ||
545 | uint8_t *y_buffer; | |
546 | uint8_t *u_buffer; | |
547 | uint8_t *v_buffer; | |
548 | uint8_t *alpha_buffer; | |
549 | ||
550 | uint8_t *buffer_alloc; | |
551 | int buffer_alloc_sz; | |
552 | int border; | |
553 | int frame_size; | |
554 | int subsampling_x; | |
555 | int subsampling_y; | |
556 | unsigned int bit_depth; | |
557 | enum vpx_color_space_t color_space; | |
558 | ||
559 | int corrupted; | |
560 | int flags; | |
561 | unsigned long cma_alloc_addr; | |
c23e8aee HZ |
562 | |
563 | int double_write_mode; | |
ac678990 NQ |
564 | |
565 | /* picture qos infomation*/ | |
566 | int max_qp; | |
567 | int avg_qp; | |
568 | int min_qp; | |
569 | int max_skip; | |
570 | int avg_skip; | |
571 | int min_skip; | |
572 | int max_mv; | |
573 | int min_mv; | |
574 | int avg_mv; | |
b9164398 NQ |
575 | } PIC_BUFFER_CONFIG; |
576 | ||
577 | enum BITSTREAM_PROFILE { | |
578 | PROFILE_0, | |
579 | PROFILE_1, | |
580 | PROFILE_2, | |
581 | PROFILE_3, | |
582 | MAX_PROFILES | |
583 | }; | |
584 | ||
585 | enum FRAME_TYPE { | |
586 | KEY_FRAME = 0, | |
587 | INTER_FRAME = 1, | |
588 | FRAME_TYPES, | |
589 | }; | |
590 | ||
591 | enum REFERENCE_MODE { | |
592 | SINGLE_REFERENCE = 0, | |
593 | COMPOUND_REFERENCE = 1, | |
594 | REFERENCE_MODE_SELECT = 2, | |
595 | REFERENCE_MODES = 3, | |
596 | }; | |
597 | ||
598 | #define NONE -1 | |
599 | #define INTRA_FRAME 0 | |
600 | #define LAST_FRAME 1 | |
601 | #define GOLDEN_FRAME 2 | |
602 | #define ALTREF_FRAME 3 | |
603 | #define MAX_REF_FRAMES 4 | |
604 | ||
605 | #define REFS_PER_FRAME 3 | |
606 | ||
607 | #define REF_FRAMES_LOG2 3 | |
608 | #define REF_FRAMES (1 << REF_FRAMES_LOG2) | |
dfe41deb | 609 | #define REF_FRAMES_4K (6) |
b9164398 NQ |
610 | |
611 | /*4 scratch frames for the new frames to support a maximum of 4 cores decoding | |
e0614bf7 ZZ |
612 | *in parallel, 3 for scaled references on the encoder. |
613 | *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number | |
614 | * // of framebuffers. | |
615 | *TODO(jkoleszar): These 3 extra references could probably come from the | |
616 | *normal reference pool. | |
617 | */ | |
fe96802b NQ |
618 | #define FRAME_BUFFERS (REF_FRAMES + 16) |
619 | #define HEADER_FRAME_BUFFERS (FRAME_BUFFERS) | |
620 | #define MAX_BUF_NUM (FRAME_BUFFERS) | |
a6c89e96 NQ |
621 | #define MV_BUFFER_NUM FRAME_BUFFERS |
622 | #ifdef SUPPORT_FB_DECODING | |
623 | #define STAGE_MAX_BUFFERS 16 | |
624 | #else | |
625 | #define STAGE_MAX_BUFFERS 0 | |
626 | #endif | |
b9164398 NQ |
627 | |
628 | #define FRAME_CONTEXTS_LOG2 2 | |
629 | #define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2) | |
fe96802b NQ |
630 | /*buffer + header buffer + workspace*/ |
631 | #ifdef MV_USE_FIXED_BUF | |
632 | #define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1) | |
633 | #define VF_BUFFER_IDX(n) (n) | |
634 | #define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n) | |
635 | #define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS) | |
636 | #else | |
a6c89e96 NQ |
637 | #define MAX_BMMU_BUFFER_NUM \ |
638 | (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1) | |
fe96802b NQ |
639 | #define VF_BUFFER_IDX(n) (n) |
640 | #define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n) | |
a6c89e96 NQ |
641 | #define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n) |
642 | #define WORK_SPACE_BUF_ID \ | |
643 | (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM) | |
fe96802b | 644 | #endif |
b9164398 NQ |
645 | |
646 | struct RefCntBuffer_s { | |
647 | int ref_count; | |
648 | /*MV_REF *mvs;*/ | |
649 | int mi_rows; | |
650 | int mi_cols; | |
651 | struct vpx_codec_frame_buffer_s raw_frame_buffer; | |
652 | struct PIC_BUFFER_CONFIG_s buf; | |
653 | ||
654 | /*The Following variables will only be used in frame parallel decode. | |
e0614bf7 ZZ |
655 | * |
656 | *frame_worker_owner indicates which FrameWorker owns this buffer. NULL means | |
657 | *that no FrameWorker owns, or is decoding, this buffer. | |
658 | *VP9Worker *frame_worker_owner; | |
659 | * | |
660 | *row and col indicate which position frame has been decoded to in real | |
661 | *pixel unit. They are reset to -1 when decoding begins and set to INT_MAX | |
662 | *when the frame is fully decoded. | |
663 | */ | |
b9164398 NQ |
664 | int row; |
665 | int col; | |
666 | } RefCntBuffer; | |
667 | ||
668 | struct RefBuffer_s { | |
669 | /*TODO(dkovalev): idx is not really required and should be removed, now it | |
e0614bf7 ZZ |
670 | *is used in vp9_onyxd_if.c |
671 | */ | |
b9164398 NQ |
672 | int idx; |
673 | struct PIC_BUFFER_CONFIG_s *buf; | |
674 | /*struct scale_factors sf;*/ | |
675 | } RefBuffer; | |
676 | ||
677 | struct InternalFrameBuffer_s { | |
678 | uint8_t *data; | |
679 | size_t size; | |
680 | int in_use; | |
681 | } InternalFrameBuffer; | |
682 | ||
683 | struct InternalFrameBufferList_s { | |
684 | int num_internal_frame_buffers; | |
685 | struct InternalFrameBuffer_s *int_fb; | |
686 | } InternalFrameBufferList; | |
687 | ||
688 | struct BufferPool_s { | |
689 | /*Protect BufferPool from being accessed by several FrameWorkers at | |
e0614bf7 ZZ |
690 | *the same time during frame parallel decode. |
691 | *TODO(hkuang): Try to use atomic variable instead of locking the whole pool. | |
692 | * | |
693 | *Private data associated with the frame buffer callbacks. | |
694 | *void *cb_priv; | |
695 | * | |
696 | *vpx_get_frame_buffer_cb_fn_t get_fb_cb; | |
697 | *vpx_release_frame_buffer_cb_fn_t release_fb_cb; | |
698 | */ | |
b9164398 NQ |
699 | |
700 | struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS]; | |
701 | ||
702 | /*Frame buffers allocated internally by the codec.*/ | |
703 | struct InternalFrameBufferList_s int_frame_buffers; | |
704 | unsigned long flags; | |
705 | spinlock_t lock; | |
706 | ||
707 | } BufferPool; | |
708 | ||
fe96802b NQ |
709 | #define lock_buffer_pool(pool, flags) \ |
710 | spin_lock_irqsave(&pool->lock, flags) | |
711 | ||
712 | #define unlock_buffer_pool(pool, flags) \ | |
713 | spin_unlock_irqrestore(&pool->lock, flags) | |
b9164398 NQ |
714 | |
715 | struct VP9_Common_s { | |
716 | enum vpx_color_space_t color_space; | |
717 | int width; | |
718 | int height; | |
719 | int display_width; | |
720 | int display_height; | |
721 | int last_width; | |
722 | int last_height; | |
723 | ||
724 | int subsampling_x; | |
725 | int subsampling_y; | |
726 | ||
727 | int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/ | |
728 | ||
729 | struct PIC_BUFFER_CONFIG_s *frame_to_show; | |
730 | struct RefCntBuffer_s *prev_frame; | |
731 | ||
732 | /*TODO(hkuang): Combine this with cur_buf in macroblockd.*/ | |
733 | struct RefCntBuffer_s *cur_frame; | |
734 | ||
735 | int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */ | |
736 | ||
737 | /*Prepare ref_frame_map for the next frame. | |
e0614bf7 ZZ |
738 | *Only used in frame parallel decode. |
739 | */ | |
b9164398 NQ |
740 | int next_ref_frame_map[REF_FRAMES]; |
741 | ||
742 | /* TODO(jkoleszar): could expand active_ref_idx to 4, | |
e0614bf7 ZZ |
743 | *with 0 as intra, and roll new_fb_idx into it. |
744 | */ | |
b9164398 NQ |
745 | |
746 | /*Each frame can reference REFS_PER_FRAME buffers*/ | |
747 | struct RefBuffer_s frame_refs[REFS_PER_FRAME]; | |
748 | ||
749 | int prev_fb_idx; | |
750 | int new_fb_idx; | |
fe96802b | 751 | int cur_fb_idx_mmu; |
b9164398 NQ |
752 | /*last frame's frame type for motion search*/ |
753 | enum FRAME_TYPE last_frame_type; | |
754 | enum FRAME_TYPE frame_type; | |
755 | ||
756 | int show_frame; | |
757 | int last_show_frame; | |
758 | int show_existing_frame; | |
759 | ||
760 | /*Flag signaling that the frame is encoded using only INTRA modes.*/ | |
761 | uint8_t intra_only; | |
762 | uint8_t last_intra_only; | |
763 | ||
764 | int allow_high_precision_mv; | |
765 | ||
766 | /*Flag signaling that the frame context should be reset to default | |
e0614bf7 ZZ |
767 | *values. 0 or 1 implies don't reset, 2 reset just the context |
768 | *specified in the frame header, 3 reset all contexts. | |
769 | */ | |
b9164398 NQ |
770 | int reset_frame_context; |
771 | ||
772 | /*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in | |
e0614bf7 ZZ |
773 | * MODE_INFO (8-pixel) units. |
774 | */ | |
b9164398 NQ |
775 | int MBs; |
776 | int mb_rows, mi_rows; | |
777 | int mb_cols, mi_cols; | |
778 | int mi_stride; | |
779 | ||
780 | /*Whether to use previous frame's motion vectors for prediction.*/ | |
781 | int use_prev_frame_mvs; | |
782 | ||
783 | int refresh_frame_context; /* Two state 0 = NO, 1 = YES */ | |
784 | ||
785 | int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */ | |
786 | ||
787 | /*struct loopfilter lf;*/ | |
788 | /*struct segmentation seg;*/ | |
789 | ||
790 | /*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/ | |
791 | /* in pbi.*/ | |
792 | int frame_parallel_decode; /* frame-based threading.*/ | |
793 | ||
794 | /*Context probabilities for reference frame prediction*/ | |
795 | /*MV_REFERENCE_FRAME comp_fixed_ref;*/ | |
796 | /*MV_REFERENCE_FRAME comp_var_ref[2];*/ | |
797 | enum REFERENCE_MODE reference_mode; | |
798 | ||
799 | /*FRAME_CONTEXT *fc; */ /* this frame entropy */ | |
800 | /*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/ | |
801 | /*unsigned int frame_context_idx; *//* Context to use/update */ | |
802 | /*FRAME_COUNTS counts;*/ | |
803 | ||
804 | unsigned int current_video_frame; | |
805 | enum BITSTREAM_PROFILE profile; | |
806 | ||
807 | enum vpx_bit_depth_t bit_depth; | |
808 | ||
809 | int error_resilient_mode; | |
810 | int frame_parallel_decoding_mode; | |
811 | ||
812 | int byte_alignment; | |
813 | int skip_loop_filter; | |
814 | ||
815 | /*External BufferPool passed from outside.*/ | |
816 | struct BufferPool_s *buffer_pool; | |
817 | ||
818 | int above_context_alloc_cols; | |
819 | ||
b7706e1e | 820 | }; |
b9164398 | 821 | |
fe96802b NQ |
822 | static void set_canvas(struct VP9Decoder_s *pbi, |
823 | struct PIC_BUFFER_CONFIG_s *pic_config); | |
b9164398 NQ |
824 | static int prepare_display_buf(struct VP9Decoder_s *pbi, |
825 | struct PIC_BUFFER_CONFIG_s *pic_config); | |
b9164398 | 826 | |
ac678990 NQ |
827 | static void fill_frame_info(struct VP9Decoder_s *pbi, |
828 | struct PIC_BUFFER_CONFIG_s *frame, | |
829 | unsigned int framesize, | |
830 | unsigned int pts); | |
831 | ||
b9164398 NQ |
832 | static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm) |
833 | { | |
834 | return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf; | |
835 | } | |
836 | ||
837 | static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx) | |
838 | { | |
839 | const int ref_index = *idx; | |
840 | ||
841 | if (ref_index >= 0 && bufs[ref_index].ref_count > 0) { | |
842 | bufs[ref_index].ref_count--; | |
843 | /*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n", | |
e0614bf7 ZZ |
844 | * ref_index, bufs[ref_index].ref_count); |
845 | */ | |
b9164398 NQ |
846 | } |
847 | ||
848 | *idx = new_idx; | |
849 | ||
850 | bufs[new_idx].ref_count++; | |
851 | /*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n", | |
e0614bf7 ZZ |
852 | * new_idx, bufs[new_idx].ref_count); |
853 | */ | |
b9164398 NQ |
854 | } |
855 | ||
856 | int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb) | |
857 | { | |
858 | struct InternalFrameBuffer_s *const int_fb = | |
859 | (struct InternalFrameBuffer_s *)fb->priv; | |
860 | if (int_fb) | |
861 | int_fb->in_use = 0; | |
862 | return 0; | |
863 | } | |
864 | ||
865 | static int compute_losless_comp_body_size(int width, int height, | |
866 | uint8_t is_bit_depth_10); | |
867 | ||
868 | static void setup_display_size(struct VP9_Common_s *cm, union param_u *params, | |
869 | int print_header_info) | |
870 | { | |
871 | cm->display_width = cm->width; | |
872 | cm->display_height = cm->height; | |
873 | if (params->p.display_size_present) { | |
874 | if (print_header_info) | |
875 | pr_info(" * 1-bit display_size_present read : 1\n"); | |
876 | cm->display_width = params->p.display_width; | |
877 | cm->display_height = params->p.display_height; | |
878 | /*vp9_read_frame_size(rb, &cm->display_width, | |
e0614bf7 ZZ |
879 | * &cm->display_height); |
880 | */ | |
b9164398 NQ |
881 | } else { |
882 | if (print_header_info) | |
883 | pr_info(" * 1-bit display_size_present read : 0\n"); | |
884 | } | |
885 | } | |
886 | ||
546484c5 | 887 | |
888 | uint8_t print_header_info = 0; | |
889 | ||
890 | struct buff_s { | |
891 | u32 buf_start; | |
892 | u32 buf_size; | |
893 | u32 buf_end; | |
894 | } buff_t; | |
895 | ||
896 | struct BuffInfo_s { | |
897 | u32 max_width; | |
898 | u32 max_height; | |
899 | u32 start_adr; | |
900 | u32 end_adr; | |
901 | struct buff_s ipp; | |
902 | struct buff_s sao_abv; | |
903 | struct buff_s sao_vb; | |
904 | struct buff_s short_term_rps; | |
905 | struct buff_s vps; | |
906 | struct buff_s sps; | |
907 | struct buff_s pps; | |
908 | struct buff_s sao_up; | |
909 | struct buff_s swap_buf; | |
910 | struct buff_s swap_buf2; | |
911 | struct buff_s scalelut; | |
912 | struct buff_s dblk_para; | |
913 | struct buff_s dblk_data; | |
914 | struct buff_s seg_map; | |
546484c5 | 915 | struct buff_s mmu_vbh; |
916 | struct buff_s cm_header; | |
546484c5 | 917 | struct buff_s mpred_above; |
918 | #ifdef MV_USE_FIXED_BUF | |
919 | struct buff_s mpred_mv; | |
920 | #endif | |
921 | struct buff_s rpm; | |
922 | struct buff_s lmem; | |
923 | } BuffInfo_t; | |
924 | ||
925 | #ifdef MULTI_INSTANCE_SUPPORT | |
926 | #define DEC_RESULT_NONE 0 | |
927 | #define DEC_RESULT_DONE 1 | |
928 | #define DEC_RESULT_AGAIN 2 | |
929 | #define DEC_RESULT_CONFIG_PARAM 3 | |
930 | #define DEC_RESULT_ERROR 4 | |
931 | #define DEC_INIT_PICLIST 5 | |
932 | #define DEC_UNINIT_PICLIST 6 | |
933 | #define DEC_RESULT_GET_DATA 7 | |
934 | #define DEC_RESULT_GET_DATA_RETRY 8 | |
935 | #define DEC_RESULT_EOS 9 | |
936 | #define DEC_RESULT_FORCE_EXIT 10 | |
937 | ||
a6c89e96 NQ |
938 | #define DEC_S1_RESULT_NONE 0 |
939 | #define DEC_S1_RESULT_DONE 1 | |
940 | #define DEC_S1_RESULT_FORCE_EXIT 2 | |
941 | #define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0 | |
942 | ||
943 | #ifdef FB_DECODING_TEST_SCHEDULE | |
944 | #define TEST_SET_NONE 0 | |
945 | #define TEST_SET_PIC_DONE 1 | |
946 | #define TEST_SET_S2_DONE 2 | |
947 | #endif | |
948 | ||
546484c5 | 949 | static void vp9_work(struct work_struct *work); |
950 | #endif | |
951 | struct loop_filter_info_n; | |
952 | struct loopfilter; | |
953 | struct segmentation; | |
954 | ||
a6c89e96 NQ |
955 | #ifdef SUPPORT_FB_DECODING |
956 | static void mpred_process(struct VP9Decoder_s *pbi); | |
957 | static void vp9_s1_work(struct work_struct *work); | |
958 | ||
959 | struct stage_buf_s { | |
960 | int index; | |
961 | unsigned short rpm[RPM_END - RPM_BEGIN]; | |
962 | }; | |
963 | ||
964 | static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM]; | |
965 | ||
966 | static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM]; | |
967 | ||
968 | #ifdef FB_DECODING_TEST_SCHEDULE | |
969 | u32 stage_buf_num; /* = 16;*/ | |
970 | #else | |
971 | u32 stage_buf_num; | |
972 | #endif | |
973 | #endif | |
974 | ||
546484c5 | 975 | struct VP9Decoder_s { |
976 | #ifdef MULTI_INSTANCE_SUPPORT | |
977 | unsigned char index; | |
978 | ||
979 | struct device *cma_dev; | |
980 | struct platform_device *platform_dev; | |
981 | void (*vdec_cb)(struct vdec_s *, void *); | |
982 | void *vdec_cb_arg; | |
983 | struct vframe_chunk_s *chunk; | |
984 | int dec_result; | |
985 | struct work_struct work; | |
a994f6d6 | 986 | struct work_struct set_clk_work; |
546484c5 | 987 | u32 start_shift_bytes; |
988 | ||
989 | struct BuffInfo_s work_space_buf_store; | |
990 | unsigned long buf_start; | |
991 | u32 buf_size; | |
992 | u32 cma_alloc_count; | |
993 | unsigned long cma_alloc_addr; | |
994 | uint8_t eos; | |
995 | unsigned long int start_process_time; | |
996 | unsigned last_lcu_idx; | |
997 | int decode_timeout_count; | |
998 | unsigned timeout_num; | |
a5c5bec0 | 999 | int save_buffer_mode; |
546484c5 | 1000 | |
1001 | int double_write_mode; | |
1002 | #endif | |
546484c5 | 1003 | long used_4k_num; |
b7706e1e | 1004 | |
546484c5 | 1005 | unsigned char m_ins_flag; |
1006 | char *provider_name; | |
1007 | union param_u param; | |
1008 | int frame_count; | |
1009 | int pic_count; | |
1010 | u32 stat; | |
1011 | struct timer_list timer; | |
1012 | u32 frame_dur; | |
1013 | u32 frame_ar; | |
1014 | int fatal_error; | |
1015 | uint8_t init_flag; | |
ca482a9c | 1016 | uint8_t first_sc_checked; |
546484c5 | 1017 | uint8_t process_busy; |
1018 | #define PROC_STATE_INIT 0 | |
1019 | #define PROC_STATE_DECODESLICE 1 | |
1020 | #define PROC_STATE_SENDAGAIN 2 | |
1021 | uint8_t process_state; | |
1022 | u32 ucode_pause_pos; | |
1023 | ||
1024 | int show_frame_num; | |
546484c5 | 1025 | struct buff_s mc_buf_spec; |
546484c5 | 1026 | struct dec_sysinfo vvp9_amstream_dec_info; |
1027 | void *rpm_addr; | |
1028 | void *lmem_addr; | |
1029 | dma_addr_t rpm_phy_addr; | |
1030 | dma_addr_t lmem_phy_addr; | |
1031 | unsigned short *lmem_ptr; | |
1032 | unsigned short *debug_ptr; | |
1033 | ||
1034 | void *prob_buffer_addr; | |
1035 | void *count_buffer_addr; | |
1036 | dma_addr_t prob_buffer_phy_addr; | |
1037 | dma_addr_t count_buffer_phy_addr; | |
1038 | ||
546484c5 | 1039 | void *frame_mmu_map_addr; |
1040 | dma_addr_t frame_mmu_map_phy_addr; | |
b7706e1e | 1041 | |
546484c5 | 1042 | unsigned int use_cma_flag; |
1043 | ||
1044 | struct BUF_s m_BUF[MAX_BUF_NUM]; | |
a6c89e96 | 1045 | struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM]; |
546484c5 | 1046 | u32 used_buf_num; |
1047 | DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); | |
1048 | DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); | |
1049 | DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE); | |
1050 | struct vframe_s vfpool[VF_POOL_SIZE]; | |
1051 | u32 vf_pre_count; | |
1052 | u32 vf_get_count; | |
1053 | u32 vf_put_count; | |
1054 | int buf_num; | |
1055 | int pic_num; | |
1056 | int lcu_size_log2; | |
1057 | unsigned int losless_comp_body_size; | |
1058 | ||
1059 | u32 video_signal_type; | |
1060 | ||
1061 | int pts_mode; | |
1062 | int last_lookup_pts; | |
1063 | int last_pts; | |
1064 | u64 last_lookup_pts_us64; | |
1065 | u64 last_pts_us64; | |
1066 | u64 shift_byte_count; | |
1067 | ||
1068 | u32 pts_unstable; | |
1069 | u32 frame_cnt_window; | |
1070 | u32 pts1, pts2; | |
1071 | u32 last_duration; | |
1072 | u32 duration_from_pts_done; | |
1073 | bool vp9_first_pts_ready; | |
1074 | ||
1075 | u32 shift_byte_count_lo; | |
1076 | u32 shift_byte_count_hi; | |
1077 | int pts_mode_switching_count; | |
1078 | int pts_mode_recovery_count; | |
1079 | ||
1080 | bool get_frame_dur; | |
1081 | u32 saved_resolution; | |
1082 | ||
1083 | /**/ | |
1084 | struct VP9_Common_s common; | |
1085 | struct RefCntBuffer_s *cur_buf; | |
1086 | int refresh_frame_flags; | |
1087 | uint8_t need_resync; | |
1088 | uint8_t hold_ref_buf; | |
1089 | uint8_t ready_for_new_data; | |
1090 | struct BufferPool_s vp9_buffer_pool; | |
b7706e1e | 1091 | |
546484c5 | 1092 | struct BuffInfo_s *work_space_buf; |
b7706e1e | 1093 | |
546484c5 | 1094 | struct buff_s *mc_buf; |
b7706e1e | 1095 | |
546484c5 | 1096 | unsigned int frame_width; |
1097 | unsigned int frame_height; | |
1098 | ||
1099 | unsigned short *rpm_ptr; | |
1100 | int init_pic_w; | |
1101 | int init_pic_h; | |
1102 | int lcu_total; | |
1103 | int lcu_size; | |
1104 | ||
1105 | int slice_type; | |
1106 | ||
1107 | int skip_flag; | |
1108 | int decode_idx; | |
1109 | int slice_idx; | |
1110 | uint8_t has_keyframe; | |
1111 | uint8_t wait_buf; | |
1112 | uint8_t error_flag; | |
1113 | ||
1114 | /* bit 0, for decoding; bit 1, for displaying */ | |
1115 | uint8_t ignore_bufmgr_error; | |
1116 | int PB_skip_mode; | |
1117 | int PB_skip_count_after_decoding; | |
1118 | /*hw*/ | |
1119 | ||
1120 | /*lf*/ | |
1121 | int default_filt_lvl; | |
1122 | struct loop_filter_info_n *lfi; | |
1123 | struct loopfilter *lf; | |
1124 | struct segmentation *seg_4lf; | |
1125 | /**/ | |
1126 | struct vdec_info *gvs; | |
1127 | ||
1128 | u32 pre_stream_offset; | |
1129 | ||
1130 | unsigned int dec_status; | |
1131 | u32 last_put_idx; | |
1132 | int new_frame_displayed; | |
1133 | void *mmu_box; | |
1134 | void *bmmu_box; | |
b7706e1e | 1135 | int mmu_enable; |
546484c5 | 1136 | struct vframe_master_display_colour_s vf_dp; |
1137 | struct firmware_s *fw; | |
1138 | int max_pic_w; | |
1139 | int max_pic_h; | |
a6c89e96 NQ |
1140 | #ifdef SUPPORT_FB_DECODING |
1141 | int dec_s1_result; | |
1142 | int s1_test_cmd; | |
1143 | struct work_struct s1_work; | |
1144 | int used_stage_buf_num; | |
1145 | int s1_pos; | |
1146 | int s2_pos; | |
1147 | void *stage_mmu_map_addr; | |
1148 | dma_addr_t stage_mmu_map_phy_addr; | |
1149 | struct stage_buf_s *s1_buf; | |
1150 | struct stage_buf_s *s2_buf; | |
1151 | struct stage_buf_s *stage_bufs | |
1152 | [STAGE_MAX_BUFFERS]; | |
1153 | unsigned char run2_busy; | |
1154 | ||
1155 | int s1_mv_buf_index; | |
1156 | int s1_mv_buf_index_pre; | |
1157 | int s1_mv_buf_index_pre_pre; | |
1158 | unsigned long s1_mpred_mv_wr_start_addr; | |
1159 | unsigned long s1_mpred_mv_wr_start_addr_pre; | |
1160 | unsigned short s1_intra_only; | |
1161 | unsigned short s1_frame_type; | |
1162 | unsigned short s1_width; | |
1163 | unsigned short s1_height; | |
1164 | unsigned short s1_last_show_frame; | |
1165 | union param_u s1_param; | |
1166 | u8 back_not_run_ready; | |
1167 | #endif | |
ca482a9c HZ |
1168 | int need_cache_size; |
1169 | u64 sc_start_time; | |
187af067 | 1170 | bool postproc_done; |
1171 | int low_latency_flag; | |
0eb79ad7 | 1172 | bool no_head; |
2cd6815e NQ |
1173 | bool pic_list_init_done; |
1174 | bool pic_list_init_done2; | |
1175 | bool is_used_v4l; | |
1176 | void *v4l2_ctx; | |
ac678990 NQ |
1177 | int frameinfo_enable; |
1178 | struct vframe_qos_s vframe_qos; | |
b7706e1e | 1179 | }; |
546484c5 | 1180 | |
3d58646a NQ |
1181 | static int vp9_print(struct VP9Decoder_s *pbi, |
1182 | int flag, const char *fmt, ...) | |
1183 | { | |
1184 | #define HEVC_PRINT_BUF 256 | |
1185 | unsigned char buf[HEVC_PRINT_BUF]; | |
1186 | int len = 0; | |
1187 | ||
1188 | if (pbi == NULL || | |
1189 | (flag == 0) || | |
1190 | (debug & flag)) { | |
1191 | va_list args; | |
1192 | ||
1193 | va_start(args, fmt); | |
1194 | if (pbi) | |
1195 | len = sprintf(buf, "[%d]", pbi->index); | |
1196 | vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args); | |
1197 | pr_debug("%s", buf); | |
1198 | va_end(args); | |
1199 | } | |
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | static int is_oversize(int w, int h) | |
1204 | { | |
1205 | int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)? | |
1206 | MAX_SIZE_8K : MAX_SIZE_4K; | |
1207 | ||
1208 | if (w <= 0 || h <= 0) | |
1209 | return true; | |
1210 | ||
1211 | if (h != 0 && (w > max / h)) | |
1212 | return true; | |
1213 | ||
1214 | return false; | |
1215 | } | |
1216 | ||
2cd6815e NQ |
1217 | static int v4l_get_fb(struct aml_vcodec_ctx *ctx, struct vdec_fb **out) |
1218 | { | |
1219 | int ret = 0; | |
1220 | ||
1221 | ret = ctx->dec_if->get_param(ctx->drv_handle, | |
1222 | GET_PARAM_FREE_FRAME_BUFFER, out); | |
2cd6815e NQ |
1223 | |
1224 | return ret; | |
1225 | } | |
1226 | ||
546484c5 | 1227 | static void resize_context_buffers(struct VP9Decoder_s *pbi, |
1228 | struct VP9_Common_s *cm, int width, int height) | |
b9164398 NQ |
1229 | { |
1230 | if (cm->width != width || cm->height != height) { | |
1231 | /* to do ..*/ | |
546484c5 | 1232 | if (pbi != NULL) { |
1233 | pbi->vp9_first_pts_ready = 0; | |
1234 | pbi->duration_from_pts_done = 0; | |
1235 | } | |
b9164398 NQ |
1236 | cm->width = width; |
1237 | cm->height = height; | |
1238 | pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width, | |
1239 | cm->height, width, height); | |
1240 | } | |
1241 | /* | |
e0614bf7 ZZ |
1242 | *if (cm->cur_frame->mvs == NULL || |
1243 | * cm->mi_rows > cm->cur_frame->mi_rows || | |
1244 | * cm->mi_cols > cm->cur_frame->mi_cols) { | |
1245 | * resize_mv_buffer(cm); | |
1246 | *} | |
1247 | */ | |
b9164398 NQ |
1248 | } |
1249 | ||
1250 | static int valid_ref_frame_size(int ref_width, int ref_height, | |
1251 | int this_width, int this_height) { | |
1252 | return 2 * this_width >= ref_width && | |
1253 | 2 * this_height >= ref_height && | |
1254 | this_width <= 16 * ref_width && | |
1255 | this_height <= 16 * ref_height; | |
1256 | } | |
1257 | ||
1258 | /* | |
e0614bf7 ZZ |
1259 | *static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth, |
1260 | * int ref_xss, int ref_yss, | |
1261 | * enum vpx_bit_depth_t this_bit_depth, | |
1262 | * int this_xss, int this_yss) { | |
1263 | * return ref_bit_depth == this_bit_depth && ref_xss == this_xss && | |
1264 | * ref_yss == this_yss; | |
1265 | *} | |
1266 | */ | |
b9164398 NQ |
1267 | |
1268 | ||
1269 | static int setup_frame_size( | |
1270 | struct VP9Decoder_s *pbi, | |
1271 | struct VP9_Common_s *cm, union param_u *params, | |
1272 | unsigned int *mmu_index_adr, | |
1273 | int print_header_info) { | |
1274 | int width, height; | |
1275 | struct BufferPool_s * const pool = cm->buffer_pool; | |
1276 | struct PIC_BUFFER_CONFIG_s *ybf; | |
1277 | int ret = 0; | |
1278 | ||
1279 | width = params->p.width; | |
1280 | height = params->p.height; | |
3d58646a NQ |
1281 | if (is_oversize(width, height)) { |
1282 | vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__); | |
1283 | return -1; | |
1284 | } | |
1285 | ||
b9164398 NQ |
1286 | /*vp9_read_frame_size(rb, &width, &height);*/ |
1287 | if (print_header_info) | |
1288 | pr_info(" * 16-bits w read : %d (width : %d)\n", width, height); | |
1289 | if (print_header_info) | |
1290 | pr_info | |
1291 | (" * 16-bits h read : %d (height : %d)\n", width, height); | |
1292 | ||
1293 | WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width); | |
df841122 | 1294 | #ifdef VP9_10B_HED_FB |
6276f4ff | 1295 | WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width); |
df841122 | 1296 | #endif |
6276f4ff | 1297 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
b7706e1e | 1298 | ret = vp9_alloc_mmu(pbi, |
b9164398 | 1299 | cm->new_fb_idx, |
b7706e1e | 1300 | params->p.width, |
1301 | params->p.height, | |
1302 | params->p.bit_depth, | |
1303 | mmu_index_adr); | |
1304 | if (ret != 0) { | |
1305 | pr_err("can't alloc need mmu1,idx %d ret =%d\n", | |
1306 | cm->new_fb_idx, | |
1307 | ret); | |
1308 | return ret; | |
1309 | } | |
1310 | cm->cur_fb_idx_mmu = cm->new_fb_idx; | |
b9164398 | 1311 | } |
b9164398 | 1312 | |
546484c5 | 1313 | resize_context_buffers(pbi, cm, width, height); |
b9164398 NQ |
1314 | setup_display_size(cm, params, print_header_info); |
1315 | #if 0 | |
1316 | lock_buffer_pool(pool); | |
1317 | if (vp9_realloc_frame_buffer( | |
1318 | get_frame_new_buffer(cm), cm->width, cm->height, | |
1319 | cm->subsampling_x, cm->subsampling_y, | |
1320 | #if CONFIG_VP9_HIGHBITDEPTH | |
1321 | cm->use_highbitdepth, | |
1322 | #endif | |
1323 | VP9_DEC_BORDER_IN_PIXELS, | |
1324 | cm->byte_alignment, | |
1325 | &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer, | |
1326 | pool->get_fb_cb, pool->cb_priv)) { | |
1327 | unlock_buffer_pool(pool); | |
1328 | vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR, | |
1329 | "Failed to allocate frame buffer"); | |
1330 | } | |
1331 | unlock_buffer_pool(pool); | |
1332 | #else | |
1333 | /* porting */ | |
1334 | ybf = get_frame_new_buffer(cm); | |
1335 | ybf->y_crop_width = width; | |
1336 | ybf->y_crop_height = height; | |
1337 | ybf->bit_depth = params->p.bit_depth; | |
1338 | #endif | |
1339 | pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x; | |
1340 | pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y; | |
1341 | pool->frame_bufs[cm->new_fb_idx].buf.bit_depth = | |
1342 | (unsigned int)cm->bit_depth; | |
1343 | pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space; | |
1344 | return ret; | |
1345 | } | |
1346 | ||
1347 | static int setup_frame_size_with_refs( | |
1348 | struct VP9Decoder_s *pbi, | |
1349 | struct VP9_Common_s *cm, | |
1350 | union param_u *params, | |
1351 | unsigned int *mmu_index_adr, | |
1352 | int print_header_info) { | |
1353 | ||
1354 | int width, height; | |
1355 | int found = 0, i; | |
1356 | int has_valid_ref_frame = 0; | |
1357 | struct PIC_BUFFER_CONFIG_s *ybf; | |
1358 | struct BufferPool_s * const pool = cm->buffer_pool; | |
1359 | int ret = 0; | |
1360 | ||
1361 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
1362 | if ((params->p.same_frame_size >> | |
1363 | (REFS_PER_FRAME - i - 1)) & 0x1) { | |
1364 | struct PIC_BUFFER_CONFIG_s *const buf = | |
1365 | cm->frame_refs[i].buf; | |
1366 | /*if (print_header_info) | |
e0614bf7 ZZ |
1367 | * pr_info |
1368 | * ("1-bit same_frame_size[%d] read : 1\n", i); | |
1369 | */ | |
b9164398 NQ |
1370 | width = buf->y_crop_width; |
1371 | height = buf->y_crop_height; | |
1372 | /*if (print_header_info) | |
e0614bf7 ZZ |
1373 | * pr_info |
1374 | * (" - same_frame_size width : %d\n", width); | |
1375 | */ | |
b9164398 | 1376 | /*if (print_header_info) |
e0614bf7 ZZ |
1377 | * pr_info |
1378 | * (" - same_frame_size height : %d\n", height); | |
1379 | */ | |
b9164398 NQ |
1380 | found = 1; |
1381 | break; | |
a6c89e96 | 1382 | } else { |
b9164398 | 1383 | /*if (print_header_info) |
e0614bf7 ZZ |
1384 | * pr_info |
1385 | * ("1-bit same_frame_size[%d] read : 0\n", i); | |
1386 | */ | |
b9164398 NQ |
1387 | } |
1388 | } | |
1389 | ||
1390 | if (!found) { | |
1391 | /*vp9_read_frame_size(rb, &width, &height);*/ | |
1392 | width = params->p.width; | |
1393 | height = params->p.height; | |
1394 | /*if (print_header_info) | |
e0614bf7 ZZ |
1395 | * pr_info |
1396 | * (" * 16-bits w read : %d (width : %d)\n", | |
1397 | * width, height); | |
1398 | *if (print_header_info) | |
1399 | * pr_info | |
1400 | * (" * 16-bits h read : %d (height : %d)\n", | |
1401 | * width, height); | |
1402 | */ | |
b9164398 NQ |
1403 | } |
1404 | ||
3d58646a NQ |
1405 | if (is_oversize(width, height)) { |
1406 | vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__); | |
b9164398 NQ |
1407 | return -1; |
1408 | } | |
1409 | ||
1410 | params->p.width = width; | |
1411 | params->p.height = height; | |
1412 | ||
1413 | WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width); | |
6276f4ff | 1414 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
b7706e1e | 1415 | /*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx); |
1416 | *cm->prev_fb_idx = cm->new_fb_idx; | |
1417 | */ | |
1418 | /* pr_info | |
1419 | * ("[DEBUG DEBUG]Before alloc_mmu, | |
1420 | * prev_fb_idx : %d, new_fb_idx : %d\r\n", | |
1421 | * cm->prev_fb_idx, cm->new_fb_idx); | |
1422 | */ | |
1423 | ret = vp9_alloc_mmu(pbi, cm->new_fb_idx, | |
1424 | params->p.width, params->p.height, | |
1425 | params->p.bit_depth, mmu_index_adr); | |
1426 | if (ret != 0) { | |
1427 | pr_err("can't alloc need mmu,idx %d\r\n", | |
1428 | cm->new_fb_idx); | |
1429 | return ret; | |
1430 | } | |
1431 | cm->cur_fb_idx_mmu = cm->new_fb_idx; | |
b9164398 | 1432 | } |
b9164398 NQ |
1433 | |
1434 | /*Check to make sure at least one of frames that this frame references | |
e0614bf7 ZZ |
1435 | *has valid dimensions. |
1436 | */ | |
b9164398 NQ |
1437 | for (i = 0; i < REFS_PER_FRAME; ++i) { |
1438 | struct RefBuffer_s * const ref_frame = &cm->frame_refs[i]; | |
e0614bf7 | 1439 | |
b9164398 NQ |
1440 | has_valid_ref_frame |= |
1441 | valid_ref_frame_size(ref_frame->buf->y_crop_width, | |
1442 | ref_frame->buf->y_crop_height, | |
1443 | width, height); | |
1444 | } | |
1445 | if (!has_valid_ref_frame) { | |
1446 | pr_err("Error: Referenced frame has invalid size\r\n"); | |
1447 | return -1; | |
1448 | } | |
1449 | #if 0 | |
1450 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
a6c89e96 NQ |
1451 | struct RefBuffer_s * const ref_frame = |
1452 | &cm->frame_refs[i]; | |
1453 | if (!valid_ref_frame_img_fmt( | |
1454 | ref_frame->buf->bit_depth, | |
1455 | ref_frame->buf->subsampling_x, | |
1456 | ref_frame->buf->subsampling_y, | |
1457 | cm->bit_depth, | |
1458 | cm->subsampling_x, | |
1459 | cm->subsampling_y)) | |
1460 | pr_err | |
b9164398 NQ |
1461 | ("Referenced frame incompatible color fmt\r\n"); |
1462 | return -1; | |
1463 | } | |
1464 | #endif | |
546484c5 | 1465 | resize_context_buffers(pbi, cm, width, height); |
b9164398 NQ |
1466 | setup_display_size(cm, params, print_header_info); |
1467 | ||
1468 | #if 0 | |
1469 | lock_buffer_pool(pool); | |
1470 | if (vp9_realloc_frame_buffer( | |
1471 | get_frame_new_buffer(cm), cm->width, cm->height, | |
1472 | cm->subsampling_x, cm->subsampling_y, | |
1473 | #if CONFIG_VP9_HIGHBITDEPTH | |
1474 | cm->use_highbitdepth, | |
1475 | #endif | |
1476 | VP9_DEC_BORDER_IN_PIXELS, | |
1477 | cm->byte_alignment, | |
1478 | &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer, | |
1479 | pool->get_fb_cb, | |
1480 | pool->cb_priv)) { | |
e0614bf7 ZZ |
1481 | unlock_buffer_pool(pool); |
1482 | vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR, | |
1483 | "Failed to allocate frame buffer"); | |
b9164398 NQ |
1484 | } |
1485 | unlock_buffer_pool(pool); | |
1486 | #else | |
1487 | /* porting */ | |
1488 | ybf = get_frame_new_buffer(cm); | |
1489 | ybf->y_crop_width = width; | |
1490 | ybf->y_crop_height = height; | |
1491 | ybf->bit_depth = params->p.bit_depth; | |
1492 | #endif | |
1493 | pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x; | |
1494 | pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y; | |
1495 | pool->frame_bufs[cm->new_fb_idx].buf.bit_depth = | |
1496 | (unsigned int)cm->bit_depth; | |
1497 | pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space; | |
1498 | return ret; | |
1499 | } | |
1500 | ||
c20e6c85 | 1501 | static inline bool close_to(int a, int b, int m) |
1502 | { | |
1503 | return (abs(a - b) < m) ? true : false; | |
1504 | } | |
1505 | ||
b9164398 NQ |
1506 | #ifdef MULTI_INSTANCE_SUPPORT |
1507 | static int vp9_print_cont(struct VP9Decoder_s *pbi, | |
1508 | int flag, const char *fmt, ...) | |
1509 | { | |
1510 | unsigned char buf[HEVC_PRINT_BUF]; | |
1511 | int len = 0; | |
e0614bf7 | 1512 | |
b9164398 NQ |
1513 | if (pbi == NULL || |
1514 | (flag == 0) || | |
1515 | (debug & flag)) { | |
1516 | va_list args; | |
e0614bf7 | 1517 | |
b9164398 NQ |
1518 | va_start(args, fmt); |
1519 | vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args); | |
fbe200cf | 1520 | pr_debug("%s", buf); |
b9164398 NQ |
1521 | va_end(args); |
1522 | } | |
1523 | return 0; | |
1524 | } | |
fe96802b | 1525 | |
a6c89e96 NQ |
1526 | static void trigger_schedule(struct VP9Decoder_s *pbi) |
1527 | { | |
1528 | if (pbi->vdec_cb) | |
1529 | pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg); | |
1530 | } | |
1531 | ||
fe96802b NQ |
1532 | static void reset_process_time(struct VP9Decoder_s *pbi) |
1533 | { | |
1534 | if (pbi->start_process_time) { | |
1535 | unsigned process_time = | |
1536 | 1000 * (jiffies - pbi->start_process_time) / HZ; | |
1537 | pbi->start_process_time = 0; | |
1538 | if (process_time > max_process_time[pbi->index]) | |
1539 | max_process_time[pbi->index] = process_time; | |
1540 | } | |
1541 | } | |
1542 | ||
1543 | static void start_process_time(struct VP9Decoder_s *pbi) | |
1544 | { | |
1545 | pbi->start_process_time = jiffies; | |
1546 | pbi->decode_timeout_count = 0; | |
1547 | pbi->last_lcu_idx = 0; | |
1548 | } | |
1549 | ||
1550 | static void timeout_process(struct VP9Decoder_s *pbi) | |
1551 | { | |
1552 | pbi->timeout_num++; | |
1553 | amhevc_stop(); | |
1554 | vp9_print(pbi, | |
1555 | 0, "%s decoder timeout\n", __func__); | |
1556 | ||
1557 | pbi->dec_result = DEC_RESULT_DONE; | |
1558 | reset_process_time(pbi); | |
1559 | vdec_schedule_work(&pbi->work); | |
1560 | } | |
1561 | ||
c23e8aee HZ |
1562 | static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi) |
1563 | { | |
b7706e1e | 1564 | return ((double_write_mode & 0x80000000) == 0) ? |
c23e8aee HZ |
1565 | pbi->double_write_mode : |
1566 | (double_write_mode & 0x7fffffff); | |
1567 | } | |
1568 | ||
fe96802b NQ |
1569 | static int get_double_write_mode(struct VP9Decoder_s *pbi) |
1570 | { | |
c23e8aee HZ |
1571 | u32 valid_dw_mode = get_valid_double_write_mode(pbi); |
1572 | u32 dw; | |
1573 | if (valid_dw_mode == 0x100) { | |
1574 | struct VP9_Common_s *cm = &pbi->common; | |
976f3376 HZ |
1575 | struct PIC_BUFFER_CONFIG_s *cur_pic_config; |
1576 | int w, h; | |
1577 | ||
1578 | if (!cm->cur_frame) | |
1579 | return 1;/*no valid frame,*/ | |
1580 | cur_pic_config = &cm->cur_frame->buf; | |
1581 | w = cur_pic_config->y_crop_width; | |
1582 | h = cur_pic_config->y_crop_width; | |
c23e8aee HZ |
1583 | if (w > 1920 && h > 1088) |
1584 | dw = 0x4; /*1:2*/ | |
1585 | else | |
1586 | dw = 0x1; /*1:1*/ | |
1587 | ||
1588 | return dw; | |
1589 | } | |
1590 | ||
1591 | return valid_dw_mode; | |
1592 | } | |
1593 | ||
1594 | /* for double write buf alloc */ | |
1595 | static int get_double_write_mode_init(struct VP9Decoder_s *pbi) | |
1596 | { | |
1597 | u32 valid_dw_mode = get_valid_double_write_mode(pbi); | |
1598 | if (valid_dw_mode == 0x100) { | |
1599 | u32 dw; | |
1600 | int w = pbi->init_pic_w; | |
1601 | int h = pbi->init_pic_h; | |
1602 | if (w > 1920 && h > 1088) | |
1603 | dw = 0x4; /*1:2*/ | |
1604 | else | |
1605 | dw = 0x1; /*1:1*/ | |
1606 | ||
1607 | return dw; | |
1608 | } | |
1609 | return valid_dw_mode; | |
fe96802b | 1610 | } |
b9164398 | 1611 | #endif |
c23e8aee HZ |
1612 | |
1613 | static int get_double_write_ratio(struct VP9Decoder_s *pbi, | |
1614 | int dw_mode) | |
1615 | { | |
1616 | int ratio = 1; | |
1617 | if ((dw_mode == 2) || | |
1618 | (dw_mode == 3)) | |
1619 | ratio = 4; | |
1620 | else if (dw_mode == 4) | |
1621 | ratio = 2; | |
1622 | return ratio; | |
1623 | } | |
1624 | ||
df841122 | 1625 | //#define MAX_4K_NUM 0x1200 |
b7706e1e | 1626 | |
b9164398 NQ |
1627 | int vp9_alloc_mmu( |
1628 | struct VP9Decoder_s *pbi, | |
1629 | int cur_buf_idx, | |
1630 | int pic_width, | |
1631 | int pic_height, | |
1632 | unsigned short bit_depth, | |
1633 | unsigned int *mmu_index_adr) | |
1634 | { | |
1635 | int bit_depth_10 = (bit_depth == VPX_BITS_10); | |
1636 | int picture_size; | |
df841122 | 1637 | int cur_mmu_4k_number, max_frame_num; |
976f3376 HZ |
1638 | if (!pbi->mmu_box) { |
1639 | pr_err("error no mmu box!\n"); | |
1640 | return -1; | |
1641 | } | |
6276f4ff HZ |
1642 | if (pbi->double_write_mode & 0x10) |
1643 | return 0; | |
976f3376 HZ |
1644 | if (bit_depth >= VPX_BITS_12) { |
1645 | pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW; | |
1646 | pr_err("fatal_error, un support bit depth 12!\n\n"); | |
1647 | return -1; | |
1648 | } | |
b9164398 NQ |
1649 | picture_size = compute_losless_comp_body_size(pic_width, pic_height, |
1650 | bit_depth_10); | |
1651 | cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12); | |
df841122 | 1652 | |
6f5ee885 | 1653 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) |
df841122 | 1654 | max_frame_num = MAX_FRAME_8K_NUM; |
1655 | else | |
1656 | max_frame_num = MAX_FRAME_4K_NUM; | |
1657 | ||
1658 | if (cur_mmu_4k_number > max_frame_num) { | |
d481db31 NQ |
1659 | pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n", |
1660 | cur_mmu_4k_number, pic_width, pic_height); | |
1661 | return -1; | |
1662 | } | |
b9164398 NQ |
1663 | return decoder_mmu_box_alloc_idx( |
1664 | pbi->mmu_box, | |
1665 | cur_buf_idx, | |
1666 | cur_mmu_4k_number, | |
1667 | mmu_index_adr); | |
1668 | } | |
b7706e1e | 1669 | |
fe96802b NQ |
1670 | |
1671 | #ifndef MV_USE_FIXED_BUF | |
1672 | static void dealloc_mv_bufs(struct VP9Decoder_s *pbi) | |
1673 | { | |
1674 | int i; | |
a6c89e96 | 1675 | for (i = 0; i < MV_BUFFER_NUM; i++) { |
fe96802b NQ |
1676 | if (pbi->m_mv_BUF[i].start_adr) { |
1677 | if (debug) | |
1678 | pr_info( | |
1679 | "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n", | |
1680 | i, pbi->m_mv_BUF[i].start_adr, | |
1681 | pbi->m_mv_BUF[i].size, | |
1682 | pbi->m_mv_BUF[i].used_flag); | |
1683 | decoder_bmmu_box_free_idx( | |
1684 | pbi->bmmu_box, | |
1685 | MV_BUFFER_IDX(i)); | |
1686 | pbi->m_mv_BUF[i].start_adr = 0; | |
1687 | pbi->m_mv_BUF[i].size = 0; | |
1688 | pbi->m_mv_BUF[i].used_flag = 0; | |
1689 | } | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | static int alloc_mv_buf(struct VP9Decoder_s *pbi, | |
1694 | int i, int size) | |
1695 | { | |
1696 | int ret = 0; | |
1697 | if (decoder_bmmu_box_alloc_buf_phy | |
1698 | (pbi->bmmu_box, | |
1699 | MV_BUFFER_IDX(i), size, | |
1700 | DRIVER_NAME, | |
1701 | &pbi->m_mv_BUF[i].start_adr) < 0) { | |
1702 | pbi->m_mv_BUF[i].start_adr = 0; | |
1703 | ret = -1; | |
1704 | } else { | |
1705 | pbi->m_mv_BUF[i].size = size; | |
1706 | pbi->m_mv_BUF[i].used_flag = 0; | |
1707 | ret = 0; | |
1708 | if (debug) { | |
1709 | pr_info( | |
1710 | "MV Buffer %d: start_adr %p size %x\n", | |
1711 | i, | |
1712 | (void *)pbi->m_mv_BUF[i].start_adr, | |
1713 | pbi->m_mv_BUF[i].size); | |
1714 | } | |
1715 | } | |
1716 | return ret; | |
1717 | } | |
1718 | ||
1719 | static int init_mv_buf_list(struct VP9Decoder_s *pbi) | |
1720 | { | |
1721 | int i; | |
1722 | int ret = 0; | |
a6c89e96 | 1723 | int count = MV_BUFFER_NUM; |
fe96802b NQ |
1724 | int pic_width = pbi->init_pic_w; |
1725 | int pic_height = pbi->init_pic_h; | |
1726 | int lcu_size = 64; /*fixed 64*/ | |
1727 | int pic_width_64 = (pic_width + 63) & (~0x3f); | |
1728 | int pic_height_32 = (pic_height + 31) & (~0x1f); | |
1729 | int pic_width_lcu = (pic_width_64 % lcu_size) ? | |
1730 | pic_width_64 / lcu_size + 1 | |
1731 | : pic_width_64 / lcu_size; | |
1732 | int pic_height_lcu = (pic_height_32 % lcu_size) ? | |
1733 | pic_height_32 / lcu_size + 1 | |
1734 | : pic_height_32 / lcu_size; | |
1735 | int lcu_total = pic_width_lcu * pic_height_lcu; | |
1736 | int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) & | |
1737 | (~0xffff); | |
dfe41deb RZ |
1738 | if (mv_buf_margin > 0) |
1739 | count = REF_FRAMES + mv_buf_margin; | |
a674e3cd | 1740 | |
dfe41deb RZ |
1741 | if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088) |
1742 | count = REF_FRAMES_4K + mv_buf_margin; | |
df841122 | 1743 | |
a674e3cd | 1744 | if (debug) { |
1745 | pr_info("%s w:%d, h:%d, count: %d\n", | |
1746 | __func__, pbi->init_pic_w, pbi->init_pic_h, count); | |
1747 | } | |
1748 | ||
a6c89e96 NQ |
1749 | for (i = 0; |
1750 | i < count && i < MV_BUFFER_NUM; i++) { | |
fe96802b NQ |
1751 | if (alloc_mv_buf(pbi, i, size) < 0) { |
1752 | ret = -1; | |
1753 | break; | |
1754 | } | |
1755 | } | |
1756 | return ret; | |
1757 | } | |
1758 | ||
1759 | static int get_mv_buf(struct VP9Decoder_s *pbi, | |
a6c89e96 NQ |
1760 | int *mv_buf_index, |
1761 | unsigned long *mpred_mv_wr_start_addr) | |
fe96802b NQ |
1762 | { |
1763 | int i; | |
1764 | int ret = -1; | |
a6c89e96 | 1765 | for (i = 0; i < MV_BUFFER_NUM; i++) { |
fe96802b NQ |
1766 | if (pbi->m_mv_BUF[i].start_adr && |
1767 | pbi->m_mv_BUF[i].used_flag == 0) { | |
1768 | pbi->m_mv_BUF[i].used_flag = 1; | |
1769 | ret = i; | |
1770 | break; | |
1771 | } | |
1772 | } | |
1773 | ||
1774 | if (ret >= 0) { | |
a6c89e96 NQ |
1775 | *mv_buf_index = ret; |
1776 | *mpred_mv_wr_start_addr = | |
fe96802b NQ |
1777 | (pbi->m_mv_BUF[ret].start_adr + 0xffff) & |
1778 | (~0xffff); | |
1779 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
1780 | pr_info( | |
1781 | "%s => %d (%ld) size 0x%x\n", | |
1782 | __func__, ret, | |
a6c89e96 | 1783 | *mpred_mv_wr_start_addr, |
fe96802b NQ |
1784 | pbi->m_mv_BUF[ret].size); |
1785 | } else { | |
1786 | pr_info( | |
1787 | "%s: Error, mv buf is not enough\n", | |
1788 | __func__); | |
1789 | } | |
1790 | return ret; | |
1791 | } | |
1792 | ||
1793 | static void put_mv_buf(struct VP9Decoder_s *pbi, | |
a6c89e96 | 1794 | int *mv_buf_index) |
fe96802b | 1795 | { |
a6c89e96 NQ |
1796 | int i = *mv_buf_index; |
1797 | if (i >= MV_BUFFER_NUM) { | |
fe96802b NQ |
1798 | if (debug & VP9_DEBUG_BUFMGR_MORE) |
1799 | pr_info( | |
1800 | "%s: index %d beyond range\n", | |
1801 | __func__, i); | |
1802 | return; | |
1803 | } | |
1804 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
1805 | pr_info( | |
1806 | "%s(%d): used_flag(%d)\n", | |
1807 | __func__, i, | |
1808 | pbi->m_mv_BUF[i].used_flag); | |
1809 | ||
a6c89e96 | 1810 | *mv_buf_index = -1; |
fe96802b NQ |
1811 | if (pbi->m_mv_BUF[i].start_adr && |
1812 | pbi->m_mv_BUF[i].used_flag) | |
1813 | pbi->m_mv_BUF[i].used_flag = 0; | |
1814 | } | |
1815 | ||
1816 | static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi) | |
1817 | { | |
1818 | struct VP9_Common_s *const cm = &pbi->common; | |
1819 | struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; | |
1820 | int i; | |
1821 | for (i = 0; i < pbi->used_buf_num; ++i) { | |
1822 | if ((frame_bufs[i].ref_count == 0) && | |
1823 | (frame_bufs[i].buf.index != -1) && | |
1824 | (frame_bufs[i].buf.mv_buf_index >= 0) | |
1825 | ) | |
a6c89e96 NQ |
1826 | put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index); |
1827 | } | |
1828 | } | |
1829 | ||
1830 | #ifdef SUPPORT_FB_DECODING | |
1831 | static bool mv_buf_available(struct VP9Decoder_s *pbi) | |
1832 | { | |
1833 | int i; | |
1834 | bool ret = 0; | |
1835 | for (i = 0; i < MV_BUFFER_NUM; i++) { | |
1836 | if (pbi->m_mv_BUF[i].start_adr && | |
1837 | pbi->m_mv_BUF[i].used_flag == 0) { | |
1838 | ret = 1; | |
1839 | break; | |
1840 | } | |
1841 | } | |
1842 | return ret; | |
1843 | } | |
1844 | #endif | |
1845 | #endif | |
1846 | ||
1847 | #ifdef SUPPORT_FB_DECODING | |
1848 | static void init_stage_buf(struct VP9Decoder_s *pbi) | |
1849 | { | |
1850 | uint i; | |
1851 | for (i = 0; i < STAGE_MAX_BUFFERS | |
1852 | && i < stage_buf_num; i++) { | |
1853 | pbi->stage_bufs[i] = | |
1854 | vmalloc(sizeof(struct stage_buf_s)); | |
1855 | if (pbi->stage_bufs[i] == NULL) { | |
1856 | vp9_print(pbi, | |
1857 | 0, "%s vmalloc fail\n", __func__); | |
1858 | break; | |
1859 | } | |
1860 | pbi->stage_bufs[i]->index = i; | |
1861 | } | |
1862 | pbi->used_stage_buf_num = i; | |
1863 | pbi->s1_pos = 0; | |
1864 | pbi->s2_pos = 0; | |
1865 | pbi->s1_buf = NULL; | |
1866 | pbi->s2_buf = NULL; | |
1867 | pbi->s1_mv_buf_index = FRAME_BUFFERS; | |
1868 | pbi->s1_mv_buf_index_pre = FRAME_BUFFERS; | |
1869 | pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS; | |
1870 | ||
1871 | if (pbi->used_stage_buf_num > 0) | |
1872 | vp9_print(pbi, | |
1873 | 0, "%s 2 stage decoding buf %d\n", | |
1874 | __func__, | |
1875 | pbi->used_stage_buf_num); | |
1876 | } | |
1877 | ||
1878 | static void uninit_stage_buf(struct VP9Decoder_s *pbi) | |
1879 | { | |
1880 | int i; | |
1881 | for (i = 0; i < pbi->used_stage_buf_num; i++) { | |
1882 | if (pbi->stage_bufs[i]) | |
1883 | vfree(pbi->stage_bufs[i]); | |
1884 | pbi->stage_bufs[i] = NULL; | |
1885 | } | |
1886 | pbi->used_stage_buf_num = 0; | |
1887 | pbi->s1_pos = 0; | |
1888 | pbi->s2_pos = 0; | |
1889 | pbi->s1_buf = NULL; | |
1890 | pbi->s2_buf = NULL; | |
1891 | } | |
1892 | ||
1893 | static int get_s1_buf( | |
1894 | struct VP9Decoder_s *pbi) | |
1895 | { | |
1896 | struct stage_buf_s *buf = NULL; | |
1897 | int ret = -1; | |
1898 | int buf_page_num = MAX_STAGE_PAGE_NUM; | |
1899 | int next_s1_pos = pbi->s1_pos + 1; | |
1900 | ||
1901 | if (next_s1_pos >= pbi->used_stage_buf_num) | |
1902 | next_s1_pos = 0; | |
1903 | if (next_s1_pos == pbi->s2_pos) { | |
1904 | pbi->s1_buf = NULL; | |
1905 | return ret; | |
1906 | } | |
1907 | ||
1908 | buf = pbi->stage_bufs[pbi->s1_pos]; | |
1909 | ret = decoder_mmu_box_alloc_idx( | |
1910 | pbi->mmu_box, | |
1911 | buf->index, | |
1912 | buf_page_num, | |
1913 | pbi->stage_mmu_map_addr); | |
1914 | if (ret < 0) { | |
1915 | vp9_print(pbi, 0, | |
1916 | "%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n", | |
1917 | __func__, buf->index, | |
1918 | pbi->s1_pos, pbi->s2_pos); | |
1919 | buf = NULL; | |
1920 | } else { | |
1921 | vp9_print(pbi, VP9_DEBUG_2_STAGE, | |
1922 | "%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n", | |
1923 | __func__, buf_page_num, buf->index, | |
1924 | pbi->s1_pos, pbi->s2_pos); | |
fe96802b | 1925 | } |
a6c89e96 NQ |
1926 | pbi->s1_buf = buf; |
1927 | return ret; | |
1928 | } | |
1929 | ||
1930 | static void inc_s1_pos(struct VP9Decoder_s *pbi) | |
1931 | { | |
1932 | struct stage_buf_s *buf = | |
1933 | pbi->stage_bufs[pbi->s1_pos]; | |
1934 | ||
1935 | int used_page_num = | |
1936 | #ifdef FB_DECODING_TEST_SCHEDULE | |
1937 | MAX_STAGE_PAGE_NUM/2; | |
1938 | #else | |
1939 | (READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16); | |
1940 | #endif | |
1941 | decoder_mmu_box_free_idx_tail(pbi->mmu_box, | |
1942 | FRAME_BUFFERS + buf->index, used_page_num); | |
1943 | ||
1944 | pbi->s1_pos++; | |
1945 | if (pbi->s1_pos >= pbi->used_stage_buf_num) | |
1946 | pbi->s1_pos = 0; | |
1947 | ||
1948 | vp9_print(pbi, VP9_DEBUG_2_STAGE, | |
1949 | "%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n", | |
1950 | __func__, used_page_num, buf->index, | |
1951 | pbi->s1_pos, pbi->s2_pos); | |
1952 | } | |
1953 | ||
1954 | #define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos) | |
1955 | ||
1956 | static int get_s2_buf( | |
1957 | struct VP9Decoder_s *pbi) | |
1958 | { | |
1959 | int ret = -1; | |
1960 | struct stage_buf_s *buf = NULL; | |
1961 | if (s2_buf_available(pbi)) { | |
1962 | buf = pbi->stage_bufs[pbi->s2_pos]; | |
1963 | vp9_print(pbi, VP9_DEBUG_2_STAGE, | |
1964 | "%s for index %d (s1_pos %d s2_pos %d)\n", | |
1965 | __func__, buf->index, | |
1966 | pbi->s1_pos, pbi->s2_pos); | |
1967 | pbi->s2_buf = buf; | |
1968 | ret = 0; | |
1969 | } | |
1970 | return ret; | |
1971 | } | |
1972 | ||
1973 | static void inc_s2_pos(struct VP9Decoder_s *pbi) | |
1974 | { | |
1975 | struct stage_buf_s *buf = | |
1976 | pbi->stage_bufs[pbi->s2_pos]; | |
1977 | decoder_mmu_box_free_idx(pbi->mmu_box, | |
1978 | FRAME_BUFFERS + buf->index); | |
1979 | pbi->s2_pos++; | |
1980 | if (pbi->s2_pos >= pbi->used_stage_buf_num) | |
1981 | pbi->s2_pos = 0; | |
1982 | vp9_print(pbi, VP9_DEBUG_2_STAGE, | |
1983 | "%s for index %d (s1_pos %d s2_pos %d)\n", | |
1984 | __func__, buf->index, | |
1985 | pbi->s1_pos, pbi->s2_pos); | |
1986 | } | |
1987 | ||
1988 | static int get_free_stage_buf_num(struct VP9Decoder_s *pbi) | |
1989 | { | |
1990 | int num; | |
1991 | if (pbi->s1_pos >= pbi->s2_pos) | |
1992 | num = pbi->used_stage_buf_num - | |
1993 | (pbi->s1_pos - pbi->s2_pos) - 1; | |
1994 | else | |
1995 | num = (pbi->s2_pos - pbi->s1_pos) - 1; | |
1996 | return num; | |
1997 | } | |
1998 | ||
1999 | #ifndef FB_DECODING_TEST_SCHEDULE | |
2000 | static DEFINE_SPINLOCK(fb_core_spin_lock); | |
2001 | ||
2002 | static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi) | |
2003 | { | |
2004 | /* to do: VLSI review | |
2005 | completion of last LCU decoding in BACK | |
2006 | */ | |
2007 | return 1; | |
2008 | } | |
2009 | ||
2010 | static void start_s1_decoding(struct VP9Decoder_s *pbi) | |
2011 | { | |
2012 | /* to do: VLSI review | |
2013 | after parser, how to start LCU decoding in BACK | |
2014 | */ | |
fe96802b | 2015 | } |
a6c89e96 NQ |
2016 | |
2017 | static void fb_reset_core(struct vdec_s *vdec, u32 mask) | |
2018 | { | |
2019 | /* to do: VLSI review | |
2020 | 1. how to disconnect DMC for FRONT and BACK | |
2021 | 2. reset bit 13, 24, FRONT or BACK ?? | |
2022 | */ | |
2023 | ||
2024 | unsigned long flags; | |
2025 | u32 reset_bits = 0; | |
2026 | if (mask & HW_MASK_FRONT) | |
2027 | WRITE_VREG(HEVC_STREAM_CONTROL, 0); | |
2028 | spin_lock_irqsave(&fb_core_spin_lock, flags); | |
2029 | codec_dmcbus_write(DMC_REQ_CTRL, | |
2030 | codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4))); | |
2031 | spin_unlock_irqrestore(&fb_core_spin_lock, flags); | |
2032 | ||
2033 | while (!(codec_dmcbus_read(DMC_CHAN_STS) | |
2034 | & (1 << 4))) | |
2035 | ; | |
2036 | ||
2037 | if ((mask & HW_MASK_FRONT) && | |
2038 | input_frame_based(vdec)) | |
2039 | WRITE_VREG(HEVC_STREAM_CONTROL, 0); | |
2040 | ||
2041 | /* | |
2042 | * 2: assist | |
2043 | * 3: parser | |
2044 | * 4: parser_state | |
2045 | * 8: dblk | |
2046 | * 11:mcpu | |
2047 | * 12:ccpu | |
2048 | * 13:ddr | |
2049 | * 14:iqit | |
2050 | * 15:ipp | |
2051 | * 17:qdct | |
2052 | * 18:mpred | |
2053 | * 19:sao | |
2054 | * 24:hevc_afifo | |
2055 | */ | |
2056 | if (mask & HW_MASK_FRONT) { | |
2057 | reset_bits = | |
2058 | (1<<3)|(1<<4)|(1<<11)| | |
2059 | (1<<12)|(1<<18); | |
2060 | } | |
2061 | if (mask & HW_MASK_BACK) { | |
2062 | reset_bits = | |
2063 | (1<<8)|(1<<13)|(1<<14)|(1<<15)| | |
2064 | (1<<17)|(1<<19)|(1<<24); | |
2065 | } | |
2066 | WRITE_VREG(DOS_SW_RESET3, reset_bits); | |
2067 | #if 0 | |
2068 | (1<<3)|(1<<4)|(1<<8)|(1<<11)| | |
2069 | (1<<12)|(1<<13)|(1<<14)|(1<<15)| | |
2070 | (1<<17)|(1<<18)|(1<<19)|(1<<24); | |
2071 | #endif | |
2072 | WRITE_VREG(DOS_SW_RESET3, 0); | |
2073 | ||
2074 | ||
2075 | spin_lock_irqsave(&fb_core_spin_lock, flags); | |
2076 | codec_dmcbus_write(DMC_REQ_CTRL, | |
2077 | codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4)); | |
2078 | spin_unlock_irqrestore(&fb_core_spin_lock, flags); | |
2079 | ||
2080 | } | |
2081 | #endif | |
2082 | ||
fe96802b NQ |
2083 | #endif |
2084 | ||
a6c89e96 | 2085 | |
fe96802b NQ |
2086 | static int get_free_fb(struct VP9Decoder_s *pbi) |
2087 | { | |
2088 | struct VP9_Common_s *const cm = &pbi->common; | |
2089 | struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; | |
2090 | int i; | |
2091 | unsigned long flags; | |
2092 | ||
2093 | lock_buffer_pool(cm->buffer_pool, flags); | |
2094 | if (debug & VP9_DEBUG_BUFMGR_MORE) { | |
2095 | for (i = 0; i < pbi->used_buf_num; ++i) { | |
2096 | pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n", | |
2097 | __func__, i, frame_bufs[i].ref_count, | |
2098 | frame_bufs[i].buf.vf_ref, | |
2099 | frame_bufs[i].buf.index); | |
2100 | } | |
2101 | } | |
2102 | for (i = 0; i < pbi->used_buf_num; ++i) { | |
2103 | if ((frame_bufs[i].ref_count == 0) && | |
2104 | (frame_bufs[i].buf.vf_ref == 0) && | |
2105 | (frame_bufs[i].buf.index != -1) | |
2106 | ) | |
2107 | break; | |
2108 | } | |
2109 | if (i != pbi->used_buf_num) { | |
2110 | frame_bufs[i].ref_count = 1; | |
2111 | /*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n", | |
2112 | i, frame_bufs[i].ref_count);*/ | |
2113 | } else { | |
2114 | /* Reset i to be INVALID_IDX to indicate | |
2115 | no free buffer found*/ | |
2116 | i = INVALID_IDX; | |
2117 | } | |
2118 | ||
2119 | unlock_buffer_pool(cm->buffer_pool, flags); | |
2120 | return i; | |
2121 | } | |
2122 | ||
2123 | static int get_free_buf_count(struct VP9Decoder_s *pbi) | |
2124 | { | |
2125 | struct VP9_Common_s *const cm = &pbi->common; | |
2126 | struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; | |
2127 | int i; | |
2128 | int free_buf_count = 0; | |
2129 | for (i = 0; i < pbi->used_buf_num; ++i) | |
2130 | if ((frame_bufs[i].ref_count == 0) && | |
2131 | (frame_bufs[i].buf.vf_ref == 0) && | |
2132 | (frame_bufs[i].buf.index != -1) | |
2133 | ) | |
2134 | free_buf_count++; | |
2135 | return free_buf_count; | |
2136 | } | |
2137 | ||
b9164398 NQ |
2138 | static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs, |
2139 | struct BufferPool_s *const pool) | |
2140 | { | |
2141 | if (idx >= 0) { | |
2142 | --frame_bufs[idx].ref_count; | |
2143 | /*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx, | |
e0614bf7 ZZ |
2144 | * frame_bufs[idx].ref_count); |
2145 | */ | |
b9164398 | 2146 | /*A worker may only get a free framebuffer index when |
e0614bf7 ZZ |
2147 | *calling get_free_fb. But the private buffer is not set up |
2148 | *until finish decoding header. So any error happens during | |
2149 | *decoding header, the frame_bufs will not have valid priv | |
2150 | *buffer. | |
2151 | */ | |
b9164398 NQ |
2152 | |
2153 | if (frame_bufs[idx].ref_count == 0 && | |
2154 | frame_bufs[idx].raw_frame_buffer.priv) | |
2155 | vp9_release_frame_buffer | |
2156 | (&frame_bufs[idx].raw_frame_buffer); | |
2157 | } | |
2158 | } | |
2159 | ||
2160 | static void generate_next_ref_frames(struct VP9Decoder_s *pbi) | |
2161 | { | |
2162 | struct VP9_Common_s *const cm = &pbi->common; | |
2163 | struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; | |
2164 | struct BufferPool_s *const pool = cm->buffer_pool; | |
2165 | int mask, ref_index = 0; | |
fe96802b | 2166 | unsigned long flags; |
b9164398 NQ |
2167 | |
2168 | /* Generate next_ref_frame_map.*/ | |
fe96802b | 2169 | lock_buffer_pool(pool, flags); |
b9164398 NQ |
2170 | for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) { |
2171 | if (mask & 1) { | |
2172 | cm->next_ref_frame_map[ref_index] = cm->new_fb_idx; | |
2173 | ++frame_bufs[cm->new_fb_idx].ref_count; | |
2174 | /*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n", | |
e0614bf7 ZZ |
2175 | *cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count); |
2176 | */ | |
b9164398 NQ |
2177 | } else |
2178 | cm->next_ref_frame_map[ref_index] = | |
2179 | cm->ref_frame_map[ref_index]; | |
2180 | /* Current thread holds the reference frame.*/ | |
2181 | if (cm->ref_frame_map[ref_index] >= 0) { | |
2182 | ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count; | |
2183 | /*pr_info | |
e0614bf7 ZZ |
2184 | *("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n", |
2185 | *cm->ref_frame_map[ref_index], | |
2186 | *frame_bufs[cm->ref_frame_map[ref_index]].ref_count); | |
2187 | */ | |
b9164398 NQ |
2188 | } |
2189 | ++ref_index; | |
2190 | } | |
2191 | ||
2192 | for (; ref_index < REF_FRAMES; ++ref_index) { | |
2193 | cm->next_ref_frame_map[ref_index] = | |
2194 | cm->ref_frame_map[ref_index]; | |
2195 | /* Current thread holds the reference frame.*/ | |
2196 | if (cm->ref_frame_map[ref_index] >= 0) { | |
2197 | ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count; | |
2198 | /*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n", | |
e0614bf7 ZZ |
2199 | *cm->ref_frame_map[ref_index], |
2200 | *frame_bufs[cm->ref_frame_map[ref_index]].ref_count); | |
2201 | */ | |
b9164398 NQ |
2202 | } |
2203 | } | |
fe96802b | 2204 | unlock_buffer_pool(pool, flags); |
b9164398 NQ |
2205 | return; |
2206 | } | |
2207 | ||
2208 | static void refresh_ref_frames(struct VP9Decoder_s *pbi) | |
2209 | ||
2210 | { | |
2211 | struct VP9_Common_s *const cm = &pbi->common; | |
2212 | struct BufferPool_s *pool = cm->buffer_pool; | |
2213 | struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; | |
2214 | int mask, ref_index = 0; | |
fe96802b | 2215 | unsigned long flags; |
b9164398 | 2216 | |
fe96802b | 2217 | lock_buffer_pool(pool, flags); |
b9164398 NQ |
2218 | for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) { |
2219 | const int old_idx = cm->ref_frame_map[ref_index]; | |
2220 | /*Current thread releases the holding of reference frame.*/ | |
2221 | decrease_ref_count(old_idx, frame_bufs, pool); | |
2222 | ||
2223 | /*Release the reference frame in reference map.*/ | |
2224 | if ((mask & 1) && old_idx >= 0) | |
2225 | decrease_ref_count(old_idx, frame_bufs, pool); | |
2226 | cm->ref_frame_map[ref_index] = | |
2227 | cm->next_ref_frame_map[ref_index]; | |
2228 | ++ref_index; | |
2229 | } | |
2230 | ||
2231 | /*Current thread releases the holding of reference frame.*/ | |
2232 | for (; ref_index < REF_FRAMES && !cm->show_existing_frame; | |
2233 | ++ref_index) { | |
2234 | const int old_idx = cm->ref_frame_map[ref_index]; | |
e0614bf7 | 2235 | |
b9164398 NQ |
2236 | decrease_ref_count(old_idx, frame_bufs, pool); |
2237 | cm->ref_frame_map[ref_index] = | |
2238 | cm->next_ref_frame_map[ref_index]; | |
2239 | } | |
fe96802b | 2240 | unlock_buffer_pool(pool, flags); |
b9164398 NQ |
2241 | return; |
2242 | } | |
b7706e1e | 2243 | |
b9164398 NQ |
2244 | int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params) |
2245 | { | |
2246 | struct VP9_Common_s *const cm = &pbi->common; | |
2247 | struct BufferPool_s *pool = cm->buffer_pool; | |
2248 | struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; | |
2249 | int i; | |
2250 | int ret; | |
2251 | ||
2252 | pbi->ready_for_new_data = 0; | |
2253 | ||
2254 | if (pbi->has_keyframe == 0 && | |
2255 | params->p.frame_type != KEY_FRAME){ | |
2256 | on_no_keyframe_skiped++; | |
2257 | return -2; | |
2258 | } | |
2259 | pbi->has_keyframe = 1; | |
2260 | on_no_keyframe_skiped = 0; | |
b7706e1e | 2261 | #if 0 |
2262 | if (pbi->mmu_enable) { | |
2263 | if (!pbi->m_ins_flag) | |
2264 | pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); | |
2265 | if (cm->prev_fb_idx >= 0) { | |
2266 | decoder_mmu_box_free_idx_tail(pbi->mmu_box, | |
2267 | cm->prev_fb_idx, pbi->used_4k_num); | |
2268 | } | |
a6c89e96 NQ |
2269 | } |
2270 | #endif | |
b9164398 NQ |
2271 | if (cm->new_fb_idx >= 0 |
2272 | && frame_bufs[cm->new_fb_idx].ref_count == 0){ | |
2273 | vp9_release_frame_buffer | |
2274 | (&frame_bufs[cm->new_fb_idx].raw_frame_buffer); | |
2275 | } | |
2276 | /*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n", | |
2277 | cm->prev_fb_idx, cm->new_fb_idx);*/ | |
fe96802b NQ |
2278 | #ifndef MV_USE_FIXED_BUF |
2279 | put_un_used_mv_bufs(pbi); | |
2280 | if (debug & VP9_DEBUG_BUFMGR_DETAIL) | |
2281 | dump_pic_list(pbi); | |
2282 | #endif | |
2283 | cm->new_fb_idx = get_free_fb(pbi); | |
b9164398 NQ |
2284 | if (cm->new_fb_idx == INVALID_IDX) { |
2285 | pr_info("get_free_fb error\r\n"); | |
2286 | return -1; | |
2287 | } | |
fe96802b | 2288 | #ifndef MV_USE_FIXED_BUF |
a6c89e96 NQ |
2289 | #ifdef SUPPORT_FB_DECODING |
2290 | if (pbi->used_stage_buf_num == 0) { | |
2291 | #endif | |
2292 | if (get_mv_buf(pbi, | |
2293 | &pool->frame_bufs[cm->new_fb_idx]. | |
2294 | buf.mv_buf_index, | |
2295 | &pool->frame_bufs[cm->new_fb_idx]. | |
2296 | buf.mpred_mv_wr_start_addr | |
2297 | ) < 0) { | |
2298 | pr_info("get_mv_buf fail\r\n"); | |
2299 | return -1; | |
2300 | } | |
2301 | if (debug & VP9_DEBUG_BUFMGR_DETAIL) | |
2302 | dump_pic_list(pbi); | |
2303 | #ifdef SUPPORT_FB_DECODING | |
fe96802b | 2304 | } |
a6c89e96 | 2305 | #endif |
fe96802b NQ |
2306 | #endif |
2307 | cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx]; | |
2308 | /*if (debug & VP9_DEBUG_BUFMGR) | |
2309 | pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__, | |
2310 | cm->new_fb_idx);*/ | |
2311 | ||
b9164398 | 2312 | pbi->cur_buf = &frame_bufs[cm->new_fb_idx]; |
b7706e1e | 2313 | if (pbi->mmu_enable) { |
2314 | /* moved to after picture size ready | |
2315 | *alloc_mmu(cm, params->p.width, params->p.height, | |
2316 | *params->p.bit_depth, pbi->frame_mmu_map_addr); | |
2317 | */ | |
2318 | cm->prev_fb_idx = cm->new_fb_idx; | |
2319 | } | |
b9164398 NQ |
2320 | /*read_uncompressed_header()*/ |
2321 | cm->last_frame_type = cm->frame_type; | |
2322 | cm->last_intra_only = cm->intra_only; | |
2323 | cm->profile = params->p.profile; | |
2324 | if (cm->profile >= MAX_PROFILES) { | |
2325 | pr_err("Error: Unsupported profile %d\r\n", cm->profile); | |
2326 | return -1; | |
2327 | } | |
2328 | cm->show_existing_frame = params->p.show_existing_frame; | |
2329 | if (cm->show_existing_frame) { | |
2330 | /* Show an existing frame directly.*/ | |
2331 | int frame_to_show_idx = params->p.frame_to_show_idx; | |
2332 | int frame_to_show; | |
fe96802b | 2333 | unsigned long flags; |
b9164398 NQ |
2334 | if (frame_to_show_idx >= REF_FRAMES) { |
2335 | pr_info("frame_to_show_idx %d exceed max index\r\n", | |
2336 | frame_to_show_idx); | |
2337 | return -1; | |
2338 | } | |
2339 | ||
2340 | frame_to_show = cm->ref_frame_map[frame_to_show_idx]; | |
2341 | /*pr_info("frame_to_show %d\r\n", frame_to_show);*/ | |
fe96802b | 2342 | lock_buffer_pool(pool, flags); |
b9164398 NQ |
2343 | if (frame_to_show < 0 || |
2344 | frame_bufs[frame_to_show].ref_count < 1) { | |
fe96802b | 2345 | unlock_buffer_pool(pool, flags); |
b9164398 NQ |
2346 | pr_err |
2347 | ("Error:Buffer %d does not contain a decoded frame", | |
2348 | frame_to_show); | |
2349 | return -1; | |
2350 | } | |
2351 | ||
2352 | ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show); | |
fe96802b | 2353 | unlock_buffer_pool(pool, flags); |
b9164398 NQ |
2354 | pbi->refresh_frame_flags = 0; |
2355 | /*cm->lf.filter_level = 0;*/ | |
2356 | cm->show_frame = 1; | |
2357 | ||
2358 | /* | |
e0614bf7 ZZ |
2359 | *if (pbi->frame_parallel_decode) { |
2360 | * for (i = 0; i < REF_FRAMES; ++i) | |
2361 | * cm->next_ref_frame_map[i] = | |
2362 | * cm->ref_frame_map[i]; | |
2363 | *} | |
2364 | */ | |
b9164398 NQ |
2365 | /* do not decode, search next start code */ |
2366 | return 1; | |
2367 | } | |
2368 | cm->frame_type = params->p.frame_type; | |
2369 | cm->show_frame = params->p.show_frame; | |
2370 | cm->error_resilient_mode = params->p.error_resilient_mode; | |
2371 | ||
2372 | ||
2373 | if (cm->frame_type == KEY_FRAME) { | |
2374 | pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1; | |
2375 | ||
2376 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
2377 | cm->frame_refs[i].idx = INVALID_IDX; | |
2378 | cm->frame_refs[i].buf = NULL; | |
2379 | } | |
2380 | ||
2381 | ret = setup_frame_size(pbi, | |
2382 | cm, params, pbi->frame_mmu_map_addr, | |
2383 | print_header_info); | |
2384 | if (ret) | |
2385 | return -1; | |
2386 | if (pbi->need_resync) { | |
2387 | memset(&cm->ref_frame_map, -1, | |
2388 | sizeof(cm->ref_frame_map)); | |
2389 | pbi->need_resync = 0; | |
2390 | } | |
2391 | } else { | |
2392 | cm->intra_only = cm->show_frame ? 0 : params->p.intra_only; | |
2393 | /*if (print_header_info) { | |
e0614bf7 ZZ |
2394 | * if (cm->show_frame) |
2395 | * pr_info | |
2396 | * ("intra_only set to 0 because of show_frame\n"); | |
2397 | * else | |
2398 | * pr_info | |
2399 | * ("1-bit intra_only read: %d\n", cm->intra_only); | |
2400 | *} | |
2401 | */ | |
b9164398 NQ |
2402 | |
2403 | ||
2404 | cm->reset_frame_context = cm->error_resilient_mode ? | |
2405 | 0 : params->p.reset_frame_context; | |
2406 | if (print_header_info) { | |
2407 | if (cm->error_resilient_mode) | |
2408 | pr_info | |
2409 | ("reset to 0 error_resilient_mode\n"); | |
2410 | else | |
2411 | pr_info | |
2412 | (" * 2-bits reset_frame_context read : %d\n", | |
2413 | cm->reset_frame_context); | |
2414 | } | |
2415 | ||
2416 | if (cm->intra_only) { | |
2417 | if (cm->profile > PROFILE_0) { | |
2418 | /*read_bitdepth_colorspace_sampling(cm, | |
e0614bf7 ZZ |
2419 | * rb, print_header_info); |
2420 | */ | |
b9164398 NQ |
2421 | } else { |
2422 | /*NOTE: The intra-only frame header | |
e0614bf7 ZZ |
2423 | *does not include the specification |
2424 | *of either the color format or | |
2425 | *color sub-sampling | |
2426 | *in profile 0. VP9 specifies that the default | |
2427 | *color format should be YUV 4:2:0 in this | |
2428 | *case (normative). | |
2429 | */ | |
b9164398 NQ |
2430 | cm->color_space = VPX_CS_BT_601; |
2431 | cm->subsampling_y = cm->subsampling_x = 1; | |
2432 | cm->bit_depth = VPX_BITS_8; | |
2433 | cm->use_highbitdepth = 0; | |
2434 | } | |
2435 | ||
2436 | pbi->refresh_frame_flags = | |
2437 | params->p.refresh_frame_flags; | |
2438 | /*if (print_header_info) | |
e0614bf7 ZZ |
2439 | * pr_info("*%d-bits refresh_frame read:0x%x\n", |
2440 | * REF_FRAMES, pbi->refresh_frame_flags); | |
2441 | */ | |
b9164398 NQ |
2442 | ret = setup_frame_size(pbi, |
2443 | cm, | |
2444 | params, | |
2445 | pbi->frame_mmu_map_addr, | |
2446 | print_header_info); | |
e0614bf7 | 2447 | if (ret) |
b9164398 | 2448 | return -1; |
b9164398 NQ |
2449 | if (pbi->need_resync) { |
2450 | memset(&cm->ref_frame_map, -1, | |
2451 | sizeof(cm->ref_frame_map)); | |
2452 | pbi->need_resync = 0; | |
2453 | } | |
2454 | } else if (pbi->need_resync != 1) { /* Skip if need resync */ | |
e0614bf7 ZZ |
2455 | pbi->refresh_frame_flags = |
2456 | params->p.refresh_frame_flags; | |
2457 | if (print_header_info) | |
2458 | pr_info | |
2459 | ("*%d-bits refresh_frame read:0x%x\n", | |
2460 | REF_FRAMES, pbi->refresh_frame_flags); | |
2461 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
2462 | const int ref = | |
2463 | (params->p.ref_info >> | |
2464 | (((REFS_PER_FRAME-i-1)*4)+1)) | |
2465 | & 0x7; | |
2466 | const int idx = | |
2467 | cm->ref_frame_map[ref]; | |
2468 | struct RefBuffer_s * const ref_frame = | |
2469 | &cm->frame_refs[i]; | |
b9164398 | 2470 | if (print_header_info) |
e0614bf7 | 2471 | pr_info("*%d-bits ref[%d]read:%d\n", |
b9164398 | 2472 | REF_FRAMES_LOG2, i, ref); |
e0614bf7 ZZ |
2473 | ref_frame->idx = idx; |
2474 | ref_frame->buf = &frame_bufs[idx].buf; | |
2475 | cm->ref_frame_sign_bias[LAST_FRAME + i] | |
2476 | = (params->p.ref_info >> | |
2477 | ((REFS_PER_FRAME-i-1)*4)) & 0x1; | |
2478 | if (print_header_info) | |
2479 | pr_info("1bit ref_frame_sign_bias"); | |
2480 | /*pr_info | |
2481 | *("%dread: %d\n", | |
2482 | *LAST_FRAME+i, | |
2483 | *cm->ref_frame_sign_bias | |
2484 | *[LAST_FRAME + i]); | |
2485 | */ | |
2486 | /*pr_info | |
2487 | *("[VP9 DEBUG]%s(get ref):%d\r\n", | |
2488 | *__func__, ref_frame->idx); | |
2489 | */ | |
b9164398 | 2490 | |
e0614bf7 | 2491 | } |
b9164398 | 2492 | |
e0614bf7 ZZ |
2493 | ret = setup_frame_size_with_refs( |
2494 | pbi, | |
2495 | cm, | |
2496 | params, | |
2497 | pbi->frame_mmu_map_addr, | |
2498 | print_header_info); | |
2499 | if (ret) | |
2500 | return -1; | |
2501 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
2502 | /*struct RefBuffer_s *const ref_buf = | |
2503 | *&cm->frame_refs[i]; | |
2504 | */ | |
2505 | /* to do: | |
2506 | *vp9_setup_scale_factors_for_frame | |
2507 | */ | |
2508 | } | |
b9164398 NQ |
2509 | } |
2510 | } | |
2511 | ||
2512 | get_frame_new_buffer(cm)->bit_depth = cm->bit_depth; | |
2513 | get_frame_new_buffer(cm)->color_space = cm->color_space; | |
2514 | get_frame_new_buffer(cm)->slice_type = cm->frame_type; | |
2515 | ||
fe96802b | 2516 | if (pbi->need_resync) { |
b9164398 NQ |
2517 | pr_err |
2518 | ("Error: Keyframe/intra-only frame required to reset\r\n"); | |
fe96802b NQ |
2519 | return -1; |
2520 | } | |
b9164398 NQ |
2521 | generate_next_ref_frames(pbi); |
2522 | pbi->hold_ref_buf = 1; | |
2523 | ||
2524 | #if 0 | |
2525 | if (frame_is_intra_only(cm) || cm->error_resilient_mode) | |
2526 | vp9_setup_past_independence(cm); | |
2527 | setup_loopfilter(&cm->lf, rb, print_header_info); | |
2528 | setup_quantization(cm, &pbi->mb, rb, print_header_info); | |
2529 | setup_segmentation(&cm->seg, rb, print_header_info); | |
2530 | setup_segmentation_dequant(cm, print_header_info); | |
2531 | ||
2532 | setup_tile_info(cm, rb, print_header_info); | |
2533 | sz = vp9_rb_read_literal(rb, 16); | |
2534 | if (print_header_info) | |
2535 | pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz); | |
2536 | ||
2537 | if (sz == 0) | |
2538 | vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME, | |
2539 | "Invalid header size"); | |
2540 | #endif | |
2541 | /*end read_uncompressed_header()*/ | |
2542 | cm->use_prev_frame_mvs = !cm->error_resilient_mode && | |
2543 | cm->width == cm->last_width && | |
2544 | cm->height == cm->last_height && | |
2545 | !cm->last_intra_only && | |
2546 | cm->last_show_frame && | |
2547 | (cm->last_frame_type != KEY_FRAME); | |
2548 | ||
2549 | /*pr_info | |
e0614bf7 ZZ |
2550 | *("set use_prev_frame_mvs to %d (last_width %d last_height %d", |
2551 | *cm->use_prev_frame_mvs, cm->last_width, cm->last_height); | |
2552 | *pr_info | |
2553 | *(" last_intra_only %d last_show_frame %d last_frame_type %d)\n", | |
2554 | *cm->last_intra_only, cm->last_show_frame, cm->last_frame_type); | |
2555 | */ | |
b9164398 NQ |
2556 | return 0; |
2557 | } | |
2558 | ||
2559 | ||
2560 | void swap_frame_buffers(struct VP9Decoder_s *pbi) | |
2561 | { | |
2562 | int ref_index = 0; | |
2563 | struct VP9_Common_s *const cm = &pbi->common; | |
2564 | struct BufferPool_s *const pool = cm->buffer_pool; | |
2565 | struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; | |
fe96802b | 2566 | unsigned long flags; |
b9164398 NQ |
2567 | refresh_ref_frames(pbi); |
2568 | pbi->hold_ref_buf = 0; | |
2569 | cm->frame_to_show = get_frame_new_buffer(cm); | |
2570 | ||
2571 | /*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/ | |
fe96802b | 2572 | lock_buffer_pool(pool, flags); |
b9164398 NQ |
2573 | --frame_bufs[cm->new_fb_idx].ref_count; |
2574 | /*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx, | |
e0614bf7 ZZ |
2575 | * frame_bufs[cm->new_fb_idx].ref_count); |
2576 | */ | |
fe96802b | 2577 | unlock_buffer_pool(pool, flags); |
b9164398 NQ |
2578 | /*}*/ |
2579 | ||
2580 | /*Invalidate these references until the next frame starts.*/ | |
2581 | for (ref_index = 0; ref_index < 3; ref_index++) | |
2582 | cm->frame_refs[ref_index].idx = -1; | |
2583 | } | |
2584 | ||
2585 | #if 0 | |
2586 | static void check_resync(vpx_codec_alg_priv_t *const ctx, | |
2587 | const struct VP9Decoder_s *const pbi) | |
2588 | { | |
2589 | /* Clear resync flag if worker got a key frame or intra only frame.*/ | |
2590 | if (ctx->need_resync == 1 && pbi->need_resync == 0 && | |
2591 | (pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME)) | |
2592 | ctx->need_resync = 0; | |
2593 | } | |
2594 | #endif | |
2595 | ||
2596 | int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd) | |
2597 | { | |
2598 | struct VP9_Common_s *const cm = &pbi->common; | |
2599 | int ret = -1; | |
2600 | ||
2601 | if (pbi->ready_for_new_data == 1) | |
2602 | return ret; | |
2603 | ||
2604 | pbi->ready_for_new_data = 1; | |
2605 | ||
2606 | /* no raw frame to show!!! */ | |
2607 | if (!cm->show_frame) | |
2608 | return ret; | |
2609 | ||
2610 | pbi->ready_for_new_data = 1; | |
2611 | ||
2612 | *sd = *cm->frame_to_show; | |
2613 | ret = 0; | |
2614 | ||
2615 | return ret; | |
2616 | } | |
2617 | ||
2618 | int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i, | |
2619 | struct buff_s *mc_buf_i) { | |
2620 | struct VP9_Common_s *cm = &pbi->common; | |
2621 | ||
a674e3cd | 2622 | /*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/ |
b9164398 NQ |
2623 | pbi->frame_count = 0; |
2624 | pbi->pic_count = 0; | |
2625 | pbi->pre_stream_offset = 0; | |
2626 | cm->buffer_pool = &pbi->vp9_buffer_pool; | |
2627 | spin_lock_init(&cm->buffer_pool->lock); | |
2628 | cm->prev_fb_idx = INVALID_IDX; | |
2629 | cm->new_fb_idx = INVALID_IDX; | |
fe96802b NQ |
2630 | pbi->used_4k_num = -1; |
2631 | cm->cur_fb_idx_mmu = INVALID_IDX; | |
5b851ff9 | 2632 | pr_debug |
b9164398 NQ |
2633 | ("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n", |
2634 | cm->prev_fb_idx, cm->new_fb_idx); | |
2635 | pbi->need_resync = 1; | |
2636 | /* Initialize the references to not point to any frame buffers.*/ | |
2637 | memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map)); | |
2638 | memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map)); | |
2639 | cm->current_video_frame = 0; | |
2640 | pbi->ready_for_new_data = 1; | |
2641 | ||
2642 | /* private init */ | |
2643 | pbi->work_space_buf = buf_spec_i; | |
b7706e1e | 2644 | if (!pbi->mmu_enable) |
2645 | pbi->mc_buf = mc_buf_i; | |
2646 | ||
b9164398 NQ |
2647 | pbi->rpm_addr = NULL; |
2648 | pbi->lmem_addr = NULL; | |
2649 | ||
2650 | pbi->use_cma_flag = 0; | |
2651 | pbi->decode_idx = 0; | |
2652 | pbi->slice_idx = 0; | |
2653 | /*int m_uiMaxCUWidth = 1<<7;*/ | |
2654 | /*int m_uiMaxCUHeight = 1<<7;*/ | |
2655 | pbi->has_keyframe = 0; | |
2656 | pbi->skip_flag = 0; | |
2657 | pbi->wait_buf = 0; | |
2658 | pbi->error_flag = 0; | |
2659 | ||
2660 | pbi->pts_mode = PTS_NORMAL; | |
2661 | pbi->last_pts = 0; | |
2662 | pbi->last_lookup_pts = 0; | |
2663 | pbi->last_pts_us64 = 0; | |
2664 | pbi->last_lookup_pts_us64 = 0; | |
2665 | pbi->shift_byte_count = 0; | |
2666 | pbi->shift_byte_count_lo = 0; | |
2667 | pbi->shift_byte_count_hi = 0; | |
2668 | pbi->pts_mode_switching_count = 0; | |
2669 | pbi->pts_mode_recovery_count = 0; | |
2670 | ||
2671 | pbi->buf_num = 0; | |
2672 | pbi->pic_num = 0; | |
2673 | ||
2674 | return 0; | |
2675 | } | |
2676 | ||
2677 | ||
2678 | int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi) | |
2679 | { | |
2680 | struct VP9_Common_s *cm = &pbi->common; | |
2681 | struct PIC_BUFFER_CONFIG_s sd; | |
e0614bf7 | 2682 | |
187af067 | 2683 | if (pbi->postproc_done) |
2684 | return 0; | |
2685 | pbi->postproc_done = 1; | |
b9164398 NQ |
2686 | swap_frame_buffers(pbi); |
2687 | if (!cm->show_existing_frame) { | |
2688 | cm->last_show_frame = cm->show_frame; | |
2689 | cm->prev_frame = cm->cur_frame; | |
2690 | #if 0 | |
2691 | if (cm->seg.enabled && !pbi->frame_parallel_decode) | |
2692 | vp9_swap_current_and_last_seg_map(cm); | |
2693 | #endif | |
2694 | } | |
2695 | cm->last_width = cm->width; | |
2696 | cm->last_height = cm->height; | |
2697 | if (cm->show_frame) | |
2698 | cm->current_video_frame++; | |
2699 | ||
2700 | if (vp9_get_raw_frame(pbi, &sd) == 0) { | |
2701 | /*pr_info("Display frame index %d\r\n", sd.index);*/ | |
2702 | sd.stream_offset = pbi->pre_stream_offset; | |
2703 | prepare_display_buf(pbi, &sd); | |
2704 | pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT); | |
e0614bf7 ZZ |
2705 | } |
2706 | ||
2707 | /* else | |
2708 | * pr_info | |
2709 | * ("Not display this frame,ready_for_new_data%d show_frame%d\r\n", | |
2710 | * pbi->ready_for_new_data, cm->show_frame); | |
2711 | */ | |
b9164398 NQ |
2712 | return 0; |
2713 | } | |
2714 | ||
2715 | struct VP9Decoder_s vp9_decoder; | |
2716 | union param_u vp9_param; | |
2717 | ||
2718 | /************************************************** | |
e0614bf7 ZZ |
2719 | * |
2720 | *VP9 buffer management end | |
2721 | * | |
2722 | *************************************************** | |
2723 | */ | |
b9164398 NQ |
2724 | |
2725 | ||
2726 | #define HEVC_CM_BODY_START_ADDR 0x3626 | |
2727 | #define HEVC_CM_BODY_LENGTH 0x3627 | |
2728 | #define HEVC_CM_HEADER_LENGTH 0x3629 | |
2729 | #define HEVC_CM_HEADER_OFFSET 0x362b | |
2730 | ||
2731 | #define LOSLESS_COMPRESS_MODE | |
b9164398 NQ |
2732 | |
2733 | /*#define DECOMP_HEADR_SURGENT*/ | |
3a5df697 | 2734 | #ifdef VP9_10B_NV21 |
2735 | static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/ | |
2736 | #else | |
b9164398 | 2737 | static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */ |
3a5df697 | 2738 | #endif |
b9164398 NQ |
2739 | static u32 enable_mem_saving = 1; |
2740 | static u32 force_w_h; | |
2741 | ||
2742 | static u32 force_fps; | |
2743 | ||
2744 | ||
2745 | const u32 vp9_version = 201602101; | |
2746 | static u32 debug; | |
2747 | static u32 radr; | |
2748 | static u32 rval; | |
2749 | static u32 pop_shorts; | |
2750 | static u32 dbg_cmd; | |
2751 | static u32 dbg_skip_decode_index; | |
2752 | static u32 endian = 0xff0; | |
2753 | #ifdef ERROR_HANDLE_DEBUG | |
2754 | static u32 dbg_nal_skip_flag; | |
2755 | /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */ | |
2756 | static u32 dbg_nal_skip_count; | |
2757 | #endif | |
2758 | /*for debug*/ | |
b9164398 NQ |
2759 | static u32 decode_pic_begin; |
2760 | static uint slice_parse_begin; | |
2761 | static u32 step; | |
2762 | #ifdef MIX_STREAM_SUPPORT | |
b9164398 NQ |
2763 | static u32 buf_alloc_width = 4096; |
2764 | static u32 buf_alloc_height = 2304; | |
a6c89e96 NQ |
2765 | static u32 vp9_max_pic_w = 4096; |
2766 | static u32 vp9_max_pic_h = 2304; | |
a6c89e96 | 2767 | |
b9164398 NQ |
2768 | static u32 dynamic_buf_num_margin; |
2769 | #else | |
2770 | static u32 buf_alloc_width; | |
2771 | static u32 buf_alloc_height; | |
2772 | static u32 dynamic_buf_num_margin = 7; | |
2773 | #endif | |
2774 | static u32 buf_alloc_depth = 10; | |
2775 | static u32 buf_alloc_size; | |
2776 | /* | |
e0614bf7 ZZ |
2777 | *bit[0]: 0, |
2778 | * bit[1]: 0, always release cma buffer when stop | |
2779 | * bit[1]: 1, never release cma buffer when stop | |
2780 | *bit[0]: 1, when stop, release cma buffer if blackout is 1; | |
2781 | *do not release cma buffer is blackout is not 1 | |
2782 | * | |
2783 | *bit[2]: 0, when start decoding, check current displayed buffer | |
2784 | * (only for buffer decoded by vp9) if blackout is 0 | |
2785 | * 1, do not check current displayed buffer | |
2786 | * | |
2787 | *bit[3]: 1, if blackout is not 1, do not release current | |
2788 | * displayed cma buffer always. | |
2789 | */ | |
b9164398 | 2790 | /* set to 1 for fast play; |
e0614bf7 ZZ |
2791 | * set to 8 for other case of "keep last frame" |
2792 | */ | |
b9164398 NQ |
2793 | static u32 buffer_mode = 1; |
2794 | /* buffer_mode_dbg: debug only*/ | |
2795 | static u32 buffer_mode_dbg = 0xffff0000; | |
2796 | /**/ | |
2797 | ||
2798 | /* | |
e0614bf7 ZZ |
2799 | *bit 0, 1: only display I picture; |
2800 | *bit 1, 1: only decode I picture; | |
2801 | */ | |
b9164398 NQ |
2802 | static u32 i_only_flag; |
2803 | ||
187af067 | 2804 | static u32 low_latency_flag; |
b9164398 | 2805 | |
0eb79ad7 RZ |
2806 | static u32 no_head; |
2807 | ||
b9164398 NQ |
2808 | static u32 max_decoding_time; |
2809 | /* | |
e0614bf7 ZZ |
2810 | *error handling |
2811 | */ | |
b9164398 | 2812 | /*error_handle_policy: |
e0614bf7 ZZ |
2813 | *bit 0: 0, auto skip error_skip_nal_count nals before error recovery; |
2814 | *1, skip error_skip_nal_count nals before error recovery; | |
2815 | *bit 1 (valid only when bit0 == 1): | |
2816 | *1, wait vps/sps/pps after error recovery; | |
2817 | *bit 2 (valid only when bit0 == 0): | |
2818 | *0, auto search after error recovery (vp9_recover() called); | |
2819 | *1, manual search after error recovery | |
2820 | *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2)) | |
2821 | * | |
2822 | *bit 4: 0, set error_mark after reset/recover | |
2823 | * 1, do not set error_mark after reset/recover | |
2824 | *bit 5: 0, check total lcu for every picture | |
2825 | * 1, do not check total lcu | |
2826 | * | |
2827 | */ | |
b9164398 NQ |
2828 | |
2829 | static u32 error_handle_policy; | |
2830 | /*static u32 parser_sei_enable = 1;*/ | |
dfe41deb RZ |
2831 | #define MAX_BUF_NUM_NORMAL 12 |
2832 | #define MAX_BUF_NUM_LESS 10 | |
2833 | static u32 max_buf_num = MAX_BUF_NUM_NORMAL; | |
2834 | #define MAX_BUF_NUM_SAVE_BUF 8 | |
b9164398 | 2835 | |
fe96802b | 2836 | static u32 run_ready_min_buf_num = 2; |
b9164398 | 2837 | |
a5c5bec0 | 2838 | |
b9164398 NQ |
2839 | static DEFINE_MUTEX(vvp9_mutex); |
2840 | #ifndef MULTI_INSTANCE_SUPPORT | |
2841 | static struct device *cma_dev; | |
2842 | #endif | |
2843 | ||
2844 | #define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0 | |
2845 | #define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1 | |
2846 | #define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2 | |
2847 | #define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3 | |
2848 | #define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4 | |
2849 | #define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5 | |
2850 | #define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6 | |
2851 | #define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7 | |
2852 | #define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8 | |
2853 | #define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9 | |
2854 | #define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A | |
2855 | #define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B | |
2856 | #define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D | |
2857 | #define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E | |
2858 | #define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F | |
2859 | #define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F | |
2860 | #define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L | |
2861 | #ifdef MULTI_INSTANCE_SUPPORT | |
2862 | #define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M | |
2863 | #define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N | |
2864 | #else | |
2865 | #define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M | |
2866 | #define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N | |
2867 | #endif | |
2868 | #define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G | |
2869 | #define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H | |
2870 | ||
2871 | ||
2872 | /* | |
e0614bf7 ZZ |
2873 | *ucode parser/search control |
2874 | *bit 0: 0, header auto parse; 1, header manual parse | |
2875 | *bit 1: 0, auto skip for noneseamless stream; 1, no skip | |
2876 | *bit [3:2]: valid when bit1==0; | |
2877 | *0, auto skip nal before first vps/sps/pps/idr; | |
2878 | *1, auto skip nal before first vps/sps/pps | |
2879 | *2, auto skip nal before first vps/sps/pps, | |
2880 | * and not decode until the first I slice (with slice address of 0) | |
2881 | * | |
2882 | *3, auto skip before first I slice (nal_type >=16 && nal_type<=21) | |
2883 | *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) ) | |
2884 | *bit [16]: for NAL_UNIT_EOS when bit0 is 0: | |
2885 | * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm | |
2886 | *bit [17]: for NAL_SEI when bit0 is 0: | |
2887 | * 0, do not parse SEI in ucode; 1, parse SEI in ucode | |
2888 | *bit [31:20]: used by ucode for debug purpose | |
2889 | */ | |
b9164398 | 2890 | #define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I |
a6c89e96 NQ |
2891 | /*[31:24] chip feature |
2892 | 31: 0, use MBOX1; 1, use MBOX0 | |
2893 | */ | |
b9164398 NQ |
2894 | #define DECODE_MODE HEVC_ASSIST_SCRATCH_J |
2895 | #define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K | |
2896 | ||
2897 | #ifdef MULTI_INSTANCE_SUPPORT | |
2898 | #define RPM_BUF_SIZE (0x400 * 2) | |
2899 | #else | |
2900 | #define RPM_BUF_SIZE (0x80*2) | |
2901 | #endif | |
2902 | #define LMEM_BUF_SIZE (0x400 * 2) | |
2903 | ||
df841122 | 2904 | #define WORK_BUF_SPEC_NUM 3 |
b9164398 NQ |
2905 | static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = { |
2906 | { | |
2907 | /* 8M bytes */ | |
2908 | .max_width = 1920, | |
2909 | .max_height = 1088, | |
2910 | .ipp = { | |
2911 | /* IPP work space calculation : | |
e0614bf7 ZZ |
2912 | * 4096 * (Y+CbCr+Flags) = 12k, round to 16k |
2913 | */ | |
b9164398 NQ |
2914 | .buf_size = 0x4000, |
2915 | }, | |
2916 | .sao_abv = { | |
2917 | .buf_size = 0x30000, | |
2918 | }, | |
2919 | .sao_vb = { | |
2920 | .buf_size = 0x30000, | |
2921 | }, | |
2922 | .short_term_rps = { | |
2923 | /* SHORT_TERM_RPS - Max 64 set, 16 entry every set, | |
e0614bf7 ZZ |
2924 | * total 64x16x2 = 2048 bytes (0x800) |
2925 | */ | |
b9164398 NQ |
2926 | .buf_size = 0x800, |
2927 | }, | |
2928 | .vps = { | |
2929 | /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
2930 | * total 0x0800 bytes |
2931 | */ | |
b9164398 NQ |
2932 | .buf_size = 0x800, |
2933 | }, | |
2934 | .sps = { | |
2935 | /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
2936 | * total 0x0800 bytes |
2937 | */ | |
b9164398 NQ |
2938 | .buf_size = 0x800, |
2939 | }, | |
2940 | .pps = { | |
2941 | /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
2942 | * total 0x2000 bytes |
2943 | */ | |
b9164398 NQ |
2944 | .buf_size = 0x2000, |
2945 | }, | |
2946 | .sao_up = { | |
2947 | /* SAO UP STORE AREA - Max 640(10240/16) LCU, | |
e0614bf7 ZZ |
2948 | * each has 16 bytes total 0x2800 bytes |
2949 | */ | |
b9164398 NQ |
2950 | .buf_size = 0x2800, |
2951 | }, | |
2952 | .swap_buf = { | |
2953 | /* 256cyclex64bit = 2K bytes 0x800 | |
e0614bf7 ZZ |
2954 | * (only 144 cycles valid) |
2955 | */ | |
b9164398 NQ |
2956 | .buf_size = 0x800, |
2957 | }, | |
2958 | .swap_buf2 = { | |
2959 | .buf_size = 0x800, | |
2960 | }, | |
2961 | .scalelut = { | |
2962 | /* support up to 32 SCALELUT 1024x32 = | |
e0614bf7 ZZ |
2963 | * 32Kbytes (0x8000) |
2964 | */ | |
b9164398 NQ |
2965 | .buf_size = 0x8000, |
2966 | }, | |
2967 | .dblk_para = { | |
2968 | /* DBLK -> Max 256(4096/16) LCU, | |
e0614bf7 ZZ |
2969 | *each para 1024bytes(total:0x40000), |
2970 | *data 1024bytes(total:0x40000) | |
2971 | */ | |
b9164398 NQ |
2972 | .buf_size = 0x80000, |
2973 | }, | |
2974 | .dblk_data = { | |
2975 | .buf_size = 0x80000, | |
2976 | }, | |
2977 | .seg_map = { | |
2978 | /*4096x2304/64/64 *24 = 0xd800 Bytes*/ | |
2979 | .buf_size = 0xd800, | |
2980 | }, | |
b9164398 NQ |
2981 | .mmu_vbh = { |
2982 | .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/ | |
2983 | }, | |
fe96802b | 2984 | #if 0 |
b9164398 NQ |
2985 | .cm_header = { |
2986 | /*add one for keeper.*/ | |
2987 | .buf_size = MMU_COMPRESS_HEADER_SIZE * | |
2988 | (FRAME_BUFFERS + 1), | |
2989 | /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */ | |
2990 | }, | |
2991 | #endif | |
2992 | .mpred_above = { | |
2993 | .buf_size = 0x10000, /* 2 * size of hevc*/ | |
2994 | }, | |
fe96802b | 2995 | #ifdef MV_USE_FIXED_BUF |
b9164398 NQ |
2996 | .mpred_mv = {/* 1080p, 0x40000 per buffer */ |
2997 | .buf_size = 0x40000 * FRAME_BUFFERS, | |
2998 | }, | |
fe96802b | 2999 | #endif |
b9164398 NQ |
3000 | .rpm = { |
3001 | .buf_size = RPM_BUF_SIZE, | |
3002 | }, | |
3003 | .lmem = { | |
3004 | .buf_size = 0x400 * 2, | |
3005 | } | |
3006 | }, | |
3007 | { | |
3008 | .max_width = 4096, | |
3009 | .max_height = 2304, | |
3010 | .ipp = { | |
3011 | /* IPP work space calculation : | |
e0614bf7 ZZ |
3012 | * 4096 * (Y+CbCr+Flags) = 12k, round to 16k |
3013 | */ | |
b9164398 NQ |
3014 | .buf_size = 0x4000, |
3015 | }, | |
3016 | .sao_abv = { | |
3017 | .buf_size = 0x30000, | |
3018 | }, | |
3019 | .sao_vb = { | |
3020 | .buf_size = 0x30000, | |
3021 | }, | |
3022 | .short_term_rps = { | |
3023 | /* SHORT_TERM_RPS - Max 64 set, 16 entry every set, | |
e0614bf7 ZZ |
3024 | * total 64x16x2 = 2048 bytes (0x800) |
3025 | */ | |
b9164398 NQ |
3026 | .buf_size = 0x800, |
3027 | }, | |
3028 | .vps = { | |
3029 | /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
3030 | * total 0x0800 bytes |
3031 | */ | |
b9164398 NQ |
3032 | .buf_size = 0x800, |
3033 | }, | |
3034 | .sps = { | |
3035 | /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
3036 | * total 0x0800 bytes |
3037 | */ | |
b9164398 NQ |
3038 | .buf_size = 0x800, |
3039 | }, | |
3040 | .pps = { | |
3041 | /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
3042 | * total 0x2000 bytes |
3043 | */ | |
b9164398 NQ |
3044 | .buf_size = 0x2000, |
3045 | }, | |
3046 | .sao_up = { | |
3047 | /* SAO UP STORE AREA - Max 640(10240/16) LCU, | |
e0614bf7 ZZ |
3048 | * each has 16 bytes total 0x2800 bytes |
3049 | */ | |
b9164398 NQ |
3050 | .buf_size = 0x2800, |
3051 | }, | |
3052 | .swap_buf = { | |
3053 | /* 256cyclex64bit = 2K bytes 0x800 | |
e0614bf7 ZZ |
3054 | * (only 144 cycles valid) |
3055 | */ | |
b9164398 NQ |
3056 | .buf_size = 0x800, |
3057 | }, | |
3058 | .swap_buf2 = { | |
3059 | .buf_size = 0x800, | |
3060 | }, | |
3061 | .scalelut = { | |
3062 | /* support up to 32 SCALELUT 1024x32 = 32Kbytes | |
e0614bf7 ZZ |
3063 | * (0x8000) |
3064 | */ | |
b9164398 NQ |
3065 | .buf_size = 0x8000, |
3066 | }, | |
3067 | .dblk_para = { | |
3068 | /* DBLK -> Max 256(4096/16) LCU, | |
e0614bf7 ZZ |
3069 | *each para 1024bytes(total:0x40000), |
3070 | *data 1024bytes(total:0x40000) | |
3071 | */ | |
b9164398 NQ |
3072 | .buf_size = 0x80000, |
3073 | }, | |
3074 | .dblk_data = { | |
3075 | .buf_size = 0x80000, | |
3076 | }, | |
3077 | .seg_map = { | |
3078 | /*4096x2304/64/64 *24 = 0xd800 Bytes*/ | |
3079 | .buf_size = 0xd800, | |
3080 | }, | |
b9164398 NQ |
3081 | .mmu_vbh = { |
3082 | .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/ | |
3083 | }, | |
fe96802b | 3084 | #if 0 |
b9164398 NQ |
3085 | .cm_header = { |
3086 | /*add one for keeper.*/ | |
3087 | .buf_size = MMU_COMPRESS_HEADER_SIZE * | |
3088 | (FRAME_BUFFERS + 1), | |
3089 | /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */ | |
3090 | }, | |
3091 | #endif | |
3092 | .mpred_above = { | |
3093 | .buf_size = 0x10000, /* 2 * size of hevc*/ | |
3094 | }, | |
fe96802b | 3095 | #ifdef MV_USE_FIXED_BUF |
b9164398 NQ |
3096 | .mpred_mv = { |
3097 | /* .buf_size = 0x100000*16, | |
e0614bf7 ZZ |
3098 | * //4k2k , 0x100000 per buffer |
3099 | */ | |
b9164398 NQ |
3100 | /* 4096x2304 , 0x120000 per buffer */ |
3101 | .buf_size = 0x120000 * FRAME_BUFFERS, | |
3102 | }, | |
fe96802b | 3103 | #endif |
b9164398 NQ |
3104 | .rpm = { |
3105 | .buf_size = RPM_BUF_SIZE, | |
3106 | }, | |
3107 | .lmem = { | |
3108 | .buf_size = 0x400 * 2, | |
3109 | } | |
df841122 | 3110 | }, |
3111 | { | |
3112 | .max_width = 4096*2, | |
3113 | .max_height = 2304*2, | |
3114 | .ipp = { | |
3115 | // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k | |
3116 | .buf_size = 0x4000*2, | |
3117 | }, | |
3118 | .sao_abv = { | |
3119 | .buf_size = 0x30000*2, | |
3120 | }, | |
3121 | .sao_vb = { | |
3122 | .buf_size = 0x30000*2, | |
3123 | }, | |
3124 | .short_term_rps = { | |
3125 | // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800) | |
3126 | .buf_size = 0x800, | |
3127 | }, | |
3128 | .vps = { | |
3129 | // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes | |
3130 | .buf_size = 0x800, | |
3131 | }, | |
3132 | .sps = { | |
3133 | // SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes | |
3134 | .buf_size = 0x800, | |
3135 | }, | |
3136 | .pps = { | |
3137 | // PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes | |
3138 | .buf_size = 0x2000, | |
3139 | }, | |
3140 | .sao_up = { | |
3141 | // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes | |
3142 | .buf_size = 0x2800*2, | |
3143 | }, | |
3144 | .swap_buf = { | |
3145 | // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid) | |
3146 | .buf_size = 0x800, | |
3147 | }, | |
3148 | .swap_buf2 = { | |
3149 | .buf_size = 0x800, | |
3150 | }, | |
3151 | .scalelut = { | |
3152 | // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000) | |
3153 | .buf_size = 0x8000*2, | |
3154 | }, | |
3155 | .dblk_para = { | |
3156 | // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000) | |
3157 | .buf_size = 0x80000*2, | |
3158 | }, | |
3159 | .dblk_data = { | |
3160 | .buf_size = 0x80000*2, | |
3161 | }, | |
8deb3449 NQ |
3162 | .seg_map = { |
3163 | /*4096x2304/64/64 *24 = 0xd800 Bytes*/ | |
3164 | .buf_size = 0xd800*4, | |
3165 | }, | |
df841122 | 3166 | .mmu_vbh = { |
3167 | .buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K | |
3168 | }, | |
e0e39311 | 3169 | #if 0 |
df841122 | 3170 | .cm_header = { |
3171 | //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) | |
3172 | .buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) | |
3173 | }, | |
e0e39311 | 3174 | #endif |
df841122 | 3175 | .mpred_above = { |
3176 | .buf_size = 0x10000*2, /* 2 * size of hevc*/ | |
3177 | }, | |
3178 | #ifdef MV_USE_FIXED_BUF | |
3179 | .mpred_mv = { | |
3180 | //4k2k , 0x100000 per buffer */ | |
3181 | /* 4096x2304 , 0x120000 per buffer */ | |
e0e39311 | 3182 | .buf_size = 0x120000 * FRAME_BUFFERS * 4, |
df841122 | 3183 | }, |
3184 | #endif | |
3185 | .rpm = { | |
e0e39311 | 3186 | .buf_size = RPM_BUF_SIZE, |
3187 | }, | |
3188 | .lmem = { | |
3189 | .buf_size = 0x400 * 2, | |
df841122 | 3190 | } |
b9164398 NQ |
3191 | } |
3192 | }; | |
3193 | ||
3194 | ||
3195 | /*Losless compression body buffer size 4K per 64x32 (jt)*/ | |
3196 | int compute_losless_comp_body_size(int width, int height, | |
3197 | uint8_t is_bit_depth_10) | |
3198 | { | |
3199 | int width_x64; | |
3200 | int height_x32; | |
3201 | int bsize; | |
e0614bf7 | 3202 | |
b9164398 NQ |
3203 | width_x64 = width + 63; |
3204 | width_x64 >>= 6; | |
3205 | height_x32 = height + 31; | |
3206 | height_x32 >>= 5; | |
b7706e1e | 3207 | bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32; |
b9164398 NQ |
3208 | if (debug & VP9_DEBUG_BUFMGR_MORE) |
3209 | pr_info("%s(%d,%d,%d)=>%d\n", | |
3210 | __func__, width, height, | |
3211 | is_bit_depth_10, bsize); | |
3212 | ||
3213 | return bsize; | |
3214 | } | |
3215 | ||
3216 | /* Losless compression header buffer size 32bytes per 128x64 (jt)*/ | |
3217 | static int compute_losless_comp_header_size(int width, int height) | |
3218 | { | |
3219 | int width_x128; | |
3220 | int height_x64; | |
3221 | int hsize; | |
e0614bf7 | 3222 | |
b9164398 NQ |
3223 | width_x128 = width + 127; |
3224 | width_x128 >>= 7; | |
3225 | height_x64 = height + 63; | |
3226 | height_x64 >>= 6; | |
3227 | ||
3228 | hsize = 32 * width_x128 * height_x64; | |
3229 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
3230 | pr_info("%s(%d,%d)=>%d\n", | |
3231 | __func__, width, height, | |
3232 | hsize); | |
3233 | ||
3234 | return hsize; | |
3235 | } | |
3236 | ||
3237 | static void init_buff_spec(struct VP9Decoder_s *pbi, | |
3238 | struct BuffInfo_s *buf_spec) | |
3239 | { | |
3240 | void *mem_start_virt; | |
e0614bf7 | 3241 | |
b9164398 NQ |
3242 | buf_spec->ipp.buf_start = buf_spec->start_adr; |
3243 | buf_spec->sao_abv.buf_start = | |
3244 | buf_spec->ipp.buf_start + buf_spec->ipp.buf_size; | |
3245 | ||
3246 | buf_spec->sao_vb.buf_start = | |
3247 | buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size; | |
3248 | buf_spec->short_term_rps.buf_start = | |
3249 | buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size; | |
3250 | buf_spec->vps.buf_start = | |
3251 | buf_spec->short_term_rps.buf_start + | |
3252 | buf_spec->short_term_rps.buf_size; | |
3253 | buf_spec->sps.buf_start = | |
3254 | buf_spec->vps.buf_start + buf_spec->vps.buf_size; | |
3255 | buf_spec->pps.buf_start = | |
3256 | buf_spec->sps.buf_start + buf_spec->sps.buf_size; | |
3257 | buf_spec->sao_up.buf_start = | |
3258 | buf_spec->pps.buf_start + buf_spec->pps.buf_size; | |
3259 | buf_spec->swap_buf.buf_start = | |
3260 | buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size; | |
3261 | buf_spec->swap_buf2.buf_start = | |
3262 | buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size; | |
3263 | buf_spec->scalelut.buf_start = | |
3264 | buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size; | |
3265 | buf_spec->dblk_para.buf_start = | |
3266 | buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size; | |
3267 | buf_spec->dblk_data.buf_start = | |
3268 | buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size; | |
3269 | buf_spec->seg_map.buf_start = | |
3270 | buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size; | |
b7706e1e | 3271 | if (pbi == NULL || pbi->mmu_enable) { |
3272 | buf_spec->mmu_vbh.buf_start = | |
3273 | buf_spec->seg_map.buf_start + | |
3274 | buf_spec->seg_map.buf_size; | |
3275 | buf_spec->mpred_above.buf_start = | |
3276 | buf_spec->mmu_vbh.buf_start + | |
3277 | buf_spec->mmu_vbh.buf_size; | |
3278 | } else { | |
3279 | buf_spec->mpred_above.buf_start = | |
a6c89e96 | 3280 | buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size; |
b7706e1e | 3281 | } |
fe96802b | 3282 | #ifdef MV_USE_FIXED_BUF |
b9164398 NQ |
3283 | buf_spec->mpred_mv.buf_start = |
3284 | buf_spec->mpred_above.buf_start + | |
3285 | buf_spec->mpred_above.buf_size; | |
fe96802b NQ |
3286 | |
3287 | buf_spec->rpm.buf_start = | |
3288 | buf_spec->mpred_mv.buf_start + | |
3289 | buf_spec->mpred_mv.buf_size; | |
3290 | #else | |
3291 | buf_spec->rpm.buf_start = | |
3292 | buf_spec->mpred_above.buf_start + | |
3293 | buf_spec->mpred_above.buf_size; | |
3294 | ||
3295 | #endif | |
3296 | buf_spec->lmem.buf_start = | |
3297 | buf_spec->rpm.buf_start + | |
3298 | buf_spec->rpm.buf_size; | |
3299 | buf_spec->end_adr = | |
3300 | buf_spec->lmem.buf_start + | |
3301 | buf_spec->lmem.buf_size; | |
3302 | ||
7d2e7e17 NQ |
3303 | if (!pbi) |
3304 | return; | |
3305 | ||
3306 | if (!vdec_secure(hw_to_vdec(pbi))) { | |
fe96802b NQ |
3307 | mem_start_virt = |
3308 | codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start); | |
3309 | if (mem_start_virt) { | |
7d2e7e17 NQ |
3310 | memset(mem_start_virt, 0, |
3311 | buf_spec->dblk_para.buf_size); | |
fe96802b NQ |
3312 | codec_mm_dma_flush(mem_start_virt, |
3313 | buf_spec->dblk_para.buf_size, | |
3314 | DMA_TO_DEVICE); | |
b9164398 | 3315 | } else { |
7d2e7e17 NQ |
3316 | mem_start_virt = codec_mm_vmap( |
3317 | buf_spec->dblk_para.buf_start, | |
3318 | buf_spec->dblk_para.buf_size); | |
3319 | if (mem_start_virt) { | |
3320 | memset(mem_start_virt, 0, | |
3321 | buf_spec->dblk_para.buf_size); | |
3322 | codec_mm_dma_flush(mem_start_virt, | |
3323 | buf_spec->dblk_para.buf_size, | |
3324 | DMA_TO_DEVICE); | |
3325 | codec_mm_unmap_phyaddr(mem_start_virt); | |
3326 | } else { | |
3327 | /*not virt for tvp playing, | |
3328 | may need clear on ucode.*/ | |
3329 | pr_err("mem_start_virt failed\n"); | |
3330 | } | |
b7706e1e | 3331 | } |
7d2e7e17 NQ |
3332 | } |
3333 | ||
3334 | if (debug) { | |
3335 | pr_info("%s workspace (%x %x) size = %x\n", __func__, | |
3336 | buf_spec->start_adr, buf_spec->end_adr, | |
3337 | buf_spec->end_adr - buf_spec->start_adr); | |
3338 | } | |
3339 | ||
3340 | if (debug) { | |
3341 | pr_info("ipp.buf_start :%x\n", | |
3342 | buf_spec->ipp.buf_start); | |
3343 | pr_info("sao_abv.buf_start :%x\n", | |
3344 | buf_spec->sao_abv.buf_start); | |
3345 | pr_info("sao_vb.buf_start :%x\n", | |
3346 | buf_spec->sao_vb.buf_start); | |
3347 | pr_info("short_term_rps.buf_start :%x\n", | |
3348 | buf_spec->short_term_rps.buf_start); | |
3349 | pr_info("vps.buf_start :%x\n", | |
3350 | buf_spec->vps.buf_start); | |
3351 | pr_info("sps.buf_start :%x\n", | |
3352 | buf_spec->sps.buf_start); | |
3353 | pr_info("pps.buf_start :%x\n", | |
3354 | buf_spec->pps.buf_start); | |
3355 | pr_info("sao_up.buf_start :%x\n", | |
3356 | buf_spec->sao_up.buf_start); | |
3357 | pr_info("swap_buf.buf_start :%x\n", | |
3358 | buf_spec->swap_buf.buf_start); | |
3359 | pr_info("swap_buf2.buf_start :%x\n", | |
3360 | buf_spec->swap_buf2.buf_start); | |
3361 | pr_info("scalelut.buf_start :%x\n", | |
3362 | buf_spec->scalelut.buf_start); | |
3363 | pr_info("dblk_para.buf_start :%x\n", | |
3364 | buf_spec->dblk_para.buf_start); | |
3365 | pr_info("dblk_data.buf_start :%x\n", | |
3366 | buf_spec->dblk_data.buf_start); | |
3367 | pr_info("seg_map.buf_start :%x\n", | |
3368 | buf_spec->seg_map.buf_start); | |
3369 | if (pbi->mmu_enable) { | |
3370 | pr_info("mmu_vbh.buf_start :%x\n", | |
3371 | buf_spec->mmu_vbh.buf_start); | |
3372 | } | |
3373 | pr_info("mpred_above.buf_start :%x\n", | |
3374 | buf_spec->mpred_above.buf_start); | |
fe96802b | 3375 | #ifdef MV_USE_FIXED_BUF |
7d2e7e17 NQ |
3376 | pr_info("mpred_mv.buf_start :%x\n", |
3377 | buf_spec->mpred_mv.buf_start); | |
fe96802b | 3378 | #endif |
7d2e7e17 NQ |
3379 | if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) { |
3380 | pr_info("rpm.buf_start :%x\n", | |
3381 | buf_spec->rpm.buf_start); | |
b9164398 NQ |
3382 | } |
3383 | } | |
b9164398 NQ |
3384 | } |
3385 | ||
c23e8aee HZ |
3386 | /* cache_util.c */ |
3387 | #define THODIYIL_MCRCC_CANVAS_ALGX 4 | |
3388 | ||
3389 | static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX; | |
3390 | ||
3391 | static void mcrcc_perfcount_reset(void) | |
3392 | { | |
3393 | if (debug & VP9_DEBUG_CACHE) | |
3394 | pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n"); | |
3395 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1); | |
3396 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0); | |
3397 | return; | |
3398 | } | |
3399 | ||
3400 | static unsigned raw_mcr_cnt_total_prev; | |
3401 | static unsigned hit_mcr_0_cnt_total_prev; | |
3402 | static unsigned hit_mcr_1_cnt_total_prev; | |
3403 | static unsigned byp_mcr_cnt_nchcanv_total_prev; | |
3404 | static unsigned byp_mcr_cnt_nchoutwin_total_prev; | |
3405 | ||
3406 | static void mcrcc_get_hitrate(unsigned reset_pre) | |
3407 | { | |
3408 | unsigned delta_hit_mcr_0_cnt; | |
3409 | unsigned delta_hit_mcr_1_cnt; | |
3410 | unsigned delta_raw_mcr_cnt; | |
3411 | unsigned delta_mcr_cnt_nchcanv; | |
3412 | unsigned delta_mcr_cnt_nchoutwin; | |
3413 | ||
3414 | unsigned tmp; | |
3415 | unsigned raw_mcr_cnt; | |
3416 | unsigned hit_mcr_cnt; | |
3417 | unsigned byp_mcr_cnt_nchoutwin; | |
3418 | unsigned byp_mcr_cnt_nchcanv; | |
3419 | int hitrate; | |
3420 | if (reset_pre) { | |
3421 | raw_mcr_cnt_total_prev = 0; | |
3422 | hit_mcr_0_cnt_total_prev = 0; | |
3423 | hit_mcr_1_cnt_total_prev = 0; | |
3424 | byp_mcr_cnt_nchcanv_total_prev = 0; | |
3425 | byp_mcr_cnt_nchoutwin_total_prev = 0; | |
3426 | } | |
3427 | if (debug & VP9_DEBUG_CACHE) | |
3428 | pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n"); | |
3429 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1)); | |
3430 | raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3431 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1)); | |
3432 | hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3433 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1)); | |
3434 | byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3435 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1)); | |
3436 | byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3437 | ||
3438 | if (debug & VP9_DEBUG_CACHE) | |
3439 | pr_info("raw_mcr_cnt_total: %d\n", | |
3440 | raw_mcr_cnt); | |
3441 | if (debug & VP9_DEBUG_CACHE) | |
3442 | pr_info("hit_mcr_cnt_total: %d\n", | |
3443 | hit_mcr_cnt); | |
3444 | if (debug & VP9_DEBUG_CACHE) | |
3445 | pr_info("byp_mcr_cnt_nchoutwin_total: %d\n", | |
3446 | byp_mcr_cnt_nchoutwin); | |
3447 | if (debug & VP9_DEBUG_CACHE) | |
3448 | pr_info("byp_mcr_cnt_nchcanv_total: %d\n", | |
3449 | byp_mcr_cnt_nchcanv); | |
3450 | ||
3451 | delta_raw_mcr_cnt = raw_mcr_cnt - | |
3452 | raw_mcr_cnt_total_prev; | |
3453 | delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv - | |
3454 | byp_mcr_cnt_nchcanv_total_prev; | |
3455 | delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin - | |
3456 | byp_mcr_cnt_nchoutwin_total_prev; | |
3457 | raw_mcr_cnt_total_prev = raw_mcr_cnt; | |
3458 | byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv; | |
3459 | byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin; | |
3460 | ||
3461 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1)); | |
3462 | tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3463 | if (debug & VP9_DEBUG_CACHE) | |
3464 | pr_info("miss_mcr_0_cnt_total: %d\n", tmp); | |
3465 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1)); | |
3466 | tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3467 | if (debug & VP9_DEBUG_CACHE) | |
3468 | pr_info("miss_mcr_1_cnt_total: %d\n", tmp); | |
3469 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1)); | |
3470 | tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3471 | if (debug & VP9_DEBUG_CACHE) | |
3472 | pr_info("hit_mcr_0_cnt_total: %d\n", tmp); | |
3473 | delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev; | |
3474 | hit_mcr_0_cnt_total_prev = tmp; | |
3475 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1)); | |
3476 | tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3477 | if (debug & VP9_DEBUG_CACHE) | |
3478 | pr_info("hit_mcr_1_cnt_total: %d\n", tmp); | |
3479 | delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev; | |
3480 | hit_mcr_1_cnt_total_prev = tmp; | |
3481 | ||
3482 | if (delta_raw_mcr_cnt != 0) { | |
3483 | hitrate = 100 * delta_hit_mcr_0_cnt | |
3484 | / delta_raw_mcr_cnt; | |
3485 | if (debug & VP9_DEBUG_CACHE) | |
3486 | pr_info("CANV0_HIT_RATE : %d\n", hitrate); | |
3487 | hitrate = 100 * delta_hit_mcr_1_cnt | |
3488 | / delta_raw_mcr_cnt; | |
3489 | if (debug & VP9_DEBUG_CACHE) | |
3490 | pr_info("CANV1_HIT_RATE : %d\n", hitrate); | |
3491 | hitrate = 100 * delta_mcr_cnt_nchcanv | |
3492 | / delta_raw_mcr_cnt; | |
3493 | if (debug & VP9_DEBUG_CACHE) | |
3494 | pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate); | |
3495 | hitrate = 100 * delta_mcr_cnt_nchoutwin | |
3496 | / delta_raw_mcr_cnt; | |
3497 | if (debug & VP9_DEBUG_CACHE) | |
3498 | pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate); | |
3499 | } | |
3500 | ||
3501 | ||
3502 | if (raw_mcr_cnt != 0) { | |
3503 | hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt; | |
3504 | if (debug & VP9_DEBUG_CACHE) | |
3505 | pr_info("MCRCC_HIT_RATE : %d\n", hitrate); | |
3506 | hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv) | |
3507 | / raw_mcr_cnt; | |
3508 | if (debug & VP9_DEBUG_CACHE) | |
3509 | pr_info("MCRCC_BYP_RATE : %d\n", hitrate); | |
3510 | } else { | |
3511 | if (debug & VP9_DEBUG_CACHE) | |
3512 | pr_info("MCRCC_HIT_RATE : na\n"); | |
3513 | if (debug & VP9_DEBUG_CACHE) | |
3514 | pr_info("MCRCC_BYP_RATE : na\n"); | |
3515 | } | |
3516 | return; | |
3517 | } | |
3518 | ||
3519 | ||
3520 | static void decomp_perfcount_reset(void) | |
3521 | { | |
3522 | if (debug & VP9_DEBUG_CACHE) | |
3523 | pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n"); | |
3524 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1); | |
3525 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0); | |
3526 | return; | |
3527 | } | |
3528 | ||
3529 | static void decomp_get_hitrate(void) | |
3530 | { | |
3531 | unsigned raw_mcr_cnt; | |
3532 | unsigned hit_mcr_cnt; | |
3533 | int hitrate; | |
3534 | if (debug & VP9_DEBUG_CACHE) | |
3535 | pr_info("[cache_util.c] Entered decomp_get_hitrate...\n"); | |
3536 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1)); | |
3537 | raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3538 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1)); | |
3539 | hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3540 | ||
3541 | if (debug & VP9_DEBUG_CACHE) | |
3542 | pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt); | |
3543 | if (debug & VP9_DEBUG_CACHE) | |
3544 | pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt); | |
3545 | ||
3546 | if (raw_mcr_cnt != 0) { | |
3547 | hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt; | |
3548 | if (debug & VP9_DEBUG_CACHE) | |
3549 | pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate); | |
3550 | } else { | |
3551 | if (debug & VP9_DEBUG_CACHE) | |
3552 | pr_info("DECOMP_HCACHE_HIT_RATE : na\n"); | |
3553 | } | |
3554 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1)); | |
3555 | raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3556 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1)); | |
3557 | hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3558 | ||
3559 | if (debug & VP9_DEBUG_CACHE) | |
3560 | pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt); | |
3561 | if (debug & VP9_DEBUG_CACHE) | |
3562 | pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt); | |
3563 | ||
3564 | if (raw_mcr_cnt != 0) { | |
3565 | hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt; | |
3566 | if (debug & VP9_DEBUG_CACHE) | |
3567 | pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate); | |
3568 | } else { | |
3569 | if (debug & VP9_DEBUG_CACHE) | |
3570 | pr_info("DECOMP_DCACHE_HIT_RATE : na\n"); | |
3571 | } | |
3572 | return; | |
3573 | } | |
3574 | ||
3575 | static void decomp_get_comprate(void) | |
3576 | { | |
3577 | unsigned raw_ucomp_cnt; | |
3578 | unsigned fast_comp_cnt; | |
3579 | unsigned slow_comp_cnt; | |
3580 | int comprate; | |
3581 | ||
3582 | if (debug & VP9_DEBUG_CACHE) | |
3583 | pr_info("[cache_util.c] Entered decomp_get_comprate...\n"); | |
3584 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1)); | |
3585 | fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3586 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1)); | |
3587 | slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3588 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1)); | |
3589 | raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3590 | ||
3591 | if (debug & VP9_DEBUG_CACHE) | |
3592 | pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt); | |
3593 | if (debug & VP9_DEBUG_CACHE) | |
3594 | pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt); | |
3595 | if (debug & VP9_DEBUG_CACHE) | |
3596 | pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt); | |
3597 | ||
3598 | if (raw_ucomp_cnt != 0) { | |
3599 | comprate = (fast_comp_cnt + slow_comp_cnt) | |
3600 | * 100 / raw_ucomp_cnt; | |
3601 | if (debug & VP9_DEBUG_CACHE) | |
3602 | pr_info("DECOMP_COMP_RATIO : %d\n", comprate); | |
3603 | } else { | |
3604 | if (debug & VP9_DEBUG_CACHE) | |
3605 | pr_info("DECOMP_COMP_RATIO : na\n"); | |
3606 | } | |
3607 | return; | |
3608 | } | |
3609 | /* cache_util.c end */ | |
3610 | ||
b9164398 | 3611 | /*==================================================== |
e0614bf7 ZZ |
3612 | *======================================================================== |
3613 | *vp9_prob define | |
3614 | *======================================================================== | |
3615 | */ | |
b9164398 NQ |
3616 | #define VP9_PARTITION_START 0 |
3617 | #define VP9_PARTITION_SIZE_STEP (3 * 4) | |
3618 | #define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP) | |
3619 | #define VP9_PARTITION_KEY_START 0 | |
3620 | #define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE | |
3621 | #define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE) | |
3622 | #define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE) | |
3623 | #define VP9_SKIP_SIZE 4 /* only use 3*/ | |
3624 | #define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE) | |
3625 | #define VP9_TX_MODE_8_0_OFFSET 0 | |
3626 | #define VP9_TX_MODE_8_1_OFFSET 1 | |
3627 | #define VP9_TX_MODE_16_0_OFFSET 2 | |
3628 | #define VP9_TX_MODE_16_1_OFFSET 4 | |
3629 | #define VP9_TX_MODE_32_0_OFFSET 6 | |
3630 | #define VP9_TX_MODE_32_1_OFFSET 9 | |
3631 | #define VP9_TX_MODE_SIZE 12 | |
3632 | #define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE) | |
3633 | #define VP9_COEF_BAND_0_OFFSET 0 | |
3634 | #define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1) | |
3635 | #define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3) | |
3636 | #define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3) | |
3637 | #define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3) | |
3638 | #define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3) | |
3639 | #define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/ | |
3640 | #define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET) | |
3641 | #define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET) | |
3642 | #define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET) | |
3643 | #define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET) | |
3644 | #define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET) | |
3645 | #define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET) | |
3646 | #define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE) | |
3647 | #define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/ | |
3648 | #define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE) | |
3649 | #define VP9_INTERP_SIZE 8 | |
3650 | #define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE) | |
3651 | #define VP9_INTRA_INTER_SIZE 4 | |
3652 | #define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START | |
3653 | #define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE) | |
3654 | #define VP9_COMP_INTER_START \ | |
3655 | (VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE) | |
3656 | #define VP9_COMP_INTER_SIZE 5 | |
3657 | #define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE) | |
3658 | #define VP9_COMP_REF_SIZE 5 | |
3659 | #define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE) | |
3660 | #define VP9_SINGLE_REF_SIZE 10 | |
3661 | #define VP9_REF_MODE_START VP9_COMP_INTER_START | |
3662 | #define VP9_REF_MODE_SIZE \ | |
3663 | (VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE) | |
3664 | #define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE) | |
3665 | #define VP9_IF_Y_MODE_SIZE 36 | |
3666 | #define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE) | |
3667 | #define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/ | |
3668 | #define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE) | |
3669 | #define VP9_MV_JOINTS_SIZE 3 | |
3670 | #define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE) | |
3671 | #define VP9_MV_SIGN_0_SIZE 1 | |
3672 | #define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE) | |
3673 | #define VP9_MV_CLASSES_0_SIZE 10 | |
3674 | #define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE) | |
3675 | #define VP9_MV_CLASS0_0_SIZE 1 | |
3676 | #define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE) | |
3677 | #define VP9_MV_BITS_0_SIZE 10 | |
3678 | #define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE) | |
3679 | #define VP9_MV_SIGN_1_SIZE 1 | |
3680 | #define VP9_MV_CLASSES_1_START \ | |
3681 | (VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE) | |
3682 | #define VP9_MV_CLASSES_1_SIZE 10 | |
3683 | #define VP9_MV_CLASS0_1_START \ | |
3684 | (VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE) | |
3685 | #define VP9_MV_CLASS0_1_SIZE 1 | |
3686 | #define VP9_MV_BITS_1_START \ | |
3687 | (VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE) | |
3688 | #define VP9_MV_BITS_1_SIZE 10 | |
3689 | #define VP9_MV_CLASS0_FP_0_START \ | |
3690 | (VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE) | |
3691 | #define VP9_MV_CLASS0_FP_0_SIZE 9 | |
3692 | #define VP9_MV_CLASS0_FP_1_START \ | |
3693 | (VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE) | |
3694 | #define VP9_MV_CLASS0_FP_1_SIZE 9 | |
3695 | #define VP9_MV_CLASS0_HP_0_START \ | |
3696 | (VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE) | |
3697 | #define VP9_MV_CLASS0_HP_0_SIZE 2 | |
3698 | #define VP9_MV_CLASS0_HP_1_START \ | |
3699 | (VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE) | |
3700 | #define VP9_MV_CLASS0_HP_1_SIZE 2 | |
3701 | #define VP9_MV_START VP9_MV_JOINTS_START | |
3702 | #define VP9_MV_SIZE 72 /*only use 69*/ | |
3703 | ||
3704 | #define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE) | |
3705 | ||
3706 | ||
3707 | /*======================================================================== | |
e0614bf7 ZZ |
3708 | * vp9_count_mem define |
3709 | *======================================================================== | |
3710 | */ | |
b9164398 NQ |
3711 | #define VP9_COEF_COUNT_START 0 |
3712 | #define VP9_COEF_COUNT_BAND_0_OFFSET 0 | |
3713 | #define VP9_COEF_COUNT_BAND_1_OFFSET \ | |
3714 | (VP9_COEF_COUNT_BAND_0_OFFSET + 3*5) | |
3715 | #define VP9_COEF_COUNT_BAND_2_OFFSET \ | |
3716 | (VP9_COEF_COUNT_BAND_1_OFFSET + 6*5) | |
3717 | #define VP9_COEF_COUNT_BAND_3_OFFSET \ | |
3718 | (VP9_COEF_COUNT_BAND_2_OFFSET + 6*5) | |
3719 | #define VP9_COEF_COUNT_BAND_4_OFFSET \ | |
3720 | (VP9_COEF_COUNT_BAND_3_OFFSET + 6*5) | |
3721 | #define VP9_COEF_COUNT_BAND_5_OFFSET \ | |
3722 | (VP9_COEF_COUNT_BAND_4_OFFSET + 6*5) | |
3723 | #define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */ | |
3724 | #define VP9_COEF_COUNT_4X4_START \ | |
3725 | (VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET) | |
3726 | #define VP9_COEF_COUNT_8X8_START \ | |
3727 | (VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET) | |
3728 | #define VP9_COEF_COUNT_16X16_START \ | |
3729 | (VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET) | |
3730 | #define VP9_COEF_COUNT_32X32_START \ | |
3731 | (VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET) | |
3732 | #define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET) | |
3733 | #define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET) | |
3734 | ||
3735 | #define VP9_INTRA_INTER_COUNT_START \ | |
3736 | (VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE) | |
3737 | #define VP9_INTRA_INTER_COUNT_SIZE (4*2) | |
3738 | #define VP9_COMP_INTER_COUNT_START \ | |
3739 | (VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE) | |
3740 | #define VP9_COMP_INTER_COUNT_SIZE (5*2) | |
3741 | #define VP9_COMP_REF_COUNT_START \ | |
3742 | (VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE) | |
3743 | #define VP9_COMP_REF_COUNT_SIZE (5*2) | |
3744 | #define VP9_SINGLE_REF_COUNT_START \ | |
3745 | (VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE) | |
3746 | #define VP9_SINGLE_REF_COUNT_SIZE (10*2) | |
3747 | #define VP9_TX_MODE_COUNT_START \ | |
3748 | (VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE) | |
3749 | #define VP9_TX_MODE_COUNT_SIZE (12*2) | |
3750 | #define VP9_SKIP_COUNT_START \ | |
3751 | (VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE) | |
3752 | #define VP9_SKIP_COUNT_SIZE (3*2) | |
3753 | #define VP9_MV_SIGN_0_COUNT_START \ | |
3754 | (VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE) | |
3755 | #define VP9_MV_SIGN_0_COUNT_SIZE (1*2) | |
3756 | #define VP9_MV_SIGN_1_COUNT_START \ | |
3757 | (VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE) | |
3758 | #define VP9_MV_SIGN_1_COUNT_SIZE (1*2) | |
3759 | #define VP9_MV_BITS_0_COUNT_START \ | |
3760 | (VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE) | |
3761 | #define VP9_MV_BITS_0_COUNT_SIZE (10*2) | |
3762 | #define VP9_MV_BITS_1_COUNT_START \ | |
3763 | (VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE) | |
3764 | #define VP9_MV_BITS_1_COUNT_SIZE (10*2) | |
3765 | #define VP9_MV_CLASS0_HP_0_COUNT_START \ | |
3766 | (VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE) | |
3767 | #define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2) | |
3768 | #define VP9_MV_CLASS0_HP_1_COUNT_START \ | |
3769 | (VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE) | |
3770 | #define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2) | |
3771 | /* Start merge_tree*/ | |
3772 | #define VP9_INTER_MODE_COUNT_START \ | |
3773 | (VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE) | |
3774 | #define VP9_INTER_MODE_COUNT_SIZE (7*4) | |
3775 | #define VP9_IF_Y_MODE_COUNT_START \ | |
3776 | (VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE) | |
3777 | #define VP9_IF_Y_MODE_COUNT_SIZE (10*4) | |
3778 | #define VP9_IF_UV_MODE_COUNT_START \ | |
3779 | (VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE) | |
3780 | #define VP9_IF_UV_MODE_COUNT_SIZE (10*10) | |
3781 | #define VP9_PARTITION_P_COUNT_START \ | |
3782 | (VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE) | |
3783 | #define VP9_PARTITION_P_COUNT_SIZE (4*4*4) | |
3784 | #define VP9_INTERP_COUNT_START \ | |
3785 | (VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE) | |
3786 | #define VP9_INTERP_COUNT_SIZE (4*3) | |
3787 | #define VP9_MV_JOINTS_COUNT_START \ | |
3788 | (VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE) | |
3789 | #define VP9_MV_JOINTS_COUNT_SIZE (1 * 4) | |
3790 | #define VP9_MV_CLASSES_0_COUNT_START \ | |
3791 | (VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE) | |
3792 | #define VP9_MV_CLASSES_0_COUNT_SIZE (1*11) | |
3793 | #define VP9_MV_CLASS0_0_COUNT_START \ | |
3794 | (VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE) | |
3795 | #define VP9_MV_CLASS0_0_COUNT_SIZE (1*2) | |
3796 | #define VP9_MV_CLASSES_1_COUNT_START \ | |
3797 | (VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE) | |
3798 | #define VP9_MV_CLASSES_1_COUNT_SIZE (1*11) | |
3799 | #define VP9_MV_CLASS0_1_COUNT_START \ | |
3800 | (VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE) | |
3801 | #define VP9_MV_CLASS0_1_COUNT_SIZE (1*2) | |
3802 | #define VP9_MV_CLASS0_FP_0_COUNT_START \ | |
3803 | (VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE) | |
3804 | #define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4) | |
3805 | #define VP9_MV_CLASS0_FP_1_COUNT_START \ | |
3806 | (VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE) | |
3807 | #define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4) | |
3808 | ||
3809 | ||
3810 | #define DC_PRED 0 /* Average of above and left pixels*/ | |
3811 | #define V_PRED 1 /* Vertical*/ | |
3812 | #define H_PRED 2 /* Horizontal*/ | |
3813 | #define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/ | |
3814 | #define D135_PRED 4 /* Directional 135 deg = 180 - 45*/ | |
3815 | #define D117_PRED 5 /* Directional 117 deg = 180 - 63*/ | |
3816 | #define D153_PRED 6 /* Directional 153 deg = 180 - 27*/ | |
3817 | #define D207_PRED 7 /* Directional 207 deg = 180 + 27*/ | |
3818 | #define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/ | |
3819 | #define TM_PRED 9 /*True-motion*/ | |
3820 | ||
3821 | int clip_prob(int p) | |
3822 | { | |
3823 | return (p > 255) ? 255 : (p < 1) ? 1 : p; | |
3824 | } | |
3825 | ||
3826 | #define ROUND_POWER_OF_TWO(value, n) \ | |
3827 | (((value) + (1 << ((n) - 1))) >> (n)) | |
3828 | ||
3829 | #define MODE_MV_COUNT_SAT 20 | |
3830 | static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = { | |
3831 | 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64, | |
3832 | 70, 76, 83, 89, 96, 102, 108, 115, 121, 128 | |
3833 | }; | |
3834 | ||
3835 | void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob, | |
3836 | int coef_node_start, int tree_left, int tree_right, int tree_i, | |
3837 | int node) { | |
3838 | ||
3839 | int prob_32, prob_res, prob_shift; | |
3840 | int pre_prob, new_prob; | |
3841 | int den, m_count, get_prob, factor; | |
e0614bf7 | 3842 | |
b9164398 NQ |
3843 | prob_32 = prev_prob[coef_node_start / 4 * 2]; |
3844 | prob_res = coef_node_start & 3; | |
3845 | prob_shift = prob_res * 8; | |
3846 | pre_prob = (prob_32 >> prob_shift) & 0xff; | |
3847 | ||
3848 | den = tree_left + tree_right; | |
3849 | ||
3850 | if (den == 0) | |
3851 | new_prob = pre_prob; | |
3852 | else { | |
3853 | m_count = (den < MODE_MV_COUNT_SAT) ? | |
3854 | den : MODE_MV_COUNT_SAT; | |
3855 | get_prob = clip_prob( | |
3856 | div_r32(((int64_t)tree_left * 256 + (den >> 1)), | |
3857 | den)); | |
3858 | /*weighted_prob*/ | |
3859 | factor = count_to_update_factor[m_count]; | |
3860 | new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor) | |
3861 | + get_prob * factor, 8); | |
3862 | } | |
3863 | cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2] | |
3864 | & (~(0xff << prob_shift))) | (new_prob << prob_shift); | |
3865 | ||
3866 | /*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n", | |
e0614bf7 ZZ |
3867 | *tree_i, node, pre_prob, new_prob, tree_left, tree_right, |
3868 | *cur_prob[coef_node_start/4*2]); | |
3869 | */ | |
b9164398 NQ |
3870 | } |
3871 | ||
3872 | ||
3873 | /*void adapt_coef_probs(void)*/ | |
3874 | void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc, | |
3875 | unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count) | |
3876 | { | |
3877 | /* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes) | |
e0614bf7 ZZ |
3878 | *unsigned int prev_prob[496*2]; |
3879 | *unsigned int cur_prob[496*2]; | |
3880 | *0x300 * 128bits = 0x3000 (32K Bytes) | |
3881 | *unsigned int count[0x300*4]; | |
3882 | */ | |
b9164398 NQ |
3883 | |
3884 | int tx_size, coef_tx_size_start, coef_count_tx_size_start; | |
3885 | int plane, coef_plane_start, coef_count_plane_start; | |
3886 | int type, coef_type_start, coef_count_type_start; | |
3887 | int band, coef_band_start, coef_count_band_start; | |
3888 | int cxt_num; | |
3889 | int cxt, coef_cxt_start, coef_count_cxt_start; | |
3890 | int node, coef_node_start, coef_count_node_start; | |
3891 | ||
3892 | int tree_i, tree_left, tree_right; | |
3893 | int mvd_i; | |
3894 | ||
3895 | int count_sat = 24; | |
3896 | /*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, | |
e0614bf7 ZZ |
3897 | *use 128 |
3898 | */ | |
b9164398 NQ |
3899 | /* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/ |
3900 | /*int update_factor = (pic_count == 1) ? 128 : 112;*/ | |
3901 | int update_factor = cur_kf ? 112 : | |
3902 | prev_kf ? 128 : 112; | |
3903 | ||
3904 | int prob_32; | |
3905 | int prob_res; | |
3906 | int prob_shift; | |
3907 | int pre_prob; | |
3908 | ||
3909 | int num, den; | |
3910 | int get_prob; | |
3911 | int m_count; | |
3912 | int factor; | |
3913 | ||
3914 | int new_prob; | |
3915 | ||
3916 | if (debug & VP9_DEBUG_MERGE) | |
3917 | pr_info | |
3918 | ("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n", | |
3919 | pre_fc, prev_kf, cur_kf); | |
3920 | ||
3921 | /*adapt_coef_probs*/ | |
3922 | for (tx_size = 0; tx_size < 4; tx_size++) { | |
3923 | coef_tx_size_start = VP9_COEF_START | |
3924 | + tx_size * 4 * VP9_COEF_SIZE_ONE_SET; | |
3925 | coef_count_tx_size_start = VP9_COEF_COUNT_START | |
3926 | + tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET; | |
3927 | coef_plane_start = coef_tx_size_start; | |
3928 | coef_count_plane_start = coef_count_tx_size_start; | |
3929 | for (plane = 0; plane < 2; plane++) { | |
3930 | coef_type_start = coef_plane_start; | |
3931 | coef_count_type_start = coef_count_plane_start; | |
3932 | for (type = 0; type < 2; type++) { | |
3933 | coef_band_start = coef_type_start; | |
3934 | coef_count_band_start = coef_count_type_start; | |
3935 | for (band = 0; band < 6; band++) { | |
3936 | if (band == 0) | |
3937 | cxt_num = 3; | |
3938 | else | |
3939 | cxt_num = 6; | |
3940 | coef_cxt_start = coef_band_start; | |
3941 | coef_count_cxt_start = | |
3942 | coef_count_band_start; | |
3943 | for (cxt = 0; cxt < cxt_num; cxt++) { | |
3944 | const int n0 = | |
3945 | count[coef_count_cxt_start]; | |
3946 | const int n1 = | |
3947 | count[coef_count_cxt_start + 1]; | |
3948 | const int n2 = | |
3949 | count[coef_count_cxt_start + 2]; | |
3950 | const int neob = | |
3951 | count[coef_count_cxt_start + 3]; | |
3952 | const int nneob = | |
3953 | count[coef_count_cxt_start + 4]; | |
3954 | const unsigned int | |
3955 | branch_ct[3][2] = { | |
3956 | { neob, nneob }, | |
3957 | { n0, n1 + n2 }, | |
3958 | { n1, n2 } | |
3959 | }; | |
3960 | coef_node_start = | |
3961 | coef_cxt_start; | |
3962 | for | |
3963 | (node = 0; node < 3; node++) { | |
3964 | prob_32 = | |
3965 | prev_prob[ | |
3966 | coef_node_start | |
3967 | / 4 * 2]; | |
3968 | prob_res = | |
3969 | coef_node_start & 3; | |
3970 | prob_shift = | |
3971 | prob_res * 8; | |
3972 | pre_prob = | |
3973 | (prob_32 >> prob_shift) | |
3974 | & 0xff; | |
3975 | ||
3976 | /*get_binary_prob*/ | |
3977 | num = | |
3978 | branch_ct[node][0]; | |
3979 | den = | |
3980 | branch_ct[node][0] + | |
3981 | branch_ct[node][1]; | |
3982 | m_count = (den < | |
3983 | count_sat) | |
3984 | ? den : count_sat; | |
3985 | ||
3986 | get_prob = | |
3987 | (den == 0) ? 128u : | |
3988 | clip_prob( | |
3989 | div_r32(((int64_t) | |
3990 | num * 256 | |
3991 | + (den >> 1)), | |
3992 | den)); | |
3993 | ||
3994 | factor = | |
3995 | update_factor * m_count | |
3996 | / count_sat; | |
3997 | new_prob = | |
3998 | ROUND_POWER_OF_TWO | |
3999 | (pre_prob * | |
4000 | (256 - factor) + | |
4001 | get_prob * factor, 8); | |
4002 | ||
4003 | cur_prob[coef_node_start | |
4004 | / 4 * 2] = | |
4005 | (cur_prob | |
4006 | [coef_node_start | |
4007 | / 4 * 2] & (~(0xff << | |
4008 | prob_shift))) | | |
4009 | (new_prob << | |
4010 | prob_shift); | |
4011 | ||
4012 | coef_node_start += 1; | |
4013 | } | |
4014 | ||
4015 | coef_cxt_start = | |
4016 | coef_cxt_start + 3; | |
4017 | coef_count_cxt_start = | |
4018 | coef_count_cxt_start | |
4019 | + 5; | |
4020 | } | |
4021 | if (band == 0) { | |
4022 | coef_band_start += 10; | |
4023 | coef_count_band_start += 15; | |
4024 | } else { | |
4025 | coef_band_start += 18; | |
4026 | coef_count_band_start += 30; | |
4027 | } | |
4028 | } | |
4029 | coef_type_start += VP9_COEF_SIZE_ONE_SET; | |
4030 | coef_count_type_start += | |
4031 | VP9_COEF_COUNT_SIZE_ONE_SET; | |
4032 | } | |
4033 | coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET; | |
4034 | coef_count_plane_start += | |
4035 | 2 * VP9_COEF_COUNT_SIZE_ONE_SET; | |
4036 | } | |
4037 | } | |
4038 | ||
e0614bf7 | 4039 | if (cur_kf == 0) { |
b9164398 NQ |
4040 | /*mode_mv_merge_probs - merge_intra_inter_prob*/ |
4041 | for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START; | |
4042 | coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START + | |
4043 | VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) { | |
4044 | ||
4045 | if (coef_count_node_start == | |
4046 | VP9_INTRA_INTER_COUNT_START) { | |
4047 | if (debug & VP9_DEBUG_MERGE) | |
4048 | pr_info(" # merge_intra_inter_prob\n"); | |
4049 | coef_node_start = VP9_INTRA_INTER_START; | |
4050 | } else if (coef_count_node_start == | |
4051 | VP9_COMP_INTER_COUNT_START) { | |
4052 | if (debug & VP9_DEBUG_MERGE) | |
4053 | pr_info(" # merge_comp_inter_prob\n"); | |
4054 | coef_node_start = VP9_COMP_INTER_START; | |
4055 | } | |
4056 | /* | |
e0614bf7 ZZ |
4057 | *else if (coef_count_node_start == |
4058 | * VP9_COMP_REF_COUNT_START) { | |
4059 | * pr_info(" # merge_comp_inter_prob\n"); | |
4060 | * coef_node_start = VP9_COMP_REF_START; | |
4061 | *} | |
4062 | *else if (coef_count_node_start == | |
4063 | * VP9_SINGLE_REF_COUNT_START) { | |
4064 | * pr_info(" # merge_comp_inter_prob\n"); | |
4065 | * coef_node_start = VP9_SINGLE_REF_START; | |
4066 | *} | |
4067 | */ | |
b9164398 NQ |
4068 | else if (coef_count_node_start == |
4069 | VP9_TX_MODE_COUNT_START) { | |
4070 | if (debug & VP9_DEBUG_MERGE) | |
4071 | pr_info(" # merge_tx_mode_probs\n"); | |
4072 | coef_node_start = VP9_TX_MODE_START; | |
4073 | } else if (coef_count_node_start == | |
4074 | VP9_SKIP_COUNT_START) { | |
4075 | if (debug & VP9_DEBUG_MERGE) | |
4076 | pr_info(" # merge_skip_probs\n"); | |
4077 | coef_node_start = VP9_SKIP_START; | |
4078 | } else if (coef_count_node_start == | |
4079 | VP9_MV_SIGN_0_COUNT_START) { | |
4080 | if (debug & VP9_DEBUG_MERGE) | |
4081 | pr_info(" # merge_sign_0\n"); | |
4082 | coef_node_start = VP9_MV_SIGN_0_START; | |
4083 | } else if (coef_count_node_start == | |
4084 | VP9_MV_SIGN_1_COUNT_START) { | |
4085 | if (debug & VP9_DEBUG_MERGE) | |
4086 | pr_info(" # merge_sign_1\n"); | |
4087 | coef_node_start = VP9_MV_SIGN_1_START; | |
4088 | } else if (coef_count_node_start == | |
4089 | VP9_MV_BITS_0_COUNT_START) { | |
4090 | if (debug & VP9_DEBUG_MERGE) | |
4091 | pr_info(" # merge_bits_0\n"); | |
4092 | coef_node_start = VP9_MV_BITS_0_START; | |
4093 | } else if (coef_count_node_start == | |
4094 | VP9_MV_BITS_1_COUNT_START) { | |
4095 | if (debug & VP9_DEBUG_MERGE) | |
4096 | pr_info(" # merge_bits_1\n"); | |
4097 | coef_node_start = VP9_MV_BITS_1_START; | |
4098 | } else if (coef_count_node_start == | |
4099 | VP9_MV_CLASS0_HP_0_COUNT_START) { | |
4100 | if (debug & VP9_DEBUG_MERGE) | |
4101 | pr_info(" # merge_class0_hp\n"); | |
4102 | coef_node_start = VP9_MV_CLASS0_HP_0_START; | |
4103 | } | |
4104 | ||
4105 | ||
4106 | den = count[coef_count_node_start] + | |
4107 | count[coef_count_node_start + 1]; | |
4108 | ||
4109 | prob_32 = prev_prob[coef_node_start / 4 * 2]; | |
4110 | prob_res = coef_node_start & 3; | |
4111 | prob_shift = prob_res * 8; | |
4112 | pre_prob = (prob_32 >> prob_shift) & 0xff; | |
4113 | ||
4114 | if (den == 0) | |
4115 | new_prob = pre_prob; | |
4116 | else { | |
4117 | m_count = (den < MODE_MV_COUNT_SAT) ? | |
4118 | den : MODE_MV_COUNT_SAT; | |
4119 | get_prob = | |
4120 | clip_prob( | |
4121 | div_r32(((int64_t)count[coef_count_node_start] | |
4122 | * 256 + (den >> 1)), | |
4123 | den)); | |
4124 | /*weighted_prob*/ | |
4125 | factor = count_to_update_factor[m_count]; | |
4126 | new_prob = | |
4127 | ROUND_POWER_OF_TWO(pre_prob * (256 - factor) | |
4128 | + get_prob * factor, 8); | |
4129 | } | |
4130 | cur_prob[coef_node_start / 4 * 2] = | |
4131 | (cur_prob[coef_node_start / 4 * 2] & | |
4132 | (~(0xff << prob_shift))) | |
4133 | | (new_prob << prob_shift); | |
4134 | ||
4135 | coef_node_start = coef_node_start + 1; | |
4136 | } | |
4137 | if (debug & VP9_DEBUG_MERGE) | |
4138 | pr_info(" # merge_vp9_inter_mode_tree\n"); | |
4139 | coef_node_start = VP9_INTER_MODE_START; | |
4140 | coef_count_node_start = VP9_INTER_MODE_COUNT_START; | |
4141 | for (tree_i = 0; tree_i < 7; tree_i++) { | |
4142 | for (node = 0; node < 3; node++) { | |
4143 | switch (node) { | |
4144 | case 2: | |
4145 | tree_left = | |
4146 | count[coef_count_node_start + 1]; | |
4147 | tree_right = | |
4148 | count[coef_count_node_start + 3]; | |
4149 | break; | |
4150 | case 1: | |
4151 | tree_left = | |
4152 | count[coef_count_node_start + 0]; | |
4153 | tree_right = | |
4154 | count[coef_count_node_start + 1] | |
4155 | + count[coef_count_node_start + 3]; | |
4156 | break; | |
4157 | default: | |
4158 | tree_left = | |
4159 | count[coef_count_node_start + 2]; | |
4160 | tree_right = | |
4161 | count[coef_count_node_start + 0] | |
4162 | + count[coef_count_node_start + 1] | |
4163 | + count[coef_count_node_start + 3]; | |
4164 | break; | |
4165 | ||
4166 | } | |
4167 | ||
4168 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4169 | coef_node_start, tree_left, tree_right, | |
4170 | tree_i, node); | |
4171 | ||
4172 | coef_node_start = coef_node_start + 1; | |
4173 | } | |
4174 | coef_count_node_start = coef_count_node_start + 4; | |
4175 | } | |
4176 | if (debug & VP9_DEBUG_MERGE) | |
4177 | pr_info(" # merge_vp9_intra_mode_tree\n"); | |
4178 | coef_node_start = VP9_IF_Y_MODE_START; | |
4179 | coef_count_node_start = VP9_IF_Y_MODE_COUNT_START; | |
4180 | for (tree_i = 0; tree_i < 14; tree_i++) { | |
4181 | for (node = 0; node < 9; node++) { | |
4182 | switch (node) { | |
4183 | case 8: | |
4184 | tree_left = | |
4185 | count[coef_count_node_start+D153_PRED]; | |
4186 | tree_right = | |
4187 | count[coef_count_node_start+D207_PRED]; | |
4188 | break; | |
4189 | case 7: | |
4190 | tree_left = | |
4191 | count[coef_count_node_start+D63_PRED]; | |
4192 | tree_right = | |
4193 | count[coef_count_node_start+D207_PRED] + | |
4194 | count[coef_count_node_start+D153_PRED]; | |
4195 | break; | |
4196 | case 6: | |
4197 | tree_left = | |
4198 | count[coef_count_node_start + D45_PRED]; | |
4199 | tree_right = | |
4200 | count[coef_count_node_start+D207_PRED] + | |
4201 | count[coef_count_node_start+D153_PRED] + | |
4202 | count[coef_count_node_start+D63_PRED]; | |
4203 | break; | |
4204 | case 5: | |
4205 | tree_left = | |
4206 | count[coef_count_node_start+D135_PRED]; | |
4207 | tree_right = | |
4208 | count[coef_count_node_start+D117_PRED]; | |
4209 | break; | |
4210 | case 4: | |
4211 | tree_left = | |
4212 | count[coef_count_node_start+H_PRED]; | |
4213 | tree_right = | |
4214 | count[coef_count_node_start+D117_PRED] + | |
4215 | count[coef_count_node_start+D135_PRED]; | |
4216 | break; | |
4217 | case 3: | |
4218 | tree_left = | |
4219 | count[coef_count_node_start+H_PRED] + | |
4220 | count[coef_count_node_start+D117_PRED] + | |
4221 | count[coef_count_node_start+D135_PRED]; | |
4222 | tree_right = | |
4223 | count[coef_count_node_start+D45_PRED] + | |
4224 | count[coef_count_node_start+D207_PRED] + | |
4225 | count[coef_count_node_start+D153_PRED] + | |
4226 | count[coef_count_node_start+D63_PRED]; | |
4227 | break; | |
4228 | case 2: | |
4229 | tree_left = | |
4230 | count[coef_count_node_start+V_PRED]; | |
4231 | tree_right = | |
4232 | count[coef_count_node_start+H_PRED] + | |
4233 | count[coef_count_node_start+D117_PRED] + | |
4234 | count[coef_count_node_start+D135_PRED] + | |
4235 | count[coef_count_node_start+D45_PRED] + | |
4236 | count[coef_count_node_start+D207_PRED] + | |
4237 | count[coef_count_node_start+D153_PRED] + | |
4238 | count[coef_count_node_start+D63_PRED]; | |
4239 | break; | |
4240 | case 1: | |
4241 | tree_left = | |
4242 | count[coef_count_node_start+TM_PRED]; | |
4243 | tree_right = | |
4244 | count[coef_count_node_start+V_PRED] + | |
4245 | count[coef_count_node_start+H_PRED] + | |
4246 | count[coef_count_node_start+D117_PRED] + | |
4247 | count[coef_count_node_start+D135_PRED] + | |
4248 | count[coef_count_node_start+D45_PRED] + | |
4249 | count[coef_count_node_start+D207_PRED] + | |
4250 | count[coef_count_node_start+D153_PRED] + | |
4251 | count[coef_count_node_start+D63_PRED]; | |
4252 | break; | |
4253 | default: | |
4254 | tree_left = | |
4255 | count[coef_count_node_start+DC_PRED]; | |
4256 | tree_right = | |
4257 | count[coef_count_node_start+TM_PRED] + | |
4258 | count[coef_count_node_start+V_PRED] + | |
4259 | count[coef_count_node_start+H_PRED] + | |
4260 | count[coef_count_node_start+D117_PRED] + | |
4261 | count[coef_count_node_start+D135_PRED] + | |
4262 | count[coef_count_node_start+D45_PRED] + | |
4263 | count[coef_count_node_start+D207_PRED] + | |
4264 | count[coef_count_node_start+D153_PRED] + | |
4265 | count[coef_count_node_start+D63_PRED]; | |
4266 | break; | |
4267 | ||
4268 | } | |
4269 | ||
4270 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4271 | coef_node_start, tree_left, tree_right, | |
4272 | tree_i, node); | |
4273 | ||
4274 | coef_node_start = coef_node_start + 1; | |
4275 | } | |
4276 | coef_count_node_start = coef_count_node_start + 10; | |
4277 | } | |
4278 | ||
4279 | if (debug & VP9_DEBUG_MERGE) | |
4280 | pr_info(" # merge_vp9_partition_tree\n"); | |
4281 | coef_node_start = VP9_PARTITION_P_START; | |
4282 | coef_count_node_start = VP9_PARTITION_P_COUNT_START; | |
4283 | for (tree_i = 0; tree_i < 16; tree_i++) { | |
4284 | for (node = 0; node < 3; node++) { | |
4285 | switch (node) { | |
4286 | case 2: | |
4287 | tree_left = | |
4288 | count[coef_count_node_start + 2]; | |
4289 | tree_right = | |
4290 | count[coef_count_node_start + 3]; | |
4291 | break; | |
4292 | case 1: | |
4293 | tree_left = | |
4294 | count[coef_count_node_start + 1]; | |
4295 | tree_right = | |
4296 | count[coef_count_node_start + 2] + | |
4297 | count[coef_count_node_start + 3]; | |
4298 | break; | |
4299 | default: | |
4300 | tree_left = | |
4301 | count[coef_count_node_start + 0]; | |
4302 | tree_right = | |
4303 | count[coef_count_node_start + 1] + | |
4304 | count[coef_count_node_start + 2] + | |
4305 | count[coef_count_node_start + 3]; | |
4306 | break; | |
4307 | ||
4308 | } | |
4309 | ||
4310 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4311 | coef_node_start, | |
4312 | tree_left, tree_right, tree_i, node); | |
4313 | ||
4314 | coef_node_start = coef_node_start + 1; | |
4315 | } | |
4316 | coef_count_node_start = coef_count_node_start + 4; | |
4317 | } | |
4318 | ||
4319 | if (debug & VP9_DEBUG_MERGE) | |
4320 | pr_info(" # merge_vp9_switchable_interp_tree\n"); | |
4321 | coef_node_start = VP9_INTERP_START; | |
4322 | coef_count_node_start = VP9_INTERP_COUNT_START; | |
4323 | for (tree_i = 0; tree_i < 4; tree_i++) { | |
4324 | for (node = 0; node < 2; node++) { | |
4325 | switch (node) { | |
4326 | case 1: | |
4327 | tree_left = | |
4328 | count[coef_count_node_start + 1]; | |
4329 | tree_right = | |
4330 | count[coef_count_node_start + 2]; | |
4331 | break; | |
4332 | default: | |
4333 | tree_left = | |
4334 | count[coef_count_node_start + 0]; | |
4335 | tree_right = | |
4336 | count[coef_count_node_start + 1] + | |
4337 | count[coef_count_node_start + 2]; | |
4338 | break; | |
4339 | ||
4340 | } | |
4341 | ||
4342 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4343 | coef_node_start, | |
4344 | tree_left, tree_right, tree_i, node); | |
4345 | ||
4346 | coef_node_start = coef_node_start + 1; | |
4347 | } | |
4348 | coef_count_node_start = coef_count_node_start + 3; | |
4349 | } | |
4350 | ||
4351 | if (debug & VP9_DEBUG_MERGE) | |
4352 | pr_info("# merge_vp9_mv_joint_tree\n"); | |
4353 | coef_node_start = VP9_MV_JOINTS_START; | |
4354 | coef_count_node_start = VP9_MV_JOINTS_COUNT_START; | |
4355 | for (tree_i = 0; tree_i < 1; tree_i++) { | |
4356 | for (node = 0; node < 3; node++) { | |
4357 | switch (node) { | |
4358 | case 2: | |
4359 | tree_left = | |
4360 | count[coef_count_node_start + 2]; | |
4361 | tree_right = | |
4362 | count[coef_count_node_start + 3]; | |
4363 | break; | |
4364 | case 1: | |
4365 | tree_left = | |
4366 | count[coef_count_node_start + 1]; | |
4367 | tree_right = | |
4368 | count[coef_count_node_start + 2] + | |
4369 | count[coef_count_node_start + 3]; | |
4370 | break; | |
4371 | default: | |
4372 | tree_left = | |
4373 | count[coef_count_node_start + 0]; | |
4374 | tree_right = | |
4375 | count[coef_count_node_start + 1] + | |
4376 | count[coef_count_node_start + 2] + | |
4377 | count[coef_count_node_start + 3]; | |
4378 | break; | |
4379 | } | |
4380 | ||
4381 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4382 | coef_node_start, | |
4383 | tree_left, tree_right, tree_i, node); | |
4384 | ||
4385 | coef_node_start = coef_node_start + 1; | |
4386 | } | |
4387 | coef_count_node_start = coef_count_node_start + 4; | |
4388 | } | |
4389 | ||
4390 | for (mvd_i = 0; mvd_i < 2; mvd_i++) { | |
4391 | if (debug & VP9_DEBUG_MERGE) | |
4392 | pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i); | |
4393 | coef_node_start = | |
4394 | mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START; | |
4395 | coef_count_node_start = | |
4396 | mvd_i ? VP9_MV_CLASSES_1_COUNT_START | |
4397 | : VP9_MV_CLASSES_0_COUNT_START; | |
4398 | tree_i = 0; | |
4399 | for (node = 0; node < 10; node++) { | |
4400 | switch (node) { | |
4401 | case 9: | |
4402 | tree_left = | |
4403 | count[coef_count_node_start + 9]; | |
4404 | tree_right = | |
4405 | count[coef_count_node_start + 10]; | |
4406 | break; | |
4407 | case 8: | |
4408 | tree_left = | |
4409 | count[coef_count_node_start + 7]; | |
4410 | tree_right = | |
4411 | count[coef_count_node_start + 8]; | |
4412 | break; | |
4413 | case 7: | |
4414 | tree_left = | |
4415 | count[coef_count_node_start + 7] + | |
4416 | count[coef_count_node_start + 8]; | |
4417 | tree_right = | |
4418 | count[coef_count_node_start + 9] + | |
4419 | count[coef_count_node_start + 10]; | |
4420 | break; | |
4421 | case 6: | |
4422 | tree_left = | |
4423 | count[coef_count_node_start + 6]; | |
4424 | tree_right = | |
4425 | count[coef_count_node_start + 7] + | |
4426 | count[coef_count_node_start + 8] + | |
4427 | count[coef_count_node_start + 9] + | |
4428 | count[coef_count_node_start + 10]; | |
4429 | break; | |
4430 | case 5: | |
4431 | tree_left = | |
4432 | count[coef_count_node_start + 4]; | |
4433 | tree_right = | |
4434 | count[coef_count_node_start + 5]; | |
4435 | break; | |
4436 | case 4: | |
4437 | tree_left = | |
4438 | count[coef_count_node_start + 4] + | |
4439 | count[coef_count_node_start + 5]; | |
4440 | tree_right = | |
4441 | count[coef_count_node_start + 6] + | |
4442 | count[coef_count_node_start + 7] + | |
4443 | count[coef_count_node_start + 8] + | |
4444 | count[coef_count_node_start + 9] + | |
4445 | count[coef_count_node_start + 10]; | |
4446 | break; | |
4447 | case 3: | |
4448 | tree_left = | |
4449 | count[coef_count_node_start + 2]; | |
4450 | tree_right = | |
4451 | count[coef_count_node_start + 3]; | |
4452 | break; | |
4453 | case 2: | |
4454 | tree_left = | |
4455 | count[coef_count_node_start + 2] + | |
4456 | count[coef_count_node_start + 3]; | |
4457 | tree_right = | |
4458 | count[coef_count_node_start + 4] + | |
4459 | count[coef_count_node_start + 5] + | |
4460 | count[coef_count_node_start + 6] + | |
4461 | count[coef_count_node_start + 7] + | |
4462 | count[coef_count_node_start + 8] + | |
4463 | count[coef_count_node_start + 9] + | |
4464 | count[coef_count_node_start + 10]; | |
4465 | break; | |
4466 | case 1: | |
4467 | tree_left = | |
4468 | count[coef_count_node_start + 1]; | |
4469 | tree_right = | |
4470 | count[coef_count_node_start + 2] + | |
4471 | count[coef_count_node_start + 3] + | |
4472 | count[coef_count_node_start + 4] + | |
4473 | count[coef_count_node_start + 5] + | |
4474 | count[coef_count_node_start + 6] + | |
4475 | count[coef_count_node_start + 7] + | |
4476 | count[coef_count_node_start + 8] + | |
4477 | count[coef_count_node_start + 9] + | |
4478 | count[coef_count_node_start + 10]; | |
4479 | break; | |
4480 | default: | |
4481 | tree_left = | |
4482 | count[coef_count_node_start + 0]; | |
4483 | tree_right = | |
4484 | count[coef_count_node_start + 1] + | |
4485 | count[coef_count_node_start + 2] + | |
4486 | count[coef_count_node_start + 3] + | |
4487 | count[coef_count_node_start + 4] + | |
4488 | count[coef_count_node_start + 5] + | |
4489 | count[coef_count_node_start + 6] + | |
4490 | count[coef_count_node_start + 7] + | |
4491 | count[coef_count_node_start + 8] + | |
4492 | count[coef_count_node_start + 9] + | |
4493 | count[coef_count_node_start + 10]; | |
4494 | break; | |
4495 | ||
4496 | } | |
4497 | ||
4498 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4499 | coef_node_start, tree_left, tree_right, | |
4500 | tree_i, node); | |
4501 | ||
4502 | coef_node_start = coef_node_start + 1; | |
4503 | } | |
4504 | ||
4505 | if (debug & VP9_DEBUG_MERGE) | |
4506 | pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i); | |
4507 | coef_node_start = | |
4508 | mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START; | |
4509 | coef_count_node_start = | |
4510 | mvd_i ? VP9_MV_CLASS0_1_COUNT_START : | |
4511 | VP9_MV_CLASS0_0_COUNT_START; | |
4512 | tree_i = 0; | |
4513 | node = 0; | |
4514 | tree_left = count[coef_count_node_start + 0]; | |
4515 | tree_right = count[coef_count_node_start + 1]; | |
4516 | ||
4517 | vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start, | |
4518 | tree_left, tree_right, tree_i, node); | |
4519 | if (debug & VP9_DEBUG_MERGE) | |
4520 | pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n", | |
4521 | mvd_i); | |
4522 | coef_node_start = | |
4523 | mvd_i ? VP9_MV_CLASS0_FP_1_START : | |
4524 | VP9_MV_CLASS0_FP_0_START; | |
4525 | coef_count_node_start = | |
4526 | mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START : | |
4527 | VP9_MV_CLASS0_FP_0_COUNT_START; | |
4528 | for (tree_i = 0; tree_i < 3; tree_i++) { | |
4529 | for (node = 0; node < 3; node++) { | |
4530 | switch (node) { | |
4531 | case 2: | |
4532 | tree_left = | |
4533 | count[coef_count_node_start + 2]; | |
4534 | tree_right = | |
4535 | count[coef_count_node_start + 3]; | |
4536 | break; | |
4537 | case 1: | |
4538 | tree_left = | |
4539 | count[coef_count_node_start + 1]; | |
4540 | tree_right = | |
4541 | count[coef_count_node_start + 2] | |
4542 | + count[coef_count_node_start + 3]; | |
4543 | break; | |
4544 | default: | |
4545 | tree_left = | |
4546 | count[coef_count_node_start + 0]; | |
4547 | tree_right = | |
4548 | count[coef_count_node_start + 1] | |
4549 | + count[coef_count_node_start + 2] | |
4550 | + count[coef_count_node_start + 3]; | |
4551 | break; | |
4552 | ||
4553 | } | |
4554 | ||
4555 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4556 | coef_node_start, tree_left, tree_right, | |
4557 | tree_i, node); | |
4558 | ||
4559 | coef_node_start = coef_node_start + 1; | |
4560 | } | |
4561 | coef_count_node_start = coef_count_node_start + 4; | |
4562 | } | |
4563 | ||
4564 | } /* for mvd_i (mvd_y or mvd_x)*/ | |
4565 | } | |
4566 | ||
4567 | } | |
4568 | ||
4569 | ||
4570 | static void uninit_mmu_buffers(struct VP9Decoder_s *pbi) | |
4571 | { | |
fe96802b NQ |
4572 | #ifndef MV_USE_FIXED_BUF |
4573 | dealloc_mv_bufs(pbi); | |
4574 | #endif | |
b7706e1e | 4575 | if (pbi->mmu_box) |
4576 | decoder_mmu_box_free(pbi->mmu_box); | |
b9164398 NQ |
4577 | pbi->mmu_box = NULL; |
4578 | ||
4579 | if (pbi->bmmu_box) | |
4580 | decoder_bmmu_box_free(pbi->bmmu_box); | |
4581 | pbi->bmmu_box = NULL; | |
4582 | } | |
4583 | ||
a6c89e96 NQ |
4584 | |
4585 | static int config_pic(struct VP9Decoder_s *pbi, | |
4586 | struct PIC_BUFFER_CONFIG_s *pic_config) | |
4587 | { | |
4588 | int ret = -1; | |
4589 | int i; | |
4590 | int pic_width = pbi->init_pic_w; | |
4591 | int pic_height = pbi->init_pic_h; | |
4592 | int lcu_size = 64; /*fixed 64*/ | |
4593 | int pic_width_64 = (pic_width + 63) & (~0x3f); | |
4594 | int pic_height_32 = (pic_height + 31) & (~0x1f); | |
4595 | int pic_width_lcu = (pic_width_64 % lcu_size) ? | |
4596 | pic_width_64 / lcu_size + 1 | |
4597 | : pic_width_64 / lcu_size; | |
4598 | int pic_height_lcu = (pic_height_32 % lcu_size) ? | |
4599 | pic_height_32 / lcu_size + 1 | |
4600 | : pic_height_32 / lcu_size; | |
4601 | int lcu_total = pic_width_lcu * pic_height_lcu; | |
4602 | #ifdef MV_USE_FIXED_BUF | |
4603 | u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start + | |
4604 | pbi->work_space_buf->mpred_mv.buf_size; | |
4605 | #endif | |
4606 | u32 y_adr = 0; | |
4607 | int buf_size = 0; | |
4608 | ||
4609 | int losless_comp_header_size = | |
4610 | compute_losless_comp_header_size(pic_width, | |
4611 | pic_height); | |
4612 | int losless_comp_body_size = compute_losless_comp_body_size(pic_width, | |
4613 | pic_height, buf_alloc_depth == 10); | |
4614 | int mc_buffer_size = losless_comp_header_size + losless_comp_body_size; | |
4615 | int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16; | |
4616 | int mc_buffer_size_u_v = 0; | |
4617 | int mc_buffer_size_u_v_h = 0; | |
4618 | int dw_mode = get_double_write_mode_init(pbi); | |
2cd6815e | 4619 | struct vdec_fb *fb = NULL; |
a6c89e96 NQ |
4620 | |
4621 | pbi->lcu_total = lcu_total; | |
4622 | ||
4623 | if (dw_mode) { | |
4624 | int pic_width_dw = pic_width / | |
4625 | get_double_write_ratio(pbi, dw_mode); | |
4626 | int pic_height_dw = pic_height / | |
4627 | get_double_write_ratio(pbi, dw_mode); | |
4628 | ||
4629 | int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f); | |
4630 | int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f); | |
4631 | int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ? | |
4632 | pic_width_64_dw / lcu_size + 1 | |
4633 | : pic_width_64_dw / lcu_size; | |
4634 | int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ? | |
b9164398 NQ |
4635 | pic_height_32_dw / lcu_size + 1 |
4636 | : pic_height_32_dw / lcu_size; | |
4637 | int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw; | |
b9164398 NQ |
4638 | mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2; |
4639 | mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16; | |
4640 | /*64k alignment*/ | |
4641 | buf_size = ((mc_buffer_size_u_v_h << 16) * 3); | |
4642 | buf_size = ((buf_size + 0xffff) >> 16) << 16; | |
4643 | } | |
b34d6d3e | 4644 | |
b9164398 NQ |
4645 | if (mc_buffer_size & 0xffff) /*64k alignment*/ |
4646 | mc_buffer_size_h += 1; | |
b7706e1e | 4647 | if ((!pbi->mmu_enable) && ((dw_mode & 0x10) == 0)) |
b9164398 | 4648 | buf_size += (mc_buffer_size_h << 16); |
b9164398 | 4649 | |
b7706e1e | 4650 | |
4651 | if (pbi->mmu_enable) { | |
4652 | pic_config->header_adr = decoder_bmmu_box_get_phy_addr( | |
a6c89e96 | 4653 | pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index)); |
b9164398 | 4654 | |
b7706e1e | 4655 | if (debug & VP9_DEBUG_BUFMGR_MORE) { |
4656 | pr_info("MMU header_adr %d: %ld\n", | |
4657 | pic_config->index, pic_config->header_adr); | |
4658 | } | |
b9164398 | 4659 | } |
b9164398 NQ |
4660 | |
4661 | i = pic_config->index; | |
fe96802b | 4662 | #ifdef MV_USE_FIXED_BUF |
b9164398 NQ |
4663 | if ((pbi->work_space_buf->mpred_mv.buf_start + |
4664 | (((i + 1) * lcu_total) * MV_MEM_UNIT)) | |
4665 | <= mpred_mv_end | |
b9164398 | 4666 | ) { |
fe96802b | 4667 | #endif |
a6c89e96 | 4668 | if (buf_size > 0) { |
2cd6815e NQ |
4669 | if (pbi->is_used_v4l) { |
4670 | ret = v4l_get_fb(pbi->v4l2_ctx, &fb); | |
4671 | if (ret) { | |
9495ddb6 NQ |
4672 | vp9_print(pbi, PRINT_FLAG_ERROR, |
4673 | "[%d] get fb fail.\n", | |
2cd6815e NQ |
4674 | ((struct aml_vcodec_ctx *) |
4675 | (pbi->v4l2_ctx))->id); | |
4676 | return ret; | |
4677 | } | |
4678 | ||
4679 | pbi->m_BUF[i].v4l_ref_buf_addr = (ulong)fb; | |
4680 | pic_config->cma_alloc_addr = | |
4681 | virt_to_phys(fb->base_y.va); | |
4682 | vp9_print(pbi, PRINT_FLAG_V4L_DETAIL, | |
4683 | "[%d] %s(), v4l ref buf addr: 0x%x\n", | |
4684 | ((struct aml_vcodec_ctx *) | |
4685 | (pbi->v4l2_ctx))->id, __func__, fb); | |
4686 | } else { | |
4687 | ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, | |
4688 | VF_BUFFER_IDX(i), | |
4689 | buf_size, DRIVER_NAME, | |
4690 | &pic_config->cma_alloc_addr); | |
4691 | if (ret < 0) { | |
4692 | pr_info( | |
4693 | "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n", | |
4694 | VF_BUFFER_IDX(i), | |
4695 | buf_size | |
4696 | ); | |
4697 | return ret; | |
4698 | } | |
a6c89e96 NQ |
4699 | } |
4700 | ||
4701 | if (pic_config->cma_alloc_addr) | |
4702 | y_adr = pic_config->cma_alloc_addr; | |
4703 | else { | |
4704 | pr_info( | |
4705 | "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n", | |
4706 | VF_BUFFER_IDX(i), | |
4707 | buf_size | |
4708 | ); | |
4709 | return -1; | |
4710 | } | |
b34d6d3e | 4711 | } |
a6c89e96 NQ |
4712 | { |
4713 | /*ensure get_pic_by_POC() | |
4714 | not get the buffer not decoded*/ | |
4715 | pic_config->BUF_index = i; | |
4716 | pic_config->lcu_total = lcu_total; | |
4717 | ||
4718 | pic_config->comp_body_size = losless_comp_body_size; | |
4719 | pic_config->buf_size = buf_size; | |
b7706e1e | 4720 | |
a6c89e96 NQ |
4721 | pic_config->mc_canvas_y = pic_config->index; |
4722 | pic_config->mc_canvas_u_v = pic_config->index; | |
a6c89e96 | 4723 | if (dw_mode & 0x10) { |
b7706e1e | 4724 | pic_config->dw_y_adr = y_adr; |
4725 | pic_config->dw_u_v_adr = y_adr + | |
4726 | ((mc_buffer_size_u_v_h << 16) << 1); | |
a6c89e96 NQ |
4727 | |
4728 | pic_config->mc_canvas_y = | |
4729 | (pic_config->index << 1); | |
4730 | pic_config->mc_canvas_u_v = | |
4731 | (pic_config->index << 1) + 1; | |
b7706e1e | 4732 | } else if (dw_mode) { |
a6c89e96 | 4733 | pic_config->dw_y_adr = y_adr; |
a6c89e96 | 4734 | pic_config->dw_u_v_adr = pic_config->dw_y_adr + |
b7706e1e | 4735 | ((mc_buffer_size_u_v_h << 16) << 1); |
a6c89e96 | 4736 | } |
fe96802b | 4737 | #ifdef MV_USE_FIXED_BUF |
a6c89e96 NQ |
4738 | pic_config->mpred_mv_wr_start_addr = |
4739 | pbi->work_space_buf->mpred_mv.buf_start + | |
4740 | ((pic_config->index * lcu_total) | |
4741 | * MV_MEM_UNIT); | |
fe96802b | 4742 | #endif |
a6c89e96 NQ |
4743 | if (debug) { |
4744 | pr_info | |
b7706e1e | 4745 | ("%s index %d BUF_index %d ", |
a6c89e96 | 4746 | __func__, pic_config->index, |
b7706e1e | 4747 | pic_config->BUF_index); |
a6c89e96 NQ |
4748 | pr_info |
4749 | ("comp_body_size %x comp_buf_size %x ", | |
4750 | pic_config->comp_body_size, | |
4751 | pic_config->buf_size); | |
4752 | pr_info | |
4753 | ("mpred_mv_wr_start_adr %ld\n", | |
4754 | pic_config->mpred_mv_wr_start_addr); | |
4755 | pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n", | |
4756 | pic_config->dw_y_adr, | |
4757 | pic_config->dw_u_v_adr); | |
4758 | } | |
4759 | ret = 0; | |
b9164398 | 4760 | } |
fe96802b | 4761 | #ifdef MV_USE_FIXED_BUF |
b9164398 | 4762 | } |
fe96802b | 4763 | #endif |
b9164398 NQ |
4764 | return ret; |
4765 | } | |
4766 | ||
e0e39311 | 4767 | static int vvp9_mmu_compress_header_size(struct VP9Decoder_s *pbi) |
4768 | { | |
6f5ee885 | 4769 | if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) && |
e0e39311 | 4770 | IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h)) |
4771 | return (MMU_COMPRESS_8K_HEADER_SIZE); | |
4772 | ||
4773 | return (MMU_COMPRESS_HEADER_SIZE); | |
4774 | } | |
4775 | ||
4776 | /*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/ | |
4777 | static int vvp9_frame_mmu_map_size(struct VP9Decoder_s *pbi) | |
4778 | { | |
6f5ee885 | 4779 | if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) && |
e0e39311 | 4780 | IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h)) |
4781 | return (MAX_FRAME_8K_NUM * 4); | |
4782 | ||
4783 | return (MAX_FRAME_4K_NUM * 4); | |
4784 | } | |
4785 | ||
4786 | ||
b9164398 NQ |
4787 | static void init_pic_list(struct VP9Decoder_s *pbi) |
4788 | { | |
4789 | int i; | |
4790 | struct VP9_Common_s *cm = &pbi->common; | |
4791 | struct PIC_BUFFER_CONFIG_s *pic_config; | |
df841122 | 4792 | u32 header_size; |
05afa03d | 4793 | struct vdec_s *vdec = hw_to_vdec(pbi); |
2cd6815e | 4794 | |
6276f4ff | 4795 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
e0e39311 | 4796 | header_size = vvp9_mmu_compress_header_size(pbi); |
b7706e1e | 4797 | /*alloc VP9 compress header first*/ |
4798 | for (i = 0; i < pbi->used_buf_num; i++) { | |
4799 | unsigned long buf_addr; | |
4800 | if (decoder_bmmu_box_alloc_buf_phy | |
a6c89e96 | 4801 | (pbi->bmmu_box, |
df841122 | 4802 | HEADER_BUFFER_IDX(i), header_size, |
a6c89e96 | 4803 | DRIVER_HEADER_NAME, |
b7706e1e | 4804 | &buf_addr) < 0) { |
4805 | pr_info("%s malloc compress header failed %d\n", | |
a6c89e96 | 4806 | DRIVER_HEADER_NAME, i); |
b7706e1e | 4807 | pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM; |
4808 | return; | |
4809 | } | |
b9164398 NQ |
4810 | } |
4811 | } | |
fe96802b | 4812 | for (i = 0; i < pbi->used_buf_num; i++) { |
b9164398 NQ |
4813 | pic_config = &cm->buffer_pool->frame_bufs[i].buf; |
4814 | pic_config->index = i; | |
4815 | pic_config->BUF_index = -1; | |
fe96802b | 4816 | pic_config->mv_buf_index = -1; |
05afa03d PY |
4817 | if (vdec->parallel_dec == 1) { |
4818 | pic_config->y_canvas_index = -1; | |
4819 | pic_config->uv_canvas_index = -1; | |
4820 | } | |
fe96802b | 4821 | if (config_pic(pbi, pic_config) < 0) { |
b9164398 NQ |
4822 | if (debug) |
4823 | pr_info("Config_pic %d fail\n", | |
4824 | pic_config->index); | |
4825 | pic_config->index = -1; | |
4826 | break; | |
4827 | } | |
4828 | pic_config->y_crop_width = pbi->init_pic_w; | |
4829 | pic_config->y_crop_height = pbi->init_pic_h; | |
b7706e1e | 4830 | pic_config->double_write_mode = get_double_write_mode(pbi); |
2cd6815e | 4831 | |
b7706e1e | 4832 | if (pic_config->double_write_mode) { |
4833 | set_canvas(pbi, pic_config); | |
4834 | } | |
b9164398 | 4835 | } |
fe96802b | 4836 | for (; i < pbi->used_buf_num; i++) { |
b9164398 NQ |
4837 | pic_config = &cm->buffer_pool->frame_bufs[i].buf; |
4838 | pic_config->index = -1; | |
4839 | pic_config->BUF_index = -1; | |
fe96802b | 4840 | pic_config->mv_buf_index = -1; |
05afa03d PY |
4841 | if (vdec->parallel_dec == 1) { |
4842 | pic_config->y_canvas_index = -1; | |
4843 | pic_config->uv_canvas_index = -1; | |
4844 | } | |
b9164398 | 4845 | } |
fe96802b NQ |
4846 | pr_info("%s ok, used_buf_num = %d\n", |
4847 | __func__, pbi->used_buf_num); | |
b9164398 NQ |
4848 | |
4849 | } | |
4850 | ||
b9164398 NQ |
4851 | static void init_pic_list_hw(struct VP9Decoder_s *pbi) |
4852 | { | |
4853 | int i; | |
4854 | struct VP9_Common_s *cm = &pbi->common; | |
4855 | struct PIC_BUFFER_CONFIG_s *pic_config; | |
4856 | /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/ | |
4857 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, | |
4858 | (0x1 << 1) | (0x1 << 2)); | |
4859 | ||
4860 | ||
fe96802b | 4861 | for (i = 0; i < pbi->used_buf_num; i++) { |
b9164398 NQ |
4862 | pic_config = &cm->buffer_pool->frame_bufs[i].buf; |
4863 | if (pic_config->index < 0) | |
4864 | break; | |
4865 | ||
6276f4ff HZ |
4866 | if (pbi->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) { |
4867 | ||
b7706e1e | 4868 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, |
4869 | pic_config->header_adr >> 5); | |
4870 | } else { | |
4871 | /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, | |
4872 | * pic_config->mc_y_adr | |
4873 | * | (pic_config->mc_canvas_y << 8) | 0x1); | |
4874 | */ | |
4875 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, | |
4876 | pic_config->dw_y_adr >> 5); | |
4877 | } | |
a6c89e96 | 4878 | #ifndef LOSLESS_COMPRESS_MODE |
b7706e1e | 4879 | /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, |
4880 | * pic_config->mc_u_v_adr | |
4881 | * | (pic_config->mc_canvas_u_v << 8)| 0x1); | |
4882 | */ | |
6276f4ff | 4883 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, |
b7706e1e | 4884 | pic_config->header_adr >> 5); |
4885 | #else | |
4886 | if (pic_config->double_write_mode & 0x10) { | |
b7706e1e | 4887 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, |
4888 | pic_config->dw_u_v_adr >> 5); | |
4889 | } | |
b9164398 NQ |
4890 | #endif |
4891 | } | |
4892 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1); | |
4893 | ||
4894 | /*Zero out canvas registers in IPP -- avoid simulation X*/ | |
4895 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, | |
4896 | (0 << 8) | (0 << 1) | 1); | |
4897 | for (i = 0; i < 32; i++) | |
4898 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0); | |
4899 | } | |
4900 | ||
4901 | ||
4902 | static void dump_pic_list(struct VP9Decoder_s *pbi) | |
4903 | { | |
fe96802b NQ |
4904 | struct VP9_Common_s *const cm = &pbi->common; |
4905 | struct PIC_BUFFER_CONFIG_s *pic_config; | |
4906 | int i; | |
4907 | for (i = 0; i < FRAME_BUFFERS; i++) { | |
4908 | pic_config = &cm->buffer_pool->frame_bufs[i].buf; | |
4909 | vp9_print(pbi, 0, | |
a6c89e96 | 4910 | "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n", |
fe96802b NQ |
4911 | i, |
4912 | pic_config->index, | |
4913 | #ifndef MV_USE_FIXED_BUF | |
4914 | pic_config->mv_buf_index, | |
4915 | #else | |
4916 | -1, | |
4917 | #endif | |
a6c89e96 NQ |
4918 | cm->buffer_pool-> |
4919 | frame_bufs[i].ref_count, | |
fe96802b NQ |
4920 | pic_config->vf_ref, |
4921 | pic_config->decode_idx, | |
4922 | pic_config->slice_type, | |
4923 | pic_config->y_crop_width, | |
4924 | pic_config->y_crop_height, | |
4925 | pic_config->cma_alloc_addr | |
4926 | ); | |
4927 | } | |
b9164398 NQ |
4928 | return; |
4929 | } | |
4930 | ||
4931 | static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth) | |
4932 | { | |
4933 | #ifdef LOSLESS_COMPRESS_MODE | |
4934 | unsigned int data32; | |
4935 | #endif | |
4936 | int losless_comp_header_size, losless_comp_body_size; | |
4937 | struct VP9_Common_s *cm = &pbi->common; | |
4938 | struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf; | |
e0614bf7 | 4939 | |
b9164398 NQ |
4940 | frame_width = cur_pic_config->y_crop_width; |
4941 | frame_height = cur_pic_config->y_crop_height; | |
4942 | cur_pic_config->bit_depth = bit_depth; | |
c23e8aee | 4943 | cur_pic_config->double_write_mode = get_double_write_mode(pbi); |
b9164398 NQ |
4944 | losless_comp_header_size = |
4945 | compute_losless_comp_header_size(cur_pic_config->y_crop_width, | |
4946 | cur_pic_config->y_crop_height); | |
4947 | losless_comp_body_size = | |
4948 | compute_losless_comp_body_size(cur_pic_config->y_crop_width, | |
4949 | cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10)); | |
4950 | cur_pic_config->comp_body_size = losless_comp_body_size; | |
4951 | #ifdef LOSLESS_COMPRESS_MODE | |
4952 | data32 = READ_VREG(HEVC_SAO_CTRL5); | |
4953 | if (bit_depth == VPX_BITS_10) | |
4954 | data32 &= ~(1 << 9); | |
4955 | else | |
4956 | data32 |= (1 << 9); | |
4957 | ||
4958 | WRITE_VREG(HEVC_SAO_CTRL5, data32); | |
4959 | ||
b7706e1e | 4960 | if (pbi->mmu_enable) { |
4961 | /*bit[4] : paged_mem_mode*/ | |
4962 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4)); | |
4963 | } else { | |
b9164398 | 4964 | /*bit[3] smem mdoe*/ |
b7706e1e | 4965 | if (bit_depth == VPX_BITS_10) |
4966 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3)); | |
4967 | else | |
4968 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3)); | |
4969 | } | |
6f5ee885 | 4970 | if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1) |
df841122 | 4971 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5)); |
b9164398 NQ |
4972 | /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/ |
4973 | WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size); | |
4974 | WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size); | |
4975 | WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size); | |
b7706e1e | 4976 | if (get_double_write_mode(pbi) & 0x10) |
4977 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); | |
b9164398 NQ |
4978 | #else |
4979 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); | |
4980 | #endif | |
4981 | return 0; | |
4982 | } | |
4983 | ||
4984 | static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth) | |
4985 | { | |
4986 | int i; | |
4987 | struct VP9_Common_s *cm = &pbi->common; | |
4988 | struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf; | |
4989 | uint8_t scale_enable = 0; | |
4990 | ||
fe96802b | 4991 | if (debug&VP9_DEBUG_BUFMGR_MORE) |
b9164398 NQ |
4992 | pr_info("config_mc_buffer entered .....\n"); |
4993 | ||
4994 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, | |
4995 | (0 << 8) | (0 << 1) | 1); | |
4996 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
4997 | struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf; | |
fe96802b NQ |
4998 | if (!pic_config) |
4999 | continue; | |
b9164398 NQ |
5000 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, |
5001 | (pic_config->mc_canvas_u_v << 16) | |
5002 | | (pic_config->mc_canvas_u_v << 8) | |
5003 | | pic_config->mc_canvas_y); | |
5004 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
5005 | pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n", | |
5006 | i, pic_config->mc_canvas_u_v, | |
5007 | pic_config->mc_canvas_y); | |
5008 | } | |
5009 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, | |
5010 | (16 << 8) | (0 << 1) | 1); | |
5011 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
5012 | struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf; | |
fe96802b NQ |
5013 | if (!pic_config) |
5014 | continue; | |
b9164398 NQ |
5015 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, |
5016 | (pic_config->mc_canvas_u_v << 16) | |
5017 | | (pic_config->mc_canvas_u_v << 8) | |
5018 | | pic_config->mc_canvas_y); | |
5019 | } | |
5020 | ||
5021 | /*auto_inc start index:0 field:0*/ | |
5022 | WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2); | |
5023 | /*index 0:last 1:golden 2:altref*/ | |
5024 | for (i = 0; i < REFS_PER_FRAME; i++) { | |
5025 | int ref_pic_body_size; | |
5026 | struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf; | |
fe96802b NQ |
5027 | if (!pic_config) |
5028 | continue; | |
b9164398 NQ |
5029 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width); |
5030 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height); | |
5031 | ||
5032 | if (pic_config->y_crop_width != cur_pic_config->y_crop_width || | |
5033 | pic_config->y_crop_height != cur_pic_config->y_crop_height) { | |
5034 | scale_enable |= (1 << i); | |
5035 | } | |
5036 | ref_pic_body_size = | |
5037 | compute_losless_comp_body_size(pic_config->y_crop_width, | |
5038 | pic_config->y_crop_height, (bit_depth == VPX_BITS_10)); | |
5039 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, | |
5040 | (pic_config->y_crop_width << 14) | |
5041 | / cur_pic_config->y_crop_width); | |
5042 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, | |
5043 | (pic_config->y_crop_height << 14) | |
5044 | / cur_pic_config->y_crop_height); | |
b7706e1e | 5045 | if (pbi->mmu_enable) |
5046 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0); | |
5047 | else | |
5048 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5); | |
b9164398 NQ |
5049 | } |
5050 | WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable); | |
5051 | return 0; | |
5052 | } | |
5053 | ||
5054 | static void clear_mpred_hw(struct VP9Decoder_s *pbi) | |
5055 | { | |
5056 | unsigned int data32; | |
e0614bf7 | 5057 | |
b9164398 NQ |
5058 | data32 = READ_VREG(HEVC_MPRED_CTRL4); |
5059 | data32 &= (~(1 << 6)); | |
5060 | WRITE_VREG(HEVC_MPRED_CTRL4, data32); | |
5061 | } | |
5062 | ||
5063 | static void config_mpred_hw(struct VP9Decoder_s *pbi) | |
5064 | { | |
5065 | struct VP9_Common_s *cm = &pbi->common; | |
5066 | struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf; | |
5067 | struct PIC_BUFFER_CONFIG_s *last_frame_pic_config = | |
5068 | &cm->prev_frame->buf; | |
5069 | ||
5070 | unsigned int data32; | |
5071 | int mpred_curr_lcu_x; | |
5072 | int mpred_curr_lcu_y; | |
5073 | int mpred_mv_rd_end_addr; | |
b9164398 NQ |
5074 | |
5075 | ||
5076 | mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr | |
5077 | + (last_frame_pic_config->lcu_total * MV_MEM_UNIT); | |
5078 | ||
5079 | data32 = READ_VREG(HEVC_MPRED_CURR_LCU); | |
5080 | mpred_curr_lcu_x = data32 & 0xffff; | |
5081 | mpred_curr_lcu_y = (data32 >> 16) & 0xffff; | |
5082 | ||
5083 | if (debug & VP9_DEBUG_BUFMGR) | |
5084 | pr_info("cur pic_config index %d col pic_config index %d\n", | |
5085 | cur_pic_config->index, last_frame_pic_config->index); | |
5086 | WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412); | |
5087 | WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, | |
5088 | pbi->work_space_buf->mpred_above.buf_start); | |
5089 | ||
5090 | data32 = READ_VREG(HEVC_MPRED_CTRL4); | |
5091 | ||
5092 | data32 &= (~(1 << 6)); | |
5093 | data32 |= (cm->use_prev_frame_mvs << 6); | |
5094 | WRITE_VREG(HEVC_MPRED_CTRL4, data32); | |
5095 | ||
5096 | WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR, | |
5097 | cur_pic_config->mpred_mv_wr_start_addr); | |
5098 | WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr); | |
5099 | ||
5100 | WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR, | |
5101 | last_frame_pic_config->mpred_mv_wr_start_addr); | |
5102 | WRITE_VREG(HEVC_MPRED_MV_RPTR, | |
5103 | last_frame_pic_config->mpred_mv_wr_start_addr); | |
5104 | /*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/ | |
5105 | /*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/ | |
5106 | /*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/ | |
5107 | WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr); | |
5108 | ||
5109 | } | |
5110 | ||
5111 | static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params) | |
5112 | { | |
5113 | struct VP9_Common_s *cm = &pbi->common; | |
5114 | struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf; | |
5115 | ||
5116 | unsigned int data32; | |
5117 | int lcu_size = 64; | |
5118 | int mc_buffer_size_u_v = | |
5119 | pic_config->lcu_total * lcu_size*lcu_size/2; | |
5120 | int mc_buffer_size_u_v_h = | |
5121 | (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/ | |
5122 | ||
b7706e1e | 5123 | |
fe96802b | 5124 | if (get_double_write_mode(pbi)) { |
b9164398 NQ |
5125 | WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr); |
5126 | WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr); | |
5127 | WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr); | |
5128 | WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr); | |
5129 | } else { | |
5130 | WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff); | |
5131 | WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff); | |
5132 | } | |
b7706e1e | 5133 | if (pbi->mmu_enable) |
5134 | WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr); | |
5135 | ||
b9164398 NQ |
5136 | data32 = (mc_buffer_size_u_v_h << 16) << 1; |
5137 | /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n", | |
e0614bf7 ZZ |
5138 | * data32, mc_buffer_size_u_v_h, pic_config->lcu_total); |
5139 | */ | |
b9164398 NQ |
5140 | WRITE_VREG(HEVC_SAO_Y_LENGTH, data32); |
5141 | ||
5142 | data32 = (mc_buffer_size_u_v_h << 16); | |
5143 | WRITE_VREG(HEVC_SAO_C_LENGTH, data32); | |
5144 | ||
5145 | #ifdef VP9_10B_NV21 | |
5146 | #ifdef DOS_PROJECT | |
5147 | data32 = READ_VREG(HEVC_SAO_CTRL1); | |
5148 | data32 &= (~0x3000); | |
5149 | /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/ | |
3a5df697 | 5150 | data32 |= (mem_map_mode << 12); |
b9164398 NQ |
5151 | data32 &= (~0x3); |
5152 | data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/ | |
5153 | WRITE_VREG(HEVC_SAO_CTRL1, data32); | |
5154 | /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl | |
e0614bf7 ZZ |
5155 | * [17:16] dw_h0_ctrl |
5156 | */ | |
b9164398 NQ |
5157 | data32 = READ_VREG(HEVC_SAO_CTRL5); |
5158 | /*set them all 0 for H265_NV21 (no down-scale)*/ | |
5159 | data32 &= ~(0xff << 16); | |
5160 | WRITE_VREG(HEVC_SAO_CTRL5, data32); | |
976f3376 | 5161 | data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); |
b9164398 NQ |
5162 | data32 &= (~0x30); |
5163 | /*[5:4] address_format 00:linear 01:32x32 10:64x32*/ | |
3a5df697 | 5164 | data32 |= (mem_map_mode << 4); |
b9164398 NQ |
5165 | WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); |
5166 | #else | |
5167 | /*m8baby test1902*/ | |
5168 | data32 = READ_VREG(HEVC_SAO_CTRL1); | |
5169 | data32 &= (~0x3000); | |
5170 | /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/ | |
3a5df697 | 5171 | data32 |= (mem_map_mode << 12); |
b9164398 NQ |
5172 | data32 &= (~0xff0); |
5173 | /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/ | |
5174 | data32 |= 0x880; /*.Big-Endian per 64-bit */ | |
5175 | data32 &= (~0x3); | |
5176 | data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/ | |
5177 | WRITE_VREG(HEVC_SAO_CTRL1, data32); | |
5178 | /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl | |
e0614bf7 ZZ |
5179 | *[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl |
5180 | */ | |
b9164398 NQ |
5181 | data32 = READ_VREG(HEVC_SAO_CTRL5); |
5182 | /* set them all 0 for H265_NV21 (no down-scale)*/ | |
5183 | data32 &= ~(0xff << 16); | |
5184 | WRITE_VREG(HEVC_SAO_CTRL5, data32); | |
5185 | ||
5186 | data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); | |
5187 | data32 &= (~0x30); | |
5188 | /*[5:4] address_format 00:linear 01:32x32 10:64x32*/ | |
3a5df697 | 5189 | data32 |= (mem_map_mode << 4); |
b9164398 NQ |
5190 | data32 &= (~0xF); |
5191 | data32 |= 0x8; /*Big-Endian per 64-bit*/ | |
5192 | WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); | |
5193 | #endif | |
5194 | #else | |
5195 | data32 = READ_VREG(HEVC_SAO_CTRL1); | |
5196 | data32 &= (~0x3000); | |
3a5df697 | 5197 | data32 |= (mem_map_mode << |
e0614bf7 ZZ |
5198 | 12); |
5199 | ||
5200 | /* [13:12] axi_aformat, 0-Linear, | |
5201 | * 1-32x32, 2-64x32 | |
5202 | */ | |
b9164398 NQ |
5203 | data32 &= (~0xff0); |
5204 | /* data32 |= 0x670; // Big-Endian per 64-bit */ | |
5205 | data32 |= endian; /* Big-Endian per 64-bit */ | |
63e810c0 | 5206 | if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) { |
a6c89e96 NQ |
5207 | data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/ |
5208 | if (get_double_write_mode(pbi) == 0) | |
5209 | data32 |= 0x2; /*disable double write*/ | |
6276f4ff | 5210 | else if (get_double_write_mode(pbi) & 0x10) |
b9164398 | 5211 | data32 |= 0x1; /*disable cm*/ |
a6c89e96 NQ |
5212 | } else { /* >= G12A dw write control */ |
5213 | unsigned int data; | |
5214 | data = READ_VREG(HEVC_DBLK_CFGB); | |
5215 | data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/ | |
5216 | if (get_double_write_mode(pbi) == 0) | |
5217 | data |= (0x1 << 8); /*enable first write*/ | |
6276f4ff | 5218 | else if (get_double_write_mode(pbi) & 0x10) |
a6c89e96 NQ |
5219 | data |= (0x1 << 9); /*double write only*/ |
5220 | else | |
5221 | data |= ((0x1 << 8) |(0x1 << 9)); | |
5222 | WRITE_VREG(HEVC_DBLK_CFGB, data); | |
5223 | } | |
b9164398 NQ |
5224 | WRITE_VREG(HEVC_SAO_CTRL1, data32); |
5225 | ||
fe96802b | 5226 | if (get_double_write_mode(pbi) & 0x10) { |
b9164398 | 5227 | /* [23:22] dw_v1_ctrl |
e0614bf7 ZZ |
5228 | *[21:20] dw_v0_ctrl |
5229 | *[19:18] dw_h1_ctrl | |
5230 | *[17:16] dw_h0_ctrl | |
5231 | */ | |
b9164398 NQ |
5232 | data32 = READ_VREG(HEVC_SAO_CTRL5); |
5233 | /*set them all 0 for H265_NV21 (no down-scale)*/ | |
5234 | data32 &= ~(0xff << 16); | |
5235 | WRITE_VREG(HEVC_SAO_CTRL5, data32); | |
5236 | } else { | |
5237 | data32 = READ_VREG(HEVC_SAO_CTRL5); | |
5238 | data32 &= (~(0xff << 16)); | |
c23e8aee HZ |
5239 | if (get_double_write_mode(pbi) == 2 || |
5240 | get_double_write_mode(pbi) == 3) | |
b9164398 | 5241 | data32 |= (0xff<<16); |
c23e8aee HZ |
5242 | else if (get_double_write_mode(pbi) == 4) |
5243 | data32 |= (0x33<<16); | |
b9164398 NQ |
5244 | WRITE_VREG(HEVC_SAO_CTRL5, data32); |
5245 | } | |
5246 | ||
5247 | data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); | |
5248 | data32 &= (~0x30); | |
5249 | /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */ | |
5250 | data32 |= (mem_map_mode << | |
5251 | 4); | |
5252 | data32 &= (~0xF); | |
5253 | data32 |= 0xf; /* valid only when double write only */ | |
5254 | /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */ | |
5255 | WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); | |
5256 | #endif | |
5257 | } | |
5258 | ||
a6c89e96 | 5259 | static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask) |
b9164398 NQ |
5260 | { |
5261 | struct BuffInfo_s *buf_spec = pbi->work_space_buf; | |
b9164398 | 5262 | unsigned int data32; |
b7706e1e | 5263 | |
fe96802b | 5264 | if (debug && pbi->init_flag == 0) |
b9164398 NQ |
5265 | pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n", |
5266 | __func__, | |
5267 | buf_spec->ipp.buf_start, | |
5268 | buf_spec->start_adr, | |
5269 | buf_spec->short_term_rps.buf_start, | |
5270 | buf_spec->vps.buf_start, | |
5271 | buf_spec->sps.buf_start, | |
5272 | buf_spec->pps.buf_start, | |
5273 | buf_spec->sao_up.buf_start, | |
5274 | buf_spec->swap_buf.buf_start, | |
5275 | buf_spec->swap_buf2.buf_start, | |
5276 | buf_spec->scalelut.buf_start, | |
5277 | buf_spec->dblk_para.buf_start, | |
5278 | buf_spec->dblk_data.buf_start); | |
b9164398 | 5279 | |
a6c89e96 NQ |
5280 | if (mask & HW_MASK_FRONT) { |
5281 | if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) | |
5282 | WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr); | |
5283 | ||
5284 | WRITE_VREG(HEVC_SHORT_TERM_RPS, | |
5285 | buf_spec->short_term_rps.buf_start); | |
5286 | /*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/ | |
5287 | /*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/ | |
5288 | WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start); | |
5289 | WRITE_VREG(HEVC_STREAM_SWAP_BUFFER, | |
5290 | buf_spec->swap_buf.buf_start); | |
5291 | WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, | |
5292 | buf_spec->swap_buf2.buf_start); | |
5293 | WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr); | |
5294 | ||
5295 | } | |
5296 | ||
5297 | if (mask & HW_MASK_BACK) { | |
b9164398 | 5298 | #ifdef LOSLESS_COMPRESS_MODE |
a6c89e96 NQ |
5299 | int losless_comp_header_size = |
5300 | compute_losless_comp_header_size(pbi->init_pic_w, | |
5301 | pbi->init_pic_h); | |
5302 | int losless_comp_body_size = | |
5303 | compute_losless_comp_body_size(pbi->init_pic_w, | |
5304 | pbi->init_pic_h, buf_alloc_depth == 10); | |
5305 | #endif | |
5306 | WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, | |
5307 | buf_spec->ipp.buf_start); | |
5308 | WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start); | |
5309 | WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start); | |
63e810c0 | 5310 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { |
a6c89e96 NQ |
5311 | /* cfg_addr_adp*/ |
5312 | WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start); | |
5313 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
5314 | pr_info("Write HEVC_DBLK_CFGE\n"); | |
a6c89e96 | 5315 | } |
4c9ec3c3 HZ |
5316 | /* cfg_p_addr */ |
5317 | WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start); | |
a6c89e96 NQ |
5318 | /* cfg_d_addr */ |
5319 | WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start); | |
5320 | ||
6f5ee885 | 5321 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
df841122 | 5322 | /* |
5323 | * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40 | |
5324 | * data32 = data32 * 2; | |
5325 | * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040 | |
5326 | * data32 = data32 * 2; | |
5327 | */ | |
5328 | WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k] | |
5329 | } | |
a6c89e96 | 5330 | #ifdef LOSLESS_COMPRESS_MODE |
b7706e1e | 5331 | if (pbi->mmu_enable) { |
b34d6d3e ZZ |
5332 | /*bit[4] : paged_mem_mode*/ |
5333 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4)); | |
6f5ee885 | 5334 | if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1) |
df841122 | 5335 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0); |
b7706e1e | 5336 | } else { |
b34d6d3e ZZ |
5337 | /*if(cur_pic_config->bit_depth == VPX_BITS_10) |
5338 | * WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3)); | |
5339 | */ | |
5340 | /*bit[3] smem mdoe*/ | |
5341 | /*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/ | |
5342 | /*bit[3] smem mdoe*/ | |
a6c89e96 NQ |
5343 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, |
5344 | (losless_comp_body_size >> 5)); | |
b7706e1e | 5345 | } |
5346 | /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, | |
5347 | (losless_comp_body_size >> 5));*/ | |
5348 | /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3, | |
5349 | (0xff<<20) | (0xff<<10) | 0xff);*/ | |
5350 | /*8-bit mode */ | |
5351 | WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size); | |
5352 | WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size); | |
5353 | WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size); | |
5354 | if (get_double_write_mode(pbi) & 0x10) | |
5355 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); | |
b9164398 NQ |
5356 | #else |
5357 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); | |
5358 | #endif | |
5359 | ||
b7706e1e | 5360 | if (pbi->mmu_enable) { |
b34d6d3e ZZ |
5361 | WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start); |
5362 | WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start | |
5363 | + buf_spec->mmu_vbh.buf_size/2); | |
5364 | /*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/ | |
5365 | /*data32 |= 0x1;*/ | |
5366 | /*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/ | |
b9164398 | 5367 | |
b34d6d3e ZZ |
5368 | /* use HEVC_CM_HEADER_START_ADDR */ |
5369 | data32 = READ_VREG(HEVC_SAO_CTRL5); | |
5370 | data32 |= (1<<10); | |
5371 | WRITE_VREG(HEVC_SAO_CTRL5, data32); | |
b7706e1e | 5372 | } |
5373 | ||
a6c89e96 NQ |
5374 | WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start); |
5375 | ||
b7706e1e | 5376 | WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr); |
a6c89e96 NQ |
5377 | /**/ |
5378 | WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr); | |
5379 | WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr); | |
b7706e1e | 5380 | if (pbi->mmu_enable) { |
5381 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) | |
5382 | WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr); | |
5383 | else | |
5384 | WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr); | |
5385 | } | |
b34d6d3e | 5386 | } |
b9164398 NQ |
5387 | } |
5388 | ||
5389 | ||
5390 | #ifdef VP9_LPF_LVL_UPDATE | |
5391 | /* | |
5392 | * Defines, declarations, sub-functions for vp9 de-block loop | |
5393 | filter Thr/Lvl table update | |
5394 | * - struct segmentation is for loop filter only (removed something) | |
5395 | * - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will | |
5396 | be instantiated in C_Entry | |
5397 | * - vp9_loop_filter_init run once before decoding start | |
5398 | * - vp9_loop_filter_frame_init run before every frame decoding start | |
5399 | * - set video format to VP9 is in vp9_loop_filter_init | |
5400 | */ | |
5401 | #define MAX_LOOP_FILTER 63 | |
5402 | #define MAX_REF_LF_DELTAS 4 | |
5403 | #define MAX_MODE_LF_DELTAS 2 | |
5404 | /*#define INTRA_FRAME 0*/ | |
5405 | /*#define LAST_FRAME 1*/ | |
5406 | /*#define MAX_REF_FRAMES 4*/ | |
5407 | #define SEGMENT_DELTADATA 0 | |
5408 | #define SEGMENT_ABSDATA 1 | |
5409 | #define MAX_SEGMENTS 8 | |
5410 | /*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/ | |
5411 | /*no use for loop filter, if this struct for common use, pls add it back*/ | |
5412 | /*#define PREDICTION_PROBS 3*/ | |
5413 | /* no use for loop filter, if this struct for common use, pls add it back*/ | |
5414 | ||
5415 | enum SEG_LVL_FEATURES { | |
5416 | SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/ | |
5417 | SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/ | |
5418 | SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/ | |
5419 | SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/ | |
5420 | SEG_LVL_MAX = 4 /*Number of features supported*/ | |
5421 | }; | |
5422 | ||
5423 | struct segmentation { | |
5424 | uint8_t enabled; | |
5425 | uint8_t update_map; | |
5426 | uint8_t update_data; | |
5427 | uint8_t abs_delta; | |
5428 | uint8_t temporal_update; | |
5429 | ||
5430 | /*no use for loop filter, if this struct | |
e0614bf7 ZZ |
5431 | *for common use, pls add it back |
5432 | */ | |
b9164398 NQ |
5433 | /*vp9_prob tree_probs[SEG_TREE_PROBS]; */ |
5434 | /* no use for loop filter, if this struct | |
e0614bf7 ZZ |
5435 | * for common use, pls add it back |
5436 | */ | |
b9164398 NQ |
5437 | /*vp9_prob pred_probs[PREDICTION_PROBS];*/ |
5438 | ||
5439 | int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX]; | |
5440 | unsigned int feature_mask[MAX_SEGMENTS]; | |
5441 | }; | |
5442 | ||
5443 | struct loop_filter_thresh { | |
5444 | uint8_t mblim; | |
5445 | uint8_t lim; | |
5446 | uint8_t hev_thr; | |
5447 | }; | |
5448 | ||
5449 | struct loop_filter_info_n { | |
5450 | struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1]; | |
5451 | uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS]; | |
5452 | }; | |
5453 | ||
5454 | struct loopfilter { | |
5455 | int filter_level; | |
5456 | ||
5457 | int sharpness_level; | |
5458 | int last_sharpness_level; | |
5459 | ||
5460 | uint8_t mode_ref_delta_enabled; | |
5461 | uint8_t mode_ref_delta_update; | |
5462 | ||
5463 | /*0 = Intra, Last, GF, ARF*/ | |
5464 | signed char ref_deltas[MAX_REF_LF_DELTAS]; | |
5465 | signed char last_ref_deltas[MAX_REF_LF_DELTAS]; | |
5466 | ||
5467 | /*0 = ZERO_MV, MV*/ | |
5468 | signed char mode_deltas[MAX_MODE_LF_DELTAS]; | |
5469 | signed char last_mode_deltas[MAX_MODE_LF_DELTAS]; | |
5470 | }; | |
5471 | ||
5472 | static int vp9_clamp(int value, int low, int high) | |
5473 | { | |
5474 | return value < low ? low : (value > high ? high : value); | |
5475 | } | |
5476 | ||
5477 | int segfeature_active(struct segmentation *seg, | |
5478 | int segment_id, | |
5479 | enum SEG_LVL_FEATURES feature_id) { | |
5480 | return seg->enabled && | |
5481 | (seg->feature_mask[segment_id] & (1 << feature_id)); | |
5482 | } | |
5483 | ||
5484 | int get_segdata(struct segmentation *seg, int segment_id, | |
5485 | enum SEG_LVL_FEATURES feature_id) { | |
5486 | return seg->feature_data[segment_id][feature_id]; | |
5487 | } | |
5488 | ||
5489 | static void vp9_update_sharpness(struct loop_filter_info_n *lfi, | |
5490 | int sharpness_lvl) | |
5491 | { | |
5492 | int lvl; | |
5493 | /*For each possible value for the loop filter fill out limits*/ | |
5494 | for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) { | |
5495 | /*Set loop filter parameters that control sharpness.*/ | |
5496 | int block_inside_limit = lvl >> ((sharpness_lvl > 0) + | |
5497 | (sharpness_lvl > 4)); | |
5498 | ||
5499 | if (sharpness_lvl > 0) { | |
5500 | if (block_inside_limit > (9 - sharpness_lvl)) | |
5501 | block_inside_limit = (9 - sharpness_lvl); | |
5502 | } | |
5503 | ||
5504 | if (block_inside_limit < 1) | |
5505 | block_inside_limit = 1; | |
5506 | ||
5507 | lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit; | |
5508 | lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) + | |
5509 | block_inside_limit); | |
5510 | } | |
5511 | } | |
5512 | ||
b9164398 | 5513 | /*instantiate this function once when decode is started*/ |
fe96802b | 5514 | void vp9_loop_filter_init(struct VP9Decoder_s *pbi) |
b9164398 | 5515 | { |
fe96802b NQ |
5516 | struct loop_filter_info_n *lfi = pbi->lfi; |
5517 | struct loopfilter *lf = pbi->lf; | |
5518 | struct segmentation *seg_4lf = pbi->seg_4lf; | |
b9164398 | 5519 | int i; |
df841122 | 5520 | unsigned int data32; |
fe96802b | 5521 | |
b9164398 NQ |
5522 | memset(lfi, 0, sizeof(struct loop_filter_info_n)); |
5523 | memset(lf, 0, sizeof(struct loopfilter)); | |
5524 | memset(seg_4lf, 0, sizeof(struct segmentation)); | |
5525 | lf->sharpness_level = 0; /*init to 0 */ | |
5526 | /*init limits for given sharpness*/ | |
5527 | vp9_update_sharpness(lfi, lf->sharpness_level); | |
5528 | lf->last_sharpness_level = lf->sharpness_level; | |
5529 | /*init hev threshold const vectors (actually no use) | |
e0614bf7 ZZ |
5530 | *for (i = 0; i <= MAX_LOOP_FILTER; i++) |
5531 | * lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4); | |
5532 | */ | |
b9164398 NQ |
5533 | |
5534 | /*Write to register*/ | |
5535 | for (i = 0; i < 32; i++) { | |
5536 | unsigned int thr; | |
e0614bf7 | 5537 | |
b9164398 NQ |
5538 | thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) | |
5539 | (lfi->lfthr[i * 2 + 1].mblim & 0xff); | |
5540 | thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) | | |
5541 | (lfi->lfthr[i * 2].mblim & 0xff); | |
5542 | WRITE_VREG(HEVC_DBLK_CFG9, thr); | |
5543 | } | |
5544 | ||
5545 | /*video format is VP9*/ | |
6f5ee885 | 5546 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
df841122 | 5547 | data32 = (0x3 << 14) | // (dw fifo thres r and b) |
5548 | (0x3 << 12) | // (dw fifo thres r or b) | |
5549 | (0x3 << 10) | // (dw fifo thres not r/b) | |
5550 | (0x3 << 8) | // 1st/2nd write both enable | |
5551 | (0x1 << 0); // vp9 video format | |
5552 | } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { | |
a6c89e96 | 5553 | data32 = (0x57 << 8) | /*1st/2nd write both enable*/ |
df841122 | 5554 | (0x1 << 0); /*vp9 video format*/ |
a6c89e96 | 5555 | } else |
df841122 | 5556 | data32 = 0x40400001; |
5557 | ||
5558 | WRITE_VREG(HEVC_DBLK_CFGB, data32); | |
5559 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
5560 | pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32); | |
b9164398 NQ |
5561 | } |
5562 | /* perform this function per frame*/ | |
5563 | void vp9_loop_filter_frame_init(struct segmentation *seg, | |
5564 | struct loop_filter_info_n *lfi, struct loopfilter *lf, | |
5565 | int default_filt_lvl) { | |
5566 | int i; | |
5567 | int seg_id; | |
5568 | /*n_shift is the multiplier for lf_deltas | |
e0614bf7 ZZ |
5569 | *the multiplier is 1 for when filter_lvl is between 0 and 31; |
5570 | *2 when filter_lvl is between 32 and 63 | |
5571 | */ | |
b9164398 NQ |
5572 | const int scale = 1 << (default_filt_lvl >> 5); |
5573 | ||
5574 | /*update limits if sharpness has changed*/ | |
5575 | if (lf->last_sharpness_level != lf->sharpness_level) { | |
5576 | vp9_update_sharpness(lfi, lf->sharpness_level); | |
5577 | lf->last_sharpness_level = lf->sharpness_level; | |
5578 | ||
5579 | /*Write to register*/ | |
5580 | for (i = 0; i < 32; i++) { | |
5581 | unsigned int thr; | |
e0614bf7 | 5582 | |
b9164398 NQ |
5583 | thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8) |
5584 | | (lfi->lfthr[i * 2 + 1].mblim & 0xff); | |
5585 | thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8) | |
5586 | | (lfi->lfthr[i * 2].mblim & 0xff); | |
5587 | WRITE_VREG(HEVC_DBLK_CFG9, thr); | |
5588 | } | |
5589 | } | |
5590 | ||
5591 | for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/ | |
5592 | int lvl_seg = default_filt_lvl; | |
e0614bf7 | 5593 | |
b9164398 NQ |
5594 | if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) { |
5595 | const int data = get_segdata(seg, seg_id, | |
5596 | SEG_LVL_ALT_LF); | |
5597 | lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ? | |
5598 | data : default_filt_lvl + data, | |
5599 | 0, MAX_LOOP_FILTER); | |
5600 | #ifdef DBG_LF_PRINT | |
5601 | pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg); | |
5602 | #endif | |
5603 | } | |
5604 | ||
5605 | if (!lf->mode_ref_delta_enabled) { | |
5606 | /*we could get rid of this if we assume that deltas are set to | |
e0614bf7 ZZ |
5607 | *zero when not in use; encoder always uses deltas |
5608 | */ | |
b9164398 NQ |
5609 | memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id])); |
5610 | } else { | |
5611 | int ref, mode; | |
5612 | const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME] | |
5613 | * scale; | |
5614 | #ifdef DBG_LF_PRINT | |
5615 | pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id); | |
5616 | pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]); | |
5617 | #endif | |
5618 | lfi->lvl[seg_id][INTRA_FRAME][0] = | |
5619 | vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER); | |
5620 | ||
5621 | for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) { | |
5622 | /* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/ | |
5623 | for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) { | |
5624 | /*MAX_MODE_LF_DELTAS = 2*/ | |
5625 | const int inter_lvl = | |
5626 | lvl_seg + lf->ref_deltas[ref] * scale | |
5627 | + lf->mode_deltas[mode] * scale; | |
5628 | #ifdef DBG_LF_PRINT | |
5629 | #endif | |
5630 | lfi->lvl[seg_id][ref][mode] = | |
5631 | vp9_clamp(inter_lvl, 0, | |
5632 | MAX_LOOP_FILTER); | |
5633 | } | |
5634 | } | |
5635 | } | |
5636 | } | |
5637 | ||
5638 | #ifdef DBG_LF_PRINT | |
5639 | /*print out thr/lvl table per frame*/ | |
5640 | for (i = 0; i <= MAX_LOOP_FILTER; i++) { | |
5641 | pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n", | |
5642 | i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim, | |
5643 | lfi->lfthr[i].lim); | |
5644 | } | |
5645 | for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) { | |
5646 | pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n", | |
5647 | seg_id, lfi->lvl[seg_id][0][0], | |
5648 | lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0], | |
5649 | lfi->lvl[seg_id][3][0]); | |
5650 | pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1], | |
5651 | lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1], | |
5652 | lfi->lvl[seg_id][3][1]); | |
5653 | } | |
5654 | #endif | |
5655 | ||
5656 | /*Write to register */ | |
5657 | for (i = 0; i < 16; i++) { | |
5658 | unsigned int level; | |
e0614bf7 | 5659 | |
b9164398 NQ |
5660 | level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) | |
5661 | ((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) | | |
5662 | ((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) | | |
5663 | (lfi->lvl[i >> 1][0][i & 1] & 0x3f); | |
5664 | if (!default_filt_lvl) | |
5665 | level = 0; | |
5666 | WRITE_VREG(HEVC_DBLK_CFGA, level); | |
5667 | } | |
5668 | } | |
5669 | /* VP9_LPF_LVL_UPDATE */ | |
5670 | #endif | |
5671 | ||
a6c89e96 | 5672 | static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask) |
b9164398 NQ |
5673 | { |
5674 | unsigned int data32; | |
5675 | int i; | |
a674e3cd | 5676 | const unsigned short parser_cmd[PARSER_CMD_NUMBER] = { |
5677 | 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423, | |
5678 | 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE, | |
5679 | 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A, | |
5680 | 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408, | |
5681 | 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D, | |
5682 | 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00, | |
5683 | 0x7C00 | |
5684 | }; | |
a6c89e96 | 5685 | #if 0 |
df841122 | 5686 | if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) { |
a6c89e96 NQ |
5687 | /* Set MCR fetch priorities*/ |
5688 | data32 = 0x1 | (0x1 << 2) | (0x1 <<3) | | |
5689 | (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25); | |
5690 | WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32); | |
5691 | } | |
5692 | #endif | |
fe96802b NQ |
5693 | /*if (debug & VP9_DEBUG_BUFMGR_MORE) |
5694 | pr_info("%s\n", __func__);*/ | |
a6c89e96 | 5695 | if (mask & HW_MASK_FRONT) { |
b9164398 NQ |
5696 | data32 = READ_VREG(HEVC_PARSER_INT_CONTROL); |
5697 | #if 1 | |
5698 | /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */ | |
5699 | data32 &= ~(7 << 29); | |
5700 | data32 |= (3 << 29); | |
5701 | #endif | |
5702 | data32 = data32 | | |
5703 | (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/ | |
5704 | (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/ | |
5705 | (1 << 7) |/*dec_done_int_cpu_enable*/ | |
5706 | (1 << 4) |/*startcode_found_int_cpu_enable*/ | |
5707 | (0 << 3) |/*startcode_found_int_amrisc_enable*/ | |
5708 | (1 << 0) /*parser_int_enable*/ | |
5709 | ; | |
a6c89e96 NQ |
5710 | #ifdef SUPPORT_FB_DECODING |
5711 | #ifndef FB_DECODING_TEST_SCHEDULE | |
5712 | /*fed_fb_slice_done_int_cpu_enable*/ | |
5713 | if (pbi->used_stage_buf_num > 0) | |
5714 | data32 |= (1 << 10); | |
5715 | #endif | |
5716 | #endif | |
5717 | WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32); | |
b9164398 | 5718 | |
fe96802b NQ |
5719 | data32 = READ_VREG(HEVC_SHIFT_STATUS); |
5720 | data32 = data32 | | |
5721 | (0 << 1) |/*emulation_check_off VP9 | |
5722 | do not have emulation*/ | |
5723 | (1 << 0)/*startcode_check_on*/ | |
5724 | ; | |
5725 | WRITE_VREG(HEVC_SHIFT_STATUS, data32); | |
5726 | WRITE_VREG(HEVC_SHIFT_CONTROL, | |
5727 | (0 << 14) | /*disable_start_code_protect*/ | |
5728 | (1 << 10) | /*length_zero_startcode_en for VP9*/ | |
5729 | (1 << 9) | /*length_valid_startcode_en for VP9*/ | |
5730 | (3 << 6) | /*sft_valid_wr_position*/ | |
5731 | (2 << 4) | /*emulate_code_length_sub_1*/ | |
5732 | (3 << 1) | /*start_code_length_sub_1 | |
5733 | VP9 use 0x00000001 as startcode (4 Bytes)*/ | |
5734 | (1 << 0) /*stream_shift_enable*/ | |
5735 | ); | |
b9164398 NQ |
5736 | |
5737 | WRITE_VREG(HEVC_CABAC_CONTROL, | |
5738 | (1 << 0)/*cabac_enable*/ | |
5739 | ); | |
5740 | ||
5741 | WRITE_VREG(HEVC_PARSER_CORE_CONTROL, | |
5742 | (1 << 0)/* hevc_parser_core_clk_en*/ | |
5743 | ); | |
5744 | ||
5745 | ||
5746 | WRITE_VREG(HEVC_DEC_STATUS_REG, 0); | |
5747 | ||
a6c89e96 NQ |
5748 | } |
5749 | ||
5750 | if (mask & HW_MASK_BACK) { | |
5751 | /*Initial IQIT_SCALELUT memory | |
5752 | -- just to avoid X in simulation*/ | |
b9164398 | 5753 | |
a6c89e96 NQ |
5754 | WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/ |
5755 | for (i = 0; i < 1024; i++) | |
5756 | WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0); | |
5757 | } | |
5758 | ||
5759 | if (mask & HW_MASK_FRONT) { | |
5760 | u32 decode_mode; | |
b9164398 NQ |
5761 | #ifdef ENABLE_SWAP_TEST |
5762 | WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100); | |
5763 | #else | |
5764 | WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0); | |
5765 | #endif | |
5766 | #ifdef MULTI_INSTANCE_SUPPORT | |
187af067 | 5767 | if (!pbi->m_ins_flag) { |
5768 | if (pbi->low_latency_flag) | |
5769 | decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY; | |
5770 | else | |
5771 | decode_mode = DECODE_MODE_SINGLE; | |
5772 | } else if (vdec_frame_based(hw_to_vdec(pbi))) | |
0eb79ad7 RZ |
5773 | decode_mode = pbi->no_head ? |
5774 | DECODE_MODE_MULTI_FRAMEBASE_NOHEAD : | |
5775 | DECODE_MODE_MULTI_FRAMEBASE; | |
a6c89e96 NQ |
5776 | else |
5777 | decode_mode = DECODE_MODE_MULTI_STREAMBASE; | |
5778 | #ifdef SUPPORT_FB_DECODING | |
5779 | #ifndef FB_DECODING_TEST_SCHEDULE | |
5780 | if (pbi->used_stage_buf_num > 0) | |
5781 | decode_mode |= (0x01 << 24); | |
5782 | #endif | |
5783 | #endif | |
5784 | WRITE_VREG(DECODE_MODE, decode_mode); | |
5785 | WRITE_VREG(HEVC_DECODE_SIZE, 0); | |
5786 | WRITE_VREG(HEVC_DECODE_COUNT, 0); | |
b9164398 NQ |
5787 | #else |
5788 | WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE); | |
5789 | WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0); | |
5790 | WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/ | |
5791 | #endif | |
5792 | /*Send parser_cmd*/ | |
b9164398 NQ |
5793 | WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0)); |
5794 | for (i = 0; i < PARSER_CMD_NUMBER; i++) | |
5795 | WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]); | |
5796 | WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0); | |
5797 | WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1); | |
5798 | WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2); | |
5799 | ||
5800 | ||
a6c89e96 NQ |
5801 | WRITE_VREG(HEVC_PARSER_IF_CONTROL, |
5802 | /* (1 << 8) |*/ /*sao_sw_pred_enable*/ | |
5803 | (1 << 5) | /*parser_sao_if_en*/ | |
5804 | (1 << 2) | /*parser_mpred_if_en*/ | |
5805 | (1 << 0) /*parser_scaler_if_en*/ | |
5806 | ); | |
5807 | } | |
5808 | ||
5809 | if (mask & HW_MASK_BACK) { | |
5810 | /*Changed to Start MPRED in microcode*/ | |
5811 | /* | |
5812 | pr_info("[test.c] Start MPRED\n"); | |
5813 | WRITE_VREG(HEVC_MPRED_INT_STATUS, | |
5814 | (1<<31) | |
5815 | ); | |
5816 | */ | |
5817 | WRITE_VREG(HEVCD_IPP_TOP_CNTL, | |
5818 | (0 << 1) | /*enable ipp*/ | |
5819 | (1 << 0) /*software reset ipp and mpp*/ | |
5820 | ); | |
5821 | WRITE_VREG(HEVCD_IPP_TOP_CNTL, | |
5822 | (1 << 1) | /*enable ipp*/ | |
5823 | (0 << 0) /*software reset ipp and mpp*/ | |
5824 | ); | |
b7706e1e | 5825 | if (get_double_write_mode(pbi) & 0x10) { |
b34d6d3e ZZ |
5826 | /*Enable NV21 reference read mode for MC*/ |
5827 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); | |
b7706e1e | 5828 | } |
b34d6d3e | 5829 | |
a6c89e96 NQ |
5830 | /*Initialize mcrcc and decomp perf counters*/ |
5831 | if (mcrcc_cache_alg_flag && | |
5832 | pbi->init_flag == 0) { | |
5833 | mcrcc_perfcount_reset(); | |
5834 | decomp_perfcount_reset(); | |
5835 | } | |
c23e8aee | 5836 | } |
b9164398 NQ |
5837 | return; |
5838 | } | |
5839 | ||
5840 | ||
5841 | #ifdef CONFIG_HEVC_CLK_FORCED_ON | |
5842 | static void config_vp9_clk_forced_on(void) | |
5843 | { | |
5844 | unsigned int rdata32; | |
5845 | /*IQIT*/ | |
5846 | rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL); | |
5847 | WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2)); | |
5848 | ||
5849 | /* DBLK*/ | |
5850 | rdata32 = READ_VREG(HEVC_DBLK_CFG0); | |
5851 | WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2)); | |
5852 | ||
5853 | /* SAO*/ | |
5854 | rdata32 = READ_VREG(HEVC_SAO_CTRL1); | |
5855 | WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2)); | |
5856 | ||
5857 | /*MPRED*/ | |
5858 | rdata32 = READ_VREG(HEVC_MPRED_CTRL1); | |
5859 | WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24)); | |
5860 | ||
5861 | /* PARSER*/ | |
5862 | rdata32 = READ_VREG(HEVC_STREAM_CONTROL); | |
5863 | WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15)); | |
5864 | rdata32 = READ_VREG(HEVC_SHIFT_CONTROL); | |
5865 | WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15)); | |
5866 | rdata32 = READ_VREG(HEVC_CABAC_CONTROL); | |
5867 | WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13)); | |
5868 | rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL); | |
5869 | WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15)); | |
5870 | rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL); | |
5871 | WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15)); | |
5872 | rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL); | |
5873 | WRITE_VREG(HEVC_PARSER_IF_CONTROL, | |
5874 | rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1)); | |
5875 | ||
5876 | /*IPP*/ | |
5877 | rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG); | |
5878 | WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff); | |
5879 | ||
5880 | /* MCRCC*/ | |
5881 | rdata32 = READ_VREG(HEVCD_MCRCC_CTL1); | |
5882 | WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3)); | |
5883 | } | |
5884 | #endif | |
5885 | ||
5886 | ||
5887 | #ifdef MCRCC_ENABLE | |
c23e8aee HZ |
5888 | static void dump_hit_rate(struct VP9Decoder_s *pbi) |
5889 | { | |
5890 | if (debug & VP9_DEBUG_CACHE_HIT_RATE) { | |
5891 | mcrcc_get_hitrate(pbi->m_ins_flag); | |
5892 | decomp_get_hitrate(); | |
5893 | decomp_get_comprate(); | |
5894 | } | |
5895 | } | |
5896 | ||
b9164398 NQ |
5897 | static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi) |
5898 | { | |
5899 | unsigned int rdata32; | |
5900 | unsigned short is_inter; | |
5901 | /*pr_info("Entered config_mcrcc_axi_hw...\n");*/ | |
5902 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/ | |
5903 | is_inter = ((pbi->common.frame_type != KEY_FRAME) && | |
5904 | (!pbi->common.intra_only)) ? 1 : 0; | |
5905 | if (!is_inter) { /* I-PIC*/ | |
5906 | /*remove reset -- disables clock*/ | |
5907 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0); | |
5908 | return; | |
5909 | } | |
5910 | ||
6f5ee885 | 5911 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
df841122 | 5912 | mcrcc_get_hitrate(pbi->m_ins_flag); |
5913 | decomp_get_hitrate(); | |
5914 | decomp_get_comprate(); | |
5915 | } | |
b9164398 NQ |
5916 | |
5917 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, | |
5918 | (0 << 8) | (1 << 1) | 0); | |
5919 | rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
5920 | rdata32 = rdata32 & 0xffff; | |
5921 | rdata32 = rdata32 | (rdata32 << 16); | |
5922 | WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); | |
5923 | /*Programme canvas1 */ | |
5924 | rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
5925 | rdata32 = rdata32 & 0xffff; | |
5926 | rdata32 = rdata32 | (rdata32 << 16); | |
5927 | WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); | |
5928 | /*enable mcrcc progressive-mode*/ | |
5929 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); | |
b9164398 | 5930 | } |
c23e8aee HZ |
5931 | |
5932 | static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi) | |
5933 | { | |
5934 | u32 curr_picnum = -1; | |
5935 | u32 lastref_picnum = -1; | |
5936 | u32 goldenref_picnum = -1; | |
5937 | u32 altref_picnum = -1; | |
5938 | ||
5939 | u32 lastref_delta_picnum; | |
5940 | u32 goldenref_delta_picnum; | |
5941 | u32 altref_delta_picnum; | |
5942 | ||
5943 | u32 rdata32; | |
5944 | ||
5945 | u32 lastcanvas; | |
5946 | u32 goldencanvas; | |
5947 | u32 altrefcanvas; | |
5948 | ||
5949 | u16 is_inter; | |
5950 | u16 lastref_inref; | |
5951 | u16 goldenref_inref; | |
5952 | u16 altref_inref; | |
5953 | ||
5954 | u32 refcanvas_array[3], utmp; | |
5955 | int deltapicnum_array[3], tmp; | |
5956 | ||
5957 | struct VP9_Common_s *cm = &pbi->common; | |
5958 | struct PIC_BUFFER_CONFIG_s *cur_pic_config | |
5959 | = &cm->cur_frame->buf; | |
5960 | curr_picnum = cur_pic_config->decode_idx; | |
5961 | if (cm->frame_refs[0].buf) | |
5962 | lastref_picnum = cm->frame_refs[0].buf->decode_idx; | |
5963 | if (cm->frame_refs[1].buf) | |
5964 | goldenref_picnum = cm->frame_refs[1].buf->decode_idx; | |
5965 | if (cm->frame_refs[2].buf) | |
5966 | altref_picnum = cm->frame_refs[2].buf->decode_idx; | |
5967 | ||
5968 | lastref_delta_picnum = (lastref_picnum >= curr_picnum) ? | |
5969 | (lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum); | |
5970 | goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ? | |
5971 | (goldenref_picnum - curr_picnum) : | |
5972 | (curr_picnum - goldenref_picnum); | |
5973 | altref_delta_picnum = | |
5974 | (altref_picnum >= curr_picnum) ? | |
5975 | (altref_picnum - curr_picnum) : (curr_picnum - altref_picnum); | |
5976 | ||
5977 | lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0; | |
5978 | goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0; | |
5979 | altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0; | |
5980 | ||
5981 | if (debug & VP9_DEBUG_CACHE) | |
5982 | pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n", | |
5983 | __func__, lastref_inref, goldenref_inref, altref_inref); | |
5984 | ||
5985 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */ | |
5986 | ||
5987 | is_inter = ((pbi->common.frame_type != KEY_FRAME) | |
5988 | && (!pbi->common.intra_only)) ? 1 : 0; | |
5989 | ||
5990 | if (!is_inter) { /* I-PIC */ | |
5991 | /* remove reset -- disables clock */ | |
5992 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0); | |
5993 | return; | |
5994 | } | |
5995 | ||
5996 | if (!pbi->m_ins_flag) | |
5997 | dump_hit_rate(pbi); | |
5998 | ||
5999 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0); | |
6000 | lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6001 | goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6002 | altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6003 | ||
6004 | if (debug & VP9_DEBUG_CACHE) | |
6005 | pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n", | |
6006 | lastcanvas, goldencanvas, altrefcanvas); | |
6007 | ||
6008 | altref_inref = ((altref_inref == 1) && | |
6009 | (altrefcanvas != (goldenref_inref | |
6010 | ? goldencanvas : 0xffffffff)) && | |
6011 | (altrefcanvas != (lastref_inref ? | |
6012 | lastcanvas : 0xffffffff))) ? 1 : 0; | |
6013 | goldenref_inref = ((goldenref_inref == 1) && | |
6014 | (goldencanvas != (lastref_inref ? | |
6015 | lastcanvas : 0xffffffff))) ? 1 : 0; | |
6016 | if (debug & VP9_DEBUG_CACHE) | |
6017 | pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n", | |
6018 | lastref_inref, goldenref_inref, altref_inref); | |
6019 | ||
6020 | altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff; | |
6021 | goldenref_delta_picnum = goldenref_inref ? | |
6022 | goldenref_delta_picnum : 0x7fffffff; | |
6023 | lastref_delta_picnum = lastref_inref ? | |
6024 | lastref_delta_picnum : 0x7fffffff; | |
6025 | if (debug & VP9_DEBUG_CACHE) | |
6026 | pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n", | |
6027 | lastref_delta_picnum, goldenref_delta_picnum, | |
6028 | altref_delta_picnum); | |
6029 | /*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/ | |
6030 | ||
6031 | refcanvas_array[0] = lastcanvas; | |
6032 | refcanvas_array[1] = goldencanvas; | |
6033 | refcanvas_array[2] = altrefcanvas; | |
6034 | ||
6035 | deltapicnum_array[0] = lastref_delta_picnum; | |
6036 | deltapicnum_array[1] = goldenref_delta_picnum; | |
6037 | deltapicnum_array[2] = altref_delta_picnum; | |
6038 | ||
6039 | /* sort0 : 2-to-1 */ | |
6040 | if (deltapicnum_array[2] < deltapicnum_array[1]) { | |
6041 | utmp = refcanvas_array[2]; | |
6042 | refcanvas_array[2] = refcanvas_array[1]; | |
6043 | refcanvas_array[1] = utmp; | |
6044 | tmp = deltapicnum_array[2]; | |
6045 | deltapicnum_array[2] = deltapicnum_array[1]; | |
6046 | deltapicnum_array[1] = tmp; | |
6047 | } | |
6048 | /* sort1 : 1-to-0 */ | |
6049 | if (deltapicnum_array[1] < deltapicnum_array[0]) { | |
6050 | utmp = refcanvas_array[1]; | |
6051 | refcanvas_array[1] = refcanvas_array[0]; | |
6052 | refcanvas_array[0] = utmp; | |
6053 | tmp = deltapicnum_array[1]; | |
6054 | deltapicnum_array[1] = deltapicnum_array[0]; | |
6055 | deltapicnum_array[0] = tmp; | |
6056 | } | |
6057 | /* sort2 : 2-to-1 */ | |
6058 | if (deltapicnum_array[2] < deltapicnum_array[1]) { | |
6059 | utmp = refcanvas_array[2]; refcanvas_array[2] = | |
6060 | refcanvas_array[1]; refcanvas_array[1] = utmp; | |
6061 | tmp = deltapicnum_array[2]; deltapicnum_array[2] = | |
6062 | deltapicnum_array[1]; deltapicnum_array[1] = tmp; | |
6063 | } | |
6064 | if (mcrcc_cache_alg_flag == | |
6065 | THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/ | |
6066 | /* lowest delta_picnum */ | |
6067 | rdata32 = refcanvas_array[0]; | |
6068 | rdata32 = rdata32 & 0xffff; | |
6069 | rdata32 = rdata32 | (rdata32 << 16); | |
6070 | WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); | |
6071 | ||
6072 | /* 2nd-lowest delta_picnum */ | |
6073 | rdata32 = refcanvas_array[1]; | |
6074 | rdata32 = rdata32 & 0xffff; | |
6075 | rdata32 = rdata32 | (rdata32 << 16); | |
6076 | WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); | |
6077 | } else { | |
6078 | /* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/ | |
6079 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, | |
6080 | (0 << 8) | (1<<1) | 0); | |
6081 | rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6082 | rdata32 = rdata32 & 0xffff; | |
6083 | rdata32 = rdata32 | (rdata32 << 16); | |
6084 | WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); | |
6085 | ||
6086 | /* Programme canvas1 */ | |
6087 | rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6088 | rdata32 = rdata32 & 0xffff; | |
6089 | rdata32 = rdata32 | (rdata32 << 16); | |
6090 | WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); | |
6091 | } | |
6092 | ||
6093 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */ | |
6094 | return; | |
6095 | } | |
6096 | ||
b9164398 NQ |
6097 | #endif |
6098 | ||
6099 | ||
fe96802b NQ |
6100 | static void free_lf_buf(struct VP9Decoder_s *pbi) |
6101 | { | |
6102 | if (pbi->lfi) | |
6103 | vfree(pbi->lfi); | |
6104 | if (pbi->lf) | |
6105 | vfree(pbi->lf); | |
6106 | if (pbi->seg_4lf) | |
6107 | vfree(pbi->seg_4lf); | |
6108 | pbi->lfi = NULL; | |
6109 | pbi->lf = NULL; | |
6110 | pbi->seg_4lf = NULL; | |
6111 | } | |
6112 | ||
6113 | static int alloc_lf_buf(struct VP9Decoder_s *pbi) | |
6114 | { | |
6115 | pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n)); | |
6116 | pbi->lf = vmalloc(sizeof(struct loopfilter)); | |
6117 | pbi->seg_4lf = vmalloc(sizeof(struct segmentation)); | |
6118 | if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) { | |
6119 | free_lf_buf(pbi); | |
6120 | pr_err("[test.c] vp9_loop_filter init malloc error!!!\n"); | |
6121 | return -1; | |
6122 | } | |
6123 | return 0; | |
6124 | } | |
6125 | ||
b9164398 NQ |
6126 | static void vp9_local_uninit(struct VP9Decoder_s *pbi) |
6127 | { | |
6128 | pbi->rpm_ptr = NULL; | |
6129 | pbi->lmem_ptr = NULL; | |
6130 | if (pbi->rpm_addr) { | |
5f165f39 HZ |
6131 | dma_free_coherent(amports_get_dma_device(), |
6132 | RPM_BUF_SIZE, | |
6133 | pbi->rpm_addr, | |
6134 | pbi->rpm_phy_addr); | |
b9164398 NQ |
6135 | pbi->rpm_addr = NULL; |
6136 | } | |
6137 | if (pbi->lmem_addr) { | |
e0614bf7 ZZ |
6138 | if (pbi->lmem_phy_addr) |
6139 | dma_free_coherent(amports_get_dma_device(), | |
6140 | LMEM_BUF_SIZE, pbi->lmem_addr, | |
6141 | pbi->lmem_phy_addr); | |
6142 | pbi->lmem_addr = NULL; | |
b9164398 NQ |
6143 | } |
6144 | if (pbi->prob_buffer_addr) { | |
6145 | if (pbi->prob_buffer_phy_addr) | |
6146 | dma_free_coherent(amports_get_dma_device(), | |
6147 | PROB_BUF_SIZE, pbi->prob_buffer_addr, | |
6148 | pbi->prob_buffer_phy_addr); | |
6149 | ||
6150 | pbi->prob_buffer_addr = NULL; | |
6151 | } | |
6152 | if (pbi->count_buffer_addr) { | |
6153 | if (pbi->count_buffer_phy_addr) | |
6154 | dma_free_coherent(amports_get_dma_device(), | |
6155 | COUNT_BUF_SIZE, pbi->count_buffer_addr, | |
6156 | pbi->count_buffer_phy_addr); | |
6157 | ||
6158 | pbi->count_buffer_addr = NULL; | |
6159 | } | |
b7706e1e | 6160 | if (pbi->mmu_enable) { |
e0e39311 | 6161 | u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi); |
b7706e1e | 6162 | if (pbi->frame_mmu_map_addr) { |
6163 | if (pbi->frame_mmu_map_phy_addr) | |
6164 | dma_free_coherent(amports_get_dma_device(), | |
df841122 | 6165 | mmu_map_size, |
b7706e1e | 6166 | pbi->frame_mmu_map_addr, |
a6c89e96 | 6167 | pbi->frame_mmu_map_phy_addr); |
b7706e1e | 6168 | pbi->frame_mmu_map_addr = NULL; |
6169 | } | |
a6c89e96 | 6170 | } |
a6c89e96 NQ |
6171 | #ifdef SUPPORT_FB_DECODING |
6172 | if (pbi->stage_mmu_map_addr) { | |
6173 | if (pbi->stage_mmu_map_phy_addr) | |
6174 | dma_free_coherent(amports_get_dma_device(), | |
6175 | STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS, | |
6176 | pbi->stage_mmu_map_addr, | |
6177 | pbi->stage_mmu_map_phy_addr); | |
6178 | pbi->stage_mmu_map_addr = NULL; | |
b9164398 | 6179 | } |
b9164398 | 6180 | |
a6c89e96 NQ |
6181 | uninit_stage_buf(pbi); |
6182 | #endif | |
6183 | ||
b9164398 | 6184 | #ifdef VP9_LPF_LVL_UPDATE |
fe96802b | 6185 | free_lf_buf(pbi); |
b9164398 | 6186 | #endif |
fe96802b NQ |
6187 | if (pbi->gvs) |
6188 | vfree(pbi->gvs); | |
6189 | pbi->gvs = NULL; | |
b9164398 NQ |
6190 | } |
6191 | ||
6192 | static int vp9_local_init(struct VP9Decoder_s *pbi) | |
6193 | { | |
6194 | int ret = -1; | |
6195 | /*int losless_comp_header_size, losless_comp_body_size;*/ | |
6196 | ||
6197 | struct BuffInfo_s *cur_buf_info = NULL; | |
e0614bf7 | 6198 | |
b9164398 NQ |
6199 | memset(&pbi->param, 0, sizeof(union param_u)); |
6200 | memset(&pbi->common, 0, sizeof(struct VP9_Common_s)); | |
6201 | #ifdef MULTI_INSTANCE_SUPPORT | |
6202 | cur_buf_info = &pbi->work_space_buf_store; | |
df841122 | 6203 | |
6204 | if (vdec_is_support_4k()) { | |
6f5ee885 | 6205 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
3a5df697 | 6206 | memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */ |
df841122 | 6207 | sizeof(struct BuffInfo_s)); |
6208 | } else | |
6209 | memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */ | |
6210 | sizeof(struct BuffInfo_s)); | |
6211 | } else | |
c23e8aee | 6212 | memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */ |
b9164398 | 6213 | sizeof(struct BuffInfo_s)); |
df841122 | 6214 | |
b9164398 | 6215 | cur_buf_info->start_adr = pbi->buf_start; |
b7706e1e | 6216 | if (!pbi->mmu_enable) |
6217 | pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size; | |
6218 | ||
b9164398 NQ |
6219 | #else |
6220 | /*! MULTI_INSTANCE_SUPPORT*/ | |
df841122 | 6221 | if (vdec_is_support_4k()) { |
6f5ee885 | 6222 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) |
df841122 | 6223 | cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */ |
6224 | else | |
6225 | cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */ | |
6226 | } else | |
c23e8aee | 6227 | cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */ |
df841122 | 6228 | |
b9164398 NQ |
6229 | #endif |
6230 | ||
6231 | init_buff_spec(pbi, cur_buf_info); | |
fe96802b | 6232 | vp9_bufmgr_init(pbi, cur_buf_info, NULL); |
b9164398 | 6233 | |
c23e8aee HZ |
6234 | if (!vdec_is_support_4k() |
6235 | && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) { | |
6236 | buf_alloc_width = 1920; | |
6237 | buf_alloc_height = 1088; | |
a6c89e96 NQ |
6238 | if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) { |
6239 | pbi->max_pic_w = 1920; | |
6240 | pbi->max_pic_h = 1088; | |
6241 | } | |
6f5ee885 | 6242 | } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
df841122 | 6243 | buf_alloc_width = 8192; |
6244 | buf_alloc_height = 4608; | |
c23e8aee | 6245 | } |
a6c89e96 NQ |
6246 | pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w : |
6247 | (buf_alloc_width ? buf_alloc_width : | |
b9164398 NQ |
6248 | (pbi->vvp9_amstream_dec_info.width ? |
6249 | pbi->vvp9_amstream_dec_info.width : | |
0be1523d | 6250 | pbi->work_space_buf->max_width)); |
a6c89e96 NQ |
6251 | pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h : |
6252 | (buf_alloc_height ? buf_alloc_height : | |
b9164398 NQ |
6253 | (pbi->vvp9_amstream_dec_info.height ? |
6254 | pbi->vvp9_amstream_dec_info.height : | |
0be1523d | 6255 | pbi->work_space_buf->max_height)); |
3a5df697 | 6256 | |
6f5ee885 | 6257 | if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) && |
3a5df697 | 6258 | (pbi->double_write_mode != 0) && |
6259 | (((pbi->max_pic_w % 64) != 0) || | |
6260 | (pbi->vvp9_amstream_dec_info.width % 64) != 0)) | |
6261 | mem_map_mode = 2; | |
6262 | ||
fe96802b NQ |
6263 | #ifndef MV_USE_FIXED_BUF |
6264 | if (init_mv_buf_list(pbi) < 0) { | |
6265 | pr_err("%s: init_mv_buf_list fail\n", __func__); | |
6266 | return -1; | |
6267 | } | |
6268 | #endif | |
dfe41deb RZ |
6269 | if (pbi->save_buffer_mode) |
6270 | pbi->used_buf_num = MAX_BUF_NUM_SAVE_BUF; | |
a5c5bec0 | 6271 | else |
dfe41deb | 6272 | pbi->used_buf_num = max_buf_num; |
b7706e1e | 6273 | |
fe96802b NQ |
6274 | if (pbi->used_buf_num > MAX_BUF_NUM) |
6275 | pbi->used_buf_num = MAX_BUF_NUM; | |
6276 | if (pbi->used_buf_num > FRAME_BUFFERS) | |
6277 | pbi->used_buf_num = FRAME_BUFFERS; | |
b9164398 | 6278 | |
976f3376 | 6279 | pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param) |
b9164398 NQ |
6280 | & 0x40) >> 6; |
6281 | ||
b9164398 | 6282 | if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) { |
5f165f39 HZ |
6283 | pbi->rpm_addr = dma_alloc_coherent(amports_get_dma_device(), |
6284 | RPM_BUF_SIZE, | |
6285 | &pbi->rpm_phy_addr, GFP_KERNEL); | |
b9164398 NQ |
6286 | if (pbi->rpm_addr == NULL) { |
6287 | pr_err("%s: failed to alloc rpm buffer\n", __func__); | |
6288 | return -1; | |
6289 | } | |
6290 | ||
b9164398 NQ |
6291 | pbi->rpm_ptr = pbi->rpm_addr; |
6292 | } | |
6293 | ||
fe96802b NQ |
6294 | pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(), |
6295 | LMEM_BUF_SIZE, | |
6296 | &pbi->lmem_phy_addr, GFP_KERNEL); | |
6297 | if (pbi->lmem_addr == NULL) { | |
6298 | pr_err("%s: failed to alloc lmem buffer\n", __func__); | |
6299 | return -1; | |
6300 | } | |
e0614bf7 | 6301 | pbi->lmem_ptr = pbi->lmem_addr; |
fe96802b | 6302 | |
b9164398 NQ |
6303 | pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(), |
6304 | PROB_BUF_SIZE, | |
6305 | &pbi->prob_buffer_phy_addr, GFP_KERNEL); | |
6306 | if (pbi->prob_buffer_addr == NULL) { | |
6307 | pr_err("%s: failed to alloc prob_buffer\n", __func__); | |
6308 | return -1; | |
6309 | } | |
6310 | memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE); | |
b9164398 NQ |
6311 | pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(), |
6312 | COUNT_BUF_SIZE, | |
6313 | &pbi->count_buffer_phy_addr, GFP_KERNEL); | |
6314 | if (pbi->count_buffer_addr == NULL) { | |
6315 | pr_err("%s: failed to alloc count_buffer\n", __func__); | |
6316 | return -1; | |
6317 | } | |
6318 | memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE); | |
5f165f39 | 6319 | |
b7706e1e | 6320 | if (pbi->mmu_enable) { |
e0e39311 | 6321 | u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi); |
b7706e1e | 6322 | pbi->frame_mmu_map_addr = |
6323 | dma_alloc_coherent(amports_get_dma_device(), | |
df841122 | 6324 | mmu_map_size, |
a6c89e96 | 6325 | &pbi->frame_mmu_map_phy_addr, GFP_KERNEL); |
b7706e1e | 6326 | if (pbi->frame_mmu_map_addr == NULL) { |
6327 | pr_err("%s: failed to alloc count_buffer\n", __func__); | |
6328 | return -1; | |
6329 | } | |
6330 | memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE); | |
a6c89e96 | 6331 | } |
a6c89e96 NQ |
6332 | #ifdef SUPPORT_FB_DECODING |
6333 | if (pbi->m_ins_flag && stage_buf_num > 0) { | |
6334 | pbi->stage_mmu_map_addr = | |
6335 | dma_alloc_coherent(amports_get_dma_device(), | |
6336 | STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS, | |
6337 | &pbi->stage_mmu_map_phy_addr, GFP_KERNEL); | |
6338 | if (pbi->stage_mmu_map_addr == NULL) { | |
b34d6d3e ZZ |
6339 | pr_err("%s: failed to alloc count_buffer\n", __func__); |
6340 | return -1; | |
6341 | } | |
a6c89e96 NQ |
6342 | memset(pbi->stage_mmu_map_addr, |
6343 | 0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS); | |
b34d6d3e | 6344 | |
a6c89e96 NQ |
6345 | init_stage_buf(pbi); |
6346 | } | |
6347 | #endif | |
b9164398 NQ |
6348 | |
6349 | ret = 0; | |
6350 | return ret; | |
6351 | } | |
6352 | ||
6353 | /******************************************** | |
6354 | * Mailbox command | |
6355 | ********************************************/ | |
6356 | #define CMD_FINISHED 0 | |
6357 | #define CMD_ALLOC_VIEW 1 | |
6358 | #define CMD_FRAME_DISPLAY 3 | |
6359 | #define CMD_DEBUG 10 | |
6360 | ||
6361 | ||
6362 | #define DECODE_BUFFER_NUM_MAX 32 | |
6363 | #define DISPLAY_BUFFER_NUM 6 | |
6364 | ||
6365 | #define video_domain_addr(adr) (adr&0x7fffffff) | |
6366 | #define DECODER_WORK_SPACE_SIZE 0x800000 | |
6367 | ||
6368 | #define spec2canvas(x) \ | |
6369 | (((x)->uv_canvas_index << 16) | \ | |
6370 | ((x)->uv_canvas_index << 8) | \ | |
6371 | ((x)->y_canvas_index << 0)) | |
6372 | ||
6373 | ||
fe96802b NQ |
6374 | static void set_canvas(struct VP9Decoder_s *pbi, |
6375 | struct PIC_BUFFER_CONFIG_s *pic_config) | |
b9164398 | 6376 | { |
05afa03d | 6377 | struct vdec_s *vdec = hw_to_vdec(pbi); |
b9164398 NQ |
6378 | int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4; |
6379 | int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4; | |
6380 | int blkmode = mem_map_mode; | |
6381 | /*CANVAS_BLKMODE_64X32*/ | |
c23e8aee HZ |
6382 | if (pic_config->double_write_mode) { |
6383 | canvas_w = pic_config->y_crop_width / | |
6384 | get_double_write_ratio(pbi, | |
6385 | pic_config->double_write_mode); | |
6386 | canvas_h = pic_config->y_crop_height / | |
6387 | get_double_write_ratio(pbi, | |
6388 | pic_config->double_write_mode); | |
b9164398 NQ |
6389 | |
6390 | if (mem_map_mode == 0) | |
6391 | canvas_w = ALIGN(canvas_w, 32); | |
6392 | else | |
6393 | canvas_w = ALIGN(canvas_w, 64); | |
6394 | canvas_h = ALIGN(canvas_h, 32); | |
6395 | ||
05afa03d PY |
6396 | if (vdec->parallel_dec == 1) { |
6397 | if (pic_config->y_canvas_index == -1) | |
6398 | pic_config->y_canvas_index = | |
6399 | vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id); | |
6400 | if (pic_config->uv_canvas_index == -1) | |
6401 | pic_config->uv_canvas_index = | |
6402 | vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id); | |
6403 | } else { | |
6404 | pic_config->y_canvas_index = 128 + pic_config->index * 2; | |
6405 | pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1; | |
6406 | } | |
b9164398 NQ |
6407 | |
6408 | canvas_config_ex(pic_config->y_canvas_index, | |
6409 | pic_config->dw_y_adr, canvas_w, canvas_h, | |
6410 | CANVAS_ADDR_NOWRAP, blkmode, 0x7); | |
6411 | canvas_config_ex(pic_config->uv_canvas_index, | |
6412 | pic_config->dw_u_v_adr, canvas_w, canvas_h, | |
6413 | CANVAS_ADDR_NOWRAP, blkmode, 0x7); | |
6276f4ff | 6414 | |
b9164398 NQ |
6415 | #ifdef MULTI_INSTANCE_SUPPORT |
6416 | pic_config->canvas_config[0].phy_addr = | |
6417 | pic_config->dw_y_adr; | |
6418 | pic_config->canvas_config[0].width = | |
6419 | canvas_w; | |
6420 | pic_config->canvas_config[0].height = | |
6421 | canvas_h; | |
6422 | pic_config->canvas_config[0].block_mode = | |
6423 | blkmode; | |
6424 | pic_config->canvas_config[0].endian = 7; | |
6425 | ||
6426 | pic_config->canvas_config[1].phy_addr = | |
6427 | pic_config->dw_u_v_adr; | |
6428 | pic_config->canvas_config[1].width = | |
6429 | canvas_w; | |
6430 | pic_config->canvas_config[1].height = | |
6431 | canvas_h; | |
6432 | pic_config->canvas_config[1].block_mode = | |
6433 | blkmode; | |
6434 | pic_config->canvas_config[1].endian = 7; | |
6435 | #endif | |
b9164398 | 6436 | } |
b9164398 NQ |
6437 | } |
6438 | ||
6439 | ||
6440 | static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf) | |
6441 | { | |
6442 | unsigned int ar; | |
b9164398 NQ |
6443 | vf->duration = pbi->frame_dur; |
6444 | vf->duration_pulldown = 0; | |
6445 | vf->flag = 0; | |
d481db31 NQ |
6446 | vf->prop.master_display_colour = pbi->vf_dp; |
6447 | vf->signal_type = pbi->video_signal_type; | |
9edb8e76 HZ |
6448 | if (vf->compWidth && vf->compHeight) |
6449 | pbi->frame_ar = vf->compHeight * 0x100 / vf->compWidth; | |
b9164398 NQ |
6450 | ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX); |
6451 | vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); | |
6452 | ||
b9164398 NQ |
6453 | } |
6454 | ||
6455 | static int vvp9_vf_states(struct vframe_states *states, void *op_arg) | |
6456 | { | |
6457 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; | |
6458 | ||
6459 | states->vf_pool_size = VF_POOL_SIZE; | |
6460 | states->buf_free_num = kfifo_len(&pbi->newframe_q); | |
6461 | states->buf_avail_num = kfifo_len(&pbi->display_q); | |
6462 | ||
6463 | if (step == 2) | |
6464 | states->buf_avail_num = 0; | |
6465 | return 0; | |
6466 | } | |
6467 | ||
6468 | static struct vframe_s *vvp9_vf_peek(void *op_arg) | |
6469 | { | |
c64ff275 | 6470 | struct vframe_s *vf[2] = {0, 0}; |
b9164398 | 6471 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; |
e0614bf7 | 6472 | |
b9164398 NQ |
6473 | if (step == 2) |
6474 | return NULL; | |
6475 | ||
c64ff275 | 6476 | if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) { |
6477 | if (vf[1]) { | |
6478 | vf[0]->next_vf_pts_valid = true; | |
6479 | vf[0]->next_vf_pts = vf[1]->pts; | |
6480 | } else | |
6481 | vf[0]->next_vf_pts_valid = false; | |
6482 | return vf[0]; | |
6483 | } | |
b9164398 NQ |
6484 | |
6485 | return NULL; | |
6486 | } | |
6487 | ||
6488 | static struct vframe_s *vvp9_vf_get(void *op_arg) | |
6489 | { | |
6490 | struct vframe_s *vf; | |
6491 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; | |
e0614bf7 | 6492 | |
b9164398 NQ |
6493 | if (step == 2) |
6494 | return NULL; | |
6495 | else if (step == 1) | |
6496 | step = 2; | |
6497 | ||
6498 | if (kfifo_get(&pbi->display_q, &vf)) { | |
c64ff275 | 6499 | struct vframe_s *next_vf; |
b9164398 | 6500 | uint8_t index = vf->index & 0xff; |
a35da9f0 | 6501 | if (index < pbi->used_buf_num) { |
fe96802b NQ |
6502 | pbi->vf_get_count++; |
6503 | if (debug & VP9_DEBUG_BUFMGR) | |
6504 | pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n", | |
6505 | __func__, vf->type, | |
6506 | vf->width, vf->height, | |
6507 | vf->pts, | |
6508 | vf->pts_us64); | |
c64ff275 | 6509 | |
6510 | if (kfifo_peek(&pbi->display_q, &next_vf)) { | |
6511 | vf->next_vf_pts_valid = true; | |
6512 | vf->next_vf_pts = next_vf->pts; | |
6513 | } else | |
6514 | vf->next_vf_pts_valid = false; | |
6515 | ||
b9164398 | 6516 | return vf; |
fe96802b | 6517 | } |
b9164398 NQ |
6518 | } |
6519 | return NULL; | |
6520 | } | |
6521 | ||
6522 | static void vvp9_vf_put(struct vframe_s *vf, void *op_arg) | |
6523 | { | |
6524 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; | |
6525 | uint8_t index = vf->index & 0xff; | |
6526 | ||
6527 | kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf); | |
fe96802b | 6528 | pbi->vf_put_count++; |
a35da9f0 | 6529 | if (index < pbi->used_buf_num) { |
b9164398 NQ |
6530 | struct VP9_Common_s *cm = &pbi->common; |
6531 | struct BufferPool_s *pool = cm->buffer_pool; | |
fe96802b NQ |
6532 | unsigned long flags; |
6533 | ||
6534 | lock_buffer_pool(pool, flags); | |
b9164398 NQ |
6535 | if (pool->frame_bufs[index].buf.vf_ref > 0) |
6536 | pool->frame_bufs[index].buf.vf_ref--; | |
6537 | ||
6538 | if (pbi->wait_buf) | |
a6c89e96 | 6539 | WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, |
b9164398 NQ |
6540 | 0x1); |
6541 | pbi->last_put_idx = index; | |
6542 | pbi->new_frame_displayed++; | |
fe96802b | 6543 | unlock_buffer_pool(pool, flags); |
a6c89e96 NQ |
6544 | #ifdef SUPPORT_FB_DECODING |
6545 | if (pbi->used_stage_buf_num > 0 && | |
6546 | pbi->back_not_run_ready) | |
6547 | trigger_schedule(pbi); | |
6548 | #endif | |
b9164398 NQ |
6549 | } |
6550 | ||
6551 | } | |
6552 | ||
6553 | static int vvp9_event_cb(int type, void *data, void *private_data) | |
6554 | { | |
6555 | if (type & VFRAME_EVENT_RECEIVER_RESET) { | |
6556 | #if 0 | |
6557 | unsigned long flags; | |
e0614bf7 | 6558 | |
b9164398 NQ |
6559 | amhevc_stop(); |
6560 | #ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER | |
6561 | vf_light_unreg_provider(&vvp9_vf_prov); | |
6562 | #endif | |
6563 | spin_lock_irqsave(&pbi->lock, flags); | |
6564 | vvp9_local_init(); | |
6565 | vvp9_prot_init(); | |
6566 | spin_unlock_irqrestore(&pbi->lock, flags); | |
6567 | #ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER | |
6568 | vf_reg_provider(&vvp9_vf_prov); | |
6569 | #endif | |
6570 | amhevc_start(); | |
6571 | #endif | |
6572 | } | |
6573 | ||
6574 | return 0; | |
6575 | } | |
6576 | ||
6577 | void inc_vf_ref(struct VP9Decoder_s *pbi, int index) | |
6578 | { | |
6579 | struct VP9_Common_s *cm = &pbi->common; | |
e0614bf7 | 6580 | |
b9164398 NQ |
6581 | cm->buffer_pool->frame_bufs[index].buf.vf_ref++; |
6582 | ||
fe96802b | 6583 | if (debug & VP9_DEBUG_BUFMGR_MORE) |
b9164398 NQ |
6584 | pr_info("%s index = %d new vf_ref = %d\r\n", |
6585 | __func__, index, | |
6586 | cm->buffer_pool->frame_bufs[index].buf.vf_ref); | |
6587 | } | |
6588 | ||
c20e6c85 | 6589 | static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid) |
6590 | { | |
6591 | u32 old_duration, pts_duration = 0; | |
6592 | u32 pts = vf->pts; | |
6593 | ||
6594 | if (pbi->get_frame_dur == true) | |
6595 | return true; | |
6596 | ||
6597 | pbi->frame_cnt_window++; | |
6598 | if (!(pbi->vp9_first_pts_ready == 1)) { | |
6599 | if (valid) { | |
6600 | pbi->pts1 = pts; | |
6601 | pbi->frame_cnt_window = 0; | |
6602 | pbi->duration_from_pts_done = 0; | |
6603 | pbi->vp9_first_pts_ready = 1; | |
6604 | } else { | |
6605 | return false; | |
6606 | } | |
6607 | } else { | |
6608 | if (pts < pbi->pts1) { | |
6609 | if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) { | |
6610 | pbi->pts1 = pts; | |
6611 | pbi->frame_cnt_window = 0; | |
6612 | } | |
6613 | } | |
6614 | ||
6615 | if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) && | |
6616 | (pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) { | |
6617 | old_duration = pbi->frame_dur; | |
6618 | pbi->pts2 = pts; | |
6619 | pts_duration = (((pbi->pts2 - pbi->pts1) * 16) / | |
6620 | (pbi->frame_cnt_window * 15)); | |
6621 | ||
6622 | if (close_to(pts_duration, old_duration, 2000)) { | |
6623 | pbi->frame_dur = pts_duration; | |
6624 | if ((debug & VP9_DEBUG_OUT_PTS) != 0) | |
6625 | pr_info("use calc duration %d\n", pts_duration); | |
6626 | } | |
6627 | ||
6628 | if (pbi->duration_from_pts_done == 0) { | |
6629 | if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) { | |
6630 | pbi->duration_from_pts_done = 1; | |
6631 | } else { | |
6632 | if (!close_to(pts_duration, | |
6633 | old_duration, 1000) && | |
6634 | !close_to(pts_duration, | |
6635 | pbi->frame_dur, 1000) && | |
6636 | close_to(pts_duration, | |
6637 | pbi->last_duration, 200)) { | |
6638 | /* frame_dur must | |
6639 | * wrong,recover it. | |
6640 | */ | |
6641 | pbi->frame_dur = pts_duration; | |
6642 | } | |
6643 | pbi->pts1 = pbi->pts2; | |
6644 | pbi->frame_cnt_window = 0; | |
6645 | pbi->duration_from_pts_done = 0; | |
6646 | } | |
6647 | } | |
6648 | pbi->last_duration = pts_duration; | |
6649 | } | |
6650 | } | |
6651 | return true; | |
6652 | } | |
6653 | ||
b7706e1e | 6654 | static void update_vf_memhandle(struct VP9Decoder_s *pbi, |
6655 | struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic) | |
6656 | { | |
6657 | if (pic->index < 0) { | |
6658 | vf->mem_handle = NULL; | |
6659 | vf->mem_head_handle = NULL; | |
6660 | } else if (vf->type & VIDTYPE_SCATTER) { | |
6661 | vf->mem_handle = | |
6662 | decoder_mmu_box_get_mem_handle( | |
6663 | pbi->mmu_box, pic->index); | |
6664 | vf->mem_head_handle = | |
6665 | decoder_bmmu_box_get_mem_handle( | |
6666 | pbi->bmmu_box, | |
6667 | HEADER_BUFFER_IDX(pic->BUF_index)); | |
6668 | } else { | |
6669 | vf->mem_handle = | |
6670 | decoder_bmmu_box_get_mem_handle( | |
6671 | pbi->bmmu_box, VF_BUFFER_IDX(pic->BUF_index)); | |
6672 | vf->mem_head_handle = NULL; | |
6673 | /*vf->mem_head_handle = | |
6674 | *decoder_bmmu_box_get_mem_handle( | |
6675 | *hevc->bmmu_box, VF_BUFFER_IDX(BUF_index)); | |
6676 | */ | |
6677 | } | |
6678 | } | |
ac678990 | 6679 | |
b9164398 NQ |
6680 | static int prepare_display_buf(struct VP9Decoder_s *pbi, |
6681 | struct PIC_BUFFER_CONFIG_s *pic_config) | |
6682 | { | |
6683 | struct vframe_s *vf = NULL; | |
6684 | int stream_offset = pic_config->stream_offset; | |
6685 | unsigned short slice_type = pic_config->slice_type; | |
5f2400c0 | 6686 | u32 pts_valid = 0, pts_us64_valid = 0; |
6687 | u32 pts_save; | |
6688 | u64 pts_us64_save; | |
a8f62ee0 | 6689 | u32 frame_size; |
c20e6c85 | 6690 | |
b9164398 NQ |
6691 | if (debug & VP9_DEBUG_BUFMGR) |
6692 | pr_info("%s index = %d\r\n", __func__, pic_config->index); | |
6693 | if (kfifo_get(&pbi->newframe_q, &vf) == 0) { | |
6694 | pr_info("fatal error, no available buffer slot."); | |
6695 | return -1; | |
6696 | } | |
6697 | ||
c23e8aee | 6698 | if (pic_config->double_write_mode) |
fe96802b | 6699 | set_canvas(pbi, pic_config); |
c23e8aee | 6700 | |
fe96802b | 6701 | display_frame_count[pbi->index]++; |
b9164398 | 6702 | if (vf) { |
2cd6815e NQ |
6703 | if (pbi->is_used_v4l) { |
6704 | vf->v4l_mem_handle | |
6705 | = pbi->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr; | |
6706 | vp9_print(pbi, PRINT_FLAG_V4L_DETAIL, | |
6707 | "[%d] %s(), v4l mem handle: 0x%lx\n", | |
6708 | ((struct aml_vcodec_ctx *)(pbi->v4l2_ctx))->id, | |
6709 | __func__, vf->v4l_mem_handle); | |
6710 | } | |
6711 | ||
fe96802b NQ |
6712 | #ifdef MULTI_INSTANCE_SUPPORT |
6713 | if (vdec_frame_based(hw_to_vdec(pbi))) { | |
6714 | vf->pts = pic_config->pts; | |
6715 | vf->pts_us64 = pic_config->pts64; | |
c20e6c85 | 6716 | if (vf->pts != 0 || vf->pts_us64 != 0) { |
6717 | pts_valid = 1; | |
6718 | pts_us64_valid = 1; | |
6719 | } else { | |
6720 | pts_valid = 0; | |
6721 | pts_us64_valid = 0; | |
6722 | } | |
fe96802b NQ |
6723 | } else |
6724 | #endif | |
b9164398 | 6725 | /* if (pts_lookup_offset(PTS_TYPE_VIDEO, |
e0614bf7 ZZ |
6726 | * stream_offset, &vf->pts, 0) != 0) { |
6727 | */ | |
b9164398 | 6728 | if (pts_lookup_offset_us64 |
a8f62ee0 RZ |
6729 | (PTS_TYPE_VIDEO, stream_offset, &vf->pts, |
6730 | &frame_size, 0, | |
6731 | &vf->pts_us64) != 0) { | |
b9164398 NQ |
6732 | #ifdef DEBUG_PTS |
6733 | pbi->pts_missed++; | |
6734 | #endif | |
6735 | vf->pts = 0; | |
6736 | vf->pts_us64 = 0; | |
c20e6c85 | 6737 | pts_valid = 0; |
6738 | pts_us64_valid = 0; | |
6739 | } else { | |
b9164398 | 6740 | #ifdef DEBUG_PTS |
b9164398 NQ |
6741 | pbi->pts_hit++; |
6742 | #endif | |
c20e6c85 | 6743 | pts_valid = 1; |
6744 | pts_us64_valid = 1; | |
6745 | } | |
6746 | ||
ac678990 NQ |
6747 | fill_frame_info(pbi, pic_config, frame_size, vf->pts); |
6748 | ||
5f2400c0 | 6749 | pts_save = vf->pts; |
6750 | pts_us64_save = vf->pts_us64; | |
c20e6c85 | 6751 | if (pbi->pts_unstable) { |
6752 | frame_duration_adapt(pbi, vf, pts_valid); | |
6753 | if (pbi->duration_from_pts_done) { | |
6754 | pbi->pts_mode = PTS_NONE_REF_USE_DURATION; | |
6755 | } else { | |
6756 | if (pts_valid || pts_us64_valid) | |
6757 | pbi->pts_mode = PTS_NORMAL; | |
6758 | } | |
6759 | } | |
b9164398 NQ |
6760 | |
6761 | if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0) | |
6762 | && pbi->get_frame_dur) { | |
6763 | int pts_diff = (int)vf->pts - pbi->last_lookup_pts; | |
6764 | ||
6765 | if (pts_diff < 0) { | |
6766 | pbi->pts_mode_switching_count++; | |
6767 | pbi->pts_mode_recovery_count = 0; | |
6768 | ||
6769 | if (pbi->pts_mode_switching_count >= | |
6770 | PTS_MODE_SWITCHING_THRESHOLD) { | |
6771 | pbi->pts_mode = | |
6772 | PTS_NONE_REF_USE_DURATION; | |
6773 | pr_info | |
6774 | ("HEVC: switch to n_d mode.\n"); | |
6775 | } | |
6776 | ||
6777 | } else { | |
6778 | int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD; | |
e0614bf7 | 6779 | |
b9164398 NQ |
6780 | pbi->pts_mode_recovery_count++; |
6781 | if (pbi->pts_mode_recovery_count > p) { | |
6782 | pbi->pts_mode_switching_count = 0; | |
6783 | pbi->pts_mode_recovery_count = 0; | |
6784 | } | |
6785 | } | |
6786 | } | |
6787 | ||
6788 | if (vf->pts != 0) | |
6789 | pbi->last_lookup_pts = vf->pts; | |
6790 | ||
6791 | if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION) | |
6792 | && (slice_type != KEY_FRAME)) | |
6793 | vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur); | |
6794 | pbi->last_pts = vf->pts; | |
6795 | ||
6796 | if (vf->pts_us64 != 0) | |
6797 | pbi->last_lookup_pts_us64 = vf->pts_us64; | |
6798 | ||
6799 | if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION) | |
6800 | && (slice_type != KEY_FRAME)) { | |
6801 | vf->pts_us64 = | |
6802 | pbi->last_pts_us64 + | |
6803 | (DUR2PTS(pbi->frame_dur) * 100 / 9); | |
6804 | } | |
6805 | pbi->last_pts_us64 = vf->pts_us64; | |
6806 | if ((debug & VP9_DEBUG_OUT_PTS) != 0) { | |
6807 | pr_info | |
546484c5 | 6808 | ("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n", |
6809 | pbi->pts_mode, pbi->frame_dur, vf->pts, | |
6810 | vf->pts_us64, pts_save, pts_us64_save); | |
b9164398 NQ |
6811 | } |
6812 | ||
5f2400c0 | 6813 | if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) { |
6814 | vf->disp_pts = vf->pts; | |
6815 | vf->disp_pts_us64 = vf->pts_us64; | |
6816 | vf->pts = pts_save; | |
6817 | vf->pts_us64 = pts_us64_save; | |
6818 | } else { | |
6819 | vf->disp_pts = 0; | |
6820 | vf->disp_pts_us64 = 0; | |
6821 | } | |
6822 | ||
b9164398 | 6823 | vf->index = 0xff00 | pic_config->index; |
fe96802b | 6824 | |
c23e8aee | 6825 | if (pic_config->double_write_mode & 0x10) { |
b9164398 NQ |
6826 | /* double write only */ |
6827 | vf->compBodyAddr = 0; | |
6828 | vf->compHeadAddr = 0; | |
6829 | } else { | |
b7706e1e | 6830 | if (pbi->mmu_enable) { |
6831 | vf->compBodyAddr = 0; | |
6832 | vf->compHeadAddr = pic_config->header_adr; | |
6833 | } else { | |
6834 | /*vf->compBodyAddr = pic_config->mc_y_adr; | |
6835 | *vf->compHeadAddr = pic_config->mc_y_adr + | |
6836 | *pic_config->comp_body_size; */ | |
6837 | /*head adr*/ | |
6838 | } | |
6839 | vf->canvas0Addr = vf->canvas1Addr = 0; | |
b9164398 | 6840 | } |
c23e8aee | 6841 | if (pic_config->double_write_mode) { |
b9164398 NQ |
6842 | vf->type = VIDTYPE_PROGRESSIVE | |
6843 | VIDTYPE_VIU_FIELD; | |
6844 | vf->type |= VIDTYPE_VIU_NV21; | |
e0e39311 | 6845 | if ((pic_config->double_write_mode == 3) && |
6846 | (!IS_8K_SIZE(pic_config->y_crop_width, | |
6847 | pic_config->y_crop_height))) { | |
fe96802b | 6848 | vf->type |= VIDTYPE_COMPRESS; |
b7706e1e | 6849 | if (pbi->mmu_enable) |
6850 | vf->type |= VIDTYPE_SCATTER; | |
fe96802b | 6851 | } |
b9164398 NQ |
6852 | #ifdef MULTI_INSTANCE_SUPPORT |
6853 | if (pbi->m_ins_flag) { | |
e0614bf7 ZZ |
6854 | vf->canvas0Addr = vf->canvas1Addr = -1; |
6855 | vf->plane_num = 2; | |
6856 | vf->canvas0_config[0] = | |
6857 | pic_config->canvas_config[0]; | |
6858 | vf->canvas0_config[1] = | |
6859 | pic_config->canvas_config[1]; | |
6860 | vf->canvas1_config[0] = | |
6861 | pic_config->canvas_config[0]; | |
6862 | vf->canvas1_config[1] = | |
6863 | pic_config->canvas_config[1]; | |
b9164398 NQ |
6864 | |
6865 | } else | |
6866 | #endif | |
6867 | vf->canvas0Addr = vf->canvas1Addr = | |
6868 | spec2canvas(pic_config); | |
6869 | } else { | |
6870 | vf->canvas0Addr = vf->canvas1Addr = 0; | |
6871 | vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD; | |
b7706e1e | 6872 | if (pbi->mmu_enable) |
6873 | vf->type |= VIDTYPE_SCATTER; | |
fe96802b NQ |
6874 | } |
6875 | ||
6876 | switch (pic_config->bit_depth) { | |
6877 | case VPX_BITS_8: | |
6878 | vf->bitdepth = BITDEPTH_Y8 | | |
6879 | BITDEPTH_U8 | BITDEPTH_V8; | |
6880 | break; | |
6881 | case VPX_BITS_10: | |
6882 | case VPX_BITS_12: | |
6883 | vf->bitdepth = BITDEPTH_Y10 | | |
6884 | BITDEPTH_U10 | BITDEPTH_V10; | |
6885 | break; | |
6886 | default: | |
6887 | vf->bitdepth = BITDEPTH_Y10 | | |
6888 | BITDEPTH_U10 | BITDEPTH_V10; | |
6889 | break; | |
6890 | } | |
6891 | if ((vf->type & VIDTYPE_COMPRESS) == 0) | |
6892 | vf->bitdepth = | |
6893 | BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8; | |
6894 | if (pic_config->bit_depth == VPX_BITS_8) | |
6895 | vf->bitdepth |= BITDEPTH_SAVING_MODE; | |
6896 | ||
b9164398 | 6897 | /* if((vf->width!=pic_config->width)| |
e0614bf7 ZZ |
6898 | * (vf->height!=pic_config->height)) |
6899 | */ | |
b9164398 NQ |
6900 | /* pr_info("aaa: %d/%d, %d/%d\n", |
6901 | vf->width,vf->height, pic_config->width, | |
6902 | pic_config->height); */ | |
c23e8aee HZ |
6903 | vf->width = pic_config->y_crop_width / |
6904 | get_double_write_ratio(pbi, | |
6905 | pic_config->double_write_mode); | |
6906 | vf->height = pic_config->y_crop_height / | |
6907 | get_double_write_ratio(pbi, | |
6908 | pic_config->double_write_mode); | |
b9164398 NQ |
6909 | if (force_w_h != 0) { |
6910 | vf->width = (force_w_h >> 16) & 0xffff; | |
6911 | vf->height = force_w_h & 0xffff; | |
6912 | } | |
6913 | vf->compWidth = pic_config->y_crop_width; | |
6914 | vf->compHeight = pic_config->y_crop_height; | |
9edb8e76 | 6915 | set_frame_info(pbi, vf); |
b9164398 NQ |
6916 | if (force_fps & 0x100) { |
6917 | u32 rate = force_fps & 0xff; | |
e0614bf7 | 6918 | |
b9164398 NQ |
6919 | if (rate) |
6920 | vf->duration = 96000/rate; | |
6921 | else | |
6922 | vf->duration = 0; | |
6923 | } | |
b7706e1e | 6924 | update_vf_memhandle(pbi, vf, pic_config); |
c23e8aee | 6925 | if (!(pic_config->y_crop_width == 196 |
a6c89e96 NQ |
6926 | && pic_config->y_crop_height == 196 |
6927 | && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0 | |
6928 | )) { | |
b9164398 | 6929 | inc_vf_ref(pbi, pic_config->index); |
5050c738 | 6930 | decoder_do_frame_check(hw_to_vdec(pbi), vf); |
b9164398 | 6931 | kfifo_put(&pbi->display_q, (const struct vframe_s *)vf); |
a093654a | 6932 | ATRACE_COUNTER(MODULE_NAME, vf->pts); |
fe96802b NQ |
6933 | pbi->vf_pre_count++; |
6934 | #ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC | |
6935 | /*count info*/ | |
6936 | gvs->frame_dur = pbi->frame_dur; | |
6937 | vdec_count_info(gvs, 0, stream_offset); | |
6938 | #endif | |
97fe3d16 | 6939 | hw_to_vdec(pbi)->vdec_fps_detec(hw_to_vdec(pbi)->id); |
b9164398 NQ |
6940 | vf_notify_receiver(pbi->provider_name, |
6941 | VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); | |
c23e8aee HZ |
6942 | } else { |
6943 | pbi->stat |= VP9_TRIGGER_FRAME_DONE; | |
6944 | hevc_source_changed(VFORMAT_VP9, 196, 196, 30); | |
6945 | pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n", | |
6946 | __func__, __LINE__, vf->width, | |
6947 | vf->height, pbi->stat); | |
6948 | } | |
b9164398 NQ |
6949 | } |
6950 | ||
6951 | return 0; | |
6952 | } | |
6953 | ||
2cd6815e NQ |
6954 | static int notify_v4l_eos(struct vdec_s *vdec) |
6955 | { | |
6956 | struct VP9Decoder_s *hw = (struct VP9Decoder_s *)vdec->private; | |
6957 | struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx); | |
6958 | struct vframe_s *vf = NULL; | |
6959 | struct vdec_fb *fb = NULL; | |
6960 | ||
6961 | if (hw->is_used_v4l && hw->eos) { | |
6962 | if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) { | |
6963 | vp9_print(hw, 0, | |
6964 | "%s fatal error, no available buffer slot.\n", | |
6965 | __func__); | |
6966 | return -1; | |
6967 | } | |
6968 | ||
6969 | if (v4l_get_fb(hw->v4l2_ctx, &fb)) { | |
6970 | pr_err("[%d] get fb fail.\n", ctx->id); | |
6971 | return -1; | |
6972 | } | |
6973 | ||
6974 | vf->timestamp = ULONG_MAX; | |
6975 | vf->v4l_mem_handle = (unsigned long)fb; | |
6976 | vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L; | |
6977 | ||
6978 | kfifo_put(&hw->display_q, (const struct vframe_s *)vf); | |
6979 | vf_notify_receiver(vdec->vf_provider_name, | |
6980 | VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); | |
6981 | ||
6982 | pr_info("[%d] VP9 EOS notify.\n", ctx->id); | |
6983 | } | |
6984 | ||
6985 | return 0; | |
6986 | } | |
6987 | ||
b9164398 NQ |
6988 | static void get_rpm_param(union param_u *params) |
6989 | { | |
6990 | int i; | |
6991 | unsigned int data32; | |
e0614bf7 | 6992 | |
b9164398 NQ |
6993 | if (debug & VP9_DEBUG_BUFMGR) |
6994 | pr_info("enter %s\r\n", __func__); | |
6995 | for (i = 0; i < 128; i++) { | |
6996 | do { | |
6997 | data32 = READ_VREG(RPM_CMD_REG); | |
6998 | /*pr_info("%x\n", data32);*/ | |
6999 | } while ((data32 & 0x10000) == 0); | |
7000 | params->l.data[i] = data32&0xffff; | |
7001 | /*pr_info("%x\n", data32);*/ | |
7002 | WRITE_VREG(RPM_CMD_REG, 0); | |
7003 | } | |
7004 | if (debug & VP9_DEBUG_BUFMGR) | |
7005 | pr_info("leave %s\r\n", __func__); | |
7006 | } | |
7007 | static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi) | |
7008 | { | |
7009 | int i; | |
e0614bf7 | 7010 | |
b9164398 NQ |
7011 | if (!(debug & VP9_DEBUG_BUFMGR_MORE)) |
7012 | return; | |
7013 | pr_info("vp9_param: (%d)\n", pbi->slice_idx); | |
7014 | for (i = 0; i < (RPM_END-RPM_BEGIN); i++) { | |
7015 | pr_info("%04x ", vp9_param.l.data[i]); | |
7016 | if (((i + 1) & 0xf) == 0) | |
7017 | pr_info("\n"); | |
7018 | } | |
7019 | pr_info("=============param==========\r\n"); | |
7020 | pr_info("profile %x\r\n", vp9_param.p.profile); | |
7021 | pr_info("show_existing_frame %x\r\n", | |
7022 | vp9_param.p.show_existing_frame); | |
7023 | pr_info("frame_to_show_idx %x\r\n", | |
7024 | vp9_param.p.frame_to_show_idx); | |
7025 | pr_info("frame_type %x\r\n", vp9_param.p.frame_type); | |
7026 | pr_info("show_frame %x\r\n", vp9_param.p.show_frame); | |
7027 | pr_info("e.r.r.o.r_resilient_mode %x\r\n", | |
7028 | vp9_param.p.error_resilient_mode); | |
7029 | pr_info("intra_only %x\r\n", vp9_param.p.intra_only); | |
7030 | pr_info("display_size_present %x\r\n", | |
7031 | vp9_param.p.display_size_present); | |
7032 | pr_info("reset_frame_context %x\r\n", | |
7033 | vp9_param.p.reset_frame_context); | |
7034 | pr_info("refresh_frame_flags %x\r\n", | |
7035 | vp9_param.p.refresh_frame_flags); | |
7036 | pr_info("bit_depth %x\r\n", vp9_param.p.bit_depth); | |
7037 | pr_info("width %x\r\n", vp9_param.p.width); | |
7038 | pr_info("height %x\r\n", vp9_param.p.height); | |
7039 | pr_info("display_width %x\r\n", vp9_param.p.display_width); | |
7040 | pr_info("display_height %x\r\n", vp9_param.p.display_height); | |
7041 | pr_info("ref_info %x\r\n", vp9_param.p.ref_info); | |
7042 | pr_info("same_frame_size %x\r\n", vp9_param.p.same_frame_size); | |
7043 | if (!(debug & VP9_DEBUG_DBG_LF_PRINT)) | |
7044 | return; | |
7045 | pr_info("mode_ref_delta_enabled: 0x%x\r\n", | |
7046 | vp9_param.p.mode_ref_delta_enabled); | |
7047 | pr_info("sharpness_level: 0x%x\r\n", | |
7048 | vp9_param.p.sharpness_level); | |
7049 | pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n", | |
7050 | vp9_param.p.ref_deltas[0], vp9_param.p.ref_deltas[1], | |
7051 | vp9_param.p.ref_deltas[2], vp9_param.p.ref_deltas[3]); | |
7052 | pr_info("mode_deltas: 0x%x, 0x%x\r\n", vp9_param.p.mode_deltas[0], | |
7053 | vp9_param.p.mode_deltas[1]); | |
7054 | pr_info("filter_level: 0x%x\r\n", vp9_param.p.filter_level); | |
7055 | pr_info("seg_enabled: 0x%x\r\n", vp9_param.p.seg_enabled); | |
7056 | pr_info("seg_abs_delta: 0x%x\r\n", vp9_param.p.seg_abs_delta); | |
7057 | pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n", | |
7058 | (vp9_param.p.seg_lf_info[0]>>15 & 1), | |
7059 | (vp9_param.p.seg_lf_info[1]>>15 & 1), | |
7060 | (vp9_param.p.seg_lf_info[2]>>15 & 1), | |
7061 | (vp9_param.p.seg_lf_info[3]>>15 & 1), | |
7062 | (vp9_param.p.seg_lf_info[4]>>15 & 1), | |
7063 | (vp9_param.p.seg_lf_info[5]>>15 & 1), | |
7064 | (vp9_param.p.seg_lf_info[6]>>15 & 1), | |
7065 | (vp9_param.p.seg_lf_info[7]>>15 & 1)); | |
7066 | pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n", | |
7067 | (vp9_param.p.seg_lf_info[0] & 0x13f), | |
7068 | (vp9_param.p.seg_lf_info[1] & 0x13f), | |
7069 | (vp9_param.p.seg_lf_info[2] & 0x13f), | |
7070 | (vp9_param.p.seg_lf_info[3] & 0x13f), | |
7071 | (vp9_param.p.seg_lf_info[4] & 0x13f), | |
7072 | (vp9_param.p.seg_lf_info[5] & 0x13f), | |
7073 | (vp9_param.p.seg_lf_info[6] & 0x13f), | |
7074 | (vp9_param.p.seg_lf_info[7] & 0x13f)); | |
7075 | ||
7076 | } | |
7077 | ||
b7706e1e | 7078 | |
fe96802b NQ |
7079 | static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi) |
7080 | { | |
7081 | struct VP9_Common_s *const cm = &pbi->common; | |
6276f4ff HZ |
7082 | if (pbi->double_write_mode & 0x10) |
7083 | return; | |
fe96802b | 7084 | if (cm->cur_fb_idx_mmu != INVALID_IDX) { |
144f5ee8 | 7085 | if (pbi->used_4k_num == -1) { |
fe96802b NQ |
7086 | pbi->used_4k_num = |
7087 | (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); | |
144f5ee8 HZ |
7088 | if (pbi->m_ins_flag) |
7089 | hevc_mmu_dma_check(hw_to_vdec(pbi)); | |
7090 | } | |
fe96802b NQ |
7091 | decoder_mmu_box_free_idx_tail(pbi->mmu_box, |
7092 | cm->cur_fb_idx_mmu, pbi->used_4k_num); | |
fe96802b NQ |
7093 | cm->cur_fb_idx_mmu = INVALID_IDX; |
7094 | pbi->used_4k_num = -1; | |
7095 | } | |
7096 | } | |
7097 | ||
7098 | #ifdef MULTI_INSTANCE_SUPPORT | |
7099 | static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi) | |
7100 | { | |
7101 | struct VP9_Common_s *const cm = &pbi->common; | |
6276f4ff HZ |
7102 | if (pbi->double_write_mode & 0x10) |
7103 | return; | |
fe96802b NQ |
7104 | if (cm->cur_fb_idx_mmu != INVALID_IDX) { |
7105 | decoder_mmu_box_free_idx(pbi->mmu_box, | |
7106 | cm->cur_fb_idx_mmu); | |
7107 | ||
7108 | cm->cur_fb_idx_mmu = INVALID_IDX; | |
7109 | pbi->used_4k_num = -1; | |
7110 | } | |
7111 | } | |
7112 | #endif | |
b7706e1e | 7113 | |
fe96802b NQ |
7114 | |
7115 | static void dec_again_process(struct VP9Decoder_s *pbi) | |
7116 | { | |
7117 | amhevc_stop(); | |
7118 | pbi->dec_result = DEC_RESULT_AGAIN; | |
7119 | if (pbi->process_state == | |
7120 | PROC_STATE_DECODESLICE) { | |
7121 | pbi->process_state = | |
7122 | PROC_STATE_SENDAGAIN; | |
b7706e1e | 7123 | if (pbi->mmu_enable) |
7124 | vp9_recycle_mmu_buf(pbi); | |
fe96802b NQ |
7125 | } |
7126 | reset_process_time(pbi); | |
7127 | vdec_schedule_work(&pbi->work); | |
7128 | } | |
7129 | ||
a6c89e96 NQ |
7130 | int continue_decoding(struct VP9Decoder_s *pbi) |
7131 | { | |
7132 | int ret; | |
7133 | int i; | |
7134 | struct VP9_Common_s *const cm = &pbi->common; | |
7135 | debug_buffer_mgr_more(pbi); | |
7136 | ||
7137 | bit_depth_luma = vp9_param.p.bit_depth; | |
7138 | bit_depth_chroma = vp9_param.p.bit_depth; | |
7139 | ||
7140 | if (pbi->process_state != PROC_STATE_SENDAGAIN) { | |
7141 | ret = vp9_bufmgr_process(pbi, &vp9_param); | |
7142 | if (!pbi->m_ins_flag) | |
7143 | pbi->slice_idx++; | |
7144 | } else { | |
7145 | union param_u *params = &vp9_param; | |
6276f4ff | 7146 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
b7706e1e | 7147 | ret = vp9_alloc_mmu(pbi, |
a6c89e96 | 7148 | cm->new_fb_idx, |
b7706e1e | 7149 | params->p.width, |
7150 | params->p.height, | |
7151 | params->p.bit_depth, | |
7152 | pbi->frame_mmu_map_addr); | |
7153 | if (ret >= 0) | |
7154 | cm->cur_fb_idx_mmu = cm->new_fb_idx; | |
7155 | else | |
7156 | pr_err("can't alloc need mmu1,idx %d ret =%d\n", | |
7157 | cm->new_fb_idx, | |
7158 | ret); | |
7159 | } else { | |
7160 | ret = 0; | |
7161 | } | |
a6c89e96 NQ |
7162 | WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, |
7163 | (params->p.height << 16) | params->p.width); | |
7164 | } | |
7165 | if (ret < 0) { | |
7166 | pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n", | |
7167 | ret); | |
7168 | WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL); | |
7169 | cm->show_frame = 0; | |
b7706e1e | 7170 | if (pbi->mmu_enable) |
7171 | vp9_recycle_mmu_buf(pbi); | |
a6c89e96 NQ |
7172 | #ifdef MULTI_INSTANCE_SUPPORT |
7173 | if (pbi->m_ins_flag) { | |
7174 | pbi->dec_result = DEC_RESULT_DONE; | |
7175 | #ifdef SUPPORT_FB_DECODING | |
7176 | if (pbi->used_stage_buf_num == 0) | |
7177 | #endif | |
7178 | amhevc_stop(); | |
7179 | vdec_schedule_work(&pbi->work); | |
7180 | } | |
7181 | #endif | |
7182 | return ret; | |
7183 | } else if (ret == 0) { | |
7184 | struct PIC_BUFFER_CONFIG_s *cur_pic_config | |
7185 | = &cm->cur_frame->buf; | |
7186 | cur_pic_config->decode_idx = pbi->frame_count; | |
7187 | ||
7188 | if (pbi->process_state != PROC_STATE_SENDAGAIN) { | |
7189 | if (!pbi->m_ins_flag) { | |
7190 | pbi->frame_count++; | |
7191 | decode_frame_count[pbi->index] | |
7192 | = pbi->frame_count; | |
7193 | } | |
7194 | #ifdef MULTI_INSTANCE_SUPPORT | |
7195 | if (pbi->chunk) { | |
7196 | cur_pic_config->pts = pbi->chunk->pts; | |
7197 | cur_pic_config->pts64 = pbi->chunk->pts64; | |
7198 | } | |
7199 | #endif | |
7200 | } | |
7201 | /*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/ | |
7202 | config_pic_size(pbi, vp9_param.p.bit_depth); | |
7203 | ||
7204 | if ((pbi->common.frame_type != KEY_FRAME) | |
7205 | && (!pbi->common.intra_only)) { | |
7206 | config_mc_buffer(pbi, vp9_param.p.bit_depth); | |
7207 | #ifdef SUPPORT_FB_DECODING | |
7208 | if (pbi->used_stage_buf_num == 0) | |
7209 | #endif | |
7210 | config_mpred_hw(pbi); | |
7211 | } else { | |
7212 | #ifdef SUPPORT_FB_DECODING | |
7213 | if (pbi->used_stage_buf_num == 0) | |
7214 | #endif | |
7215 | clear_mpred_hw(pbi); | |
7216 | } | |
7217 | #ifdef MCRCC_ENABLE | |
7218 | if (mcrcc_cache_alg_flag) | |
7219 | config_mcrcc_axi_hw_new(pbi); | |
7220 | else | |
7221 | config_mcrcc_axi_hw(pbi); | |
7222 | #endif | |
7223 | config_sao_hw(pbi, &vp9_param); | |
7224 | ||
7225 | #ifdef VP9_LPF_LVL_UPDATE | |
b7706e1e | 7226 | /* |
7227 | * Get loop filter related picture level parameters from Parser | |
7228 | */ | |
7229 | pbi->lf->mode_ref_delta_enabled = vp9_param.p.mode_ref_delta_enabled; | |
7230 | pbi->lf->sharpness_level = vp9_param.p.sharpness_level; | |
7231 | for (i = 0; i < 4; i++) | |
7232 | pbi->lf->ref_deltas[i] = vp9_param.p.ref_deltas[i]; | |
7233 | for (i = 0; i < 2; i++) | |
7234 | pbi->lf->mode_deltas[i] = vp9_param.p.mode_deltas[i]; | |
7235 | pbi->default_filt_lvl = vp9_param.p.filter_level; | |
7236 | pbi->seg_4lf->enabled = vp9_param.p.seg_enabled; | |
7237 | pbi->seg_4lf->abs_delta = vp9_param.p.seg_abs_delta; | |
7238 | for (i = 0; i < MAX_SEGMENTS; i++) | |
7239 | pbi->seg_4lf->feature_mask[i] = (vp9_param.p.seg_lf_info[i] & | |
7240 | 0x8000) ? (1 << SEG_LVL_ALT_LF) : 0; | |
7241 | for (i = 0; i < MAX_SEGMENTS; i++) | |
7242 | pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF] | |
7243 | = (vp9_param.p.seg_lf_info[i] | |
7244 | & 0x100) ? -(vp9_param.p.seg_lf_info[i] | |
7245 | & 0x3f) : (vp9_param.p.seg_lf_info[i] & 0x3f); | |
7246 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { | |
7247 | /*Set pipeline mode*/ | |
7248 | uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB); | |
7249 | /*dblk pipeline mode=1 for performance*/ | |
7250 | if (vp9_param.p.width >= 1280) | |
7251 | lpf_data32 |= (0x1 << 4); | |
7252 | else | |
7253 | lpf_data32 &= ~(0x3 << 4); | |
7254 | WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32); | |
7255 | } | |
7256 | /* | |
7257 | * Update loop filter Thr/Lvl table for every frame | |
7258 | */ | |
7259 | /*pr_info | |
7260 | ("vp9_loop_filter (run before every frame decoding start)\n");*/ | |
7261 | vp9_loop_filter_frame_init(pbi->seg_4lf, | |
7262 | pbi->lfi, pbi->lf, pbi->default_filt_lvl); | |
a6c89e96 | 7263 | #endif |
b7706e1e | 7264 | /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/ |
7265 | WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE); | |
a6c89e96 NQ |
7266 | } else { |
7267 | pr_info("Skip search next start code\n"); | |
7268 | cm->prev_fb_idx = INVALID_IDX; | |
7269 | /*skip, search next start code*/ | |
7270 | WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE); | |
7271 | } | |
7272 | pbi->process_state = PROC_STATE_DECODESLICE; | |
6276f4ff | 7273 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
87046a60 | 7274 | if (pbi->last_put_idx < pbi->used_buf_num) { |
b7706e1e | 7275 | struct RefCntBuffer_s *frame_bufs = |
7276 | cm->buffer_pool->frame_bufs; | |
7277 | int i = pbi->last_put_idx; | |
7278 | /*free not used buffers.*/ | |
7279 | if ((frame_bufs[i].ref_count == 0) && | |
7280 | (frame_bufs[i].buf.vf_ref == 0) && | |
7281 | (frame_bufs[i].buf.index != -1)) { | |
7282 | decoder_mmu_box_free_idx(pbi->mmu_box, i); | |
7283 | } | |
7284 | pbi->last_put_idx = -1; | |
a6c89e96 | 7285 | } |
a6c89e96 | 7286 | } |
a6c89e96 NQ |
7287 | return ret; |
7288 | } | |
7289 | ||
ac678990 NQ |
7290 | static void fill_frame_info(struct VP9Decoder_s *pbi, |
7291 | struct PIC_BUFFER_CONFIG_s *frame, | |
7292 | unsigned int framesize, | |
7293 | unsigned int pts) | |
7294 | { | |
7295 | struct vframe_qos_s *vframe_qos = &pbi->vframe_qos; | |
7296 | ||
7297 | if (frame->slice_type == KEY_FRAME) | |
7298 | vframe_qos->type = 1; | |
7299 | else if (frame->slice_type == INTER_FRAME) | |
7300 | vframe_qos->type = 2; | |
7301 | /* | |
7302 | #define SHOW_QOS_INFO | |
7303 | */ | |
7304 | vframe_qos->size = framesize; | |
7305 | vframe_qos->pts = pts; | |
7306 | #ifdef SHOW_QOS_INFO | |
7307 | vp9_print(pbi, 0, "slice:%d\n", frame->slice_type); | |
7308 | #endif | |
7309 | vframe_qos->max_mv = frame->max_mv; | |
7310 | vframe_qos->avg_mv = frame->avg_mv; | |
7311 | vframe_qos->min_mv = frame->min_mv; | |
7312 | #ifdef SHOW_QOS_INFO | |
7313 | vp9_print(pbi, 0, "mv: max:%d, avg:%d, min:%d\n", | |
7314 | vframe_qos->max_mv, | |
7315 | vframe_qos->avg_mv, | |
7316 | vframe_qos->min_mv); | |
7317 | #endif | |
7318 | vframe_qos->max_qp = frame->max_qp; | |
7319 | vframe_qos->avg_qp = frame->avg_qp; | |
7320 | vframe_qos->min_qp = frame->min_qp; | |
7321 | #ifdef SHOW_QOS_INFO | |
7322 | vp9_print(pbi, 0, "qp: max:%d, avg:%d, min:%d\n", | |
7323 | vframe_qos->max_qp, | |
7324 | vframe_qos->avg_qp, | |
7325 | vframe_qos->min_qp); | |
7326 | #endif | |
7327 | vframe_qos->max_skip = frame->max_skip; | |
7328 | vframe_qos->avg_skip = frame->avg_skip; | |
7329 | vframe_qos->min_skip = frame->min_skip; | |
7330 | #ifdef SHOW_QOS_INFO | |
7331 | vp9_print(pbi, 0, "skip: max:%d, avg:%d, min:%d\n", | |
7332 | vframe_qos->max_skip, | |
7333 | vframe_qos->avg_skip, | |
7334 | vframe_qos->min_skip); | |
7335 | #endif | |
7336 | vframe_qos->num++; | |
7337 | ||
7338 | if (pbi->frameinfo_enable) | |
7339 | vdec_fill_frame_info(vframe_qos, 1); | |
7340 | } | |
7341 | ||
7342 | /* only when we decoded one field or one frame, | |
7343 | we can call this function to get qos info*/ | |
7344 | static void get_picture_qos_info(struct VP9Decoder_s *pbi) | |
7345 | { | |
7346 | struct PIC_BUFFER_CONFIG_s *frame = &pbi->cur_buf->buf; | |
7347 | ||
7348 | if (!frame) | |
7349 | return; | |
7350 | ||
7351 | if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) { | |
7352 | unsigned char a[3]; | |
7353 | unsigned char i, j, t; | |
7354 | unsigned long data; | |
7355 | ||
7356 | data = READ_VREG(HEVC_MV_INFO); | |
7357 | if (frame->slice_type == KEY_FRAME) | |
7358 | data = 0; | |
7359 | a[0] = data & 0xff; | |
7360 | a[1] = (data >> 8) & 0xff; | |
7361 | a[2] = (data >> 16) & 0xff; | |
7362 | ||
7363 | for (i = 0; i < 3; i++) { | |
7364 | for (j = i+1; j < 3; j++) { | |
7365 | if (a[j] < a[i]) { | |
7366 | t = a[j]; | |
7367 | a[j] = a[i]; | |
7368 | a[i] = t; | |
7369 | } else if (a[j] == a[i]) { | |
7370 | a[i]++; | |
7371 | t = a[j]; | |
7372 | a[j] = a[i]; | |
7373 | a[i] = t; | |
7374 | } | |
7375 | } | |
7376 | } | |
7377 | frame->max_mv = a[2]; | |
7378 | frame->avg_mv = a[1]; | |
7379 | frame->min_mv = a[0]; | |
7380 | ||
7381 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7382 | "mv data %x a[0]= %x a[1]= %x a[2]= %x\n", | |
7383 | data, a[0], a[1], a[2]); | |
7384 | ||
7385 | data = READ_VREG(HEVC_QP_INFO); | |
7386 | a[0] = data & 0x1f; | |
7387 | a[1] = (data >> 8) & 0x3f; | |
7388 | a[2] = (data >> 16) & 0x7f; | |
7389 | ||
7390 | for (i = 0; i < 3; i++) { | |
7391 | for (j = i+1; j < 3; j++) { | |
7392 | if (a[j] < a[i]) { | |
7393 | t = a[j]; | |
7394 | a[j] = a[i]; | |
7395 | a[i] = t; | |
7396 | } else if (a[j] == a[i]) { | |
7397 | a[i]++; | |
7398 | t = a[j]; | |
7399 | a[j] = a[i]; | |
7400 | a[i] = t; | |
7401 | } | |
7402 | } | |
7403 | } | |
7404 | frame->max_qp = a[2]; | |
7405 | frame->avg_qp = a[1]; | |
7406 | frame->min_qp = a[0]; | |
7407 | ||
7408 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7409 | "qp data %x a[0]= %x a[1]= %x a[2]= %x\n", | |
7410 | data, a[0], a[1], a[2]); | |
7411 | ||
7412 | data = READ_VREG(HEVC_SKIP_INFO); | |
7413 | a[0] = data & 0x1f; | |
7414 | a[1] = (data >> 8) & 0x3f; | |
7415 | a[2] = (data >> 16) & 0x7f; | |
7416 | ||
7417 | for (i = 0; i < 3; i++) { | |
7418 | for (j = i+1; j < 3; j++) { | |
7419 | if (a[j] < a[i]) { | |
7420 | t = a[j]; | |
7421 | a[j] = a[i]; | |
7422 | a[i] = t; | |
7423 | } else if (a[j] == a[i]) { | |
7424 | a[i]++; | |
7425 | t = a[j]; | |
7426 | a[j] = a[i]; | |
7427 | a[i] = t; | |
7428 | } | |
7429 | } | |
7430 | } | |
7431 | frame->max_skip = a[2]; | |
7432 | frame->avg_skip = a[1]; | |
7433 | frame->min_skip = a[0]; | |
7434 | ||
7435 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7436 | "skip data %x a[0]= %x a[1]= %x a[2]= %x\n", | |
7437 | data, a[0], a[1], a[2]); | |
7438 | } else { | |
7439 | uint32_t blk88_y_count; | |
7440 | uint32_t blk88_c_count; | |
7441 | uint32_t blk22_mv_count; | |
7442 | uint32_t rdata32; | |
7443 | int32_t mv_hi; | |
7444 | int32_t mv_lo; | |
7445 | uint32_t rdata32_l; | |
7446 | uint32_t mvx_L0_hi; | |
7447 | uint32_t mvy_L0_hi; | |
7448 | uint32_t mvx_L1_hi; | |
7449 | uint32_t mvy_L1_hi; | |
7450 | int64_t value; | |
7451 | uint64_t temp_value; | |
7452 | int pic_number = frame->decode_idx; | |
7453 | ||
7454 | frame->max_mv = 0; | |
7455 | frame->avg_mv = 0; | |
7456 | frame->min_mv = 0; | |
7457 | ||
7458 | frame->max_skip = 0; | |
7459 | frame->avg_skip = 0; | |
7460 | frame->min_skip = 0; | |
7461 | ||
7462 | frame->max_qp = 0; | |
7463 | frame->avg_qp = 0; | |
7464 | frame->min_qp = 0; | |
7465 | ||
7466 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n", | |
7467 | frame->slice_type, | |
7468 | pic_number); | |
7469 | ||
7470 | /* set rd_idx to 0 */ | |
7471 | WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0); | |
7472 | ||
7473 | blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7474 | if (blk88_y_count == 0) { | |
7475 | ||
7476 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7477 | "[Picture %d Quality] NO Data yet.\n", | |
7478 | pic_number); | |
7479 | ||
7480 | /* reset all counts */ | |
7481 | WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8)); | |
7482 | return; | |
7483 | } | |
7484 | /* qp_y_sum */ | |
7485 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7486 | ||
7487 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7488 | "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n", | |
7489 | pic_number, rdata32/blk88_y_count, | |
7490 | rdata32, blk88_y_count); | |
7491 | ||
7492 | frame->avg_qp = rdata32/blk88_y_count; | |
7493 | /* intra_y_count */ | |
7494 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7495 | ||
7496 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7497 | "[Picture %d Quality] Y intra rate : %d%c (%d)\n", | |
7498 | pic_number, rdata32*100/blk88_y_count, | |
7499 | '%', rdata32); | |
7500 | ||
7501 | /* skipped_y_count */ | |
7502 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7503 | ||
7504 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7505 | "[Picture %d Quality] Y skipped rate : %d%c (%d)\n", | |
7506 | pic_number, rdata32*100/blk88_y_count, | |
7507 | '%', rdata32); | |
7508 | ||
7509 | frame->avg_skip = rdata32*100/blk88_y_count; | |
7510 | /* coeff_non_zero_y_count */ | |
7511 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7512 | ||
7513 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7514 | "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n", | |
7515 | pic_number, (100 - rdata32*100/(blk88_y_count*1)), | |
7516 | '%', rdata32); | |
7517 | ||
7518 | /* blk66_c_count */ | |
7519 | blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7520 | if (blk88_c_count == 0) { | |
7521 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7522 | "[Picture %d Quality] NO Data yet.\n", | |
7523 | pic_number); | |
7524 | /* reset all counts */ | |
7525 | WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8)); | |
7526 | return; | |
7527 | } | |
7528 | /* qp_c_sum */ | |
7529 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7530 | ||
7531 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7532 | "[Picture %d Quality] C QP AVG : %d (%d/%d)\n", | |
7533 | pic_number, rdata32/blk88_c_count, | |
7534 | rdata32, blk88_c_count); | |
7535 | ||
7536 | /* intra_c_count */ | |
7537 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7538 | ||
7539 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7540 | "[Picture %d Quality] C intra rate : %d%c (%d)\n", | |
7541 | pic_number, rdata32*100/blk88_c_count, | |
7542 | '%', rdata32); | |
7543 | ||
7544 | /* skipped_cu_c_count */ | |
7545 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7546 | ||
7547 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7548 | "[Picture %d Quality] C skipped rate : %d%c (%d)\n", | |
7549 | pic_number, rdata32*100/blk88_c_count, | |
7550 | '%', rdata32); | |
7551 | ||
7552 | /* coeff_non_zero_c_count */ | |
7553 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7554 | ||
7555 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7556 | "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n", | |
7557 | pic_number, (100 - rdata32*100/(blk88_c_count*1)), | |
7558 | '%', rdata32); | |
7559 | ||
7560 | /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0], | |
7561 | 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */ | |
7562 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7563 | ||
7564 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7565 | "[Picture %d Quality] Y QP min : %d\n", | |
7566 | pic_number, (rdata32>>0)&0xff); | |
7567 | ||
7568 | frame->min_qp = (rdata32>>0)&0xff; | |
7569 | ||
7570 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7571 | "[Picture %d Quality] Y QP max : %d\n", | |
7572 | pic_number, (rdata32>>8)&0xff); | |
7573 | ||
7574 | frame->max_qp = (rdata32>>8)&0xff; | |
7575 | ||
7576 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7577 | "[Picture %d Quality] C QP min : %d\n", | |
7578 | pic_number, (rdata32>>16)&0xff); | |
7579 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7580 | "[Picture %d Quality] C QP max : %d\n", | |
7581 | pic_number, (rdata32>>24)&0xff); | |
7582 | ||
7583 | /* blk22_mv_count */ | |
7584 | blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7585 | if (blk22_mv_count == 0) { | |
7586 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7587 | "[Picture %d Quality] NO MV Data yet.\n", | |
7588 | pic_number); | |
7589 | /* reset all counts */ | |
7590 | WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8)); | |
7591 | return; | |
7592 | } | |
7593 | /* mvy_L1_count[39:32], mvx_L1_count[39:32], | |
7594 | mvy_L0_count[39:32], mvx_L0_count[39:32] */ | |
7595 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7596 | /* should all be 0x00 or 0xff */ | |
7597 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7598 | "[Picture %d Quality] MV AVG High Bits: 0x%X\n", | |
7599 | pic_number, rdata32); | |
7600 | ||
7601 | mvx_L0_hi = ((rdata32>>0)&0xff); | |
7602 | mvy_L0_hi = ((rdata32>>8)&0xff); | |
7603 | mvx_L1_hi = ((rdata32>>16)&0xff); | |
7604 | mvy_L1_hi = ((rdata32>>24)&0xff); | |
7605 | ||
7606 | /* mvx_L0_count[31:0] */ | |
7607 | rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7608 | temp_value = mvx_L0_hi; | |
7609 | temp_value = (temp_value << 32) | rdata32_l; | |
7610 | ||
7611 | if (mvx_L0_hi & 0x80) | |
7612 | value = 0xFFFFFFF000000000 | temp_value; | |
7613 | else | |
7614 | value = temp_value; | |
7615 | ||
7616 | value = div_s64(value, blk22_mv_count); | |
7617 | ||
7618 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7619 | "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n", | |
7620 | pic_number, (int)value, | |
7621 | value, blk22_mv_count); | |
7622 | ||
7623 | frame->avg_mv = value; | |
7624 | ||
7625 | /* mvy_L0_count[31:0] */ | |
7626 | rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7627 | temp_value = mvy_L0_hi; | |
7628 | temp_value = (temp_value << 32) | rdata32_l; | |
7629 | ||
7630 | if (mvy_L0_hi & 0x80) | |
7631 | value = 0xFFFFFFF000000000 | temp_value; | |
7632 | else | |
7633 | value = temp_value; | |
7634 | ||
7635 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7636 | "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n", | |
7637 | pic_number, rdata32_l/blk22_mv_count, | |
7638 | value, blk22_mv_count); | |
7639 | ||
7640 | /* mvx_L1_count[31:0] */ | |
7641 | rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7642 | temp_value = mvx_L1_hi; | |
7643 | temp_value = (temp_value << 32) | rdata32_l; | |
7644 | if (mvx_L1_hi & 0x80) | |
7645 | value = 0xFFFFFFF000000000 | temp_value; | |
7646 | else | |
7647 | value = temp_value; | |
7648 | ||
7649 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7650 | "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n", | |
7651 | pic_number, rdata32_l/blk22_mv_count, | |
7652 | value, blk22_mv_count); | |
7653 | ||
7654 | /* mvy_L1_count[31:0] */ | |
7655 | rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7656 | temp_value = mvy_L1_hi; | |
7657 | temp_value = (temp_value << 32) | rdata32_l; | |
7658 | if (mvy_L1_hi & 0x80) | |
7659 | value = 0xFFFFFFF000000000 | temp_value; | |
7660 | else | |
7661 | value = temp_value; | |
7662 | ||
7663 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7664 | "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n", | |
7665 | pic_number, rdata32_l/blk22_mv_count, | |
7666 | value, blk22_mv_count); | |
7667 | ||
7668 | /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */ | |
7669 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7670 | mv_hi = (rdata32>>16)&0xffff; | |
7671 | if (mv_hi & 0x8000) | |
7672 | mv_hi = 0x8000 - mv_hi; | |
7673 | ||
7674 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7675 | "[Picture %d Quality] MVX_L0 MAX : %d\n", | |
7676 | pic_number, mv_hi); | |
7677 | ||
7678 | frame->max_mv = mv_hi; | |
7679 | ||
7680 | mv_lo = (rdata32>>0)&0xffff; | |
7681 | if (mv_lo & 0x8000) | |
7682 | mv_lo = 0x8000 - mv_lo; | |
7683 | ||
7684 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7685 | "[Picture %d Quality] MVX_L0 MIN : %d\n", | |
7686 | pic_number, mv_lo); | |
7687 | ||
7688 | frame->min_mv = mv_lo; | |
7689 | ||
7690 | /* {mvy_L0_max, mvy_L0_min} */ | |
7691 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7692 | mv_hi = (rdata32>>16)&0xffff; | |
7693 | if (mv_hi & 0x8000) | |
7694 | mv_hi = 0x8000 - mv_hi; | |
7695 | ||
7696 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7697 | "[Picture %d Quality] MVY_L0 MAX : %d\n", | |
7698 | pic_number, mv_hi); | |
7699 | ||
7700 | mv_lo = (rdata32>>0)&0xffff; | |
7701 | if (mv_lo & 0x8000) | |
7702 | mv_lo = 0x8000 - mv_lo; | |
7703 | ||
7704 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7705 | "[Picture %d Quality] MVY_L0 MIN : %d\n", | |
7706 | pic_number, mv_lo); | |
7707 | ||
7708 | /* {mvx_L1_max, mvx_L1_min} */ | |
7709 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7710 | mv_hi = (rdata32>>16)&0xffff; | |
7711 | if (mv_hi & 0x8000) | |
7712 | mv_hi = 0x8000 - mv_hi; | |
7713 | ||
7714 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7715 | "[Picture %d Quality] MVX_L1 MAX : %d\n", | |
7716 | pic_number, mv_hi); | |
7717 | ||
7718 | mv_lo = (rdata32>>0)&0xffff; | |
7719 | if (mv_lo & 0x8000) | |
7720 | mv_lo = 0x8000 - mv_lo; | |
7721 | ||
7722 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7723 | "[Picture %d Quality] MVX_L1 MIN : %d\n", | |
7724 | pic_number, mv_lo); | |
7725 | ||
7726 | /* {mvy_L1_max, mvy_L1_min} */ | |
7727 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
7728 | mv_hi = (rdata32>>16)&0xffff; | |
7729 | if (mv_hi & 0x8000) | |
7730 | mv_hi = 0x8000 - mv_hi; | |
7731 | ||
7732 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7733 | "[Picture %d Quality] MVY_L1 MAX : %d\n", | |
7734 | pic_number, mv_hi); | |
7735 | ||
7736 | mv_lo = (rdata32>>0)&0xffff; | |
7737 | if (mv_lo & 0x8000) | |
7738 | mv_lo = 0x8000 - mv_lo; | |
7739 | ||
7740 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7741 | "[Picture %d Quality] MVY_L1 MIN : %d\n", | |
7742 | pic_number, mv_lo); | |
7743 | ||
7744 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL); | |
7745 | ||
7746 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
7747 | "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n", | |
7748 | pic_number, rdata32); | |
7749 | ||
7750 | /* reset all counts */ | |
7751 | WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8)); | |
7752 | } | |
7753 | } | |
7754 | ||
b9164398 NQ |
7755 | static irqreturn_t vvp9_isr_thread_fn(int irq, void *data) |
7756 | { | |
7757 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data; | |
7758 | unsigned int dec_status = pbi->dec_status; | |
a6c89e96 | 7759 | int i; |
b9164398 NQ |
7760 | |
7761 | /*if (pbi->wait_buf) | |
e0614bf7 ZZ |
7762 | * pr_info("set wait_buf to 0\r\n"); |
7763 | */ | |
fe96802b NQ |
7764 | if (pbi->eos) |
7765 | return IRQ_HANDLED; | |
b9164398 | 7766 | pbi->wait_buf = 0; |
fe96802b | 7767 | #ifdef MULTI_INSTANCE_SUPPORT |
a6c89e96 NQ |
7768 | #ifdef SUPPORT_FB_DECODING |
7769 | #ifdef FB_DECODING_TEST_SCHEDULE | |
7770 | if (pbi->s1_test_cmd == TEST_SET_PIC_DONE) | |
7771 | dec_status = HEVC_DECPIC_DATA_DONE; | |
7772 | else if (pbi->s1_test_cmd == TEST_SET_S2_DONE | |
7773 | && dec_status == HEVC_DECPIC_DATA_DONE) | |
7774 | dec_status = HEVC_S2_DECODING_DONE; | |
7775 | pbi->s1_test_cmd = TEST_SET_NONE; | |
7776 | #else | |
7777 | /*if (irq != VDEC_IRQ_0) | |
7778 | dec_status = HEVC_S2_DECODING_DONE;*/ | |
7779 | #endif | |
7780 | if (dec_status == HEVC_S2_DECODING_DONE) { | |
7781 | pbi->dec_result = DEC_RESULT_DONE; | |
7782 | vdec_schedule_work(&pbi->work); | |
7783 | #ifdef FB_DECODING_TEST_SCHEDULE | |
7784 | amhevc_stop(); | |
7785 | pbi->dec_s1_result = DEC_S1_RESULT_DONE; | |
7786 | vdec_schedule_work(&pbi->s1_work); | |
7787 | #endif | |
7788 | } else | |
7789 | #endif | |
fe96802b NQ |
7790 | if ((dec_status == HEVC_NAL_DECODE_DONE) || |
7791 | (dec_status == HEVC_SEARCH_BUFEMPTY) || | |
7792 | (dec_status == HEVC_DECODE_BUFEMPTY) | |
7793 | ) { | |
7794 | if (pbi->m_ins_flag) { | |
7795 | reset_process_time(pbi); | |
7796 | if (!vdec_frame_based(hw_to_vdec(pbi))) | |
7797 | dec_again_process(pbi); | |
7798 | else { | |
7799 | pbi->dec_result = DEC_RESULT_GET_DATA; | |
7800 | vdec_schedule_work(&pbi->work); | |
7801 | } | |
7802 | } | |
7803 | pbi->process_busy = 0; | |
7804 | return IRQ_HANDLED; | |
7805 | } else if (dec_status == HEVC_DECPIC_DATA_DONE) { | |
7806 | if (pbi->m_ins_flag) { | |
ac678990 | 7807 | get_picture_qos_info(pbi); |
a6c89e96 NQ |
7808 | #ifdef SUPPORT_FB_DECODING |
7809 | if (pbi->used_stage_buf_num > 0) { | |
7810 | reset_process_time(pbi); | |
7811 | inc_s1_pos(pbi); | |
7812 | trigger_schedule(pbi); | |
7813 | #ifdef FB_DECODING_TEST_SCHEDULE | |
7814 | pbi->s1_test_cmd = TEST_SET_S2_DONE; | |
7815 | #else | |
7816 | amhevc_stop(); | |
7817 | pbi->dec_s1_result = DEC_S1_RESULT_DONE; | |
7818 | vdec_schedule_work(&pbi->s1_work); | |
7819 | #endif | |
7820 | } else | |
7821 | #endif | |
7822 | { | |
7823 | reset_process_time(pbi); | |
187af067 | 7824 | if (pbi->vf_pre_count == 0 || pbi->low_latency_flag) |
fd6875e8 PY |
7825 | vp9_bufmgr_postproc(pbi); |
7826 | ||
a6c89e96 NQ |
7827 | pbi->dec_result = DEC_RESULT_DONE; |
7828 | amhevc_stop(); | |
7829 | if (mcrcc_cache_alg_flag) | |
7830 | dump_hit_rate(pbi); | |
7831 | vdec_schedule_work(&pbi->work); | |
7832 | } | |
187af067 | 7833 | } else { |
7834 | if (pbi->low_latency_flag) { | |
7835 | vp9_bufmgr_postproc(pbi); | |
7836 | WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); | |
7837 | #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC | |
7838 | vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_CB); | |
7839 | if (debug & PRINT_FLAG_VDEC_DETAIL) | |
7840 | pr_info("%s VP9 frame done \n", __func__); | |
7841 | #endif | |
7842 | } | |
fe96802b NQ |
7843 | } |
7844 | ||
7845 | pbi->process_busy = 0; | |
7846 | return IRQ_HANDLED; | |
7847 | } | |
7848 | #endif | |
b9164398 NQ |
7849 | |
7850 | if (dec_status == VP9_EOS) { | |
fe96802b NQ |
7851 | #ifdef MULTI_INSTANCE_SUPPORT |
7852 | if (pbi->m_ins_flag) | |
7853 | reset_process_time(pbi); | |
7854 | #endif | |
7855 | ||
b9164398 NQ |
7856 | pr_info("VP9_EOS, flush buffer\r\n"); |
7857 | ||
7858 | vp9_bufmgr_postproc(pbi); | |
7859 | ||
7860 | pr_info("send VP9_10B_DISCARD_NAL\r\n"); | |
7861 | WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL); | |
7862 | pbi->process_busy = 0; | |
fe96802b NQ |
7863 | #ifdef MULTI_INSTANCE_SUPPORT |
7864 | if (pbi->m_ins_flag) { | |
7865 | pbi->dec_result = DEC_RESULT_DONE; | |
7866 | amhevc_stop(); | |
7867 | vdec_schedule_work(&pbi->work); | |
7868 | } | |
7869 | #endif | |
7870 | return IRQ_HANDLED; | |
7871 | } else if (dec_status == HEVC_DECODE_OVER_SIZE) { | |
7872 | pr_info("vp9 decode oversize !!\n"); | |
7873 | debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC | | |
7874 | VP9_DEBUG_DIS_SYS_ERROR_PROC); | |
7875 | pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; | |
7876 | #ifdef MULTI_INSTANCE_SUPPORT | |
7877 | if (pbi->m_ins_flag) | |
7878 | reset_process_time(pbi); | |
7879 | #endif | |
b9164398 NQ |
7880 | return IRQ_HANDLED; |
7881 | } | |
7882 | ||
7883 | if (dec_status != VP9_HEAD_PARSER_DONE) { | |
7884 | pbi->process_busy = 0; | |
7885 | return IRQ_HANDLED; | |
7886 | } | |
fe96802b | 7887 | |
187af067 | 7888 | |
fe96802b | 7889 | #ifdef MULTI_INSTANCE_SUPPORT |
187af067 | 7890 | #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC |
7891 | if (pbi->m_ins_flag ==0 && pbi->low_latency_flag) { | |
7892 | vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_RUN); | |
7893 | if (debug & PRINT_FLAG_VDEC_DETAIL) | |
7894 | pr_info("%s VP9 frame header found \n", __func__); | |
7895 | } | |
7896 | #endif | |
fe96802b NQ |
7897 | if (pbi->m_ins_flag) |
7898 | reset_process_time(pbi); | |
7899 | #endif | |
a6c89e96 NQ |
7900 | if (pbi->process_state != PROC_STATE_SENDAGAIN |
7901 | #ifdef SUPPORT_FB_DECODING | |
7902 | && pbi->used_stage_buf_num == 0 | |
7903 | #endif | |
7904 | ) { | |
b7706e1e | 7905 | if (pbi->mmu_enable) |
7906 | vp9_recycle_mmu_buf_tail(pbi); | |
7907 | ||
fe96802b NQ |
7908 | |
7909 | if (pbi->frame_count > 0) | |
7910 | vp9_bufmgr_postproc(pbi); | |
7911 | } | |
b9164398 NQ |
7912 | |
7913 | if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) { | |
7914 | get_rpm_param(&vp9_param); | |
7915 | } else { | |
a6c89e96 NQ |
7916 | #ifdef SUPPORT_FB_DECODING |
7917 | if (pbi->used_stage_buf_num > 0) { | |
7918 | reset_process_time(pbi); | |
7919 | get_s1_buf(pbi); | |
7920 | ||
7921 | if (get_mv_buf(pbi, | |
7922 | &pbi->s1_mv_buf_index, | |
7923 | &pbi->s1_mpred_mv_wr_start_addr | |
7924 | ) < 0) { | |
7925 | vp9_print(pbi, 0, | |
7926 | "%s: Error get_mv_buf fail\n", | |
7927 | __func__); | |
7928 | } | |
b9164398 | 7929 | |
a6c89e96 NQ |
7930 | if (pbi->s1_buf == NULL) { |
7931 | vp9_print(pbi, 0, | |
7932 | "%s: Error get_s1_buf fail\n", | |
7933 | __func__); | |
7934 | pbi->process_busy = 0; | |
7935 | return IRQ_HANDLED; | |
fe96802b | 7936 | } |
a6c89e96 NQ |
7937 | |
7938 | for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { | |
7939 | int ii; | |
7940 | for (ii = 0; ii < 4; ii++) { | |
7941 | pbi->s1_buf->rpm[i + 3 - ii] = | |
7942 | pbi->rpm_ptr[i + 3 - ii]; | |
7943 | pbi->s1_param.l.data[i + ii] = | |
7944 | pbi->rpm_ptr[i + 3 - ii]; | |
7945 | } | |
fe96802b | 7946 | } |
a6c89e96 NQ |
7947 | |
7948 | mpred_process(pbi); | |
7949 | #ifdef FB_DECODING_TEST_SCHEDULE | |
7950 | pbi->dec_s1_result = | |
7951 | DEC_S1_RESULT_TEST_TRIGGER_DONE; | |
7952 | vdec_schedule_work(&pbi->s1_work); | |
7953 | #else | |
7954 | WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR, | |
7955 | pbi->stage_mmu_map_phy_addr + | |
7956 | pbi->s1_buf->index * STAGE_MMU_MAP_SIZE); | |
7957 | ||
7958 | start_s1_decoding(pbi); | |
fe96802b | 7959 | #endif |
a6c89e96 NQ |
7960 | start_process_time(pbi); |
7961 | pbi->process_busy = 0; | |
7962 | return IRQ_HANDLED; | |
7963 | } else | |
7964 | #endif | |
b7706e1e | 7965 | { |
7966 | for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { | |
7967 | int ii; | |
7968 | for (ii = 0; ii < 4; ii++) | |
7969 | vp9_param.l.data[i + ii] = | |
7970 | pbi->rpm_ptr[i + 3 - ii]; | |
7971 | } | |
fe96802b | 7972 | } |
b9164398 | 7973 | } |
b9164398 | 7974 | |
a6c89e96 | 7975 | continue_decoding(pbi); |
187af067 | 7976 | pbi->postproc_done = 0; |
b9164398 | 7977 | pbi->process_busy = 0; |
a6c89e96 | 7978 | |
fe96802b NQ |
7979 | #ifdef MULTI_INSTANCE_SUPPORT |
7980 | if (pbi->m_ins_flag) | |
7981 | start_process_time(pbi); | |
7982 | #endif | |
7983 | ||
b9164398 NQ |
7984 | return IRQ_HANDLED; |
7985 | } | |
7986 | ||
7987 | static irqreturn_t vvp9_isr(int irq, void *data) | |
7988 | { | |
7989 | int i; | |
7990 | unsigned int dec_status; | |
7991 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data; | |
7992 | unsigned int adapt_prob_status; | |
7993 | struct VP9_Common_s *const cm = &pbi->common; | |
fe96802b NQ |
7994 | uint debug_tag; |
7995 | ||
a6c89e96 | 7996 | WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1); |
fe96802b | 7997 | |
b9164398 NQ |
7998 | dec_status = READ_VREG(HEVC_DEC_STATUS_REG); |
7999 | adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG); | |
b34d6d3e ZZ |
8000 | if (!pbi) |
8001 | return IRQ_HANDLED; | |
b9164398 NQ |
8002 | if (pbi->init_flag == 0) |
8003 | return IRQ_HANDLED; | |
8004 | if (pbi->process_busy)/*on process.*/ | |
8005 | return IRQ_HANDLED; | |
8006 | pbi->dec_status = dec_status; | |
8007 | pbi->process_busy = 1; | |
8008 | if (debug & VP9_DEBUG_BUFMGR) | |
a6c89e96 NQ |
8009 | pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n", |
8010 | irq, | |
fe96802b NQ |
8011 | dec_status, READ_VREG(HEVC_PARSER_LCU_START), |
8012 | READ_VREG(HEVC_SHIFT_BYTE_COUNT), | |
8013 | READ_VREG(HEVC_STREAM_START_ADDR), | |
8014 | READ_VREG(HEVC_STREAM_END_ADDR), | |
8015 | READ_VREG(HEVC_STREAM_LEVEL), | |
8016 | READ_VREG(HEVC_STREAM_WR_PTR), | |
8017 | READ_VREG(HEVC_STREAM_RD_PTR) | |
8018 | ); | |
a6c89e96 NQ |
8019 | #ifdef SUPPORT_FB_DECODING |
8020 | /*if (irq != VDEC_IRQ_0) | |
8021 | return IRQ_WAKE_THREAD;*/ | |
8022 | #endif | |
b9164398 | 8023 | |
fe96802b NQ |
8024 | debug_tag = READ_HREG(DEBUG_REG1); |
8025 | if (debug_tag & 0x10000) { | |
fe96802b NQ |
8026 | pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1)); |
8027 | for (i = 0; i < 0x400; i += 4) { | |
8028 | int ii; | |
8029 | if ((i & 0xf) == 0) | |
8030 | pr_info("%03x: ", i); | |
8031 | for (ii = 0; ii < 4; ii++) { | |
8032 | pr_info("%04x ", | |
8033 | pbi->lmem_ptr[i + 3 - ii]); | |
b9164398 | 8034 | } |
fe96802b NQ |
8035 | if (((i + ii) & 0xf) == 0) |
8036 | pr_info("\n"); | |
b9164398 NQ |
8037 | } |
8038 | ||
fe96802b NQ |
8039 | if ((udebug_pause_pos == (debug_tag & 0xffff)) && |
8040 | (udebug_pause_decode_idx == 0 || | |
8041 | udebug_pause_decode_idx == pbi->slice_idx) && | |
8042 | (udebug_pause_val == 0 || | |
8043 | udebug_pause_val == READ_HREG(DEBUG_REG2))) | |
8044 | pbi->ucode_pause_pos = udebug_pause_pos; | |
8045 | else if (debug_tag & 0x20000) | |
8046 | pbi->ucode_pause_pos = 0xffffffff; | |
8047 | if (pbi->ucode_pause_pos) | |
8048 | reset_process_time(pbi); | |
8049 | else | |
8050 | WRITE_HREG(DEBUG_REG1, 0); | |
8051 | } else if (debug_tag != 0) { | |
8052 | pr_info( | |
8053 | "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1), | |
8054 | READ_HREG(DEBUG_REG2), | |
8055 | READ_VREG(HEVC_PARSER_LCU_START)); | |
8056 | if ((udebug_pause_pos == (debug_tag & 0xffff)) && | |
8057 | (udebug_pause_decode_idx == 0 || | |
8058 | udebug_pause_decode_idx == pbi->slice_idx) && | |
8059 | (udebug_pause_val == 0 || | |
8060 | udebug_pause_val == READ_HREG(DEBUG_REG2))) | |
8061 | pbi->ucode_pause_pos = udebug_pause_pos; | |
8062 | if (pbi->ucode_pause_pos) | |
8063 | reset_process_time(pbi); | |
8064 | else | |
8065 | WRITE_HREG(DEBUG_REG1, 0); | |
b9164398 NQ |
8066 | pbi->process_busy = 0; |
8067 | return IRQ_HANDLED; | |
8068 | } | |
8069 | ||
fe96802b NQ |
8070 | #ifdef MULTI_INSTANCE_SUPPORT |
8071 | if (!pbi->m_ins_flag) { | |
8072 | #endif | |
8073 | if (pbi->error_flag == 1) { | |
8074 | pbi->error_flag = 2; | |
8075 | pbi->process_busy = 0; | |
8076 | return IRQ_HANDLED; | |
8077 | } else if (pbi->error_flag == 3) { | |
8078 | pbi->process_busy = 0; | |
8079 | return IRQ_HANDLED; | |
8080 | } | |
8081 | ||
8082 | if (get_free_buf_count(pbi) <= 0) { | |
8083 | /* | |
8084 | if (pbi->wait_buf == 0) | |
8085 | pr_info("set wait_buf to 1\r\n"); | |
8086 | */ | |
8087 | pbi->wait_buf = 1; | |
8088 | pbi->process_busy = 0; | |
8089 | return IRQ_HANDLED; | |
8090 | } | |
8091 | #ifdef MULTI_INSTANCE_SUPPORT | |
b9164398 | 8092 | } |
fe96802b | 8093 | #endif |
b9164398 NQ |
8094 | if ((adapt_prob_status & 0xff) == 0xfd) { |
8095 | /*VP9_REQ_ADAPT_PROB*/ | |
8096 | int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0; | |
8097 | uint8_t *prev_prob_b = | |
8098 | ((uint8_t *)pbi->prob_buffer_addr) + | |
8099 | ((adapt_prob_status >> 8) * 0x1000); | |
8100 | uint8_t *cur_prob_b = | |
8101 | ((uint8_t *)pbi->prob_buffer_addr) + 0x4000; | |
8102 | uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr; | |
fe96802b NQ |
8103 | #ifdef MULTI_INSTANCE_SUPPORT |
8104 | if (pbi->m_ins_flag) | |
8105 | reset_process_time(pbi); | |
8106 | #endif | |
b9164398 NQ |
8107 | adapt_coef_probs(pbi->pic_count, |
8108 | (cm->last_frame_type == KEY_FRAME), | |
8109 | pre_fc, (adapt_prob_status >> 8), | |
8110 | (unsigned int *)prev_prob_b, | |
8111 | (unsigned int *)cur_prob_b, (unsigned int *)count_b); | |
8112 | ||
8113 | memcpy(prev_prob_b, cur_prob_b, PROB_SIZE); | |
8114 | WRITE_VREG(VP9_ADAPT_PROB_REG, 0); | |
8115 | pbi->pic_count += 1; | |
b9164398 | 8116 | #ifdef MULTI_INSTANCE_SUPPORT |
fe96802b NQ |
8117 | if (pbi->m_ins_flag) |
8118 | start_process_time(pbi); | |
b9164398 | 8119 | #endif |
b9164398 | 8120 | |
fe96802b | 8121 | /*return IRQ_HANDLED;*/ |
b9164398 | 8122 | } |
b9164398 NQ |
8123 | return IRQ_WAKE_THREAD; |
8124 | } | |
8125 | ||
a994f6d6 | 8126 | static void vp9_set_clk(struct work_struct *work) |
8127 | { | |
8128 | struct VP9Decoder_s *pbi = container_of(work, | |
8deb3449 NQ |
8129 | struct VP9Decoder_s, set_clk_work); |
8130 | int fps = 96000 / pbi->frame_dur; | |
a994f6d6 | 8131 | |
8deb3449 NQ |
8132 | if (hevc_source_changed(VFORMAT_VP9, |
8133 | frame_width, frame_height, fps) > 0) | |
8134 | pbi->saved_resolution = frame_width * | |
8135 | frame_height * fps; | |
a994f6d6 | 8136 | } |
8137 | ||
b9164398 NQ |
8138 | static void vvp9_put_timer_func(unsigned long arg) |
8139 | { | |
8140 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg; | |
8141 | struct timer_list *timer = &pbi->timer; | |
8142 | uint8_t empty_flag; | |
8143 | unsigned int buf_level; | |
8144 | ||
8145 | enum receviver_start_e state = RECEIVER_INACTIVE; | |
e0614bf7 | 8146 | |
b9164398 NQ |
8147 | if (pbi->m_ins_flag) { |
8148 | if (hw_to_vdec(pbi)->next_status | |
8149 | == VDEC_STATUS_DISCONNECTED) { | |
a6c89e96 NQ |
8150 | #ifdef SUPPORT_FB_DECODING |
8151 | if (pbi->run2_busy) | |
8152 | return; | |
8153 | ||
8154 | pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT; | |
8155 | vdec_schedule_work(&pbi->s1_work); | |
8156 | #endif | |
fe96802b NQ |
8157 | pbi->dec_result = DEC_RESULT_FORCE_EXIT; |
8158 | vdec_schedule_work(&pbi->work); | |
5b851ff9 | 8159 | pr_debug( |
b9164398 NQ |
8160 | "vdec requested to be disconnected\n"); |
8161 | return; | |
8162 | } | |
8163 | } | |
8164 | if (pbi->init_flag == 0) { | |
8165 | if (pbi->stat & STAT_TIMER_ARM) { | |
8166 | timer->expires = jiffies + PUT_INTERVAL; | |
8167 | add_timer(&pbi->timer); | |
8168 | } | |
8169 | return; | |
8170 | } | |
8171 | if (pbi->m_ins_flag == 0) { | |
8172 | if (vf_get_receiver(pbi->provider_name)) { | |
8173 | state = | |
8174 | vf_notify_receiver(pbi->provider_name, | |
8175 | VFRAME_EVENT_PROVIDER_QUREY_STATE, | |
8176 | NULL); | |
8177 | if ((state == RECEIVER_STATE_NULL) | |
8178 | || (state == RECEIVER_STATE_NONE)) | |
8179 | state = RECEIVER_INACTIVE; | |
8180 | } else | |
8181 | state = RECEIVER_INACTIVE; | |
8182 | ||
8183 | empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1; | |
8184 | /* error watchdog */ | |
8185 | if (empty_flag == 0) { | |
8186 | /* decoder has input */ | |
8187 | if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) { | |
8188 | ||
8189 | buf_level = READ_VREG(HEVC_STREAM_LEVEL); | |
8190 | /* receiver has no buffer to recycle */ | |
8191 | if ((state == RECEIVER_INACTIVE) && | |
8192 | (kfifo_is_empty(&pbi->display_q) && | |
8193 | buf_level > 0x200) | |
8194 | ) { | |
8195 | WRITE_VREG | |
a6c89e96 | 8196 | (HEVC_ASSIST_MBOX0_IRQ_REG, |
b9164398 NQ |
8197 | 0x1); |
8198 | } | |
8199 | } | |
8200 | ||
8201 | if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) { | |
8202 | /* receiver has no buffer to recycle */ | |
8203 | /*if ((state == RECEIVER_INACTIVE) && | |
e0614bf7 ZZ |
8204 | * (kfifo_is_empty(&pbi->display_q))) { |
8205 | *pr_info("vp9 something error,need reset\n"); | |
8206 | *} | |
8207 | */ | |
b9164398 NQ |
8208 | } |
8209 | } | |
8210 | } | |
fe96802b NQ |
8211 | #ifdef MULTI_INSTANCE_SUPPORT |
8212 | else { | |
8213 | if ( | |
8214 | (decode_timeout_val > 0) && | |
8215 | (pbi->start_process_time > 0) && | |
8216 | ((1000 * (jiffies - pbi->start_process_time) / HZ) | |
8217 | > decode_timeout_val) | |
8218 | ) { | |
8219 | int current_lcu_idx = | |
8220 | READ_VREG(HEVC_PARSER_LCU_START) | |
8221 | & 0xffffff; | |
8222 | if (pbi->last_lcu_idx == current_lcu_idx) { | |
8223 | if (pbi->decode_timeout_count > 0) | |
8224 | pbi->decode_timeout_count--; | |
8225 | if (pbi->decode_timeout_count == 0) { | |
8226 | if (input_frame_based( | |
8227 | hw_to_vdec(pbi)) || | |
8228 | (READ_VREG(HEVC_STREAM_LEVEL) > 0x200)) | |
8229 | timeout_process(pbi); | |
8230 | else { | |
8231 | vp9_print(pbi, 0, | |
8232 | "timeout & empty, again\n"); | |
8233 | dec_again_process(pbi); | |
8234 | } | |
8235 | } | |
8236 | } else { | |
8237 | start_process_time(pbi); | |
8238 | pbi->last_lcu_idx = current_lcu_idx; | |
8239 | } | |
8240 | } | |
8241 | } | |
8242 | #endif | |
8243 | ||
8244 | if ((pbi->ucode_pause_pos != 0) && | |
8245 | (pbi->ucode_pause_pos != 0xffffffff) && | |
8246 | udebug_pause_pos != pbi->ucode_pause_pos) { | |
8247 | pbi->ucode_pause_pos = 0; | |
8248 | WRITE_HREG(DEBUG_REG1, 0); | |
8249 | } | |
8250 | #ifdef MULTI_INSTANCE_SUPPORT | |
8251 | if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) { | |
8252 | pr_info( | |
8253 | "Force Send Again\r\n"); | |
8254 | debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN; | |
8255 | reset_process_time(pbi); | |
8256 | pbi->dec_result = DEC_RESULT_AGAIN; | |
8257 | if (pbi->process_state == | |
8258 | PROC_STATE_DECODESLICE) { | |
b7706e1e | 8259 | if (pbi->mmu_enable) |
8260 | vp9_recycle_mmu_buf(pbi); | |
fe96802b NQ |
8261 | pbi->process_state = |
8262 | PROC_STATE_SENDAGAIN; | |
8263 | } | |
8264 | amhevc_stop(); | |
b9164398 | 8265 | |
fe96802b | 8266 | vdec_schedule_work(&pbi->work); |
b9164398 NQ |
8267 | } |
8268 | ||
fe96802b NQ |
8269 | if (debug & VP9_DEBUG_DUMP_DATA) { |
8270 | debug &= ~VP9_DEBUG_DUMP_DATA; | |
8271 | vp9_print(pbi, 0, | |
8272 | "%s: chunk size 0x%x off 0x%x sum 0x%x\n", | |
8273 | __func__, | |
8274 | pbi->chunk->size, | |
8275 | pbi->chunk->offset, | |
8276 | get_data_check_sum(pbi, pbi->chunk->size) | |
8277 | ); | |
8278 | dump_data(pbi, pbi->chunk->size); | |
8279 | } | |
8280 | #endif | |
b9164398 NQ |
8281 | if (debug & VP9_DEBUG_DUMP_PIC_LIST) { |
8282 | dump_pic_list(pbi); | |
8283 | debug &= ~VP9_DEBUG_DUMP_PIC_LIST; | |
8284 | } | |
8285 | if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) { | |
a6c89e96 | 8286 | WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1); |
b9164398 NQ |
8287 | debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC; |
8288 | } | |
8289 | /*if (debug & VP9_DEBUG_HW_RESET) { | |
8290 | }*/ | |
b9164398 NQ |
8291 | |
8292 | if (radr != 0) { | |
8293 | if (rval != 0) { | |
8294 | WRITE_VREG(radr, rval); | |
8295 | pr_info("WRITE_VREG(%x,%x)\n", radr, rval); | |
8296 | } else | |
8297 | pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr)); | |
8298 | rval = 0; | |
8299 | radr = 0; | |
8300 | } | |
8301 | if (pop_shorts != 0) { | |
8302 | int i; | |
8303 | u32 sum = 0; | |
e0614bf7 | 8304 | |
b9164398 NQ |
8305 | pr_info("pop stream 0x%x shorts\r\n", pop_shorts); |
8306 | for (i = 0; i < pop_shorts; i++) { | |
8307 | u32 data = | |
8308 | (READ_HREG(HEVC_SHIFTED_DATA) >> 16); | |
8309 | WRITE_HREG(HEVC_SHIFT_COMMAND, | |
8310 | (1<<7)|16); | |
8311 | if ((i & 0xf) == 0) | |
8312 | pr_info("%04x:", i); | |
8313 | pr_info("%04x ", data); | |
8314 | if (((i + 1) & 0xf) == 0) | |
8315 | pr_info("\r\n"); | |
8316 | sum += data; | |
8317 | } | |
8318 | pr_info("\r\nsum = %x\r\n", sum); | |
8319 | pop_shorts = 0; | |
8320 | } | |
8321 | if (dbg_cmd != 0) { | |
8322 | if (dbg_cmd == 1) { | |
8323 | u32 disp_laddr; | |
e0614bf7 | 8324 | |
63e810c0 | 8325 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB && |
fe96802b | 8326 | get_double_write_mode(pbi) == 0) { |
b9164398 NQ |
8327 | disp_laddr = |
8328 | READ_VCBUS_REG(AFBC_BODY_BADDR) << 4; | |
8329 | } else { | |
8330 | struct canvas_s cur_canvas; | |
e0614bf7 | 8331 | |
b9164398 NQ |
8332 | canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0) |
8333 | & 0xff), &cur_canvas); | |
8334 | disp_laddr = cur_canvas.addr; | |
8335 | } | |
8336 | pr_info("current displayed buffer address %x\r\n", | |
8337 | disp_laddr); | |
8338 | } | |
8339 | dbg_cmd = 0; | |
8340 | } | |
8341 | /*don't changed at start.*/ | |
95375c25 CG |
8342 | if (pbi->get_frame_dur && pbi->show_frame_num > 60 && |
8343 | pbi->frame_dur > 0 && pbi->saved_resolution != | |
8344 | frame_width * frame_height * | |
8345 | (96000 / pbi->frame_dur)) | |
c8ed76ed | 8346 | vdec_schedule_work(&pbi->set_clk_work); |
b9164398 NQ |
8347 | |
8348 | timer->expires = jiffies + PUT_INTERVAL; | |
8349 | add_timer(timer); | |
8350 | } | |
8351 | ||
8352 | ||
fe96802b | 8353 | int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) |
b9164398 | 8354 | { |
c23e8aee HZ |
8355 | struct VP9Decoder_s *vp9 = |
8356 | (struct VP9Decoder_s *)vdec->private; | |
70809fec | 8357 | |
9b670a2d | 8358 | if (!vp9) |
70809fec NQ |
8359 | return -1; |
8360 | ||
fe96802b NQ |
8361 | vstatus->frame_width = frame_width; |
8362 | vstatus->frame_height = frame_height; | |
8363 | if (vp9->frame_dur != 0) | |
8364 | vstatus->frame_rate = 96000 / vp9->frame_dur; | |
b9164398 | 8365 | else |
fe96802b | 8366 | vstatus->frame_rate = -1; |
b9164398 | 8367 | vstatus->error_count = 0; |
fe96802b NQ |
8368 | vstatus->status = vp9->stat | vp9->fatal_error; |
8369 | vstatus->frame_dur = vp9->frame_dur; | |
8370 | #ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC | |
8371 | vstatus->bit_rate = gvs->bit_rate; | |
8372 | vstatus->frame_data = gvs->frame_data; | |
8373 | vstatus->total_data = gvs->total_data; | |
8374 | vstatus->frame_count = gvs->frame_count; | |
8375 | vstatus->error_frame_count = gvs->error_frame_count; | |
8376 | vstatus->drop_frame_count = gvs->drop_frame_count; | |
8377 | vstatus->total_data = gvs->total_data; | |
8378 | vstatus->samp_cnt = gvs->samp_cnt; | |
8379 | vstatus->offset = gvs->offset; | |
8380 | snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), | |
8381 | "%s", DRIVER_NAME); | |
8382 | #endif | |
b9164398 NQ |
8383 | return 0; |
8384 | } | |
8385 | ||
d481db31 NQ |
8386 | int vvp9_set_isreset(struct vdec_s *vdec, int isreset) |
8387 | { | |
8388 | is_reset = isreset; | |
8389 | return 0; | |
8390 | } | |
8391 | ||
b9164398 NQ |
8392 | #if 0 |
8393 | static void VP9_DECODE_INIT(void) | |
8394 | { | |
8395 | /* enable vp9 clocks */ | |
8396 | WRITE_VREG(DOS_GCLK_EN3, 0xffffffff); | |
8397 | /* *************************************************************** */ | |
8398 | /* Power ON HEVC */ | |
8399 | /* *************************************************************** */ | |
8400 | /* Powerup HEVC */ | |
8401 | WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0, | |
8402 | READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6))); | |
8403 | WRITE_VREG(DOS_MEM_PD_HEVC, 0x0); | |
8404 | WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2)); | |
8405 | WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2))); | |
8406 | /* remove isolations */ | |
8407 | WRITE_VREG(AO_RTI_GEN_PWR_ISO0, | |
8408 | READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10))); | |
8409 | ||
8410 | } | |
8411 | #endif | |
8412 | ||
a6c89e96 | 8413 | static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask) |
b9164398 NQ |
8414 | { |
8415 | unsigned int data32; | |
8416 | /* VP9_DECODE_INIT(); */ | |
a6c89e96 NQ |
8417 | vp9_config_work_space_hw(pbi, mask); |
8418 | if (mask & HW_MASK_BACK) | |
8419 | init_pic_list_hw(pbi); | |
b9164398 | 8420 | |
a6c89e96 | 8421 | vp9_init_decoder_hw(pbi, mask); |
b9164398 NQ |
8422 | |
8423 | #ifdef VP9_LPF_LVL_UPDATE | |
a6c89e96 NQ |
8424 | if (mask & HW_MASK_BACK) |
8425 | vp9_loop_filter_init(pbi); | |
b9164398 NQ |
8426 | #endif |
8427 | ||
a6c89e96 NQ |
8428 | if ((mask & HW_MASK_FRONT) == 0) |
8429 | return; | |
b9164398 | 8430 | #if 1 |
fe96802b NQ |
8431 | if (debug & VP9_DEBUG_BUFMGR_MORE) |
8432 | pr_info("%s\n", __func__); | |
b9164398 NQ |
8433 | data32 = READ_VREG(HEVC_STREAM_CONTROL); |
8434 | data32 = data32 | | |
8435 | (1 << 0)/*stream_fetch_enable*/ | |
8436 | ; | |
8437 | WRITE_VREG(HEVC_STREAM_CONTROL, data32); | |
a6c89e96 | 8438 | |
63e810c0 | 8439 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { |
a6c89e96 NQ |
8440 | if (debug & VP9_DEBUG_BUFMGR) |
8441 | pr_info("[test.c] Config STREAM_FIFO_CTL\n"); | |
8442 | data32 = READ_VREG(HEVC_STREAM_FIFO_CTL); | |
8443 | data32 = data32 | | |
8444 | (1 << 29) // stream_fifo_hole | |
8445 | ; | |
8446 | WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32); | |
8447 | } | |
b9164398 NQ |
8448 | #if 0 |
8449 | data32 = READ_VREG(HEVC_SHIFT_STARTCODE); | |
8450 | if (data32 != 0x00000100) { | |
8451 | pr_info("vp9 prot init error %d\n", __LINE__); | |
8452 | return; | |
8453 | } | |
8454 | data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); | |
8455 | if (data32 != 0x00000300) { | |
8456 | pr_info("vp9 prot init error %d\n", __LINE__); | |
8457 | return; | |
8458 | } | |
8459 | WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678); | |
8460 | WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0); | |
8461 | data32 = READ_VREG(HEVC_SHIFT_STARTCODE); | |
8462 | if (data32 != 0x12345678) { | |
8463 | pr_info("vp9 prot init error %d\n", __LINE__); | |
8464 | return; | |
8465 | } | |
8466 | data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); | |
8467 | if (data32 != 0x9abcdef0) { | |
8468 | pr_info("vp9 prot init error %d\n", __LINE__); | |
8469 | return; | |
8470 | } | |
8471 | #endif | |
8472 | WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001); | |
8473 | WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300); | |
8474 | #endif | |
8475 | ||
8476 | ||
8477 | ||
8478 | WRITE_VREG(HEVC_WAIT_FLAG, 1); | |
8479 | ||
8480 | /* WRITE_VREG(HEVC_MPSR, 1); */ | |
8481 | ||
8482 | /* clear mailbox interrupt */ | |
a6c89e96 | 8483 | WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1); |
b9164398 NQ |
8484 | |
8485 | /* enable mailbox interrupt */ | |
a6c89e96 | 8486 | WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1); |
b9164398 NQ |
8487 | |
8488 | /* disable PSCALE for hardware sharing */ | |
8489 | WRITE_VREG(HEVC_PSCALE_CTRL, 0); | |
8490 | ||
fe96802b | 8491 | WRITE_VREG(DEBUG_REG1, 0x0); |
b9164398 NQ |
8492 | /*check vps/sps/pps/i-slice in ucode*/ |
8493 | WRITE_VREG(NAL_SEARCH_CTL, 0x8); | |
8494 | ||
fe96802b | 8495 | WRITE_VREG(DECODE_STOP_POS, udebug_flag); |
a6c89e96 NQ |
8496 | #ifdef SUPPORT_FB_DECODING |
8497 | #ifndef FB_DECODING_TEST_SCHEDULE | |
8498 | if (pbi->used_stage_buf_num > 0) { | |
8499 | if (mask & HW_MASK_FRONT) { | |
8500 | data32 = READ_VREG( | |
8501 | HEVC_ASSIST_HED_FB_W_CTL); | |
8502 | data32 = data32 | | |
8503 | (1 << 0) /*hed_fb_wr_en*/ | |
8504 | ; | |
8505 | WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL, | |
8506 | data32); | |
8507 | } | |
8508 | if (mask & HW_MASK_BACK) { | |
8509 | data32 = READ_VREG( | |
8510 | HEVC_ASSIST_HED_FB_R_CTL); | |
8511 | while (data32 & (1 << 7)) { | |
8512 | /*wait finish*/ | |
8513 | data32 = READ_VREG( | |
8514 | HEVC_ASSIST_HED_FB_R_CTL); | |
8515 | } | |
8516 | data32 &= (~(0x1 << 0)); | |
8517 | /*hed_fb_rd_addr_auto_rd*/ | |
8518 | data32 &= (~(0x1 << 1)); | |
8519 | /*rd_id = 0, hed_rd_map_auto_halt_num, | |
8520 | after wr 2 ready, then start reading*/ | |
8521 | data32 |= (0x2 << 16); | |
8522 | WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL, | |
8523 | data32); | |
8524 | ||
8525 | data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/ | |
8526 | data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/ | |
8527 | data32 |= (0x1 << 0); /*hed_fb_rd_en*/ | |
8528 | WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL, | |
8529 | data32); | |
8530 | } | |
b9164398 | 8531 | |
a6c89e96 NQ |
8532 | } |
8533 | #endif | |
8534 | #endif | |
b9164398 NQ |
8535 | } |
8536 | ||
8537 | static int vvp9_local_init(struct VP9Decoder_s *pbi) | |
8538 | { | |
8539 | int i; | |
8540 | int ret; | |
8541 | int width, height; | |
fe96802b NQ |
8542 | if (alloc_lf_buf(pbi) < 0) |
8543 | return -1; | |
8544 | ||
8545 | pbi->gvs = vzalloc(sizeof(struct vdec_info)); | |
8546 | if (NULL == pbi->gvs) { | |
8547 | pr_info("the struct of vdec status malloc failed.\n"); | |
8548 | return -1; | |
8549 | } | |
b9164398 NQ |
8550 | #ifdef DEBUG_PTS |
8551 | pbi->pts_missed = 0; | |
8552 | pbi->pts_hit = 0; | |
8553 | #endif | |
8554 | pbi->new_frame_displayed = 0; | |
8555 | pbi->last_put_idx = -1; | |
8556 | pbi->saved_resolution = 0; | |
8557 | pbi->get_frame_dur = false; | |
8558 | on_no_keyframe_skiped = 0; | |
c20e6c85 | 8559 | pbi->duration_from_pts_done = 0; |
8560 | pbi->vp9_first_pts_ready = 0; | |
8561 | pbi->frame_cnt_window = 0; | |
b9164398 NQ |
8562 | width = pbi->vvp9_amstream_dec_info.width; |
8563 | height = pbi->vvp9_amstream_dec_info.height; | |
8564 | pbi->frame_dur = | |
8565 | (pbi->vvp9_amstream_dec_info.rate == | |
c20e6c85 | 8566 | 0) ? 3200 : pbi->vvp9_amstream_dec_info.rate; |
b9164398 NQ |
8567 | if (width && height) |
8568 | pbi->frame_ar = height * 0x100 / width; | |
8569 | /* | |
e0614bf7 ZZ |
8570 | *TODO:FOR VERSION |
8571 | */ | |
b9164398 NQ |
8572 | pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version, |
8573 | 0, width, height, pbi->frame_dur); | |
8574 | ||
8575 | if (pbi->frame_dur == 0) | |
8576 | pbi->frame_dur = 96000 / 24; | |
8577 | ||
8578 | INIT_KFIFO(pbi->display_q); | |
8579 | INIT_KFIFO(pbi->newframe_q); | |
8580 | ||
8581 | ||
8582 | for (i = 0; i < VF_POOL_SIZE; i++) { | |
8583 | const struct vframe_s *vf = &pbi->vfpool[i]; | |
e0614bf7 | 8584 | |
b9164398 NQ |
8585 | pbi->vfpool[i].index = -1; |
8586 | kfifo_put(&pbi->newframe_q, vf); | |
8587 | } | |
8588 | ||
8589 | ||
8590 | ret = vp9_local_init(pbi); | |
5f2400c0 | 8591 | |
c20e6c85 | 8592 | if (!pbi->pts_unstable) { |
8593 | pbi->pts_unstable = | |
8594 | (pbi->vvp9_amstream_dec_info.rate == 0)?1:0; | |
8595 | pr_info("set pts unstable\n"); | |
8596 | } | |
5f2400c0 | 8597 | |
b9164398 NQ |
8598 | return ret; |
8599 | } | |
8600 | ||
c23e8aee HZ |
8601 | |
8602 | #ifdef MULTI_INSTANCE_SUPPORT | |
8603 | static s32 vvp9_init(struct vdec_s *vdec) | |
8604 | { | |
8605 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private; | |
8606 | #else | |
b9164398 NQ |
8607 | static s32 vvp9_init(struct VP9Decoder_s *pbi) |
8608 | { | |
c23e8aee | 8609 | #endif |
668e656d | 8610 | int ret; |
6fff1c64 NQ |
8611 | int fw_size = 0x1000 * 16; |
8612 | struct firmware_s *fw = NULL; | |
b9164398 | 8613 | |
b9164398 | 8614 | pbi->stat |= STAT_TIMER_INIT; |
668e656d | 8615 | |
6fff1c64 | 8616 | if (vvp9_local_init(pbi) < 0) |
b9164398 | 8617 | return -EBUSY; |
6fff1c64 NQ |
8618 | |
8619 | fw = vmalloc(sizeof(struct firmware_s) + fw_size); | |
8620 | if (IS_ERR_OR_NULL(fw)) | |
8621 | return -ENOMEM; | |
72a7ad35 | 8622 | |
668e656d | 8623 | if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) { |
6fff1c64 NQ |
8624 | pr_err("get firmware fail.\n"); |
8625 | vfree(fw); | |
8626 | return -1; | |
b9164398 NQ |
8627 | } |
8628 | ||
6fff1c64 NQ |
8629 | fw->len = fw_size; |
8630 | ||
668e656d NQ |
8631 | INIT_WORK(&pbi->set_clk_work, vp9_set_clk); |
8632 | init_timer(&pbi->timer); | |
8633 | ||
b9164398 NQ |
8634 | #ifdef MULTI_INSTANCE_SUPPORT |
8635 | if (pbi->m_ins_flag) { | |
8636 | pbi->timer.data = (ulong) pbi; | |
8637 | pbi->timer.function = vvp9_put_timer_func; | |
8638 | pbi->timer.expires = jiffies + PUT_INTERVAL; | |
8639 | ||
c23e8aee | 8640 | /*add_timer(&pbi->timer); |
b9164398 NQ |
8641 | |
8642 | pbi->stat |= STAT_TIMER_ARM; | |
c23e8aee | 8643 | pbi->stat |= STAT_ISR_REG;*/ |
b9164398 NQ |
8644 | |
8645 | INIT_WORK(&pbi->work, vp9_work); | |
a6c89e96 NQ |
8646 | #ifdef SUPPORT_FB_DECODING |
8647 | if (pbi->used_stage_buf_num > 0) | |
8648 | INIT_WORK(&pbi->s1_work, vp9_s1_work); | |
8649 | #endif | |
6fff1c64 NQ |
8650 | pbi->fw = fw; |
8651 | ||
2cd6815e NQ |
8652 | /* picture list init.*/ |
8653 | pbi->dec_result = DEC_INIT_PICLIST; | |
8654 | vdec_schedule_work(&pbi->work); | |
8655 | ||
b9164398 NQ |
8656 | return 0; |
8657 | } | |
8658 | #endif | |
b9164398 | 8659 | amhevc_enable(); |
e0614bf7 | 8660 | |
ed867a7b NQ |
8661 | init_pic_list(pbi); |
8662 | ||
668e656d | 8663 | ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data); |
f47294da | 8664 | if (ret < 0) { |
b9164398 | 8665 | amhevc_disable(); |
6fff1c64 | 8666 | vfree(fw); |
668e656d NQ |
8667 | pr_err("VP9: the %s fw loading failed, err: %x\n", |
8668 | tee_enabled() ? "TEE" : "local", ret); | |
b9164398 NQ |
8669 | return -EBUSY; |
8670 | } | |
8671 | ||
6fff1c64 | 8672 | vfree(fw); |
b9164398 NQ |
8673 | |
8674 | pbi->stat |= STAT_MC_LOAD; | |
8675 | ||
8676 | /* enable AMRISC side protocol */ | |
a6c89e96 | 8677 | vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); |
b9164398 | 8678 | |
a6c89e96 | 8679 | if (vdec_request_threaded_irq(VDEC_IRQ_0, |
b9164398 NQ |
8680 | vvp9_isr, |
8681 | vvp9_isr_thread_fn, | |
8682 | IRQF_ONESHOT,/*run thread on this irq disabled*/ | |
8683 | "vvp9-irq", (void *)pbi)) { | |
8684 | pr_info("vvp9 irq register error.\n"); | |
8685 | amhevc_disable(); | |
8686 | return -ENOENT; | |
8687 | } | |
8688 | ||
8689 | pbi->stat |= STAT_ISR_REG; | |
8690 | ||
8691 | pbi->provider_name = PROVIDER_NAME; | |
c23e8aee HZ |
8692 | #ifdef MULTI_INSTANCE_SUPPORT |
8693 | vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, | |
8694 | &vvp9_vf_provider, pbi); | |
8695 | vf_reg_provider(&vvp9_vf_prov); | |
8696 | vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); | |
8697 | if (pbi->frame_dur != 0) { | |
8698 | if (!is_reset) | |
8699 | vf_notify_receiver(pbi->provider_name, | |
8700 | VFRAME_EVENT_PROVIDER_FR_HINT, | |
8701 | (void *) | |
8702 | ((unsigned long)pbi->frame_dur)); | |
8703 | } | |
8704 | #else | |
b9164398 NQ |
8705 | vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider, |
8706 | pbi); | |
8707 | vf_reg_provider(&vvp9_vf_prov); | |
8708 | vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); | |
d481db31 NQ |
8709 | if (!is_reset) |
8710 | vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT, | |
8711 | (void *)((unsigned long)pbi->frame_dur)); | |
c23e8aee | 8712 | #endif |
b9164398 NQ |
8713 | pbi->stat |= STAT_VF_HOOK; |
8714 | ||
8715 | pbi->timer.data = (ulong)pbi; | |
8716 | pbi->timer.function = vvp9_put_timer_func; | |
8717 | pbi->timer.expires = jiffies + PUT_INTERVAL; | |
8718 | ||
ca482a9c | 8719 | pbi->stat |= STAT_VDEC_RUN; |
b9164398 NQ |
8720 | |
8721 | add_timer(&pbi->timer); | |
8722 | ||
8723 | pbi->stat |= STAT_TIMER_ARM; | |
8724 | ||
b9164398 NQ |
8725 | amhevc_start(); |
8726 | ||
b9164398 NQ |
8727 | pbi->init_flag = 1; |
8728 | pbi->process_busy = 0; | |
8729 | pr_info("%d, vvp9_init, RP=0x%x\n", | |
8730 | __LINE__, READ_VREG(HEVC_STREAM_RD_PTR)); | |
8731 | return 0; | |
8732 | } | |
8733 | ||
c23e8aee HZ |
8734 | static int vmvp9_stop(struct VP9Decoder_s *pbi) |
8735 | { | |
8736 | pbi->init_flag = 0; | |
8737 | ||
976f3376 HZ |
8738 | if (pbi->stat & STAT_VDEC_RUN) { |
8739 | amhevc_stop(); | |
8740 | pbi->stat &= ~STAT_VDEC_RUN; | |
8741 | } | |
8742 | if (pbi->stat & STAT_ISR_REG) { | |
8743 | vdec_free_irq(VDEC_IRQ_0, (void *)pbi); | |
8744 | pbi->stat &= ~STAT_ISR_REG; | |
8745 | } | |
c23e8aee HZ |
8746 | if (pbi->stat & STAT_TIMER_ARM) { |
8747 | del_timer_sync(&pbi->timer); | |
8748 | pbi->stat &= ~STAT_TIMER_ARM; | |
8749 | } | |
8750 | ||
8751 | if (pbi->stat & STAT_VF_HOOK) { | |
8752 | if (!is_reset) | |
8753 | vf_notify_receiver(pbi->provider_name, | |
8754 | VFRAME_EVENT_PROVIDER_FR_END_HINT, | |
8755 | NULL); | |
8756 | ||
8757 | vf_unreg_provider(&vvp9_vf_prov); | |
8758 | pbi->stat &= ~STAT_VF_HOOK; | |
8759 | } | |
8760 | vp9_local_uninit(pbi); | |
8761 | reset_process_time(pbi); | |
8762 | cancel_work_sync(&pbi->work); | |
a6c89e96 NQ |
8763 | #ifdef SUPPORT_FB_DECODING |
8764 | if (pbi->used_stage_buf_num > 0) | |
8765 | cancel_work_sync(&pbi->s1_work); | |
8766 | #endif | |
a994f6d6 | 8767 | cancel_work_sync(&pbi->set_clk_work); |
c23e8aee | 8768 | uninit_mmu_buffers(pbi); |
df9574f9 HZ |
8769 | if (pbi->fw) |
8770 | vfree(pbi->fw); | |
8771 | pbi->fw = NULL; | |
c23e8aee HZ |
8772 | return 0; |
8773 | } | |
8774 | ||
b9164398 NQ |
8775 | static int vvp9_stop(struct VP9Decoder_s *pbi) |
8776 | { | |
8777 | ||
8778 | pbi->init_flag = 0; | |
ca482a9c | 8779 | pbi->first_sc_checked = 0; |
b9164398 NQ |
8780 | if (pbi->stat & STAT_VDEC_RUN) { |
8781 | amhevc_stop(); | |
8782 | pbi->stat &= ~STAT_VDEC_RUN; | |
8783 | } | |
8784 | ||
8785 | if (pbi->stat & STAT_ISR_REG) { | |
fe96802b NQ |
8786 | #ifdef MULTI_INSTANCE_SUPPORT |
8787 | if (!pbi->m_ins_flag) | |
8788 | #endif | |
a6c89e96 NQ |
8789 | WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0); |
8790 | vdec_free_irq(VDEC_IRQ_0, (void *)pbi); | |
b9164398 NQ |
8791 | pbi->stat &= ~STAT_ISR_REG; |
8792 | } | |
8793 | ||
8794 | if (pbi->stat & STAT_TIMER_ARM) { | |
8795 | del_timer_sync(&pbi->timer); | |
8796 | pbi->stat &= ~STAT_TIMER_ARM; | |
8797 | } | |
8798 | ||
8799 | if (pbi->stat & STAT_VF_HOOK) { | |
d481db31 NQ |
8800 | if (!is_reset) |
8801 | vf_notify_receiver(pbi->provider_name, | |
8802 | VFRAME_EVENT_PROVIDER_FR_END_HINT, | |
8803 | NULL); | |
b9164398 NQ |
8804 | |
8805 | vf_unreg_provider(&vvp9_vf_prov); | |
8806 | pbi->stat &= ~STAT_VF_HOOK; | |
8807 | } | |
8808 | vp9_local_uninit(pbi); | |
8809 | ||
c8ed76ed | 8810 | cancel_work_sync(&pbi->set_clk_work); |
b9164398 | 8811 | #ifdef MULTI_INSTANCE_SUPPORT |
a6c89e96 | 8812 | if (pbi->m_ins_flag) { |
a6c89e96 NQ |
8813 | #ifdef SUPPORT_FB_DECODING |
8814 | if (pbi->used_stage_buf_num > 0) | |
8815 | cancel_work_sync(&pbi->s1_work); | |
8816 | #endif | |
c8ed76ed | 8817 | cancel_work_sync(&pbi->work); |
a6c89e96 | 8818 | } else |
b9164398 | 8819 | amhevc_disable(); |
b9164398 NQ |
8820 | #else |
8821 | amhevc_disable(); | |
8822 | #endif | |
8823 | uninit_mmu_buffers(pbi); | |
8824 | ||
6fff1c64 NQ |
8825 | vfree(pbi->fw); |
8826 | pbi->fw = NULL; | |
b9164398 NQ |
8827 | return 0; |
8828 | } | |
b9164398 NQ |
8829 | static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi) |
8830 | { | |
fe96802b NQ |
8831 | int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ? |
8832 | CODEC_MM_FLAGS_TVP : 0; | |
0be1523d | 8833 | int buf_size = 48; |
ca482a9c | 8834 | |
976f3376 HZ |
8835 | if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) && |
8836 | (pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) { | |
0be1523d | 8837 | buf_size = 12; |
976f3376 HZ |
8838 | } else if ((pbi->max_pic_w * pbi->max_pic_h > 0) && |
8839 | (pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) { | |
8840 | buf_size = 4; | |
b9164398 | 8841 | } |
ca482a9c HZ |
8842 | pbi->need_cache_size = buf_size * SZ_1M; |
8843 | pbi->sc_start_time = get_jiffies_64(); | |
6276f4ff | 8844 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
b7706e1e | 8845 | pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME, |
8846 | pbi->index, FRAME_BUFFERS, | |
ca482a9c | 8847 | pbi->need_cache_size, |
b7706e1e | 8848 | tvp_flag |
8849 | ); | |
8850 | if (!pbi->mmu_box) { | |
8851 | pr_err("vp9 alloc mmu box failed!!\n"); | |
8852 | return -1; | |
8853 | } | |
a6c89e96 | 8854 | } |
b9164398 NQ |
8855 | pbi->bmmu_box = decoder_bmmu_box_alloc_box( |
8856 | DRIVER_NAME, | |
8857 | pbi->index, | |
8858 | MAX_BMMU_BUFFER_NUM, | |
8859 | 4 + PAGE_SHIFT, | |
8860 | CODEC_MM_FLAGS_CMA_CLEAR | | |
fe96802b NQ |
8861 | CODEC_MM_FLAGS_FOR_VDECODER | |
8862 | tvp_flag); | |
b9164398 NQ |
8863 | if (!pbi->bmmu_box) { |
8864 | pr_err("vp9 alloc bmmu box failed!!\n"); | |
8865 | return -1; | |
8866 | } | |
8867 | return 0; | |
8868 | } | |
a674e3cd | 8869 | |
8870 | static struct VP9Decoder_s *gHevc; | |
8871 | ||
b9164398 NQ |
8872 | static int amvdec_vp9_probe(struct platform_device *pdev) |
8873 | { | |
8874 | struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; | |
8875 | struct BUF_s BUF[MAX_BUF_NUM]; | |
a674e3cd | 8876 | struct VP9Decoder_s *pbi; |
fe96802b NQ |
8877 | int ret; |
8878 | #ifndef MULTI_INSTANCE_SUPPORT | |
8879 | int i; | |
8880 | #endif | |
5b851ff9 | 8881 | pr_debug("%s\n", __func__); |
a6c89e96 | 8882 | |
b9164398 | 8883 | mutex_lock(&vvp9_mutex); |
a674e3cd | 8884 | pbi = vmalloc(sizeof(struct VP9Decoder_s)); |
8885 | if (pbi == NULL) { | |
8886 | pr_info("\namvdec_vp9 device data allocation failed\n"); | |
8887 | mutex_unlock(&vvp9_mutex); | |
8888 | return -ENOMEM; | |
8889 | } | |
b9164398 | 8890 | |
a674e3cd | 8891 | gHevc = pbi; |
b9164398 | 8892 | memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); |
a674e3cd | 8893 | memset(pbi, 0, sizeof(struct VP9Decoder_s)); |
b9164398 NQ |
8894 | memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); |
8895 | ||
8896 | pbi->init_flag = 0; | |
ca482a9c | 8897 | pbi->first_sc_checked= 0; |
6f5ee885 | 8898 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
df841122 | 8899 | vp9_max_pic_w = 8192; |
8900 | vp9_max_pic_h = 4608; | |
df841122 | 8901 | } |
a6c89e96 NQ |
8902 | pbi->max_pic_w = vp9_max_pic_w; |
8903 | pbi->max_pic_h = vp9_max_pic_h; | |
fe96802b NQ |
8904 | |
8905 | #ifdef MULTI_INSTANCE_SUPPORT | |
8906 | pbi->eos = 0; | |
8907 | pbi->start_process_time = 0; | |
8908 | pbi->timeout_num = 0; | |
8909 | #endif | |
b9164398 NQ |
8910 | pbi->fatal_error = 0; |
8911 | pbi->show_frame_num = 0; | |
8912 | if (pdata == NULL) { | |
8913 | pr_info("\namvdec_vp9 memory resource undefined.\n"); | |
a674e3cd | 8914 | vfree(pbi); |
b9164398 NQ |
8915 | mutex_unlock(&vvp9_mutex); |
8916 | return -EFAULT; | |
8917 | } | |
8918 | pbi->m_ins_flag = 0; | |
8919 | #ifdef MULTI_INSTANCE_SUPPORT | |
fe96802b NQ |
8920 | pbi->platform_dev = pdev; |
8921 | platform_set_drvdata(pdev, pdata); | |
b9164398 | 8922 | #endif |
b7706e1e | 8923 | pbi->double_write_mode = double_write_mode; |
6276f4ff | 8924 | pbi->mmu_enable = 1; |
b9164398 | 8925 | if (amvdec_vp9_mmu_init(pbi) < 0) { |
a674e3cd | 8926 | vfree(pbi); |
fe96802b | 8927 | mutex_unlock(&vvp9_mutex); |
b9164398 NQ |
8928 | pr_err("vp9 alloc bmmu box failed!!\n"); |
8929 | return -1; | |
8930 | } | |
fe96802b NQ |
8931 | |
8932 | ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID, | |
8933 | work_buf_size, DRIVER_NAME, &pdata->mem_start); | |
8934 | if (ret < 0) { | |
8935 | uninit_mmu_buffers(pbi); | |
a674e3cd | 8936 | vfree(pbi); |
fe96802b NQ |
8937 | mutex_unlock(&vvp9_mutex); |
8938 | return ret; | |
8939 | } | |
8940 | pbi->buf_size = work_buf_size; | |
8941 | ||
8942 | #ifdef MULTI_INSTANCE_SUPPORT | |
8943 | pbi->buf_start = pdata->mem_start; | |
8944 | #else | |
b7706e1e | 8945 | if (!pbi->mmu_enable) |
8946 | pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size; | |
8947 | ||
fe96802b NQ |
8948 | for (i = 0; i < WORK_BUF_SPEC_NUM; i++) |
8949 | amvvp9_workbuff_spec[i].start_adr = pdata->mem_start; | |
8950 | #endif | |
8951 | ||
8952 | ||
b9164398 | 8953 | if (debug) { |
fe96802b NQ |
8954 | pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n", |
8955 | pdata->mem_start, pbi->buf_size); | |
b9164398 NQ |
8956 | } |
8957 | ||
8958 | if (pdata->sys_info) | |
8959 | pbi->vvp9_amstream_dec_info = *pdata->sys_info; | |
8960 | else { | |
8961 | pbi->vvp9_amstream_dec_info.width = 0; | |
8962 | pbi->vvp9_amstream_dec_info.height = 0; | |
8963 | pbi->vvp9_amstream_dec_info.rate = 30; | |
8964 | } | |
0eb79ad7 | 8965 | pbi->no_head = no_head; |
b9164398 NQ |
8966 | #ifdef MULTI_INSTANCE_SUPPORT |
8967 | pbi->cma_dev = pdata->cma_dev; | |
8968 | #else | |
8969 | cma_dev = pdata->cma_dev; | |
8970 | #endif | |
c23e8aee HZ |
8971 | |
8972 | #ifdef MULTI_INSTANCE_SUPPORT | |
8973 | pdata->private = pbi; | |
b9164398 | 8974 | pdata->dec_status = vvp9_dec_status; |
d481db31 NQ |
8975 | pdata->set_isreset = vvp9_set_isreset; |
8976 | is_reset = 0; | |
c23e8aee HZ |
8977 | if (vvp9_init(pdata) < 0) { |
8978 | #else | |
b9164398 | 8979 | if (vvp9_init(pbi) < 0) { |
c23e8aee | 8980 | #endif |
b9164398 NQ |
8981 | pr_info("\namvdec_vp9 init failed.\n"); |
8982 | vp9_local_uninit(pbi); | |
fe96802b | 8983 | uninit_mmu_buffers(pbi); |
a674e3cd | 8984 | vfree(pbi); |
9b670a2d | 8985 | pdata->dec_status = NULL; |
b9164398 NQ |
8986 | mutex_unlock(&vvp9_mutex); |
8987 | return -ENODEV; | |
8988 | } | |
8989 | /*set the max clk for smooth playing...*/ | |
8990 | hevc_source_changed(VFORMAT_VP9, | |
8991 | 4096, 2048, 60); | |
8992 | mutex_unlock(&vvp9_mutex); | |
8993 | ||
8994 | return 0; | |
8995 | } | |
8996 | ||
8997 | static int amvdec_vp9_remove(struct platform_device *pdev) | |
8998 | { | |
a674e3cd | 8999 | struct VP9Decoder_s *pbi = gHevc; |
ed867a7b NQ |
9000 | struct vdec_s *vdec = hw_to_vdec(pbi); |
9001 | int i; | |
e0614bf7 | 9002 | |
b9164398 NQ |
9003 | if (debug) |
9004 | pr_info("amvdec_vp9_remove\n"); | |
9005 | ||
9006 | mutex_lock(&vvp9_mutex); | |
9007 | ||
9008 | vvp9_stop(pbi); | |
9009 | ||
b9164398 NQ |
9010 | hevc_source_changed(VFORMAT_VP9, 0, 0, 0); |
9011 | ||
ed867a7b NQ |
9012 | if (vdec->parallel_dec == 1) { |
9013 | for (i = 0; i < FRAME_BUFFERS; i++) { | |
9014 | vdec->free_canvas_ex(pbi->common.buffer_pool-> | |
9015 | frame_bufs[i].buf.y_canvas_index, vdec->id); | |
9016 | vdec->free_canvas_ex(pbi->common.buffer_pool-> | |
9017 | frame_bufs[i].buf.uv_canvas_index, vdec->id); | |
9018 | } | |
9019 | } | |
9020 | ||
b9164398 NQ |
9021 | #ifdef DEBUG_PTS |
9022 | pr_info("pts missed %ld, pts hit %ld, duration %d\n", | |
9023 | pbi->pts_missed, pbi->pts_hit, pbi->frame_dur); | |
9024 | #endif | |
a674e3cd | 9025 | vfree(pbi); |
b9164398 NQ |
9026 | mutex_unlock(&vvp9_mutex); |
9027 | ||
9028 | return 0; | |
9029 | } | |
9030 | ||
9031 | /****************************************/ | |
1cb8d0da NQ |
9032 | #ifdef CONFIG_PM |
9033 | static int vp9_suspend(struct device *dev) | |
9034 | { | |
9035 | amhevc_suspend(to_platform_device(dev), dev->power.power_state); | |
9036 | return 0; | |
9037 | } | |
9038 | ||
9039 | static int vp9_resume(struct device *dev) | |
9040 | { | |
9041 | amhevc_resume(to_platform_device(dev)); | |
9042 | return 0; | |
9043 | } | |
9044 | ||
9045 | static const struct dev_pm_ops vp9_pm_ops = { | |
9046 | SET_SYSTEM_SLEEP_PM_OPS(vp9_suspend, vp9_resume) | |
9047 | }; | |
9048 | #endif | |
b9164398 NQ |
9049 | |
9050 | static struct platform_driver amvdec_vp9_driver = { | |
9051 | .probe = amvdec_vp9_probe, | |
9052 | .remove = amvdec_vp9_remove, | |
b9164398 NQ |
9053 | .driver = { |
9054 | .name = DRIVER_NAME, | |
1cb8d0da NQ |
9055 | #ifdef CONFIG_PM |
9056 | .pm = &vp9_pm_ops, | |
9057 | #endif | |
b9164398 NQ |
9058 | } |
9059 | }; | |
9060 | ||
9061 | static struct codec_profile_t amvdec_vp9_profile = { | |
9062 | .name = "vp9", | |
9063 | .profile = "" | |
9064 | }; | |
9065 | ||
9457f9af NQ |
9066 | static struct codec_profile_t amvdec_vp9_profile_mult; |
9067 | ||
b9164398 NQ |
9068 | static unsigned char get_data_check_sum |
9069 | (struct VP9Decoder_s *pbi, int size) | |
9070 | { | |
9071 | int jj; | |
9072 | int sum = 0; | |
7d2e7e17 NQ |
9073 | u8 *data = NULL; |
9074 | ||
9075 | if (!pbi->chunk->block->is_mapped) | |
9076 | data = codec_mm_vmap(pbi->chunk->block->start + | |
9077 | pbi->chunk->offset, size); | |
9078 | else | |
9079 | data = ((u8 *)pbi->chunk->block->start_virt) + | |
9080 | pbi->chunk->offset; | |
9081 | ||
b9164398 NQ |
9082 | for (jj = 0; jj < size; jj++) |
9083 | sum += data[jj]; | |
7d2e7e17 NQ |
9084 | |
9085 | if (!pbi->chunk->block->is_mapped) | |
9086 | codec_mm_unmap_phyaddr(data); | |
b9164398 NQ |
9087 | return sum; |
9088 | } | |
9089 | ||
9090 | static void dump_data(struct VP9Decoder_s *pbi, int size) | |
9091 | { | |
9092 | int jj; | |
7d2e7e17 | 9093 | u8 *data = NULL; |
fe96802b NQ |
9094 | int padding_size = pbi->chunk->offset & |
9095 | (VDEC_FIFO_ALIGN - 1); | |
7d2e7e17 NQ |
9096 | |
9097 | if (!pbi->chunk->block->is_mapped) | |
9098 | data = codec_mm_vmap(pbi->chunk->block->start + | |
9099 | pbi->chunk->offset, size); | |
9100 | else | |
9101 | data = ((u8 *)pbi->chunk->block->start_virt) + | |
9102 | pbi->chunk->offset; | |
9103 | ||
fe96802b NQ |
9104 | vp9_print(pbi, 0, "padding: "); |
9105 | for (jj = padding_size; jj > 0; jj--) | |
9106 | vp9_print_cont(pbi, | |
9107 | 0, | |
9108 | "%02x ", *(data - jj)); | |
9109 | vp9_print_cont(pbi, 0, "data adr %p\n", | |
9110 | data); | |
9111 | ||
b9164398 NQ |
9112 | for (jj = 0; jj < size; jj++) { |
9113 | if ((jj & 0xf) == 0) | |
9114 | vp9_print(pbi, | |
9115 | 0, | |
9116 | "%06x:", jj); | |
9117 | vp9_print_cont(pbi, | |
9118 | 0, | |
9119 | "%02x ", data[jj]); | |
9120 | if (((jj + 1) & 0xf) == 0) | |
9121 | vp9_print(pbi, | |
9122 | 0, | |
9123 | "\n"); | |
9124 | } | |
9125 | vp9_print(pbi, | |
9126 | 0, | |
9127 | "\n"); | |
7d2e7e17 NQ |
9128 | |
9129 | if (!pbi->chunk->block->is_mapped) | |
9130 | codec_mm_unmap_phyaddr(data); | |
b9164398 NQ |
9131 | } |
9132 | ||
9133 | static void vp9_work(struct work_struct *work) | |
9134 | { | |
9135 | struct VP9Decoder_s *pbi = container_of(work, | |
9136 | struct VP9Decoder_s, work); | |
b9164398 NQ |
9137 | struct vdec_s *vdec = hw_to_vdec(pbi); |
9138 | /* finished decoding one frame or error, | |
9139 | * notify vdec core to switch context | |
9140 | */ | |
fe96802b NQ |
9141 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, |
9142 | "%s dec_result %d %x %x %x\n", | |
9143 | __func__, | |
9144 | pbi->dec_result, | |
9145 | READ_VREG(HEVC_STREAM_LEVEL), | |
9146 | READ_VREG(HEVC_STREAM_WR_PTR), | |
9147 | READ_VREG(HEVC_STREAM_RD_PTR)); | |
9148 | ||
2cd6815e NQ |
9149 | if (pbi->dec_result == DEC_INIT_PICLIST) { |
9150 | init_pic_list(pbi); | |
9151 | pbi->pic_list_init_done = true; | |
9152 | return; | |
9153 | } | |
9154 | ||
fe96802b NQ |
9155 | if (((pbi->dec_result == DEC_RESULT_GET_DATA) || |
9156 | (pbi->dec_result == DEC_RESULT_GET_DATA_RETRY)) | |
9157 | && (hw_to_vdec(pbi)->next_status != | |
9158 | VDEC_STATUS_DISCONNECTED)) { | |
9159 | if (!vdec_has_more_input(vdec)) { | |
9160 | pbi->dec_result = DEC_RESULT_EOS; | |
9161 | vdec_schedule_work(&pbi->work); | |
9162 | return; | |
9163 | } | |
b9164398 | 9164 | |
b9164398 NQ |
9165 | if (pbi->dec_result == DEC_RESULT_GET_DATA) { |
9166 | vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, | |
9167 | "%s DEC_RESULT_GET_DATA %x %x %x\n", | |
9168 | __func__, | |
9169 | READ_VREG(HEVC_STREAM_LEVEL), | |
9170 | READ_VREG(HEVC_STREAM_WR_PTR), | |
9171 | READ_VREG(HEVC_STREAM_RD_PTR)); | |
9172 | vdec_vframe_dirty(vdec, pbi->chunk); | |
9173 | vdec_clean_input(vdec); | |
9174 | } | |
9175 | ||
fe96802b NQ |
9176 | if (get_free_buf_count(pbi) >= |
9177 | run_ready_min_buf_num) { | |
b9164398 | 9178 | int r; |
fe96802b | 9179 | int decode_size; |
b9164398 NQ |
9180 | r = vdec_prepare_input(vdec, &pbi->chunk); |
9181 | if (r < 0) { | |
9182 | pbi->dec_result = DEC_RESULT_GET_DATA_RETRY; | |
9183 | ||
9184 | vp9_print(pbi, | |
9185 | PRINT_FLAG_VDEC_DETAIL, | |
9186 | "amvdec_vh265: Insufficient data\n"); | |
9187 | ||
fe96802b | 9188 | vdec_schedule_work(&pbi->work); |
b9164398 NQ |
9189 | return; |
9190 | } | |
9191 | pbi->dec_result = DEC_RESULT_NONE; | |
9192 | vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, | |
9193 | "%s: chunk size 0x%x sum 0x%x\n", | |
9194 | __func__, r, | |
9195 | (debug & PRINT_FLAG_VDEC_STATUS) ? | |
9196 | get_data_check_sum(pbi, r) : 0 | |
9197 | ); | |
9198 | ||
9199 | if (debug & PRINT_FLAG_VDEC_DATA) | |
9200 | dump_data(pbi, pbi->chunk->size); | |
fe96802b NQ |
9201 | |
9202 | decode_size = pbi->chunk->size + | |
9203 | (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1)); | |
9204 | ||
9205 | WRITE_VREG(HEVC_DECODE_SIZE, | |
9206 | READ_VREG(HEVC_DECODE_SIZE) + decode_size); | |
b9164398 NQ |
9207 | |
9208 | vdec_enable_input(vdec); | |
9209 | ||
9210 | WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); | |
fe96802b NQ |
9211 | |
9212 | start_process_time(pbi); | |
9213 | ||
b9164398 NQ |
9214 | } else{ |
9215 | pbi->dec_result = DEC_RESULT_GET_DATA_RETRY; | |
9216 | ||
9217 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, | |
9218 | "amvdec_vh265: Insufficient data\n"); | |
9219 | ||
fe96802b | 9220 | vdec_schedule_work(&pbi->work); |
b9164398 NQ |
9221 | } |
9222 | return; | |
9223 | } else if (pbi->dec_result == DEC_RESULT_DONE) { | |
a6c89e96 NQ |
9224 | #ifdef SUPPORT_FB_DECODING |
9225 | if (pbi->used_stage_buf_num > 0) { | |
9226 | #ifndef FB_DECODING_TEST_SCHEDULE | |
9227 | if (!is_s2_decoding_finished(pbi)) { | |
9228 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, | |
9229 | "s2 decoding not done, check again later\n"); | |
9230 | vdec_schedule_work(&pbi->work); | |
9231 | } | |
9232 | #endif | |
9233 | inc_s2_pos(pbi); | |
9234 | if (mcrcc_cache_alg_flag) | |
9235 | dump_hit_rate(pbi); | |
9236 | } | |
9237 | #endif | |
b9164398 NQ |
9238 | /* if (!pbi->ctx_valid) |
9239 | pbi->ctx_valid = 1; */ | |
fe96802b NQ |
9240 | pbi->slice_idx++; |
9241 | pbi->frame_count++; | |
9242 | pbi->process_state = PROC_STATE_INIT; | |
9243 | decode_frame_count[pbi->index] = pbi->frame_count; | |
9244 | ||
b7706e1e | 9245 | if (pbi->mmu_enable) |
9246 | pbi->used_4k_num = | |
9247 | (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); | |
b9164398 | 9248 | vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, |
fe96802b | 9249 | "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n", |
b9164398 | 9250 | __func__, |
fe96802b | 9251 | pbi->frame_count, |
b9164398 NQ |
9252 | pbi->dec_result, |
9253 | READ_VREG(HEVC_STREAM_LEVEL), | |
9254 | READ_VREG(HEVC_STREAM_WR_PTR), | |
fe96802b NQ |
9255 | READ_VREG(HEVC_STREAM_RD_PTR), |
9256 | READ_VREG(HEVC_SHIFT_BYTE_COUNT), | |
9257 | READ_VREG(HEVC_SHIFT_BYTE_COUNT) - | |
9258 | pbi->start_shift_bytes | |
9259 | ); | |
b9164398 | 9260 | vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk); |
fe96802b NQ |
9261 | } else if (pbi->dec_result == DEC_RESULT_AGAIN) { |
9262 | /* | |
9263 | stream base: stream buf empty or timeout | |
9264 | frame base: vdec_prepare_input fail | |
9265 | */ | |
9266 | if (!vdec_has_more_input(vdec)) { | |
9267 | pbi->dec_result = DEC_RESULT_EOS; | |
9268 | vdec_schedule_work(&pbi->work); | |
9269 | return; | |
9270 | } | |
9271 | } else if (pbi->dec_result == DEC_RESULT_EOS) { | |
9272 | vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, | |
9273 | "%s: end of stream\n", | |
9274 | __func__); | |
9275 | pbi->eos = 1; | |
9276 | vp9_bufmgr_postproc(pbi); | |
2cd6815e NQ |
9277 | |
9278 | if (pbi->is_used_v4l) | |
9279 | notify_v4l_eos(hw_to_vdec(pbi)); | |
9280 | ||
fe96802b NQ |
9281 | vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk); |
9282 | } else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) { | |
9283 | vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, | |
9284 | "%s: force exit\n", | |
9285 | __func__); | |
9286 | if (pbi->stat & STAT_VDEC_RUN) { | |
9287 | amhevc_stop(); | |
9288 | pbi->stat &= ~STAT_VDEC_RUN; | |
9289 | } | |
9290 | ||
9291 | if (pbi->stat & STAT_ISR_REG) { | |
9292 | #ifdef MULTI_INSTANCE_SUPPORT | |
9293 | if (!pbi->m_ins_flag) | |
9294 | #endif | |
a6c89e96 NQ |
9295 | WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0); |
9296 | vdec_free_irq(VDEC_IRQ_0, (void *)pbi); | |
fe96802b NQ |
9297 | pbi->stat &= ~STAT_ISR_REG; |
9298 | } | |
b9164398 | 9299 | } |
976f3376 HZ |
9300 | if (pbi->stat & STAT_VDEC_RUN) { |
9301 | amhevc_stop(); | |
9302 | pbi->stat &= ~STAT_VDEC_RUN; | |
9303 | } | |
b9164398 | 9304 | |
c23e8aee HZ |
9305 | if (pbi->stat & STAT_TIMER_ARM) { |
9306 | del_timer_sync(&pbi->timer); | |
9307 | pbi->stat &= ~STAT_TIMER_ARM; | |
9308 | } | |
b9164398 | 9309 | /* mark itself has all HW resource released and input released */ |
a6c89e96 NQ |
9310 | #ifdef SUPPORT_FB_DECODING |
9311 | if (pbi->used_stage_buf_num > 0) | |
9312 | vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK); | |
9313 | else | |
9314 | vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | |
9315 | | CORE_MASK_HEVC | |
9316 | | CORE_MASK_HEVC_FRONT | |
9317 | | CORE_MASK_HEVC_BACK | |
9318 | ); | |
9319 | #else | |
05afa03d PY |
9320 | if (vdec->parallel_dec == 1) |
9321 | vdec_core_finish_run(vdec, CORE_MASK_HEVC); | |
9322 | else | |
9323 | vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | |
9324 | | CORE_MASK_HEVC); | |
a6c89e96 NQ |
9325 | #endif |
9326 | trigger_schedule(pbi); | |
b9164398 NQ |
9327 | } |
9328 | ||
9329 | static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi) | |
9330 | { | |
9331 | /* new to do ... */ | |
a6c89e96 NQ |
9332 | #if (!defined SUPPORT_FB_DECODING) |
9333 | vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); | |
9334 | #elif (defined FB_DECODING_TEST_SCHEDULE) | |
9335 | vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); | |
9336 | #else | |
9337 | if (pbi->used_stage_buf_num > 0) | |
9338 | vvp9_prot_init(pbi, HW_MASK_FRONT); | |
9339 | else | |
9340 | vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); | |
9341 | #endif | |
b9164398 NQ |
9342 | return 0; |
9343 | } | |
a6c89e96 | 9344 | static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask) |
b9164398 NQ |
9345 | { |
9346 | struct VP9Decoder_s *pbi = | |
9347 | (struct VP9Decoder_s *)vdec->private; | |
ca482a9c HZ |
9348 | int tvp = vdec_secure(hw_to_vdec(pbi)) ? |
9349 | CODEC_MM_FLAGS_TVP : 0; | |
a6c89e96 NQ |
9350 | unsigned long ret = 0; |
9351 | ||
2cd6815e | 9352 | if (!(pbi->pic_list_init_done && pbi->pic_list_init_done2) || pbi->eos) |
fe96802b | 9353 | return ret; |
ca482a9c HZ |
9354 | if (!pbi->first_sc_checked && pbi->mmu_enable) { |
9355 | int size = decoder_mmu_box_sc_check(pbi->mmu_box, tvp); | |
9356 | pbi->first_sc_checked = 1; | |
9357 | vp9_print(pbi, 0, "vp9 cached=%d need_size=%d speed= %d ms\n", | |
9358 | size, (pbi->need_cache_size >> PAGE_SHIFT), | |
9359 | (int)(get_jiffies_64() - pbi->sc_start_time) * 1000/HZ); | |
9360 | } | |
a6c89e96 NQ |
9361 | #ifdef SUPPORT_FB_DECODING |
9362 | if (pbi->used_stage_buf_num > 0) { | |
9363 | if (mask & CORE_MASK_HEVC_FRONT) { | |
9364 | if (get_free_stage_buf_num(pbi) > 0 | |
9365 | && mv_buf_available(pbi)) | |
9366 | ret |= CORE_MASK_HEVC_FRONT; | |
9367 | } | |
9368 | if (mask & CORE_MASK_HEVC_BACK) { | |
9369 | if (s2_buf_available(pbi) && | |
9370 | (get_free_buf_count(pbi) >= | |
9371 | run_ready_min_buf_num)) { | |
9372 | ret |= CORE_MASK_HEVC_BACK; | |
9373 | pbi->back_not_run_ready = 0; | |
9374 | } else | |
9375 | pbi->back_not_run_ready = 1; | |
9376 | #if 0 | |
9377 | if (get_free_buf_count(pbi) < | |
9378 | run_ready_min_buf_num) | |
9379 | dump_pic_list(pbi); | |
9380 | #endif | |
9381 | } | |
9382 | } else if (get_free_buf_count(pbi) >= | |
9383 | run_ready_min_buf_num) | |
9384 | ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC | |
9385 | | CORE_MASK_HEVC_FRONT | |
9386 | | CORE_MASK_HEVC_BACK; | |
9387 | ||
9388 | if (ret & CORE_MASK_HEVC_FRONT) | |
9389 | not_run_ready[pbi->index] = 0; | |
9390 | else | |
9391 | not_run_ready[pbi->index]++; | |
9392 | ||
9393 | if (ret & CORE_MASK_HEVC_BACK) | |
9394 | not_run2_ready[pbi->index] = 0; | |
9395 | else | |
9396 | not_run2_ready[pbi->index]++; | |
9397 | ||
9398 | vp9_print(pbi, | |
9399 | PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n", | |
9400 | __func__, mask, ret, | |
9401 | get_free_stage_buf_num(pbi), | |
9402 | mv_buf_available(pbi), | |
9403 | s2_buf_available(pbi), | |
9404 | get_free_buf_count(pbi) | |
9405 | ); | |
b9164398 | 9406 | |
a6c89e96 NQ |
9407 | return ret; |
9408 | ||
9409 | #else | |
fe96802b | 9410 | if (get_free_buf_count(pbi) >= |
05afa03d PY |
9411 | run_ready_min_buf_num) { |
9412 | if (vdec->parallel_dec == 1) | |
9413 | ret = CORE_MASK_HEVC; | |
9414 | else | |
9415 | ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC; | |
9416 | } | |
fe96802b NQ |
9417 | if (ret) |
9418 | not_run_ready[pbi->index] = 0; | |
9419 | else | |
9420 | not_run_ready[pbi->index]++; | |
a6c89e96 NQ |
9421 | |
9422 | vp9_print(pbi, | |
9423 | PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n", | |
9424 | __func__, mask, ret); | |
fe96802b | 9425 | return ret; |
a6c89e96 | 9426 | #endif |
b9164398 NQ |
9427 | } |
9428 | ||
a6c89e96 | 9429 | static void run_front(struct vdec_s *vdec) |
b9164398 NQ |
9430 | { |
9431 | struct VP9Decoder_s *pbi = | |
9432 | (struct VP9Decoder_s *)vdec->private; | |
a6c89e96 | 9433 | int ret, size; |
b9164398 | 9434 | |
fe96802b | 9435 | run_count[pbi->index]++; |
b9164398 | 9436 | /* pbi->chunk = vdec_prepare_input(vdec); */ |
a6c89e96 NQ |
9437 | #if (!defined SUPPORT_FB_DECODING) |
9438 | hevc_reset_core(vdec); | |
9439 | #elif (defined FB_DECODING_TEST_SCHEDULE) | |
fe96802b | 9440 | hevc_reset_core(vdec); |
a6c89e96 NQ |
9441 | #else |
9442 | if (pbi->used_stage_buf_num > 0) | |
9443 | fb_reset_core(vdec, HW_MASK_FRONT); | |
9444 | else | |
9445 | hevc_reset_core(vdec); | |
9446 | #endif | |
b9164398 | 9447 | |
a6c89e96 NQ |
9448 | size = vdec_prepare_input(vdec, &pbi->chunk); |
9449 | if (size < 0) { | |
fe96802b NQ |
9450 | input_empty[pbi->index]++; |
9451 | ||
b9164398 NQ |
9452 | pbi->dec_result = DEC_RESULT_AGAIN; |
9453 | ||
9454 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, | |
9455 | "ammvdec_vh265: Insufficient data\n"); | |
9456 | ||
fe96802b | 9457 | vdec_schedule_work(&pbi->work); |
b9164398 NQ |
9458 | return; |
9459 | } | |
fe96802b | 9460 | input_empty[pbi->index] = 0; |
b9164398 | 9461 | pbi->dec_result = DEC_RESULT_NONE; |
fe96802b | 9462 | pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT); |
b9164398 | 9463 | |
fe96802b NQ |
9464 | if (debug & PRINT_FLAG_VDEC_STATUS) { |
9465 | int ii; | |
9466 | vp9_print(pbi, 0, | |
9467 | "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x", | |
9468 | __func__, | |
a6c89e96 | 9469 | pbi->frame_count, size, |
fe96802b NQ |
9470 | pbi->chunk ? pbi->chunk->size : 0, |
9471 | pbi->chunk ? pbi->chunk->offset : 0, | |
a35da9f0 | 9472 | pbi->chunk ? ((vdec_frame_based(vdec) && |
fe96802b | 9473 | (debug & PRINT_FLAG_VDEC_STATUS)) ? |
a35da9f0 | 9474 | get_data_check_sum(pbi, size) : 0) : 0, |
fe96802b NQ |
9475 | READ_VREG(HEVC_STREAM_START_ADDR), |
9476 | READ_VREG(HEVC_STREAM_END_ADDR), | |
9477 | READ_VREG(HEVC_STREAM_LEVEL), | |
9478 | READ_VREG(HEVC_STREAM_WR_PTR), | |
9479 | READ_VREG(HEVC_STREAM_RD_PTR), | |
9480 | pbi->start_shift_bytes); | |
a35da9f0 | 9481 | if (vdec_frame_based(vdec) && pbi->chunk) { |
7d2e7e17 NQ |
9482 | u8 *data = NULL; |
9483 | ||
9484 | if (!pbi->chunk->block->is_mapped) | |
9485 | data = codec_mm_vmap(pbi->chunk->block->start + | |
9486 | pbi->chunk->offset, 8); | |
9487 | else | |
9488 | data = ((u8 *)pbi->chunk->block->start_virt) + | |
9489 | pbi->chunk->offset; | |
9490 | ||
fe96802b NQ |
9491 | vp9_print_cont(pbi, 0, "data adr %p:", |
9492 | data); | |
9493 | for (ii = 0; ii < 8; ii++) | |
9494 | vp9_print_cont(pbi, 0, "%02x ", | |
9495 | data[ii]); | |
7d2e7e17 NQ |
9496 | |
9497 | if (!pbi->chunk->block->is_mapped) | |
9498 | codec_mm_unmap_phyaddr(data); | |
fe96802b NQ |
9499 | } |
9500 | vp9_print_cont(pbi, 0, "\r\n"); | |
9501 | } | |
158de7c4 HZ |
9502 | if (vdec->mc_loaded) { |
9503 | /*firmware have load before, | |
9504 | and not changes to another. | |
9505 | ignore reload. | |
9506 | */ | |
9507 | } else { | |
9508 | ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data); | |
9509 | if (ret < 0) { | |
9510 | amhevc_disable(); | |
9511 | vp9_print(pbi, PRINT_FLAG_ERROR, | |
9512 | "VP9: the %s fw loading failed, err: %x\n", | |
9513 | tee_enabled() ? "TEE" : "local", ret); | |
9514 | pbi->dec_result = DEC_RESULT_FORCE_EXIT; | |
9515 | vdec_schedule_work(&pbi->work); | |
9516 | return; | |
9517 | } | |
9518 | vdec->mc_loaded = 1; | |
9519 | vdec->mc_type = VFORMAT_VP9; | |
b9164398 | 9520 | } |
a6c89e96 | 9521 | |
b9164398 | 9522 | if (vp9_hw_ctx_restore(pbi) < 0) { |
fe96802b | 9523 | vdec_schedule_work(&pbi->work); |
b9164398 NQ |
9524 | return; |
9525 | } | |
9526 | ||
9527 | vdec_enable_input(vdec); | |
9528 | ||
9529 | WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); | |
9530 | ||
9531 | if (vdec_frame_based(vdec)) { | |
9532 | if (debug & PRINT_FLAG_VDEC_DATA) | |
9533 | dump_data(pbi, pbi->chunk->size); | |
9534 | ||
9535 | WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0); | |
a6c89e96 | 9536 | size = pbi->chunk->size + |
fe96802b | 9537 | (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1)); |
b9164398 | 9538 | } |
a6c89e96 | 9539 | WRITE_VREG(HEVC_DECODE_SIZE, size); |
b9164398 NQ |
9540 | WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx); |
9541 | pbi->init_flag = 1; | |
9542 | ||
fe96802b | 9543 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, |
b9164398 NQ |
9544 | "%s: start hevc (%x %x %x)\n", |
9545 | __func__, | |
9546 | READ_VREG(HEVC_DEC_STATUS_REG), | |
9547 | READ_VREG(HEVC_MPC_E), | |
9548 | READ_VREG(HEVC_MPSR)); | |
9549 | ||
c23e8aee HZ |
9550 | start_process_time(pbi); |
9551 | mod_timer(&pbi->timer, jiffies); | |
9552 | pbi->stat |= STAT_TIMER_ARM; | |
9553 | pbi->stat |= STAT_ISR_REG; | |
b9164398 | 9554 | amhevc_start(); |
fe96802b | 9555 | pbi->stat |= STAT_VDEC_RUN; |
b9164398 NQ |
9556 | } |
9557 | ||
a6c89e96 NQ |
9558 | #ifdef SUPPORT_FB_DECODING |
9559 | static void mpred_process(struct VP9Decoder_s *pbi) | |
9560 | { | |
9561 | union param_u *params = &pbi->s1_param; | |
9562 | unsigned char use_prev_frame_mvs = | |
9563 | !params->p.error_resilient_mode && | |
9564 | params->p.width == pbi->s1_width && | |
9565 | params->p.height == pbi->s1_height && | |
9566 | !pbi->s1_intra_only && | |
9567 | pbi->s1_last_show_frame && | |
9568 | (pbi->s1_frame_type != KEY_FRAME); | |
9569 | pbi->s1_width = params->p.width; | |
9570 | pbi->s1_height = params->p.height; | |
9571 | pbi->s1_frame_type = params->p.frame_type; | |
9572 | pbi->s1_intra_only = | |
9573 | (params->p.show_frame || | |
9574 | params->p.show_existing_frame) | |
9575 | ? 0 : params->p.intra_only; | |
9576 | if ((pbi->s1_frame_type != KEY_FRAME) | |
9577 | && (!pbi->s1_intra_only)) { | |
9578 | unsigned int data32; | |
9579 | int mpred_mv_rd_end_addr; | |
9580 | ||
9581 | mpred_mv_rd_end_addr = | |
9582 | pbi->s1_mpred_mv_wr_start_addr_pre | |
9583 | + (pbi->lcu_total * MV_MEM_UNIT); | |
9584 | ||
9585 | WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412); | |
9586 | WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, | |
9587 | pbi->work_space_buf-> | |
9588 | mpred_above.buf_start); | |
9589 | ||
9590 | data32 = READ_VREG(HEVC_MPRED_CTRL4); | |
9591 | ||
9592 | data32 &= (~(1 << 6)); | |
9593 | data32 |= (use_prev_frame_mvs << 6); | |
9594 | WRITE_VREG(HEVC_MPRED_CTRL4, data32); | |
9595 | ||
9596 | WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR, | |
9597 | pbi->s1_mpred_mv_wr_start_addr); | |
9598 | WRITE_VREG(HEVC_MPRED_MV_WPTR, | |
9599 | pbi->s1_mpred_mv_wr_start_addr); | |
9600 | ||
9601 | WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR, | |
9602 | pbi->s1_mpred_mv_wr_start_addr_pre); | |
9603 | WRITE_VREG(HEVC_MPRED_MV_RPTR, | |
9604 | pbi->s1_mpred_mv_wr_start_addr_pre); | |
9605 | ||
9606 | WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, | |
9607 | mpred_mv_rd_end_addr); | |
9608 | ||
9609 | } else | |
9610 | clear_mpred_hw(pbi); | |
9611 | ||
9612 | if (!params->p.show_existing_frame) { | |
9613 | pbi->s1_mpred_mv_wr_start_addr_pre = | |
9614 | pbi->s1_mpred_mv_wr_start_addr; | |
9615 | pbi->s1_last_show_frame = | |
9616 | params->p.show_frame; | |
9617 | if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM) | |
9618 | put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre); | |
9619 | pbi->s1_mv_buf_index_pre_pre = | |
9620 | pbi->s1_mv_buf_index_pre; | |
9621 | pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index; | |
9622 | } else | |
9623 | put_mv_buf(pbi, &pbi->s1_mv_buf_index); | |
9624 | } | |
9625 | ||
9626 | static void vp9_s1_work(struct work_struct *s1_work) | |
9627 | { | |
9628 | struct VP9Decoder_s *pbi = container_of(s1_work, | |
9629 | struct VP9Decoder_s, s1_work); | |
9630 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, | |
9631 | "%s dec_s1_result %d\n", | |
9632 | __func__, | |
9633 | pbi->dec_s1_result); | |
9634 | ||
9635 | #ifdef FB_DECODING_TEST_SCHEDULE | |
9636 | if (pbi->dec_s1_result == | |
9637 | DEC_S1_RESULT_TEST_TRIGGER_DONE) { | |
9638 | pbi->s1_test_cmd = TEST_SET_PIC_DONE; | |
9639 | WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1); | |
9640 | } | |
9641 | #endif | |
9642 | if (pbi->dec_s1_result == DEC_S1_RESULT_DONE || | |
9643 | pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) { | |
9644 | ||
9645 | vdec_core_finish_run(hw_to_vdec(pbi), | |
9646 | CORE_MASK_HEVC_FRONT); | |
9647 | ||
9648 | trigger_schedule(pbi); | |
9649 | /*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/ | |
9650 | } | |
9651 | ||
9652 | } | |
9653 | ||
9654 | static void run_back(struct vdec_s *vdec) | |
9655 | { | |
9656 | struct VP9Decoder_s *pbi = | |
9657 | (struct VP9Decoder_s *)vdec->private; | |
9658 | int i; | |
9659 | run2_count[pbi->index]++; | |
9660 | if (debug & PRINT_FLAG_VDEC_STATUS) { | |
9661 | vp9_print(pbi, 0, | |
9662 | "%s", __func__); | |
9663 | } | |
9664 | pbi->run2_busy = 1; | |
9665 | #ifndef FB_DECODING_TEST_SCHEDULE | |
9666 | fb_reset_core(vdec, HW_MASK_BACK); | |
9667 | ||
9668 | vvp9_prot_init(pbi, HW_MASK_BACK); | |
9669 | #endif | |
9670 | vp9_recycle_mmu_buf_tail(pbi); | |
9671 | ||
9672 | if (pbi->frame_count > 0) | |
9673 | vp9_bufmgr_postproc(pbi); | |
9674 | ||
9675 | if (get_s2_buf(pbi) >= 0) { | |
9676 | for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { | |
9677 | int ii; | |
9678 | for (ii = 0; ii < 4; ii++) | |
9679 | vp9_param.l.data[i + ii] = | |
9680 | pbi->s2_buf->rpm[i + 3 - ii]; | |
9681 | } | |
9682 | #ifndef FB_DECODING_TEST_SCHEDULE | |
9683 | WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR, | |
9684 | pbi->stage_mmu_map_phy_addr + | |
9685 | pbi->s2_buf->index * STAGE_MMU_MAP_SIZE); | |
9686 | #endif | |
9687 | continue_decoding(pbi); | |
9688 | } | |
9689 | pbi->run2_busy = 0; | |
9690 | } | |
9691 | #endif | |
9692 | ||
9693 | static void run(struct vdec_s *vdec, unsigned long mask, | |
9694 | void (*callback)(struct vdec_s *, void *), void *arg) | |
9695 | { | |
9696 | struct VP9Decoder_s *pbi = | |
9697 | (struct VP9Decoder_s *)vdec->private; | |
9698 | ||
9699 | vp9_print(pbi, | |
9700 | PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n", | |
9701 | __func__, mask); | |
9702 | ||
9703 | run_count[pbi->index]++; | |
9704 | pbi->vdec_cb_arg = arg; | |
9705 | pbi->vdec_cb = callback; | |
9706 | #ifdef SUPPORT_FB_DECODING | |
9707 | if ((mask & CORE_MASK_HEVC) || | |
9708 | (mask & CORE_MASK_HEVC_FRONT)) | |
9709 | run_front(vdec); | |
9710 | ||
9711 | if ((pbi->used_stage_buf_num > 0) | |
9712 | && (mask & CORE_MASK_HEVC_BACK)) | |
9713 | run_back(vdec); | |
9714 | #else | |
9715 | run_front(vdec); | |
9716 | #endif | |
9717 | } | |
9718 | ||
b9164398 NQ |
9719 | static void reset(struct vdec_s *vdec) |
9720 | { | |
9721 | ||
9722 | struct VP9Decoder_s *pbi = | |
9723 | (struct VP9Decoder_s *)vdec->private; | |
9724 | ||
9725 | vp9_print(pbi, | |
9726 | PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__); | |
9727 | ||
9728 | } | |
9729 | ||
a6c89e96 | 9730 | static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq) |
b9164398 NQ |
9731 | { |
9732 | struct VP9Decoder_s *pbi = | |
9733 | (struct VP9Decoder_s *)vdec->private; | |
9734 | return vvp9_isr(0, pbi); | |
9735 | } | |
9736 | ||
a6c89e96 | 9737 | static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq) |
b9164398 NQ |
9738 | { |
9739 | struct VP9Decoder_s *pbi = | |
9740 | (struct VP9Decoder_s *)vdec->private; | |
9741 | return vvp9_isr_thread_fn(0, pbi); | |
9742 | } | |
9743 | ||
fe96802b NQ |
9744 | static void vp9_dump_state(struct vdec_s *vdec) |
9745 | { | |
9746 | struct VP9Decoder_s *pbi = | |
9747 | (struct VP9Decoder_s *)vdec->private; | |
9748 | struct VP9_Common_s *const cm = &pbi->common; | |
9749 | int i; | |
9750 | vp9_print(pbi, 0, "====== %s\n", __func__); | |
9751 | ||
9752 | vp9_print(pbi, 0, | |
9753 | "width/height (%d/%d), used_buf_num %d\n", | |
9754 | cm->width, | |
9755 | cm->height, | |
9756 | pbi->used_buf_num | |
9757 | ); | |
9758 | ||
9759 | vp9_print(pbi, 0, | |
0eb79ad7 | 9760 | "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n", |
fe96802b NQ |
9761 | input_frame_based(vdec), |
9762 | pbi->eos, | |
9763 | pbi->dec_result, | |
9764 | decode_frame_count[pbi->index], | |
9765 | display_frame_count[pbi->index], | |
9766 | run_count[pbi->index], | |
9767 | not_run_ready[pbi->index], | |
187af067 | 9768 | input_empty[pbi->index], |
0eb79ad7 RZ |
9769 | pbi->low_latency_flag, |
9770 | pbi->no_head | |
fe96802b NQ |
9771 | ); |
9772 | ||
9773 | if (vf_get_receiver(vdec->vf_provider_name)) { | |
9774 | enum receviver_start_e state = | |
9775 | vf_notify_receiver(vdec->vf_provider_name, | |
9776 | VFRAME_EVENT_PROVIDER_QUREY_STATE, | |
9777 | NULL); | |
9778 | vp9_print(pbi, 0, | |
9779 | "\nreceiver(%s) state %d\n", | |
9780 | vdec->vf_provider_name, | |
9781 | state); | |
9782 | } | |
9783 | ||
9784 | vp9_print(pbi, 0, | |
9785 | "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n", | |
9786 | __func__, | |
9787 | kfifo_len(&pbi->newframe_q), | |
9788 | VF_POOL_SIZE, | |
9789 | kfifo_len(&pbi->display_q), | |
9790 | VF_POOL_SIZE, | |
9791 | pbi->vf_pre_count, | |
9792 | pbi->vf_get_count, | |
9793 | pbi->vf_put_count, | |
9794 | get_free_buf_count(pbi), | |
9795 | run_ready_min_buf_num | |
9796 | ); | |
9797 | ||
9798 | dump_pic_list(pbi); | |
9799 | ||
9800 | for (i = 0; i < MAX_BUF_NUM; i++) { | |
9801 | vp9_print(pbi, 0, | |
9802 | "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n", | |
9803 | i, | |
9804 | pbi->m_mv_BUF[i].start_adr, | |
9805 | pbi->m_mv_BUF[i].size, | |
9806 | pbi->m_mv_BUF[i].used_flag); | |
9807 | } | |
9808 | ||
9809 | vp9_print(pbi, 0, | |
9810 | "HEVC_DEC_STATUS_REG=0x%x\n", | |
9811 | READ_VREG(HEVC_DEC_STATUS_REG)); | |
9812 | vp9_print(pbi, 0, | |
9813 | "HEVC_MPC_E=0x%x\n", | |
9814 | READ_VREG(HEVC_MPC_E)); | |
9815 | vp9_print(pbi, 0, | |
9816 | "DECODE_MODE=0x%x\n", | |
9817 | READ_VREG(DECODE_MODE)); | |
9818 | vp9_print(pbi, 0, | |
9819 | "NAL_SEARCH_CTL=0x%x\n", | |
9820 | READ_VREG(NAL_SEARCH_CTL)); | |
9821 | vp9_print(pbi, 0, | |
9822 | "HEVC_PARSER_LCU_START=0x%x\n", | |
9823 | READ_VREG(HEVC_PARSER_LCU_START)); | |
9824 | vp9_print(pbi, 0, | |
9825 | "HEVC_DECODE_SIZE=0x%x\n", | |
9826 | READ_VREG(HEVC_DECODE_SIZE)); | |
9827 | vp9_print(pbi, 0, | |
9828 | "HEVC_SHIFT_BYTE_COUNT=0x%x\n", | |
9829 | READ_VREG(HEVC_SHIFT_BYTE_COUNT)); | |
9830 | vp9_print(pbi, 0, | |
9831 | "HEVC_STREAM_START_ADDR=0x%x\n", | |
9832 | READ_VREG(HEVC_STREAM_START_ADDR)); | |
9833 | vp9_print(pbi, 0, | |
9834 | "HEVC_STREAM_END_ADDR=0x%x\n", | |
9835 | READ_VREG(HEVC_STREAM_END_ADDR)); | |
9836 | vp9_print(pbi, 0, | |
9837 | "HEVC_STREAM_LEVEL=0x%x\n", | |
9838 | READ_VREG(HEVC_STREAM_LEVEL)); | |
9839 | vp9_print(pbi, 0, | |
9840 | "HEVC_STREAM_WR_PTR=0x%x\n", | |
9841 | READ_VREG(HEVC_STREAM_WR_PTR)); | |
9842 | vp9_print(pbi, 0, | |
9843 | "HEVC_STREAM_RD_PTR=0x%x\n", | |
9844 | READ_VREG(HEVC_STREAM_RD_PTR)); | |
9845 | vp9_print(pbi, 0, | |
9846 | "PARSER_VIDEO_RP=0x%x\n", | |
9847 | READ_PARSER_REG(PARSER_VIDEO_RP)); | |
9848 | vp9_print(pbi, 0, | |
9849 | "PARSER_VIDEO_WP=0x%x\n", | |
9850 | READ_PARSER_REG(PARSER_VIDEO_WP)); | |
9851 | ||
9852 | if (input_frame_based(vdec) && | |
9853 | (debug & PRINT_FLAG_VDEC_DATA) | |
9854 | ) { | |
9855 | int jj; | |
9856 | if (pbi->chunk && pbi->chunk->block && | |
9857 | pbi->chunk->size > 0) { | |
7d2e7e17 NQ |
9858 | u8 *data = NULL; |
9859 | ||
9860 | if (!pbi->chunk->block->is_mapped) | |
9861 | data = codec_mm_vmap( | |
9862 | pbi->chunk->block->start + | |
9863 | pbi->chunk->offset, | |
9864 | pbi->chunk->size); | |
9865 | else | |
9866 | data = ((u8 *)pbi->chunk->block->start_virt) | |
9867 | + pbi->chunk->offset; | |
fe96802b NQ |
9868 | vp9_print(pbi, 0, |
9869 | "frame data size 0x%x\n", | |
9870 | pbi->chunk->size); | |
9871 | for (jj = 0; jj < pbi->chunk->size; jj++) { | |
9872 | if ((jj & 0xf) == 0) | |
9873 | vp9_print(pbi, 0, | |
9874 | "%06x:", jj); | |
9875 | vp9_print_cont(pbi, 0, | |
9876 | "%02x ", data[jj]); | |
9877 | if (((jj + 1) & 0xf) == 0) | |
9878 | vp9_print_cont(pbi, 0, | |
9879 | "\n"); | |
9880 | } | |
7d2e7e17 NQ |
9881 | |
9882 | if (!pbi->chunk->block->is_mapped) | |
9883 | codec_mm_unmap_phyaddr(data); | |
fe96802b NQ |
9884 | } |
9885 | } | |
9886 | ||
9887 | } | |
b9164398 NQ |
9888 | |
9889 | static int ammvdec_vp9_probe(struct platform_device *pdev) | |
9890 | { | |
9891 | struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; | |
fe96802b NQ |
9892 | int ret; |
9893 | int config_val; | |
d481db31 NQ |
9894 | struct vframe_content_light_level_s content_light_level; |
9895 | struct vframe_master_display_colour_s vf_dp; | |
b9164398 NQ |
9896 | |
9897 | struct BUF_s BUF[MAX_BUF_NUM]; | |
9898 | struct VP9Decoder_s *pbi = NULL; | |
5666aa9d | 9899 | pr_debug("%s\n", __func__); |
a6c89e96 | 9900 | |
b9164398 NQ |
9901 | if (pdata == NULL) { |
9902 | pr_info("\nammvdec_vp9 memory resource undefined.\n"); | |
9903 | return -EFAULT; | |
9904 | } | |
fe96802b NQ |
9905 | /*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev, |
9906 | sizeof(struct VP9Decoder_s), GFP_KERNEL);*/ | |
d481db31 | 9907 | memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s)); |
fe96802b | 9908 | pbi = vmalloc(sizeof(struct VP9Decoder_s)); |
b9164398 NQ |
9909 | if (pbi == NULL) { |
9910 | pr_info("\nammvdec_vp9 device data allocation failed\n"); | |
9911 | return -ENOMEM; | |
9912 | } | |
a674e3cd | 9913 | memset(pbi, 0, sizeof(struct VP9Decoder_s)); |
2cd6815e NQ |
9914 | |
9915 | /* the ctx from v4l2 driver. */ | |
9916 | pbi->v4l2_ctx = pdata->private; | |
9917 | ||
b9164398 NQ |
9918 | pdata->private = pbi; |
9919 | pdata->dec_status = vvp9_dec_status; | |
9920 | /* pdata->set_trickmode = set_trickmode; */ | |
9921 | pdata->run_ready = run_ready; | |
9922 | pdata->run = run; | |
9923 | pdata->reset = reset; | |
9924 | pdata->irq_handler = vp9_irq_cb; | |
9925 | pdata->threaded_irq_handler = vp9_threaded_irq_cb; | |
fe96802b | 9926 | pdata->dump_state = vp9_dump_state; |
b9164398 | 9927 | |
b9164398 | 9928 | memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); |
b9164398 NQ |
9929 | memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); |
9930 | ||
fe96802b | 9931 | pbi->index = pdev->id; |
b9164398 NQ |
9932 | |
9933 | if (pdata->use_vfm_path) | |
9934 | snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, | |
9935 | VFM_DEC_PROVIDER_NAME); | |
9936 | else | |
9937 | snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, | |
9938 | MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff); | |
9939 | ||
9940 | vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name, | |
9941 | &vvp9_vf_provider, pbi); | |
9942 | ||
9943 | pbi->provider_name = pdata->vf_provider_name; | |
9944 | platform_set_drvdata(pdev, pdata); | |
9945 | ||
9946 | pbi->platform_dev = pdev; | |
d481db31 | 9947 | pbi->video_signal_type = 0; |
b7706e1e | 9948 | pbi->m_ins_flag = 1; |
63e810c0 | 9949 | if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) |
c23e8aee | 9950 | pbi->stat |= VP9_TRIGGER_FRAME_ENABLE; |
c4ea7ef3 | 9951 | |
6f5ee885 | 9952 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
e0e39311 | 9953 | pbi->max_pic_w = 8192; |
9954 | pbi->max_pic_h = 4608; | |
b295c149 NQ |
9955 | } else { |
9956 | pbi->max_pic_w = 4096; | |
9957 | pbi->max_pic_h = 2304; | |
e0e39311 | 9958 | } |
fe96802b NQ |
9959 | #if 1 |
9960 | if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 && | |
a35da9f0 | 9961 | pdata->config_len) { |
fe96802b | 9962 | #ifdef MULTI_INSTANCE_SUPPORT |
96b88a8a HZ |
9963 | int vp9_buf_width = 0; |
9964 | int vp9_buf_height = 0; | |
fe96802b NQ |
9965 | /*use ptr config for doubel_write_mode, etc*/ |
9966 | vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config); | |
9967 | if (get_config_int(pdata->config, "vp9_double_write_mode", | |
9968 | &config_val) == 0) | |
9969 | pbi->double_write_mode = config_val; | |
9970 | else | |
9971 | pbi->double_write_mode = double_write_mode; | |
0be1523d | 9972 | |
a5c5bec0 YL |
9973 | if (get_config_int(pdata->config, "save_buffer_mode", |
9974 | &config_val) == 0) | |
9975 | pbi->save_buffer_mode = config_val; | |
9976 | else | |
9977 | pbi->save_buffer_mode = 0; | |
96b88a8a HZ |
9978 | if (get_config_int(pdata->config, "vp9_buf_width", |
9979 | &config_val) == 0) { | |
9980 | vp9_buf_width = config_val; | |
9981 | } | |
9982 | if (get_config_int(pdata->config, "vp9_buf_height", | |
9983 | &config_val) == 0) { | |
9984 | vp9_buf_height = config_val; | |
9985 | } | |
a5c5bec0 | 9986 | |
0eb79ad7 RZ |
9987 | if (get_config_int(pdata->config, "no_head", |
9988 | &config_val) == 0) | |
9989 | pbi->no_head = config_val; | |
9990 | else | |
9991 | pbi->no_head = no_head; | |
9992 | ||
0be1523d YL |
9993 | /*use ptr config for max_pic_w, etc*/ |
9994 | if (get_config_int(pdata->config, "vp9_max_pic_w", | |
9995 | &config_val) == 0) { | |
9996 | pbi->max_pic_w = config_val; | |
9997 | } | |
9998 | if (get_config_int(pdata->config, "vp9_max_pic_h", | |
9999 | &config_val) == 0) { | |
10000 | pbi->max_pic_h = config_val; | |
10001 | } | |
96b88a8a HZ |
10002 | if ((pbi->max_pic_w * pbi->max_pic_h) |
10003 | < (vp9_buf_width * vp9_buf_height)) { | |
10004 | pbi->max_pic_w = vp9_buf_width; | |
10005 | pbi->max_pic_h = vp9_buf_height; | |
10006 | vp9_print(pbi, 0, "use buf resolution\n"); | |
10007 | } | |
fe96802b | 10008 | #endif |
d481db31 NQ |
10009 | if (get_config_int(pdata->config, "HDRStaticInfo", |
10010 | &vf_dp.present_flag) == 0 | |
10011 | && vf_dp.present_flag == 1) { | |
10012 | get_config_int(pdata->config, "mG.x", | |
10013 | &vf_dp.primaries[0][0]); | |
10014 | get_config_int(pdata->config, "mG.y", | |
10015 | &vf_dp.primaries[0][1]); | |
10016 | get_config_int(pdata->config, "mB.x", | |
10017 | &vf_dp.primaries[1][0]); | |
10018 | get_config_int(pdata->config, "mB.y", | |
10019 | &vf_dp.primaries[1][1]); | |
10020 | get_config_int(pdata->config, "mR.x", | |
10021 | &vf_dp.primaries[2][0]); | |
10022 | get_config_int(pdata->config, "mR.y", | |
10023 | &vf_dp.primaries[2][1]); | |
10024 | get_config_int(pdata->config, "mW.x", | |
10025 | &vf_dp.white_point[0]); | |
10026 | get_config_int(pdata->config, "mW.y", | |
10027 | &vf_dp.white_point[1]); | |
10028 | get_config_int(pdata->config, "mMaxDL", | |
10029 | &vf_dp.luminance[0]); | |
10030 | get_config_int(pdata->config, "mMinDL", | |
10031 | &vf_dp.luminance[1]); | |
10032 | vf_dp.content_light_level.present_flag = 1; | |
10033 | get_config_int(pdata->config, "mMaxCLL", | |
10034 | &content_light_level.max_content); | |
10035 | get_config_int(pdata->config, "mMaxFALL", | |
10036 | &content_light_level.max_pic_average); | |
10037 | vf_dp.content_light_level = content_light_level; | |
10038 | pbi->video_signal_type = (1 << 29) | |
10039 | | (5 << 26) /* unspecified */ | |
10040 | | (0 << 25) /* limit */ | |
10041 | | (1 << 24) /* color available */ | |
10042 | | (9 << 16) /* 2020 */ | |
10043 | | (16 << 8) /* 2084 */ | |
10044 | | (9 << 0); /* 2020 */ | |
10045 | } | |
10046 | pbi->vf_dp = vf_dp; | |
fe96802b NQ |
10047 | } else |
10048 | #endif | |
10049 | { | |
10050 | /*pbi->vvp9_amstream_dec_info.width = 0; | |
10051 | pbi->vvp9_amstream_dec_info.height = 0; | |
10052 | pbi->vvp9_amstream_dec_info.rate = 30;*/ | |
10053 | pbi->double_write_mode = double_write_mode; | |
10054 | } | |
e0e39311 | 10055 | if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) { |
10056 | pr_err("over size: %dx%d, probe failed\n", | |
10057 | pbi->max_pic_w, pbi->max_pic_h); | |
10058 | return -1; | |
10059 | } | |
6276f4ff | 10060 | pbi->mmu_enable = 1; |
d481db31 | 10061 | video_signal_type = pbi->video_signal_type; |
2cd6815e | 10062 | |
0eb79ad7 | 10063 | if (pdata->sys_info) { |
2cd6815e | 10064 | pbi->vvp9_amstream_dec_info = *pdata->sys_info; |
0eb79ad7 RZ |
10065 | if ((unsigned long) pbi->vvp9_amstream_dec_info.param |
10066 | & 0x08) { | |
10067 | pbi->low_latency_flag = 1; | |
10068 | } else | |
10069 | pbi->low_latency_flag = 0; | |
10070 | } else { | |
2cd6815e NQ |
10071 | pbi->vvp9_amstream_dec_info.width = 0; |
10072 | pbi->vvp9_amstream_dec_info.height = 0; | |
10073 | pbi->vvp9_amstream_dec_info.rate = 30; | |
10074 | } | |
10075 | ||
10076 | pbi->is_used_v4l = (((unsigned long) | |
10077 | pbi->vvp9_amstream_dec_info.param & 0x80) >> 7); | |
10078 | if (pbi->is_used_v4l) { | |
10079 | pbi->double_write_mode = 0x10; | |
10080 | pbi->mmu_enable = 0; | |
10081 | pbi->max_pic_w = 1920; | |
10082 | pbi->max_pic_h = 1080; | |
10083 | } | |
10084 | ||
0eb79ad7 RZ |
10085 | vp9_print(pbi, 0, |
10086 | "no_head %d low_latency %d\n", | |
10087 | pbi->no_head, pbi->low_latency_flag); | |
b9164398 NQ |
10088 | #if 0 |
10089 | pbi->buf_start = pdata->mem_start; | |
10090 | pbi->buf_size = pdata->mem_end - pdata->mem_start + 1; | |
10091 | #else | |
10092 | if (amvdec_vp9_mmu_init(pbi) < 0) { | |
10093 | pr_err("vp9 alloc bmmu box failed!!\n"); | |
fe96802b NQ |
10094 | /* devm_kfree(&pdev->dev, (void *)pbi); */ |
10095 | vfree((void *)pbi); | |
9b670a2d | 10096 | pdata->dec_status = NULL; |
b9164398 NQ |
10097 | return -1; |
10098 | } | |
10099 | ||
10100 | pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE; | |
fe96802b NQ |
10101 | ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID, |
10102 | pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME, | |
10103 | &pbi->cma_alloc_addr); | |
10104 | if (ret < 0) { | |
b9164398 | 10105 | uninit_mmu_buffers(pbi); |
fe96802b NQ |
10106 | /* devm_kfree(&pdev->dev, (void *)pbi); */ |
10107 | vfree((void *)pbi); | |
9b670a2d | 10108 | pdata->dec_status = NULL; |
fe96802b | 10109 | return ret; |
b9164398 NQ |
10110 | } |
10111 | pbi->buf_start = pbi->cma_alloc_addr; | |
10112 | pbi->buf_size = work_buf_size; | |
10113 | #endif | |
b9164398 NQ |
10114 | |
10115 | pbi->init_flag = 0; | |
ca482a9c | 10116 | pbi->first_sc_checked = 0; |
b9164398 NQ |
10117 | pbi->fatal_error = 0; |
10118 | pbi->show_frame_num = 0; | |
b9164398 NQ |
10119 | |
10120 | if (debug) { | |
fe96802b | 10121 | pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n", |
b9164398 | 10122 | pbi->buf_start, |
fe96802b | 10123 | pbi->buf_size); |
b9164398 NQ |
10124 | } |
10125 | ||
b9164398 | 10126 | pbi->cma_dev = pdata->cma_dev; |
c23e8aee | 10127 | if (vvp9_init(pdata) < 0) { |
b9164398 NQ |
10128 | pr_info("\namvdec_vp9 init failed.\n"); |
10129 | vp9_local_uninit(pbi); | |
10130 | uninit_mmu_buffers(pbi); | |
fe96802b NQ |
10131 | /* devm_kfree(&pdev->dev, (void *)pbi); */ |
10132 | vfree((void *)pbi); | |
9b670a2d | 10133 | pdata->dec_status = NULL; |
b9164398 NQ |
10134 | return -ENODEV; |
10135 | } | |
c23e8aee | 10136 | vdec_set_prepare_level(pdata, start_decode_buf_level); |
fe96802b NQ |
10137 | hevc_source_changed(VFORMAT_VP9, |
10138 | 4096, 2048, 60); | |
a6c89e96 NQ |
10139 | #ifdef SUPPORT_FB_DECODING |
10140 | if (pbi->used_stage_buf_num > 0) | |
10141 | vdec_core_request(pdata, | |
10142 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK); | |
10143 | else | |
10144 | vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC | |
10145 | | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK | |
10146 | | CORE_MASK_COMBINE); | |
10147 | #else | |
05afa03d PY |
10148 | if (pdata->parallel_dec == 1) |
10149 | vdec_core_request(pdata, CORE_MASK_HEVC); | |
10150 | else | |
a6c89e96 NQ |
10151 | vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
10152 | | CORE_MASK_COMBINE); | |
10153 | #endif | |
2cd6815e | 10154 | pbi->pic_list_init_done2 = true; |
b9164398 NQ |
10155 | return 0; |
10156 | } | |
10157 | ||
10158 | static int ammvdec_vp9_remove(struct platform_device *pdev) | |
10159 | { | |
10160 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *) | |
10161 | (((struct vdec_s *)(platform_get_drvdata(pdev)))->private); | |
05afa03d PY |
10162 | struct vdec_s *vdec = hw_to_vdec(pbi); |
10163 | int i; | |
b9164398 NQ |
10164 | if (debug) |
10165 | pr_info("amvdec_vp9_remove\n"); | |
10166 | ||
c23e8aee | 10167 | vmvp9_stop(pbi); |
b9164398 | 10168 | |
a6c89e96 NQ |
10169 | #ifdef SUPPORT_FB_DECODING |
10170 | vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC | |
10171 | | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK | |
10172 | ); | |
10173 | #else | |
05afa03d PY |
10174 | if (vdec->parallel_dec == 1) |
10175 | vdec_core_release(hw_to_vdec(pbi), CORE_MASK_HEVC); | |
10176 | else | |
10177 | vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC); | |
a6c89e96 | 10178 | #endif |
b9164398 NQ |
10179 | vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED); |
10180 | ||
05afa03d PY |
10181 | if (vdec->parallel_dec == 1) { |
10182 | for (i = 0; i < FRAME_BUFFERS; i++) { | |
10183 | vdec->free_canvas_ex | |
10184 | (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index, | |
10185 | vdec->id); | |
10186 | vdec->free_canvas_ex | |
10187 | (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index, | |
10188 | vdec->id); | |
10189 | } | |
10190 | } | |
10191 | ||
b9164398 NQ |
10192 | |
10193 | #ifdef DEBUG_PTS | |
10194 | pr_info("pts missed %ld, pts hit %ld, duration %d\n", | |
10195 | pbi->pts_missed, pbi->pts_hit, pbi->frame_dur); | |
10196 | #endif | |
fe96802b NQ |
10197 | /* devm_kfree(&pdev->dev, (void *)pbi); */ |
10198 | vfree((void *)pbi); | |
b9164398 NQ |
10199 | return 0; |
10200 | } | |
10201 | ||
10202 | static struct platform_driver ammvdec_vp9_driver = { | |
10203 | .probe = ammvdec_vp9_probe, | |
10204 | .remove = ammvdec_vp9_remove, | |
b9164398 NQ |
10205 | .driver = { |
10206 | .name = MULTI_DRIVER_NAME, | |
1cb8d0da NQ |
10207 | #ifdef CONFIG_PM |
10208 | .pm = &vp9_pm_ops, | |
10209 | #endif | |
b9164398 NQ |
10210 | } |
10211 | }; | |
10212 | #endif | |
fe96802b NQ |
10213 | static struct mconfig vp9_configs[] = { |
10214 | MC_PU32("bit_depth_luma", &bit_depth_luma), | |
10215 | MC_PU32("bit_depth_chroma", &bit_depth_chroma), | |
10216 | MC_PU32("frame_width", &frame_width), | |
10217 | MC_PU32("frame_height", &frame_height), | |
10218 | MC_PU32("debug", &debug), | |
10219 | MC_PU32("radr", &radr), | |
10220 | MC_PU32("rval", &rval), | |
10221 | MC_PU32("pop_shorts", &pop_shorts), | |
10222 | MC_PU32("dbg_cmd", &dbg_cmd), | |
10223 | MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index), | |
10224 | MC_PU32("endian", &endian), | |
10225 | MC_PU32("step", &step), | |
10226 | MC_PU32("udebug_flag", &udebug_flag), | |
10227 | MC_PU32("decode_pic_begin", &decode_pic_begin), | |
10228 | MC_PU32("slice_parse_begin", &slice_parse_begin), | |
10229 | MC_PU32("i_only_flag", &i_only_flag), | |
10230 | MC_PU32("error_handle_policy", &error_handle_policy), | |
10231 | MC_PU32("buf_alloc_width", &buf_alloc_width), | |
10232 | MC_PU32("buf_alloc_height", &buf_alloc_height), | |
10233 | MC_PU32("buf_alloc_depth", &buf_alloc_depth), | |
10234 | MC_PU32("buf_alloc_size", &buf_alloc_size), | |
10235 | MC_PU32("buffer_mode", &buffer_mode), | |
10236 | MC_PU32("buffer_mode_dbg", &buffer_mode_dbg), | |
dfe41deb | 10237 | MC_PU32("max_buf_num", &max_buf_num), |
fe96802b NQ |
10238 | MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin), |
10239 | MC_PU32("mem_map_mode", &mem_map_mode), | |
10240 | MC_PU32("double_write_mode", &double_write_mode), | |
10241 | MC_PU32("enable_mem_saving", &enable_mem_saving), | |
10242 | MC_PU32("force_w_h", &force_w_h), | |
10243 | MC_PU32("force_fps", &force_fps), | |
10244 | MC_PU32("max_decoding_time", &max_decoding_time), | |
10245 | MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped), | |
10246 | MC_PU32("start_decode_buf_level", &start_decode_buf_level), | |
10247 | MC_PU32("decode_timeout_val", &decode_timeout_val), | |
a6c89e96 NQ |
10248 | MC_PU32("vp9_max_pic_w", &vp9_max_pic_w), |
10249 | MC_PU32("vp9_max_pic_h", &vp9_max_pic_h), | |
fe96802b NQ |
10250 | }; |
10251 | static struct mconfig_node vp9_node; | |
b9164398 NQ |
10252 | |
10253 | static int __init amvdec_vp9_driver_init_module(void) | |
10254 | { | |
fe96802b | 10255 | |
fe96802b | 10256 | struct BuffInfo_s *p_buf_info; |
df841122 | 10257 | |
10258 | if (vdec_is_support_4k()) { | |
6f5ee885 | 10259 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) |
df841122 | 10260 | p_buf_info = &amvvp9_workbuff_spec[2]; |
10261 | else | |
10262 | p_buf_info = &amvvp9_workbuff_spec[1]; | |
10263 | } else | |
c23e8aee | 10264 | p_buf_info = &amvvp9_workbuff_spec[0]; |
df841122 | 10265 | |
fe96802b NQ |
10266 | init_buff_spec(NULL, p_buf_info); |
10267 | work_buf_size = | |
10268 | (p_buf_info->end_adr - p_buf_info->start_adr | |
10269 | + 0xffff) & (~0xffff); | |
10270 | ||
b9164398 | 10271 | pr_debug("amvdec_vp9 module init\n"); |
b7706e1e | 10272 | |
b9164398 NQ |
10273 | error_handle_policy = 0; |
10274 | ||
10275 | #ifdef ERROR_HANDLE_DEBUG | |
10276 | dbg_nal_skip_flag = 0; | |
10277 | dbg_nal_skip_count = 0; | |
10278 | #endif | |
fe96802b | 10279 | udebug_flag = 0; |
b9164398 NQ |
10280 | decode_pic_begin = 0; |
10281 | slice_parse_begin = 0; | |
10282 | step = 0; | |
10283 | buf_alloc_size = 0; | |
10284 | #ifdef MULTI_INSTANCE_SUPPORT | |
10285 | if (platform_driver_register(&ammvdec_vp9_driver)) | |
10286 | pr_err("failed to register ammvdec_vp9 driver\n"); | |
10287 | ||
10288 | #endif | |
10289 | if (platform_driver_register(&amvdec_vp9_driver)) { | |
10290 | pr_err("failed to register amvdec_vp9 driver\n"); | |
10291 | return -ENODEV; | |
10292 | } | |
10293 | ||
6f5ee885 | 10294 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
e0e39311 | 10295 | amvdec_vp9_profile.profile = |
0eb79ad7 | 10296 | "8k, 10bit, dwrite, compressed, no_head"; |
e0e39311 | 10297 | } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL |
678a5126 JW |
10298 | /*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/ |
10299 | && get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TXL) { | |
0eb79ad7 RZ |
10300 | if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) { |
10301 | if (vdec_is_support_4k()) | |
10302 | amvdec_vp9_profile.profile = | |
10303 | "4k, 10bit, dwrite, compressed"; | |
10304 | else | |
10305 | amvdec_vp9_profile.profile = | |
10306 | "10bit, dwrite, compressed"; | |
10307 | } else { | |
10308 | if (vdec_is_support_4k()) | |
10309 | amvdec_vp9_profile.profile = | |
10310 | "4k, 10bit, dwrite, compressed, no_head"; | |
10311 | else | |
10312 | amvdec_vp9_profile.profile = | |
10313 | "10bit, dwrite, compressed, no_head"; | |
10314 | } | |
10315 | ||
b9164398 NQ |
10316 | } else { |
10317 | amvdec_vp9_profile.name = "vp9_unsupport"; | |
10318 | } | |
10319 | ||
c4ea7ef3 | 10320 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) |
dfe41deb | 10321 | max_buf_num = MAX_BUF_NUM_LESS; |
c4ea7ef3 | 10322 | |
b9164398 | 10323 | vcodec_profile_register(&amvdec_vp9_profile); |
9457f9af NQ |
10324 | amvdec_vp9_profile_mult = amvdec_vp9_profile; |
10325 | amvdec_vp9_profile_mult.name = "mvp9"; | |
10326 | vcodec_profile_register(&amvdec_vp9_profile_mult); | |
fe96802b NQ |
10327 | INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node, |
10328 | "vp9", vp9_configs, CONFIG_FOR_RW); | |
b9164398 NQ |
10329 | |
10330 | return 0; | |
10331 | } | |
10332 | ||
10333 | static void __exit amvdec_vp9_driver_remove_module(void) | |
10334 | { | |
10335 | pr_debug("amvdec_vp9 module remove.\n"); | |
10336 | #ifdef MULTI_INSTANCE_SUPPORT | |
10337 | platform_driver_unregister(&ammvdec_vp9_driver); | |
10338 | #endif | |
10339 | platform_driver_unregister(&amvdec_vp9_driver); | |
10340 | } | |
10341 | ||
10342 | /****************************************/ | |
b9164398 NQ |
10343 | |
10344 | module_param(bit_depth_luma, uint, 0664); | |
10345 | MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n"); | |
10346 | ||
10347 | module_param(bit_depth_chroma, uint, 0664); | |
10348 | MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n"); | |
10349 | ||
10350 | module_param(frame_width, uint, 0664); | |
10351 | MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n"); | |
10352 | ||
10353 | module_param(frame_height, uint, 0664); | |
10354 | MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n"); | |
10355 | ||
10356 | module_param(debug, uint, 0664); | |
10357 | MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n"); | |
10358 | ||
10359 | module_param(radr, uint, 0664); | |
fe96802b | 10360 | MODULE_PARM_DESC(radr, "\n radr\n"); |
b9164398 NQ |
10361 | |
10362 | module_param(rval, uint, 0664); | |
fe96802b | 10363 | MODULE_PARM_DESC(rval, "\n rval\n"); |
b9164398 NQ |
10364 | |
10365 | module_param(pop_shorts, uint, 0664); | |
fe96802b | 10366 | MODULE_PARM_DESC(pop_shorts, "\n rval\n"); |
b9164398 NQ |
10367 | |
10368 | module_param(dbg_cmd, uint, 0664); | |
fe96802b | 10369 | MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n"); |
b9164398 NQ |
10370 | |
10371 | module_param(dbg_skip_decode_index, uint, 0664); | |
fe96802b | 10372 | MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n"); |
b9164398 NQ |
10373 | |
10374 | module_param(endian, uint, 0664); | |
fe96802b | 10375 | MODULE_PARM_DESC(endian, "\n rval\n"); |
b9164398 NQ |
10376 | |
10377 | module_param(step, uint, 0664); | |
10378 | MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n"); | |
10379 | ||
b9164398 NQ |
10380 | module_param(decode_pic_begin, uint, 0664); |
10381 | MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n"); | |
10382 | ||
10383 | module_param(slice_parse_begin, uint, 0664); | |
10384 | MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n"); | |
10385 | ||
10386 | module_param(i_only_flag, uint, 0664); | |
10387 | MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n"); | |
10388 | ||
187af067 | 10389 | module_param(low_latency_flag, uint, 0664); |
10390 | MODULE_PARM_DESC(low_latency_flag, "\n amvdec_vp9 low_latency_flag\n"); | |
10391 | ||
0eb79ad7 RZ |
10392 | module_param(no_head, uint, 0664); |
10393 | MODULE_PARM_DESC(no_head, "\n amvdec_vp9 no_head\n"); | |
10394 | ||
b9164398 NQ |
10395 | module_param(error_handle_policy, uint, 0664); |
10396 | MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n"); | |
10397 | ||
10398 | module_param(buf_alloc_width, uint, 0664); | |
10399 | MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n"); | |
10400 | ||
10401 | module_param(buf_alloc_height, uint, 0664); | |
10402 | MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n"); | |
10403 | ||
10404 | module_param(buf_alloc_depth, uint, 0664); | |
10405 | MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n"); | |
10406 | ||
10407 | module_param(buf_alloc_size, uint, 0664); | |
10408 | MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n"); | |
10409 | ||
10410 | module_param(buffer_mode, uint, 0664); | |
10411 | MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n"); | |
10412 | ||
10413 | module_param(buffer_mode_dbg, uint, 0664); | |
10414 | MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n"); | |
10415 | /*USE_BUF_BLOCK*/ | |
dfe41deb RZ |
10416 | module_param(max_buf_num, uint, 0664); |
10417 | MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n"); | |
10418 | ||
b9164398 NQ |
10419 | module_param(dynamic_buf_num_margin, uint, 0664); |
10420 | MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n"); | |
fe96802b NQ |
10421 | |
10422 | module_param(mv_buf_margin, uint, 0664); | |
10423 | MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n"); | |
10424 | ||
10425 | module_param(run_ready_min_buf_num, uint, 0664); | |
10426 | MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n"); | |
10427 | ||
b9164398 NQ |
10428 | /**/ |
10429 | ||
10430 | module_param(mem_map_mode, uint, 0664); | |
10431 | MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n"); | |
10432 | ||
10433 | #ifdef SUPPORT_10BIT | |
10434 | module_param(double_write_mode, uint, 0664); | |
10435 | MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n"); | |
10436 | ||
10437 | module_param(enable_mem_saving, uint, 0664); | |
10438 | MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n"); | |
10439 | ||
10440 | module_param(force_w_h, uint, 0664); | |
10441 | MODULE_PARM_DESC(force_w_h, "\n force_w_h\n"); | |
10442 | #endif | |
10443 | ||
10444 | module_param(force_fps, uint, 0664); | |
10445 | MODULE_PARM_DESC(force_fps, "\n force_fps\n"); | |
10446 | ||
10447 | module_param(max_decoding_time, uint, 0664); | |
10448 | MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n"); | |
10449 | ||
10450 | module_param(on_no_keyframe_skiped, uint, 0664); | |
10451 | MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n"); | |
10452 | ||
c23e8aee HZ |
10453 | module_param(mcrcc_cache_alg_flag, uint, 0664); |
10454 | MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n"); | |
10455 | ||
b9164398 | 10456 | #ifdef MULTI_INSTANCE_SUPPORT |
fe96802b | 10457 | module_param(start_decode_buf_level, int, 0664); |
b9164398 | 10458 | MODULE_PARM_DESC(start_decode_buf_level, |
fe96802b NQ |
10459 | "\n vp9 start_decode_buf_level\n"); |
10460 | ||
10461 | module_param(decode_timeout_val, uint, 0664); | |
10462 | MODULE_PARM_DESC(decode_timeout_val, | |
10463 | "\n vp9 decode_timeout_val\n"); | |
10464 | ||
a6c89e96 NQ |
10465 | module_param(vp9_max_pic_w, uint, 0664); |
10466 | MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n"); | |
10467 | ||
10468 | module_param(vp9_max_pic_h, uint, 0664); | |
10469 | MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n"); | |
10470 | ||
fe96802b NQ |
10471 | module_param_array(decode_frame_count, uint, |
10472 | &max_decode_instance_num, 0664); | |
10473 | ||
10474 | module_param_array(display_frame_count, uint, | |
10475 | &max_decode_instance_num, 0664); | |
10476 | ||
10477 | module_param_array(max_process_time, uint, | |
10478 | &max_decode_instance_num, 0664); | |
10479 | ||
10480 | module_param_array(run_count, uint, | |
10481 | &max_decode_instance_num, 0664); | |
10482 | ||
10483 | module_param_array(input_empty, uint, | |
10484 | &max_decode_instance_num, 0664); | |
10485 | ||
10486 | module_param_array(not_run_ready, uint, | |
10487 | &max_decode_instance_num, 0664); | |
b9164398 NQ |
10488 | #endif |
10489 | ||
a6c89e96 NQ |
10490 | #ifdef SUPPORT_FB_DECODING |
10491 | module_param_array(not_run2_ready, uint, | |
10492 | &max_decode_instance_num, 0664); | |
10493 | ||
10494 | module_param_array(run2_count, uint, | |
10495 | &max_decode_instance_num, 0664); | |
10496 | ||
10497 | module_param(stage_buf_num, uint, 0664); | |
10498 | MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n"); | |
10499 | #endif | |
10500 | ||
fe96802b NQ |
10501 | module_param(udebug_flag, uint, 0664); |
10502 | MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n"); | |
10503 | ||
10504 | module_param(udebug_pause_pos, uint, 0664); | |
10505 | MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n"); | |
10506 | ||
10507 | module_param(udebug_pause_val, uint, 0664); | |
10508 | MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n"); | |
10509 | ||
10510 | module_param(udebug_pause_decode_idx, uint, 0664); | |
10511 | MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n"); | |
10512 | ||
b9164398 NQ |
10513 | module_init(amvdec_vp9_driver_init_module); |
10514 | module_exit(amvdec_vp9_driver_remove_module); | |
10515 | ||
10516 | MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver"); | |
10517 | MODULE_LICENSE("GPL"); | |
a6c89e96 | 10518 |