Commit | Line | Data |
---|---|---|
b9164398 | 1 | /* |
e0614bf7 ZZ |
2 | * drivers/amlogic/amports/vvp9.c |
3 | * | |
4 | * Copyright (C) 2015 Amlogic, Inc. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | */ | |
5b851ff9 | 17 | #define DEBUG |
b9164398 NQ |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/types.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/semaphore.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/timer.h> | |
26 | #include <linux/kfifo.h> | |
27 | #include <linux/kthread.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/amlogic/media/vfm/vframe.h> | |
31 | #include <linux/amlogic/media/utils/amstream.h> | |
32 | #include <linux/amlogic/media/utils/vformat.h> | |
33 | #include <linux/amlogic/media/frame_sync/ptsserv.h> | |
34 | #include <linux/amlogic/media/canvas/canvas.h> | |
35 | #include <linux/amlogic/media/vfm/vframe_provider.h> | |
36 | #include <linux/amlogic/media/vfm/vframe_receiver.h> | |
37 | #include <linux/dma-mapping.h> | |
38 | #include <linux/dma-contiguous.h> | |
39 | #include <linux/slab.h> | |
8f657ce9 | 40 | #include <linux/amlogic/tee.h> |
b9164398 NQ |
41 | #include "../../../stream_input/amports/amports_priv.h" |
42 | #include <linux/amlogic/media/codec_mm/codec_mm.h> | |
43 | #include "../utils/decoder_mmu_box.h" | |
44 | #include "../utils/decoder_bmmu_box.h" | |
45 | ||
46 | #define MEM_NAME "codec_vp9" | |
47 | /* #include <mach/am_regs.h> */ | |
48 | #include <linux/amlogic/media/utils/vdec_reg.h> | |
49 | #include "../utils/vdec.h" | |
50 | #include "../utils/amvdec.h" | |
187af067 | 51 | #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC |
52 | #include "../utils/vdec_profile.h" | |
53 | #endif | |
b9164398 NQ |
54 | |
55 | #include <linux/amlogic/media/video_sink/video.h> | |
fe96802b NQ |
56 | #include <linux/amlogic/media/codec_mm/configs.h> |
57 | #include "../utils/config_parser.h" | |
6fff1c64 | 58 | #include "../utils/firmware.h" |
63e810c0 | 59 | #include "../../../common/chips/decoder_cpu_ver_info.h" |
0fb7e163 | 60 | #include "../utils/vdec_v4l2_buffer_ops.h" |
71979acf | 61 | #include <media/v4l2-mem2mem.h> |
a093654a | 62 | |
b9164398 | 63 | #define MIX_STREAM_SUPPORT |
b9164398 NQ |
64 | |
65 | #include "vvp9.h" | |
a6c89e96 | 66 | |
b7706e1e | 67 | |
a6c89e96 NQ |
68 | /*#define SUPPORT_FB_DECODING*/ |
69 | /*#define FB_DECODING_TEST_SCHEDULE*/ | |
b7706e1e | 70 | |
a6c89e96 NQ |
71 | |
72 | #define HW_MASK_FRONT 0x1 | |
73 | #define HW_MASK_BACK 0x2 | |
74 | ||
b9164398 NQ |
75 | #define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442 |
76 | #define VP9D_MPP_REFINFO_DATA 0x3443 | |
77 | #define VP9D_MPP_REF_SCALE_ENBL 0x3441 | |
78 | #define HEVC_MPRED_CTRL4 0x324c | |
79 | #define HEVC_CM_HEADER_START_ADDR 0x3628 | |
80 | #define HEVC_DBLK_CFGB 0x350b | |
81 | #define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464 | |
82 | #define HEVC_SAO_MMU_VH1_ADDR 0x363b | |
83 | #define HEVC_SAO_MMU_VH0_ADDR 0x363a | |
b9164398 | 84 | |
ac678990 NQ |
85 | #define HEVC_MV_INFO 0x310d |
86 | #define HEVC_QP_INFO 0x3137 | |
87 | #define HEVC_SKIP_INFO 0x3136 | |
88 | ||
b9164398 NQ |
89 | #define VP9_10B_DEC_IDLE 0 |
90 | #define VP9_10B_DEC_FRAME_HEADER 1 | |
91 | #define VP9_10B_DEC_SLICE_SEGMENT 2 | |
92 | #define VP9_10B_DECODE_SLICE 5 | |
93 | #define VP9_10B_DISCARD_NAL 6 | |
94 | #define VP9_DUMP_LMEM 7 | |
95 | #define HEVC_DECPIC_DATA_DONE 0xa | |
96 | #define HEVC_DECPIC_DATA_ERROR 0xb | |
97 | #define HEVC_NAL_DECODE_DONE 0xe | |
98 | #define HEVC_DECODE_BUFEMPTY 0x20 | |
99 | #define HEVC_DECODE_TIMEOUT 0x21 | |
100 | #define HEVC_SEARCH_BUFEMPTY 0x22 | |
fe96802b | 101 | #define HEVC_DECODE_OVER_SIZE 0x23 |
a6c89e96 | 102 | #define HEVC_S2_DECODING_DONE 0x50 |
b9164398 NQ |
103 | #define VP9_HEAD_PARSER_DONE 0xf0 |
104 | #define VP9_HEAD_SEARCH_DONE 0xf1 | |
105 | #define VP9_EOS 0xf2 | |
106 | #define HEVC_ACTION_DONE 0xff | |
107 | ||
b9164398 NQ |
108 | #define VF_POOL_SIZE 32 |
109 | ||
110 | #undef pr_info | |
111 | #define pr_info printk | |
112 | ||
a6c89e96 NQ |
113 | #define DECODE_MODE_SINGLE ((0x80 << 24) | 0) |
114 | #define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1) | |
115 | #define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2) | |
187af067 | 116 | #define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3) |
0eb79ad7 | 117 | #define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4) |
c23e8aee HZ |
118 | |
119 | #define VP9_TRIGGER_FRAME_DONE 0x100 | |
120 | #define VP9_TRIGGER_FRAME_ENABLE 0x200 | |
121 | ||
fe96802b | 122 | #define MV_MEM_UNIT 0x240 |
b9164398 | 123 | /*--------------------------------------------------- |
e0614bf7 ZZ |
124 | * Include "parser_cmd.h" |
125 | *--------------------------------------------------- | |
126 | */ | |
b9164398 NQ |
127 | #define PARSER_CMD_SKIP_CFG_0 0x0000090b |
128 | ||
129 | #define PARSER_CMD_SKIP_CFG_1 0x1b14140f | |
130 | ||
131 | #define PARSER_CMD_SKIP_CFG_2 0x001b1910 | |
132 | ||
133 | #define PARSER_CMD_NUMBER 37 | |
134 | ||
b9164398 NQ |
135 | /*#define HEVC_PIC_STRUCT_SUPPORT*/ |
136 | /* to remove, fix build error */ | |
137 | ||
138 | /*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/ | |
139 | ||
140 | #define MULTI_INSTANCE_SUPPORT | |
141 | #define SUPPORT_10BIT | |
142 | /* #define ERROR_HANDLE_DEBUG */ | |
b9164398 NQ |
143 | |
144 | #ifndef STAT_KTHREAD | |
145 | #define STAT_KTHREAD 0x40 | |
146 | #endif | |
147 | ||
148 | #ifdef MULTI_INSTANCE_SUPPORT | |
a674e3cd | 149 | #define MAX_DECODE_INSTANCE_NUM 9 |
b9164398 | 150 | #define MULTI_DRIVER_NAME "ammvdec_vp9" |
fe96802b NQ |
151 | static unsigned int max_decode_instance_num |
152 | = MAX_DECODE_INSTANCE_NUM; | |
153 | static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM]; | |
154 | static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM]; | |
155 | static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM]; | |
156 | static unsigned int run_count[MAX_DECODE_INSTANCE_NUM]; | |
157 | static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM]; | |
158 | static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM]; | |
159 | ||
160 | static u32 decode_timeout_val = 200; | |
161 | static int start_decode_buf_level = 0x8000; | |
b7706e1e | 162 | static u32 work_buf_size; |
b9164398 | 163 | |
65ad8202 GZ |
164 | static u32 force_pts_unstable; |
165 | ||
fe96802b NQ |
166 | static u32 mv_buf_margin; |
167 | ||
168 | /* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */ | |
33d1149b | 169 | /* double_write_mode: |
170 | * 0, no double write; | |
171 | * 1, 1:1 ratio; | |
172 | * 2, (1/4):(1/4) ratio; | |
173 | * 3, (1/4):(1/4) ratio, with both compressed frame included | |
174 | * 4, (1/2):(1/2) ratio; | |
175 | * 0x10, double write only | |
176 | * 0x100, if > 1080p,use mode 4,else use mode 1; | |
177 | * 0x200, if > 1080p,use mode 2,else use mode 1; | |
178 | * 0x300, if > 720p, use mode 4, else use mode 1; | |
179 | */ | |
fe96802b NQ |
180 | static u32 double_write_mode; |
181 | ||
b9164398 NQ |
182 | #define DRIVER_NAME "amvdec_vp9" |
183 | #define MODULE_NAME "amvdec_vp9" | |
fe96802b NQ |
184 | #define DRIVER_HEADER_NAME "amvdec_vp9_header" |
185 | ||
b9164398 NQ |
186 | |
187 | #define PUT_INTERVAL (HZ/100) | |
188 | #define ERROR_SYSTEM_RESET_COUNT 200 | |
189 | ||
190 | #define PTS_NORMAL 0 | |
191 | #define PTS_NONE_REF_USE_DURATION 1 | |
192 | ||
193 | #define PTS_MODE_SWITCHING_THRESHOLD 3 | |
194 | #define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3 | |
195 | ||
196 | #define DUR2PTS(x) ((x)*90/96) | |
197 | ||
198 | struct VP9Decoder_s; | |
199 | static int vvp9_vf_states(struct vframe_states *states, void *); | |
200 | static struct vframe_s *vvp9_vf_peek(void *); | |
201 | static struct vframe_s *vvp9_vf_get(void *); | |
202 | static void vvp9_vf_put(struct vframe_s *, void *); | |
203 | static int vvp9_event_cb(int type, void *data, void *private_data); | |
204 | ||
205 | static int vvp9_stop(struct VP9Decoder_s *pbi); | |
c23e8aee HZ |
206 | #ifdef MULTI_INSTANCE_SUPPORT |
207 | static s32 vvp9_init(struct vdec_s *vdec); | |
208 | #else | |
b9164398 | 209 | static s32 vvp9_init(struct VP9Decoder_s *pbi); |
c23e8aee | 210 | #endif |
a6c89e96 | 211 | static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask); |
b9164398 NQ |
212 | static int vvp9_local_init(struct VP9Decoder_s *pbi); |
213 | static void vvp9_put_timer_func(unsigned long arg); | |
fe96802b NQ |
214 | static void dump_data(struct VP9Decoder_s *pbi, int size); |
215 | static unsigned char get_data_check_sum | |
216 | (struct VP9Decoder_s *pbi, int size); | |
217 | static void dump_pic_list(struct VP9Decoder_s *pbi); | |
b9164398 NQ |
218 | static int vp9_alloc_mmu( |
219 | struct VP9Decoder_s *pbi, | |
220 | int cur_buf_idx, | |
221 | int pic_width, | |
222 | int pic_height, | |
223 | unsigned short bit_depth, | |
224 | unsigned int *mmu_index_adr); | |
b7706e1e | 225 | |
b9164398 NQ |
226 | |
227 | static const char vvp9_dec_id[] = "vvp9-dev"; | |
228 | ||
229 | #define PROVIDER_NAME "decoder.vp9" | |
230 | #define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9" | |
231 | ||
232 | static const struct vframe_operations_s vvp9_vf_provider = { | |
233 | .peek = vvp9_vf_peek, | |
234 | .get = vvp9_vf_get, | |
235 | .put = vvp9_vf_put, | |
236 | .event_cb = vvp9_event_cb, | |
237 | .vf_states = vvp9_vf_states, | |
238 | }; | |
239 | ||
240 | static struct vframe_provider_s vvp9_vf_prov; | |
241 | ||
242 | static u32 bit_depth_luma; | |
243 | static u32 bit_depth_chroma; | |
244 | static u32 frame_width; | |
245 | static u32 frame_height; | |
246 | static u32 video_signal_type; | |
976f3376 | 247 | |
b9164398 NQ |
248 | static u32 on_no_keyframe_skiped; |
249 | ||
b9164398 NQ |
250 | #define PROB_SIZE (496 * 2 * 4) |
251 | #define PROB_BUF_SIZE (0x5000) | |
252 | #define COUNT_BUF_SIZE (0x300 * 4 * 4) | |
253 | /*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/ | |
254 | #define MAX_FRAME_4K_NUM 0x1200 | |
e0e39311 | 255 | #define MAX_FRAME_8K_NUM 0x4800 |
b9164398 | 256 | |
a6c89e96 NQ |
257 | #define HEVC_ASSIST_MMU_MAP_ADDR 0x3009 |
258 | ||
259 | #ifdef SUPPORT_FB_DECODING | |
260 | /* register define */ | |
261 | #define HEVC_ASSIST_HED_FB_W_CTL 0x3006 | |
262 | #define HEVC_ASSIST_HED_FB_R_CTL 0x3007 | |
263 | #define HEVC_ASSIST_HED_FB_ADDR 0x3008 | |
264 | #define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a | |
265 | #define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b | |
266 | ||
267 | ||
268 | #define MAX_STAGE_PAGE_NUM 0x1200 | |
269 | #define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4) | |
270 | #endif | |
b9164398 NQ |
271 | static inline int div_r32(int64_t m, int n) |
272 | { | |
273 | /* | |
e0614bf7 ZZ |
274 | *return (int)(m/n) |
275 | */ | |
b9164398 | 276 | #ifndef CONFIG_ARM64 |
ddcb7dca LC |
277 | int64_t qu = 0; |
278 | qu = div_s64(m, n); | |
279 | return (int)qu; | |
b9164398 NQ |
280 | #else |
281 | return (int)(m/n); | |
282 | #endif | |
283 | } | |
284 | ||
285 | /*USE_BUF_BLOCK*/ | |
286 | struct BUF_s { | |
287 | int index; | |
288 | unsigned int alloc_flag; | |
289 | /*buffer */ | |
290 | unsigned int cma_page_count; | |
291 | unsigned long alloc_addr; | |
292 | unsigned long start_adr; | |
293 | unsigned int size; | |
294 | ||
295 | unsigned int free_start_adr; | |
2cd6815e | 296 | ulong v4l_ref_buf_addr; |
75803959 NQ |
297 | ulong header_addr; |
298 | u32 header_size; | |
299 | u32 luma_size; | |
307badab NQ |
300 | ulong chroma_addr; |
301 | u32 chroma_size; | |
b9164398 NQ |
302 | } /*BUF_t */; |
303 | ||
fe96802b NQ |
304 | struct MVBUF_s { |
305 | unsigned long start_adr; | |
306 | unsigned int size; | |
307 | int used_flag; | |
308 | } /*MVBUF_t */; | |
b9164398 NQ |
309 | |
310 | /* #undef BUFMGR_ONLY to enable hardware configuration */ | |
311 | ||
312 | /*#define TEST_WR_PTR_INC*/ | |
df841122 | 313 | /*#define WR_PTR_INC_NUM 128*/ |
314 | #define WR_PTR_INC_NUM 1 | |
b9164398 NQ |
315 | |
316 | #define SIMULATION | |
317 | #define DOS_PROJECT | |
318 | #undef MEMORY_MAP_IN_REAL_CHIP | |
319 | ||
320 | /*#undef DOS_PROJECT*/ | |
321 | /*#define MEMORY_MAP_IN_REAL_CHIP*/ | |
322 | ||
323 | /*#define BUFFER_MGR_ONLY*/ | |
324 | /*#define CONFIG_HEVC_CLK_FORCED_ON*/ | |
325 | /*#define ENABLE_SWAP_TEST*/ | |
326 | #define MCRCC_ENABLE | |
327 | ||
b9164398 NQ |
328 | #define VP9_LPF_LVL_UPDATE |
329 | /*#define DBG_LF_PRINT*/ | |
330 | ||
331 | #ifdef VP9_10B_NV21 | |
332 | #else | |
333 | #define LOSLESS_COMPRESS_MODE | |
334 | #endif | |
335 | ||
336 | #define DOUBLE_WRITE_YSTART_TEMP 0x02000000 | |
337 | #define DOUBLE_WRITE_CSTART_TEMP 0x02900000 | |
338 | ||
339 | ||
340 | ||
341 | typedef unsigned int u32; | |
342 | typedef unsigned short u16; | |
343 | ||
344 | #define VP9_DEBUG_BUFMGR 0x01 | |
345 | #define VP9_DEBUG_BUFMGR_MORE 0x02 | |
fe96802b NQ |
346 | #define VP9_DEBUG_BUFMGR_DETAIL 0x04 |
347 | #define VP9_DEBUG_OUT_PTS 0x10 | |
b9164398 | 348 | #define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100 |
fe96802b | 349 | #define VP9_DEBUG_MERGE 0x200 |
b9164398 | 350 | #define VP9_DEBUG_DBG_LF_PRINT 0x400 |
fe96802b | 351 | #define VP9_DEBUG_REG 0x800 |
a6c89e96 NQ |
352 | #define VP9_DEBUG_2_STAGE 0x1000 |
353 | #define VP9_DEBUG_2_STAGE_MORE 0x2000 | |
ac678990 | 354 | #define VP9_DEBUG_QOS_INFO 0x4000 |
b9164398 NQ |
355 | #define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000 |
356 | #define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000 | |
357 | #define VP9_DEBUG_DUMP_PIC_LIST 0x40000 | |
358 | #define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000 | |
a6c89e96 | 359 | #define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000 |
b9164398 | 360 | #define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000 |
fe96802b NQ |
361 | #define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000 |
362 | #define VP9_DEBUG_DUMP_DATA 0x800000 | |
c23e8aee HZ |
363 | #define VP9_DEBUG_CACHE 0x1000000 |
364 | #define VP9_DEBUG_CACHE_HIT_RATE 0x2000000 | |
365 | #define IGNORE_PARAM_FROM_CONFIG 0x8000000 | |
b9164398 | 366 | #ifdef MULTI_INSTANCE_SUPPORT |
9495ddb6 NQ |
367 | #define PRINT_FLAG_ERROR 0x0 |
368 | #define PRINT_FLAG_V4L_DETAIL 0x10000000 | |
369 | #define PRINT_FLAG_VDEC_STATUS 0x20000000 | |
370 | #define PRINT_FLAG_VDEC_DETAIL 0x40000000 | |
371 | #define PRINT_FLAG_VDEC_DATA 0x80000000 | |
b9164398 NQ |
372 | #endif |
373 | ||
374 | static u32 debug; | |
d481db31 | 375 | static bool is_reset; |
fe96802b NQ |
376 | /*for debug*/ |
377 | /* | |
378 | udebug_flag: | |
379 | bit 0, enable ucode print | |
380 | bit 1, enable ucode detail print | |
381 | bit [31:16] not 0, pos to dump lmem | |
382 | bit 2, pop bits to lmem | |
383 | bit [11:8], pre-pop bits for alignment (when bit 2 is 1) | |
384 | */ | |
385 | static u32 udebug_flag; | |
386 | /* | |
387 | when udebug_flag[1:0] is not 0 | |
388 | udebug_pause_pos not 0, | |
389 | pause position | |
390 | */ | |
391 | static u32 udebug_pause_pos; | |
392 | /* | |
393 | when udebug_flag[1:0] is not 0 | |
394 | and udebug_pause_pos is not 0, | |
395 | pause only when DEBUG_REG2 is equal to this val | |
396 | */ | |
397 | static u32 udebug_pause_val; | |
398 | ||
399 | static u32 udebug_pause_decode_idx; | |
400 | ||
7c2956be PY |
401 | static u32 without_display_mode; |
402 | ||
677ab50d NQ |
403 | /* |
404 | *[3:0] 0: default use config from omx. | |
405 | * 1: force enable fence. | |
406 | * 2: disable fence. | |
407 | *[7:4] 0: fence use for driver. | |
408 | * 1: fence fd use for app. | |
409 | */ | |
410 | static u32 force_config_fence; | |
411 | ||
b9164398 NQ |
412 | #define DEBUG_REG |
413 | #ifdef DEBUG_REG | |
e0614bf7 | 414 | void WRITE_VREG_DBG2(unsigned int adr, unsigned int val) |
b9164398 NQ |
415 | { |
416 | if (debug & VP9_DEBUG_REG) | |
417 | pr_info("%s(%x, %x)\n", __func__, adr, val); | |
418 | if (adr != 0) | |
419 | WRITE_VREG(adr, val); | |
420 | } | |
421 | ||
422 | #undef WRITE_VREG | |
423 | #define WRITE_VREG WRITE_VREG_DBG2 | |
424 | #endif | |
425 | ||
c20e6c85 | 426 | #define FRAME_CNT_WINDOW_SIZE 59 |
427 | #define RATE_CORRECTION_THRESHOLD 5 | |
b9164398 | 428 | /************************************************** |
a6c89e96 NQ |
429 | |
430 | VP9 buffer management start | |
431 | ||
432 | ***************************************************/ | |
b7706e1e | 433 | |
b9164398 | 434 | #define MMU_COMPRESS_HEADER_SIZE 0x48000 |
df841122 | 435 | #define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4) |
e0e39311 | 436 | #define MAX_SIZE_8K (8192 * 4608) |
437 | #define MAX_SIZE_4K (4096 * 2304) | |
438 | #define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K) | |
b9164398 NQ |
439 | |
440 | #define INVALID_IDX -1 /* Invalid buffer index.*/ | |
441 | ||
442 | #define RPM_BEGIN 0x200 | |
443 | #define RPM_END 0x280 | |
444 | ||
445 | union param_u { | |
446 | struct { | |
447 | unsigned short data[RPM_END - RPM_BEGIN]; | |
448 | } l; | |
449 | struct { | |
450 | /* from ucode lmem, do not change this struct */ | |
451 | unsigned short profile; | |
452 | unsigned short show_existing_frame; | |
453 | unsigned short frame_to_show_idx; | |
454 | unsigned short frame_type; /*1 bit*/ | |
455 | unsigned short show_frame; /*1 bit*/ | |
456 | unsigned short error_resilient_mode; /*1 bit*/ | |
457 | unsigned short intra_only; /*1 bit*/ | |
458 | unsigned short display_size_present; /*1 bit*/ | |
459 | unsigned short reset_frame_context; | |
460 | unsigned short refresh_frame_flags; | |
461 | unsigned short width; | |
462 | unsigned short height; | |
463 | unsigned short display_width; | |
464 | unsigned short display_height; | |
465 | /* | |
e0614bf7 ZZ |
466 | *bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit)) |
467 | *bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit)) | |
468 | *bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit)) | |
469 | */ | |
b9164398 NQ |
470 | unsigned short ref_info; |
471 | /* | |
e0614bf7 ZZ |
472 | *bit[2]: same_frame_size0 |
473 | *bit[1]: same_frame_size1 | |
474 | *bit[0]: same_frame_size2 | |
475 | */ | |
b9164398 NQ |
476 | unsigned short same_frame_size; |
477 | ||
478 | unsigned short mode_ref_delta_enabled; | |
479 | unsigned short ref_deltas[4]; | |
480 | unsigned short mode_deltas[2]; | |
481 | unsigned short filter_level; | |
482 | unsigned short sharpness_level; | |
483 | unsigned short bit_depth; | |
484 | unsigned short seg_quant_info[8]; | |
485 | unsigned short seg_enabled; | |
486 | unsigned short seg_abs_delta; | |
487 | /* bit 15: feature enabled; bit 8, sign; bit[5:0], data */ | |
488 | unsigned short seg_lf_info[8]; | |
489 | } p; | |
490 | }; | |
491 | ||
492 | ||
493 | struct vpx_codec_frame_buffer_s { | |
494 | uint8_t *data; /**< Pointer to the data buffer */ | |
495 | size_t size; /**< Size of data in bytes */ | |
496 | void *priv; /**< Frame's private data */ | |
497 | }; | |
498 | ||
499 | enum vpx_color_space_t { | |
500 | VPX_CS_UNKNOWN = 0, /**< Unknown */ | |
501 | VPX_CS_BT_601 = 1, /**< BT.601 */ | |
502 | VPX_CS_BT_709 = 2, /**< BT.709 */ | |
503 | VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */ | |
504 | VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */ | |
505 | VPX_CS_BT_2020 = 5, /**< BT.2020 */ | |
506 | VPX_CS_RESERVED = 6, /**< Reserved */ | |
507 | VPX_CS_SRGB = 7 /**< sRGB */ | |
508 | }; /**< alias for enum vpx_color_space */ | |
509 | ||
510 | enum vpx_bit_depth_t { | |
511 | VPX_BITS_8 = 8, /**< 8 bits */ | |
512 | VPX_BITS_10 = 10, /**< 10 bits */ | |
513 | VPX_BITS_12 = 12, /**< 12 bits */ | |
514 | }; | |
515 | ||
516 | #define MAX_SLICE_NUM 1024 | |
517 | struct PIC_BUFFER_CONFIG_s { | |
518 | int index; | |
519 | int BUF_index; | |
fe96802b | 520 | int mv_buf_index; |
b9164398 NQ |
521 | int comp_body_size; |
522 | int buf_size; | |
523 | int vf_ref; | |
524 | int y_canvas_index; | |
525 | int uv_canvas_index; | |
526 | #ifdef MULTI_INSTANCE_SUPPORT | |
527 | struct canvas_config_s canvas_config[2]; | |
528 | #endif | |
529 | int decode_idx; | |
530 | int slice_type; | |
b9164398 | 531 | int stream_offset; |
fe96802b NQ |
532 | u32 pts; |
533 | u64 pts64; | |
0fb7e163 | 534 | u64 timestamp; |
b9164398 NQ |
535 | uint8_t error_mark; |
536 | /**/ | |
537 | int slice_idx; | |
538 | /*buffer*/ | |
b9164398 | 539 | unsigned long header_adr; |
b9164398 | 540 | unsigned long mpred_mv_wr_start_addr; |
b7706e1e | 541 | /*unsigned long mc_y_adr; |
542 | *unsigned long mc_u_v_adr; | |
543 | */ | |
b9164398 NQ |
544 | unsigned int dw_y_adr; |
545 | unsigned int dw_u_v_adr; | |
546 | int mc_canvas_y; | |
547 | int mc_canvas_u_v; | |
548 | ||
549 | int lcu_total; | |
550 | /**/ | |
551 | int y_width; | |
552 | int y_height; | |
553 | int y_crop_width; | |
554 | int y_crop_height; | |
555 | int y_stride; | |
556 | ||
557 | int uv_width; | |
558 | int uv_height; | |
559 | int uv_crop_width; | |
560 | int uv_crop_height; | |
561 | int uv_stride; | |
562 | ||
563 | int alpha_width; | |
564 | int alpha_height; | |
565 | int alpha_stride; | |
566 | ||
567 | uint8_t *y_buffer; | |
568 | uint8_t *u_buffer; | |
569 | uint8_t *v_buffer; | |
570 | uint8_t *alpha_buffer; | |
571 | ||
572 | uint8_t *buffer_alloc; | |
573 | int buffer_alloc_sz; | |
574 | int border; | |
575 | int frame_size; | |
576 | int subsampling_x; | |
577 | int subsampling_y; | |
578 | unsigned int bit_depth; | |
579 | enum vpx_color_space_t color_space; | |
580 | ||
581 | int corrupted; | |
582 | int flags; | |
583 | unsigned long cma_alloc_addr; | |
c23e8aee HZ |
584 | |
585 | int double_write_mode; | |
ac678990 NQ |
586 | |
587 | /* picture qos infomation*/ | |
588 | int max_qp; | |
589 | int avg_qp; | |
590 | int min_qp; | |
591 | int max_skip; | |
592 | int avg_skip; | |
593 | int min_skip; | |
594 | int max_mv; | |
595 | int min_mv; | |
596 | int avg_mv; | |
75803959 | 597 | |
cc41710a | 598 | u32 hw_decode_time; |
599 | u32 frame_size2; // For frame base mode | |
75803959 | 600 | bool vframe_bound; |
677ab50d NQ |
601 | |
602 | /* vdec sync. */ | |
603 | struct fence *fence; | |
8654f7f2 | 604 | |
605 | /* hdr10 plus data */ | |
606 | u32 hdr10p_data_size; | |
607 | char *hdr10p_data_buf; | |
b9164398 NQ |
608 | } PIC_BUFFER_CONFIG; |
609 | ||
610 | enum BITSTREAM_PROFILE { | |
611 | PROFILE_0, | |
612 | PROFILE_1, | |
613 | PROFILE_2, | |
614 | PROFILE_3, | |
615 | MAX_PROFILES | |
616 | }; | |
617 | ||
618 | enum FRAME_TYPE { | |
619 | KEY_FRAME = 0, | |
620 | INTER_FRAME = 1, | |
621 | FRAME_TYPES, | |
622 | }; | |
623 | ||
624 | enum REFERENCE_MODE { | |
625 | SINGLE_REFERENCE = 0, | |
626 | COMPOUND_REFERENCE = 1, | |
627 | REFERENCE_MODE_SELECT = 2, | |
628 | REFERENCE_MODES = 3, | |
629 | }; | |
630 | ||
631 | #define NONE -1 | |
632 | #define INTRA_FRAME 0 | |
633 | #define LAST_FRAME 1 | |
634 | #define GOLDEN_FRAME 2 | |
635 | #define ALTREF_FRAME 3 | |
636 | #define MAX_REF_FRAMES 4 | |
637 | ||
638 | #define REFS_PER_FRAME 3 | |
639 | ||
640 | #define REF_FRAMES_LOG2 3 | |
641 | #define REF_FRAMES (1 << REF_FRAMES_LOG2) | |
dfe41deb | 642 | #define REF_FRAMES_4K (6) |
b9164398 NQ |
643 | |
644 | /*4 scratch frames for the new frames to support a maximum of 4 cores decoding | |
e0614bf7 ZZ |
645 | *in parallel, 3 for scaled references on the encoder. |
646 | *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number | |
647 | * // of framebuffers. | |
648 | *TODO(jkoleszar): These 3 extra references could probably come from the | |
649 | *normal reference pool. | |
650 | */ | |
fe96802b NQ |
651 | #define FRAME_BUFFERS (REF_FRAMES + 16) |
652 | #define HEADER_FRAME_BUFFERS (FRAME_BUFFERS) | |
653 | #define MAX_BUF_NUM (FRAME_BUFFERS) | |
a6c89e96 NQ |
654 | #define MV_BUFFER_NUM FRAME_BUFFERS |
655 | #ifdef SUPPORT_FB_DECODING | |
656 | #define STAGE_MAX_BUFFERS 16 | |
657 | #else | |
658 | #define STAGE_MAX_BUFFERS 0 | |
659 | #endif | |
b9164398 NQ |
660 | |
661 | #define FRAME_CONTEXTS_LOG2 2 | |
662 | #define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2) | |
fe96802b NQ |
663 | /*buffer + header buffer + workspace*/ |
664 | #ifdef MV_USE_FIXED_BUF | |
665 | #define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1) | |
666 | #define VF_BUFFER_IDX(n) (n) | |
667 | #define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n) | |
668 | #define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS) | |
669 | #else | |
a6c89e96 NQ |
670 | #define MAX_BMMU_BUFFER_NUM \ |
671 | (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1) | |
fe96802b NQ |
672 | #define VF_BUFFER_IDX(n) (n) |
673 | #define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n) | |
a6c89e96 NQ |
674 | #define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n) |
675 | #define WORK_SPACE_BUF_ID \ | |
676 | (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM) | |
fe96802b | 677 | #endif |
b9164398 NQ |
678 | |
679 | struct RefCntBuffer_s { | |
680 | int ref_count; | |
681 | /*MV_REF *mvs;*/ | |
682 | int mi_rows; | |
683 | int mi_cols; | |
684 | struct vpx_codec_frame_buffer_s raw_frame_buffer; | |
685 | struct PIC_BUFFER_CONFIG_s buf; | |
686 | ||
687 | /*The Following variables will only be used in frame parallel decode. | |
e0614bf7 ZZ |
688 | * |
689 | *frame_worker_owner indicates which FrameWorker owns this buffer. NULL means | |
690 | *that no FrameWorker owns, or is decoding, this buffer. | |
691 | *VP9Worker *frame_worker_owner; | |
692 | * | |
693 | *row and col indicate which position frame has been decoded to in real | |
694 | *pixel unit. They are reset to -1 when decoding begins and set to INT_MAX | |
695 | *when the frame is fully decoded. | |
696 | */ | |
b9164398 NQ |
697 | int row; |
698 | int col; | |
699 | } RefCntBuffer; | |
700 | ||
701 | struct RefBuffer_s { | |
702 | /*TODO(dkovalev): idx is not really required and should be removed, now it | |
e0614bf7 ZZ |
703 | *is used in vp9_onyxd_if.c |
704 | */ | |
b9164398 NQ |
705 | int idx; |
706 | struct PIC_BUFFER_CONFIG_s *buf; | |
707 | /*struct scale_factors sf;*/ | |
708 | } RefBuffer; | |
709 | ||
710 | struct InternalFrameBuffer_s { | |
711 | uint8_t *data; | |
712 | size_t size; | |
713 | int in_use; | |
714 | } InternalFrameBuffer; | |
715 | ||
716 | struct InternalFrameBufferList_s { | |
717 | int num_internal_frame_buffers; | |
718 | struct InternalFrameBuffer_s *int_fb; | |
719 | } InternalFrameBufferList; | |
720 | ||
721 | struct BufferPool_s { | |
722 | /*Protect BufferPool from being accessed by several FrameWorkers at | |
e0614bf7 ZZ |
723 | *the same time during frame parallel decode. |
724 | *TODO(hkuang): Try to use atomic variable instead of locking the whole pool. | |
725 | * | |
726 | *Private data associated with the frame buffer callbacks. | |
727 | *void *cb_priv; | |
728 | * | |
729 | *vpx_get_frame_buffer_cb_fn_t get_fb_cb; | |
730 | *vpx_release_frame_buffer_cb_fn_t release_fb_cb; | |
731 | */ | |
b9164398 NQ |
732 | |
733 | struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS]; | |
734 | ||
735 | /*Frame buffers allocated internally by the codec.*/ | |
736 | struct InternalFrameBufferList_s int_frame_buffers; | |
737 | unsigned long flags; | |
738 | spinlock_t lock; | |
739 | ||
740 | } BufferPool; | |
741 | ||
fe96802b NQ |
742 | #define lock_buffer_pool(pool, flags) \ |
743 | spin_lock_irqsave(&pool->lock, flags) | |
744 | ||
745 | #define unlock_buffer_pool(pool, flags) \ | |
746 | spin_unlock_irqrestore(&pool->lock, flags) | |
b9164398 NQ |
747 | |
748 | struct VP9_Common_s { | |
749 | enum vpx_color_space_t color_space; | |
750 | int width; | |
751 | int height; | |
752 | int display_width; | |
753 | int display_height; | |
754 | int last_width; | |
755 | int last_height; | |
756 | ||
757 | int subsampling_x; | |
758 | int subsampling_y; | |
759 | ||
760 | int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/ | |
761 | ||
762 | struct PIC_BUFFER_CONFIG_s *frame_to_show; | |
763 | struct RefCntBuffer_s *prev_frame; | |
764 | ||
765 | /*TODO(hkuang): Combine this with cur_buf in macroblockd.*/ | |
766 | struct RefCntBuffer_s *cur_frame; | |
767 | ||
768 | int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */ | |
769 | ||
770 | /*Prepare ref_frame_map for the next frame. | |
e0614bf7 ZZ |
771 | *Only used in frame parallel decode. |
772 | */ | |
b9164398 NQ |
773 | int next_ref_frame_map[REF_FRAMES]; |
774 | ||
775 | /* TODO(jkoleszar): could expand active_ref_idx to 4, | |
e0614bf7 ZZ |
776 | *with 0 as intra, and roll new_fb_idx into it. |
777 | */ | |
b9164398 NQ |
778 | |
779 | /*Each frame can reference REFS_PER_FRAME buffers*/ | |
780 | struct RefBuffer_s frame_refs[REFS_PER_FRAME]; | |
781 | ||
782 | int prev_fb_idx; | |
783 | int new_fb_idx; | |
fe96802b | 784 | int cur_fb_idx_mmu; |
b9164398 NQ |
785 | /*last frame's frame type for motion search*/ |
786 | enum FRAME_TYPE last_frame_type; | |
787 | enum FRAME_TYPE frame_type; | |
788 | ||
789 | int show_frame; | |
790 | int last_show_frame; | |
791 | int show_existing_frame; | |
792 | ||
793 | /*Flag signaling that the frame is encoded using only INTRA modes.*/ | |
794 | uint8_t intra_only; | |
795 | uint8_t last_intra_only; | |
796 | ||
797 | int allow_high_precision_mv; | |
798 | ||
799 | /*Flag signaling that the frame context should be reset to default | |
e0614bf7 ZZ |
800 | *values. 0 or 1 implies don't reset, 2 reset just the context |
801 | *specified in the frame header, 3 reset all contexts. | |
802 | */ | |
b9164398 NQ |
803 | int reset_frame_context; |
804 | ||
805 | /*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in | |
e0614bf7 ZZ |
806 | * MODE_INFO (8-pixel) units. |
807 | */ | |
b9164398 NQ |
808 | int MBs; |
809 | int mb_rows, mi_rows; | |
810 | int mb_cols, mi_cols; | |
811 | int mi_stride; | |
812 | ||
813 | /*Whether to use previous frame's motion vectors for prediction.*/ | |
814 | int use_prev_frame_mvs; | |
815 | ||
816 | int refresh_frame_context; /* Two state 0 = NO, 1 = YES */ | |
817 | ||
818 | int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */ | |
819 | ||
820 | /*struct loopfilter lf;*/ | |
821 | /*struct segmentation seg;*/ | |
822 | ||
823 | /*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/ | |
824 | /* in pbi.*/ | |
825 | int frame_parallel_decode; /* frame-based threading.*/ | |
826 | ||
827 | /*Context probabilities for reference frame prediction*/ | |
828 | /*MV_REFERENCE_FRAME comp_fixed_ref;*/ | |
829 | /*MV_REFERENCE_FRAME comp_var_ref[2];*/ | |
830 | enum REFERENCE_MODE reference_mode; | |
831 | ||
832 | /*FRAME_CONTEXT *fc; */ /* this frame entropy */ | |
833 | /*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/ | |
834 | /*unsigned int frame_context_idx; *//* Context to use/update */ | |
835 | /*FRAME_COUNTS counts;*/ | |
836 | ||
837 | unsigned int current_video_frame; | |
838 | enum BITSTREAM_PROFILE profile; | |
839 | ||
840 | enum vpx_bit_depth_t bit_depth; | |
841 | ||
842 | int error_resilient_mode; | |
843 | int frame_parallel_decoding_mode; | |
844 | ||
845 | int byte_alignment; | |
846 | int skip_loop_filter; | |
847 | ||
848 | /*External BufferPool passed from outside.*/ | |
849 | struct BufferPool_s *buffer_pool; | |
850 | ||
851 | int above_context_alloc_cols; | |
852 | ||
b7706e1e | 853 | }; |
b9164398 | 854 | |
fe96802b NQ |
855 | static void set_canvas(struct VP9Decoder_s *pbi, |
856 | struct PIC_BUFFER_CONFIG_s *pic_config); | |
b9164398 NQ |
857 | static int prepare_display_buf(struct VP9Decoder_s *pbi, |
858 | struct PIC_BUFFER_CONFIG_s *pic_config); | |
b9164398 | 859 | |
ac678990 NQ |
860 | static void fill_frame_info(struct VP9Decoder_s *pbi, |
861 | struct PIC_BUFFER_CONFIG_s *frame, | |
862 | unsigned int framesize, | |
863 | unsigned int pts); | |
864 | ||
b9164398 NQ |
865 | static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm) |
866 | { | |
867 | return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf; | |
868 | } | |
869 | ||
870 | static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx) | |
871 | { | |
872 | const int ref_index = *idx; | |
873 | ||
874 | if (ref_index >= 0 && bufs[ref_index].ref_count > 0) { | |
875 | bufs[ref_index].ref_count--; | |
876 | /*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n", | |
e0614bf7 ZZ |
877 | * ref_index, bufs[ref_index].ref_count); |
878 | */ | |
b9164398 NQ |
879 | } |
880 | ||
881 | *idx = new_idx; | |
882 | ||
883 | bufs[new_idx].ref_count++; | |
884 | /*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n", | |
e0614bf7 ZZ |
885 | * new_idx, bufs[new_idx].ref_count); |
886 | */ | |
b9164398 NQ |
887 | } |
888 | ||
889 | int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb) | |
890 | { | |
891 | struct InternalFrameBuffer_s *const int_fb = | |
892 | (struct InternalFrameBuffer_s *)fb->priv; | |
893 | if (int_fb) | |
894 | int_fb->in_use = 0; | |
895 | return 0; | |
896 | } | |
897 | ||
898 | static int compute_losless_comp_body_size(int width, int height, | |
899 | uint8_t is_bit_depth_10); | |
900 | ||
901 | static void setup_display_size(struct VP9_Common_s *cm, union param_u *params, | |
902 | int print_header_info) | |
903 | { | |
904 | cm->display_width = cm->width; | |
905 | cm->display_height = cm->height; | |
906 | if (params->p.display_size_present) { | |
907 | if (print_header_info) | |
908 | pr_info(" * 1-bit display_size_present read : 1\n"); | |
909 | cm->display_width = params->p.display_width; | |
910 | cm->display_height = params->p.display_height; | |
911 | /*vp9_read_frame_size(rb, &cm->display_width, | |
e0614bf7 ZZ |
912 | * &cm->display_height); |
913 | */ | |
b9164398 NQ |
914 | } else { |
915 | if (print_header_info) | |
916 | pr_info(" * 1-bit display_size_present read : 0\n"); | |
917 | } | |
918 | } | |
919 | ||
546484c5 | 920 | |
921 | uint8_t print_header_info = 0; | |
922 | ||
923 | struct buff_s { | |
924 | u32 buf_start; | |
925 | u32 buf_size; | |
926 | u32 buf_end; | |
927 | } buff_t; | |
928 | ||
929 | struct BuffInfo_s { | |
930 | u32 max_width; | |
931 | u32 max_height; | |
932 | u32 start_adr; | |
933 | u32 end_adr; | |
934 | struct buff_s ipp; | |
935 | struct buff_s sao_abv; | |
936 | struct buff_s sao_vb; | |
937 | struct buff_s short_term_rps; | |
938 | struct buff_s vps; | |
939 | struct buff_s sps; | |
940 | struct buff_s pps; | |
941 | struct buff_s sao_up; | |
942 | struct buff_s swap_buf; | |
943 | struct buff_s swap_buf2; | |
944 | struct buff_s scalelut; | |
945 | struct buff_s dblk_para; | |
946 | struct buff_s dblk_data; | |
947 | struct buff_s seg_map; | |
546484c5 | 948 | struct buff_s mmu_vbh; |
949 | struct buff_s cm_header; | |
546484c5 | 950 | struct buff_s mpred_above; |
951 | #ifdef MV_USE_FIXED_BUF | |
952 | struct buff_s mpred_mv; | |
953 | #endif | |
954 | struct buff_s rpm; | |
955 | struct buff_s lmem; | |
956 | } BuffInfo_t; | |
546484c5 | 957 | #ifdef MULTI_INSTANCE_SUPPORT |
958 | #define DEC_RESULT_NONE 0 | |
959 | #define DEC_RESULT_DONE 1 | |
960 | #define DEC_RESULT_AGAIN 2 | |
961 | #define DEC_RESULT_CONFIG_PARAM 3 | |
962 | #define DEC_RESULT_ERROR 4 | |
963 | #define DEC_INIT_PICLIST 5 | |
964 | #define DEC_UNINIT_PICLIST 6 | |
965 | #define DEC_RESULT_GET_DATA 7 | |
966 | #define DEC_RESULT_GET_DATA_RETRY 8 | |
967 | #define DEC_RESULT_EOS 9 | |
968 | #define DEC_RESULT_FORCE_EXIT 10 | |
65ad8202 | 969 | #define DEC_RESULT_NEED_MORE_BUFFER 11 |
0fb7e163 | 970 | #define DEC_V4L2_CONTINUE_DECODING 18 |
546484c5 | 971 | |
a6c89e96 NQ |
972 | #define DEC_S1_RESULT_NONE 0 |
973 | #define DEC_S1_RESULT_DONE 1 | |
974 | #define DEC_S1_RESULT_FORCE_EXIT 2 | |
975 | #define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0 | |
976 | ||
977 | #ifdef FB_DECODING_TEST_SCHEDULE | |
978 | #define TEST_SET_NONE 0 | |
979 | #define TEST_SET_PIC_DONE 1 | |
980 | #define TEST_SET_S2_DONE 2 | |
981 | #endif | |
982 | ||
546484c5 | 983 | static void vp9_work(struct work_struct *work); |
984 | #endif | |
985 | struct loop_filter_info_n; | |
986 | struct loopfilter; | |
987 | struct segmentation; | |
988 | ||
a6c89e96 NQ |
989 | #ifdef SUPPORT_FB_DECODING |
990 | static void mpred_process(struct VP9Decoder_s *pbi); | |
991 | static void vp9_s1_work(struct work_struct *work); | |
992 | ||
993 | struct stage_buf_s { | |
994 | int index; | |
995 | unsigned short rpm[RPM_END - RPM_BEGIN]; | |
996 | }; | |
997 | ||
998 | static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM]; | |
999 | ||
1000 | static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM]; | |
1001 | ||
1002 | #ifdef FB_DECODING_TEST_SCHEDULE | |
1003 | u32 stage_buf_num; /* = 16;*/ | |
1004 | #else | |
1005 | u32 stage_buf_num; | |
1006 | #endif | |
1007 | #endif | |
1008 | ||
546484c5 | 1009 | struct VP9Decoder_s { |
1010 | #ifdef MULTI_INSTANCE_SUPPORT | |
1011 | unsigned char index; | |
1012 | ||
1013 | struct device *cma_dev; | |
1014 | struct platform_device *platform_dev; | |
1015 | void (*vdec_cb)(struct vdec_s *, void *); | |
1016 | void *vdec_cb_arg; | |
1017 | struct vframe_chunk_s *chunk; | |
1018 | int dec_result; | |
1019 | struct work_struct work; | |
dc4a2edc | 1020 | struct work_struct recycle_mmu_work; |
a994f6d6 | 1021 | struct work_struct set_clk_work; |
546484c5 | 1022 | u32 start_shift_bytes; |
1023 | ||
1024 | struct BuffInfo_s work_space_buf_store; | |
1025 | unsigned long buf_start; | |
1026 | u32 buf_size; | |
1027 | u32 cma_alloc_count; | |
1028 | unsigned long cma_alloc_addr; | |
1029 | uint8_t eos; | |
1030 | unsigned long int start_process_time; | |
1031 | unsigned last_lcu_idx; | |
1032 | int decode_timeout_count; | |
1033 | unsigned timeout_num; | |
a5c5bec0 | 1034 | int save_buffer_mode; |
546484c5 | 1035 | |
1036 | int double_write_mode; | |
1037 | #endif | |
546484c5 | 1038 | long used_4k_num; |
b7706e1e | 1039 | |
546484c5 | 1040 | unsigned char m_ins_flag; |
1041 | char *provider_name; | |
1042 | union param_u param; | |
1043 | int frame_count; | |
1044 | int pic_count; | |
1045 | u32 stat; | |
1046 | struct timer_list timer; | |
1047 | u32 frame_dur; | |
1048 | u32 frame_ar; | |
1049 | int fatal_error; | |
1050 | uint8_t init_flag; | |
ca482a9c | 1051 | uint8_t first_sc_checked; |
546484c5 | 1052 | uint8_t process_busy; |
1053 | #define PROC_STATE_INIT 0 | |
1054 | #define PROC_STATE_DECODESLICE 1 | |
1055 | #define PROC_STATE_SENDAGAIN 2 | |
1056 | uint8_t process_state; | |
1057 | u32 ucode_pause_pos; | |
1058 | ||
1059 | int show_frame_num; | |
546484c5 | 1060 | struct buff_s mc_buf_spec; |
546484c5 | 1061 | struct dec_sysinfo vvp9_amstream_dec_info; |
1062 | void *rpm_addr; | |
1063 | void *lmem_addr; | |
1064 | dma_addr_t rpm_phy_addr; | |
1065 | dma_addr_t lmem_phy_addr; | |
1066 | unsigned short *lmem_ptr; | |
1067 | unsigned short *debug_ptr; | |
1068 | ||
1069 | void *prob_buffer_addr; | |
1070 | void *count_buffer_addr; | |
1071 | dma_addr_t prob_buffer_phy_addr; | |
1072 | dma_addr_t count_buffer_phy_addr; | |
1073 | ||
546484c5 | 1074 | void *frame_mmu_map_addr; |
1075 | dma_addr_t frame_mmu_map_phy_addr; | |
b7706e1e | 1076 | |
546484c5 | 1077 | unsigned int use_cma_flag; |
1078 | ||
1079 | struct BUF_s m_BUF[MAX_BUF_NUM]; | |
a6c89e96 | 1080 | struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM]; |
546484c5 | 1081 | u32 used_buf_num; |
1082 | DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); | |
1083 | DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); | |
1084 | DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE); | |
1085 | struct vframe_s vfpool[VF_POOL_SIZE]; | |
1086 | u32 vf_pre_count; | |
1087 | u32 vf_get_count; | |
1088 | u32 vf_put_count; | |
1089 | int buf_num; | |
1090 | int pic_num; | |
1091 | int lcu_size_log2; | |
1092 | unsigned int losless_comp_body_size; | |
1093 | ||
1094 | u32 video_signal_type; | |
1095 | ||
1096 | int pts_mode; | |
1097 | int last_lookup_pts; | |
1098 | int last_pts; | |
1099 | u64 last_lookup_pts_us64; | |
1100 | u64 last_pts_us64; | |
1101 | u64 shift_byte_count; | |
1102 | ||
1103 | u32 pts_unstable; | |
1104 | u32 frame_cnt_window; | |
1105 | u32 pts1, pts2; | |
1106 | u32 last_duration; | |
1107 | u32 duration_from_pts_done; | |
1108 | bool vp9_first_pts_ready; | |
1109 | ||
1110 | u32 shift_byte_count_lo; | |
1111 | u32 shift_byte_count_hi; | |
1112 | int pts_mode_switching_count; | |
1113 | int pts_mode_recovery_count; | |
1114 | ||
1115 | bool get_frame_dur; | |
1116 | u32 saved_resolution; | |
1117 | ||
1118 | /**/ | |
1119 | struct VP9_Common_s common; | |
1120 | struct RefCntBuffer_s *cur_buf; | |
1121 | int refresh_frame_flags; | |
1122 | uint8_t need_resync; | |
1123 | uint8_t hold_ref_buf; | |
1124 | uint8_t ready_for_new_data; | |
1125 | struct BufferPool_s vp9_buffer_pool; | |
b7706e1e | 1126 | |
546484c5 | 1127 | struct BuffInfo_s *work_space_buf; |
b7706e1e | 1128 | |
546484c5 | 1129 | struct buff_s *mc_buf; |
b7706e1e | 1130 | |
546484c5 | 1131 | unsigned int frame_width; |
1132 | unsigned int frame_height; | |
1133 | ||
1134 | unsigned short *rpm_ptr; | |
1135 | int init_pic_w; | |
1136 | int init_pic_h; | |
1137 | int lcu_total; | |
1138 | int lcu_size; | |
1139 | ||
1140 | int slice_type; | |
1141 | ||
1142 | int skip_flag; | |
1143 | int decode_idx; | |
1144 | int slice_idx; | |
1145 | uint8_t has_keyframe; | |
1146 | uint8_t wait_buf; | |
1147 | uint8_t error_flag; | |
1148 | ||
1149 | /* bit 0, for decoding; bit 1, for displaying */ | |
1150 | uint8_t ignore_bufmgr_error; | |
1151 | int PB_skip_mode; | |
1152 | int PB_skip_count_after_decoding; | |
1153 | /*hw*/ | |
1154 | ||
1155 | /*lf*/ | |
1156 | int default_filt_lvl; | |
1157 | struct loop_filter_info_n *lfi; | |
1158 | struct loopfilter *lf; | |
1159 | struct segmentation *seg_4lf; | |
1160 | /**/ | |
1161 | struct vdec_info *gvs; | |
1162 | ||
1163 | u32 pre_stream_offset; | |
1164 | ||
1165 | unsigned int dec_status; | |
1166 | u32 last_put_idx; | |
1167 | int new_frame_displayed; | |
1168 | void *mmu_box; | |
1169 | void *bmmu_box; | |
b7706e1e | 1170 | int mmu_enable; |
546484c5 | 1171 | struct vframe_master_display_colour_s vf_dp; |
1172 | struct firmware_s *fw; | |
1173 | int max_pic_w; | |
1174 | int max_pic_h; | |
a6c89e96 NQ |
1175 | #ifdef SUPPORT_FB_DECODING |
1176 | int dec_s1_result; | |
1177 | int s1_test_cmd; | |
1178 | struct work_struct s1_work; | |
1179 | int used_stage_buf_num; | |
1180 | int s1_pos; | |
1181 | int s2_pos; | |
1182 | void *stage_mmu_map_addr; | |
1183 | dma_addr_t stage_mmu_map_phy_addr; | |
1184 | struct stage_buf_s *s1_buf; | |
1185 | struct stage_buf_s *s2_buf; | |
1186 | struct stage_buf_s *stage_bufs | |
1187 | [STAGE_MAX_BUFFERS]; | |
1188 | unsigned char run2_busy; | |
1189 | ||
1190 | int s1_mv_buf_index; | |
1191 | int s1_mv_buf_index_pre; | |
1192 | int s1_mv_buf_index_pre_pre; | |
1193 | unsigned long s1_mpred_mv_wr_start_addr; | |
1194 | unsigned long s1_mpred_mv_wr_start_addr_pre; | |
1195 | unsigned short s1_intra_only; | |
1196 | unsigned short s1_frame_type; | |
1197 | unsigned short s1_width; | |
1198 | unsigned short s1_height; | |
1199 | unsigned short s1_last_show_frame; | |
1200 | union param_u s1_param; | |
1201 | u8 back_not_run_ready; | |
1202 | #endif | |
ca482a9c HZ |
1203 | int need_cache_size; |
1204 | u64 sc_start_time; | |
187af067 | 1205 | bool postproc_done; |
1206 | int low_latency_flag; | |
0eb79ad7 | 1207 | bool no_head; |
2cd6815e NQ |
1208 | bool pic_list_init_done; |
1209 | bool pic_list_init_done2; | |
1210 | bool is_used_v4l; | |
1211 | void *v4l2_ctx; | |
0fb7e163 | 1212 | bool v4l_params_parsed; |
ac678990 NQ |
1213 | int frameinfo_enable; |
1214 | struct vframe_qos_s vframe_qos; | |
0fb7e163 | 1215 | u32 mem_map_mode; |
75803959 | 1216 | u32 dynamic_buf_num_margin; |
8e9fb312 | 1217 | struct vframe_s vframe_dummy; |
0baa899d | 1218 | u32 res_ch_flag; |
3be38e55 | 1219 | /*struct VP9Decoder_s vp9_decoder;*/ |
1220 | union param_u vp9_param; | |
ae727791 | 1221 | int sidebind_type; |
1222 | int sidebind_channel_id; | |
677ab50d NQ |
1223 | bool enable_fence; |
1224 | int fence_usage; | |
65ad8202 GZ |
1225 | u32 frame_mode_pts_save[FRAME_BUFFERS]; |
1226 | u64 frame_mode_pts64_save[FRAME_BUFFERS]; | |
1227 | int run_ready_min_buf_num; | |
1228 | int one_package_frame_cnt; | |
b7706e1e | 1229 | }; |
546484c5 | 1230 | |
3d58646a NQ |
1231 | static int vp9_print(struct VP9Decoder_s *pbi, |
1232 | int flag, const char *fmt, ...) | |
1233 | { | |
1234 | #define HEVC_PRINT_BUF 256 | |
1235 | unsigned char buf[HEVC_PRINT_BUF]; | |
1236 | int len = 0; | |
1237 | ||
1238 | if (pbi == NULL || | |
1239 | (flag == 0) || | |
1240 | (debug & flag)) { | |
1241 | va_list args; | |
1242 | ||
1243 | va_start(args, fmt); | |
1244 | if (pbi) | |
1245 | len = sprintf(buf, "[%d]", pbi->index); | |
1246 | vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args); | |
1247 | pr_debug("%s", buf); | |
1248 | va_end(args); | |
1249 | } | |
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | static int is_oversize(int w, int h) | |
1254 | { | |
1255 | int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)? | |
1256 | MAX_SIZE_8K : MAX_SIZE_4K; | |
1257 | ||
1258 | if (w <= 0 || h <= 0) | |
1259 | return true; | |
1260 | ||
1261 | if (h != 0 && (w > max / h)) | |
1262 | return true; | |
1263 | ||
1264 | return false; | |
1265 | } | |
1266 | ||
75803959 NQ |
1267 | static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi, |
1268 | struct PIC_BUFFER_CONFIG_s *pic); | |
2cd6815e | 1269 | |
546484c5 | 1270 | static void resize_context_buffers(struct VP9Decoder_s *pbi, |
1271 | struct VP9_Common_s *cm, int width, int height) | |
b9164398 NQ |
1272 | { |
1273 | if (cm->width != width || cm->height != height) { | |
1274 | /* to do ..*/ | |
546484c5 | 1275 | if (pbi != NULL) { |
1276 | pbi->vp9_first_pts_ready = 0; | |
1277 | pbi->duration_from_pts_done = 0; | |
1278 | } | |
b9164398 NQ |
1279 | pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width, |
1280 | cm->height, width, height); | |
0fb7e163 NQ |
1281 | cm->width = width; |
1282 | cm->height = height; | |
b9164398 NQ |
1283 | } |
1284 | /* | |
e0614bf7 ZZ |
1285 | *if (cm->cur_frame->mvs == NULL || |
1286 | * cm->mi_rows > cm->cur_frame->mi_rows || | |
1287 | * cm->mi_cols > cm->cur_frame->mi_cols) { | |
1288 | * resize_mv_buffer(cm); | |
1289 | *} | |
1290 | */ | |
b9164398 NQ |
1291 | } |
1292 | ||
1293 | static int valid_ref_frame_size(int ref_width, int ref_height, | |
1294 | int this_width, int this_height) { | |
1295 | return 2 * this_width >= ref_width && | |
1296 | 2 * this_height >= ref_height && | |
1297 | this_width <= 16 * ref_width && | |
1298 | this_height <= 16 * ref_height; | |
1299 | } | |
1300 | ||
1301 | /* | |
e0614bf7 ZZ |
1302 | *static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth, |
1303 | * int ref_xss, int ref_yss, | |
1304 | * enum vpx_bit_depth_t this_bit_depth, | |
1305 | * int this_xss, int this_yss) { | |
1306 | * return ref_bit_depth == this_bit_depth && ref_xss == this_xss && | |
1307 | * ref_yss == this_yss; | |
1308 | *} | |
1309 | */ | |
b9164398 NQ |
1310 | |
1311 | ||
1312 | static int setup_frame_size( | |
1313 | struct VP9Decoder_s *pbi, | |
1314 | struct VP9_Common_s *cm, union param_u *params, | |
1315 | unsigned int *mmu_index_adr, | |
1316 | int print_header_info) { | |
1317 | int width, height; | |
1318 | struct BufferPool_s * const pool = cm->buffer_pool; | |
1319 | struct PIC_BUFFER_CONFIG_s *ybf; | |
1320 | int ret = 0; | |
1321 | ||
1322 | width = params->p.width; | |
1323 | height = params->p.height; | |
3d58646a NQ |
1324 | if (is_oversize(width, height)) { |
1325 | vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__); | |
1326 | return -1; | |
1327 | } | |
1328 | ||
b9164398 NQ |
1329 | /*vp9_read_frame_size(rb, &width, &height);*/ |
1330 | if (print_header_info) | |
1331 | pr_info(" * 16-bits w read : %d (width : %d)\n", width, height); | |
1332 | if (print_header_info) | |
1333 | pr_info | |
1334 | (" * 16-bits h read : %d (height : %d)\n", width, height); | |
1335 | ||
1336 | WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width); | |
df841122 | 1337 | #ifdef VP9_10B_HED_FB |
6276f4ff | 1338 | WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width); |
df841122 | 1339 | #endif |
6276f4ff | 1340 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
b7706e1e | 1341 | ret = vp9_alloc_mmu(pbi, |
b9164398 | 1342 | cm->new_fb_idx, |
b7706e1e | 1343 | params->p.width, |
1344 | params->p.height, | |
1345 | params->p.bit_depth, | |
1346 | mmu_index_adr); | |
1347 | if (ret != 0) { | |
1348 | pr_err("can't alloc need mmu1,idx %d ret =%d\n", | |
1349 | cm->new_fb_idx, | |
1350 | ret); | |
1351 | return ret; | |
1352 | } | |
1353 | cm->cur_fb_idx_mmu = cm->new_fb_idx; | |
b9164398 | 1354 | } |
b9164398 | 1355 | |
546484c5 | 1356 | resize_context_buffers(pbi, cm, width, height); |
b9164398 NQ |
1357 | setup_display_size(cm, params, print_header_info); |
1358 | #if 0 | |
1359 | lock_buffer_pool(pool); | |
1360 | if (vp9_realloc_frame_buffer( | |
1361 | get_frame_new_buffer(cm), cm->width, cm->height, | |
1362 | cm->subsampling_x, cm->subsampling_y, | |
1363 | #if CONFIG_VP9_HIGHBITDEPTH | |
1364 | cm->use_highbitdepth, | |
1365 | #endif | |
1366 | VP9_DEC_BORDER_IN_PIXELS, | |
1367 | cm->byte_alignment, | |
1368 | &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer, | |
1369 | pool->get_fb_cb, pool->cb_priv)) { | |
1370 | unlock_buffer_pool(pool); | |
1371 | vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR, | |
1372 | "Failed to allocate frame buffer"); | |
1373 | } | |
1374 | unlock_buffer_pool(pool); | |
1375 | #else | |
1376 | /* porting */ | |
1377 | ybf = get_frame_new_buffer(cm); | |
0fb7e163 NQ |
1378 | if (!ybf) |
1379 | return -1; | |
1380 | ||
b9164398 NQ |
1381 | ybf->y_crop_width = width; |
1382 | ybf->y_crop_height = height; | |
1383 | ybf->bit_depth = params->p.bit_depth; | |
1384 | #endif | |
1385 | pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x; | |
1386 | pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y; | |
1387 | pool->frame_bufs[cm->new_fb_idx].buf.bit_depth = | |
1388 | (unsigned int)cm->bit_depth; | |
1389 | pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space; | |
1390 | return ret; | |
1391 | } | |
1392 | ||
1393 | static int setup_frame_size_with_refs( | |
1394 | struct VP9Decoder_s *pbi, | |
1395 | struct VP9_Common_s *cm, | |
1396 | union param_u *params, | |
1397 | unsigned int *mmu_index_adr, | |
1398 | int print_header_info) { | |
1399 | ||
1400 | int width, height; | |
1401 | int found = 0, i; | |
1402 | int has_valid_ref_frame = 0; | |
1403 | struct PIC_BUFFER_CONFIG_s *ybf; | |
1404 | struct BufferPool_s * const pool = cm->buffer_pool; | |
1405 | int ret = 0; | |
1406 | ||
1407 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
1408 | if ((params->p.same_frame_size >> | |
1409 | (REFS_PER_FRAME - i - 1)) & 0x1) { | |
1410 | struct PIC_BUFFER_CONFIG_s *const buf = | |
1411 | cm->frame_refs[i].buf; | |
1412 | /*if (print_header_info) | |
e0614bf7 ZZ |
1413 | * pr_info |
1414 | * ("1-bit same_frame_size[%d] read : 1\n", i); | |
1415 | */ | |
b9164398 NQ |
1416 | width = buf->y_crop_width; |
1417 | height = buf->y_crop_height; | |
1418 | /*if (print_header_info) | |
e0614bf7 ZZ |
1419 | * pr_info |
1420 | * (" - same_frame_size width : %d\n", width); | |
1421 | */ | |
b9164398 | 1422 | /*if (print_header_info) |
e0614bf7 ZZ |
1423 | * pr_info |
1424 | * (" - same_frame_size height : %d\n", height); | |
1425 | */ | |
b9164398 NQ |
1426 | found = 1; |
1427 | break; | |
a6c89e96 | 1428 | } else { |
b9164398 | 1429 | /*if (print_header_info) |
e0614bf7 ZZ |
1430 | * pr_info |
1431 | * ("1-bit same_frame_size[%d] read : 0\n", i); | |
1432 | */ | |
b9164398 NQ |
1433 | } |
1434 | } | |
1435 | ||
1436 | if (!found) { | |
1437 | /*vp9_read_frame_size(rb, &width, &height);*/ | |
1438 | width = params->p.width; | |
1439 | height = params->p.height; | |
1440 | /*if (print_header_info) | |
e0614bf7 ZZ |
1441 | * pr_info |
1442 | * (" * 16-bits w read : %d (width : %d)\n", | |
1443 | * width, height); | |
1444 | *if (print_header_info) | |
1445 | * pr_info | |
1446 | * (" * 16-bits h read : %d (height : %d)\n", | |
1447 | * width, height); | |
1448 | */ | |
b9164398 NQ |
1449 | } |
1450 | ||
3d58646a NQ |
1451 | if (is_oversize(width, height)) { |
1452 | vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__); | |
b9164398 NQ |
1453 | return -1; |
1454 | } | |
1455 | ||
1456 | params->p.width = width; | |
1457 | params->p.height = height; | |
1458 | ||
1459 | WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width); | |
6276f4ff | 1460 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
b7706e1e | 1461 | /*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx); |
1462 | *cm->prev_fb_idx = cm->new_fb_idx; | |
1463 | */ | |
1464 | /* pr_info | |
1465 | * ("[DEBUG DEBUG]Before alloc_mmu, | |
1466 | * prev_fb_idx : %d, new_fb_idx : %d\r\n", | |
1467 | * cm->prev_fb_idx, cm->new_fb_idx); | |
1468 | */ | |
1469 | ret = vp9_alloc_mmu(pbi, cm->new_fb_idx, | |
1470 | params->p.width, params->p.height, | |
1471 | params->p.bit_depth, mmu_index_adr); | |
1472 | if (ret != 0) { | |
1473 | pr_err("can't alloc need mmu,idx %d\r\n", | |
1474 | cm->new_fb_idx); | |
1475 | return ret; | |
1476 | } | |
1477 | cm->cur_fb_idx_mmu = cm->new_fb_idx; | |
b9164398 | 1478 | } |
b9164398 NQ |
1479 | |
1480 | /*Check to make sure at least one of frames that this frame references | |
e0614bf7 ZZ |
1481 | *has valid dimensions. |
1482 | */ | |
b9164398 NQ |
1483 | for (i = 0; i < REFS_PER_FRAME; ++i) { |
1484 | struct RefBuffer_s * const ref_frame = &cm->frame_refs[i]; | |
e0614bf7 | 1485 | |
b9164398 NQ |
1486 | has_valid_ref_frame |= |
1487 | valid_ref_frame_size(ref_frame->buf->y_crop_width, | |
1488 | ref_frame->buf->y_crop_height, | |
1489 | width, height); | |
1490 | } | |
1491 | if (!has_valid_ref_frame) { | |
1492 | pr_err("Error: Referenced frame has invalid size\r\n"); | |
1493 | return -1; | |
1494 | } | |
1495 | #if 0 | |
1496 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
a6c89e96 NQ |
1497 | struct RefBuffer_s * const ref_frame = |
1498 | &cm->frame_refs[i]; | |
1499 | if (!valid_ref_frame_img_fmt( | |
1500 | ref_frame->buf->bit_depth, | |
1501 | ref_frame->buf->subsampling_x, | |
1502 | ref_frame->buf->subsampling_y, | |
1503 | cm->bit_depth, | |
1504 | cm->subsampling_x, | |
1505 | cm->subsampling_y)) | |
1506 | pr_err | |
b9164398 NQ |
1507 | ("Referenced frame incompatible color fmt\r\n"); |
1508 | return -1; | |
1509 | } | |
1510 | #endif | |
546484c5 | 1511 | resize_context_buffers(pbi, cm, width, height); |
b9164398 NQ |
1512 | setup_display_size(cm, params, print_header_info); |
1513 | ||
1514 | #if 0 | |
1515 | lock_buffer_pool(pool); | |
1516 | if (vp9_realloc_frame_buffer( | |
1517 | get_frame_new_buffer(cm), cm->width, cm->height, | |
1518 | cm->subsampling_x, cm->subsampling_y, | |
1519 | #if CONFIG_VP9_HIGHBITDEPTH | |
1520 | cm->use_highbitdepth, | |
1521 | #endif | |
1522 | VP9_DEC_BORDER_IN_PIXELS, | |
1523 | cm->byte_alignment, | |
1524 | &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer, | |
1525 | pool->get_fb_cb, | |
1526 | pool->cb_priv)) { | |
e0614bf7 ZZ |
1527 | unlock_buffer_pool(pool); |
1528 | vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR, | |
1529 | "Failed to allocate frame buffer"); | |
b9164398 NQ |
1530 | } |
1531 | unlock_buffer_pool(pool); | |
1532 | #else | |
1533 | /* porting */ | |
1534 | ybf = get_frame_new_buffer(cm); | |
0fb7e163 NQ |
1535 | if (!ybf) |
1536 | return -1; | |
1537 | ||
b9164398 NQ |
1538 | ybf->y_crop_width = width; |
1539 | ybf->y_crop_height = height; | |
1540 | ybf->bit_depth = params->p.bit_depth; | |
1541 | #endif | |
1542 | pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x; | |
1543 | pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y; | |
1544 | pool->frame_bufs[cm->new_fb_idx].buf.bit_depth = | |
1545 | (unsigned int)cm->bit_depth; | |
1546 | pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space; | |
1547 | return ret; | |
1548 | } | |
1549 | ||
c20e6c85 | 1550 | static inline bool close_to(int a, int b, int m) |
1551 | { | |
1552 | return (abs(a - b) < m) ? true : false; | |
1553 | } | |
1554 | ||
b9164398 NQ |
1555 | #ifdef MULTI_INSTANCE_SUPPORT |
1556 | static int vp9_print_cont(struct VP9Decoder_s *pbi, | |
1557 | int flag, const char *fmt, ...) | |
1558 | { | |
1559 | unsigned char buf[HEVC_PRINT_BUF]; | |
1560 | int len = 0; | |
e0614bf7 | 1561 | |
b9164398 NQ |
1562 | if (pbi == NULL || |
1563 | (flag == 0) || | |
1564 | (debug & flag)) { | |
1565 | va_list args; | |
e0614bf7 | 1566 | |
b9164398 NQ |
1567 | va_start(args, fmt); |
1568 | vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args); | |
fbe200cf | 1569 | pr_debug("%s", buf); |
b9164398 NQ |
1570 | va_end(args); |
1571 | } | |
1572 | return 0; | |
1573 | } | |
fe96802b | 1574 | |
a6c89e96 NQ |
1575 | static void trigger_schedule(struct VP9Decoder_s *pbi) |
1576 | { | |
0fb7e163 NQ |
1577 | if (pbi->is_used_v4l) { |
1578 | struct aml_vcodec_ctx *ctx = | |
1579 | (struct aml_vcodec_ctx *)(pbi->v4l2_ctx); | |
1580 | ||
1581 | if (ctx->param_sets_from_ucode && | |
1582 | !pbi->v4l_params_parsed) | |
1583 | vdec_v4l_write_frame_sync(ctx); | |
1584 | } | |
1585 | ||
a6c89e96 NQ |
1586 | if (pbi->vdec_cb) |
1587 | pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg); | |
1588 | } | |
1589 | ||
fe96802b NQ |
1590 | static void reset_process_time(struct VP9Decoder_s *pbi) |
1591 | { | |
1592 | if (pbi->start_process_time) { | |
1593 | unsigned process_time = | |
1594 | 1000 * (jiffies - pbi->start_process_time) / HZ; | |
1595 | pbi->start_process_time = 0; | |
1596 | if (process_time > max_process_time[pbi->index]) | |
1597 | max_process_time[pbi->index] = process_time; | |
1598 | } | |
1599 | } | |
1600 | ||
1601 | static void start_process_time(struct VP9Decoder_s *pbi) | |
1602 | { | |
1603 | pbi->start_process_time = jiffies; | |
1604 | pbi->decode_timeout_count = 0; | |
1605 | pbi->last_lcu_idx = 0; | |
1606 | } | |
1607 | ||
1608 | static void timeout_process(struct VP9Decoder_s *pbi) | |
1609 | { | |
1610 | pbi->timeout_num++; | |
1611 | amhevc_stop(); | |
1612 | vp9_print(pbi, | |
1613 | 0, "%s decoder timeout\n", __func__); | |
1614 | ||
1615 | pbi->dec_result = DEC_RESULT_DONE; | |
1616 | reset_process_time(pbi); | |
1617 | vdec_schedule_work(&pbi->work); | |
1618 | } | |
1619 | ||
c23e8aee HZ |
1620 | static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi) |
1621 | { | |
b7706e1e | 1622 | return ((double_write_mode & 0x80000000) == 0) ? |
c23e8aee HZ |
1623 | pbi->double_write_mode : |
1624 | (double_write_mode & 0x7fffffff); | |
1625 | } | |
1626 | ||
d9a28922 YP |
1627 | static int v4l_parser_get_double_write_mode(struct VP9Decoder_s *pbi) |
1628 | { | |
1629 | u32 valid_dw_mode = get_valid_double_write_mode(pbi); | |
1630 | u32 dw; | |
1631 | int w, h; | |
1632 | ||
1633 | /* mask for supporting double write value bigger than 0x100 */ | |
1634 | if (valid_dw_mode & 0xffffff00) { | |
1635 | w = pbi->frame_width; | |
1636 | h = pbi->frame_height; | |
1637 | ||
1638 | dw = 0x1; /*1:1*/ | |
1639 | switch (valid_dw_mode) { | |
1640 | case 0x100: | |
1641 | if (w > 1920 && h > 1088) | |
1642 | dw = 0x4; /*1:2*/ | |
1643 | break; | |
1644 | case 0x200: | |
1645 | if (w > 1920 && h > 1088) | |
1646 | dw = 0x2; /*1:4*/ | |
1647 | break; | |
1648 | case 0x300: | |
1649 | if (w > 1280 && h > 720) | |
1650 | dw = 0x4; /*1:2*/ | |
1651 | break; | |
1652 | default: | |
1653 | break; | |
1654 | } | |
1655 | return dw; | |
1656 | } | |
1657 | ||
1658 | return valid_dw_mode; | |
1659 | } | |
1660 | ||
1661 | ||
fe96802b NQ |
1662 | static int get_double_write_mode(struct VP9Decoder_s *pbi) |
1663 | { | |
c23e8aee HZ |
1664 | u32 valid_dw_mode = get_valid_double_write_mode(pbi); |
1665 | u32 dw; | |
33d1149b | 1666 | int w, h; |
1667 | struct VP9_Common_s *cm = &pbi->common; | |
1668 | struct PIC_BUFFER_CONFIG_s *cur_pic_config; | |
1669 | ||
21d9caac | 1670 | /* mask for supporting double write value bigger than 0x100 */ |
1671 | if (valid_dw_mode & 0xffffff00) { | |
1672 | if (!cm->cur_frame) | |
1673 | return 1;/*no valid frame,*/ | |
1674 | cur_pic_config = &cm->cur_frame->buf; | |
1675 | w = cur_pic_config->y_crop_width; | |
1676 | h = cur_pic_config->y_crop_height; | |
1677 | ||
1678 | dw = 0x1; /*1:1*/ | |
1679 | switch (valid_dw_mode) { | |
1680 | case 0x100: | |
1681 | if (w > 1920 && h > 1088) | |
1682 | dw = 0x4; /*1:2*/ | |
1683 | break; | |
1684 | case 0x200: | |
1685 | if (w > 1920 && h > 1088) | |
1686 | dw = 0x2; /*1:4*/ | |
1687 | break; | |
1688 | case 0x300: | |
1689 | if (w > 1280 && h > 720) | |
1690 | dw = 0x4; /*1:2*/ | |
1691 | break; | |
1692 | default: | |
1693 | break; | |
1694 | } | |
1695 | return dw; | |
c23e8aee | 1696 | } |
21d9caac | 1697 | |
1698 | return valid_dw_mode; | |
c23e8aee HZ |
1699 | } |
1700 | ||
1701 | /* for double write buf alloc */ | |
1702 | static int get_double_write_mode_init(struct VP9Decoder_s *pbi) | |
1703 | { | |
1704 | u32 valid_dw_mode = get_valid_double_write_mode(pbi); | |
33d1149b | 1705 | u32 dw; |
1706 | int w = pbi->init_pic_w; | |
1707 | int h = pbi->init_pic_h; | |
1708 | ||
1709 | dw = 0x1; /*1:1*/ | |
1710 | switch (valid_dw_mode) { | |
1711 | case 0x100: | |
c23e8aee HZ |
1712 | if (w > 1920 && h > 1088) |
1713 | dw = 0x4; /*1:2*/ | |
33d1149b | 1714 | break; |
1715 | case 0x200: | |
1716 | if (w > 1920 && h > 1088) | |
1717 | dw = 0x2; /*1:4*/ | |
1718 | break; | |
1719 | case 0x300: | |
1720 | if (w > 1280 && h > 720) | |
1721 | dw = 0x4; /*1:2*/ | |
1722 | break; | |
1723 | default: | |
1724 | dw = valid_dw_mode; | |
1725 | break; | |
c23e8aee | 1726 | } |
33d1149b | 1727 | return dw; |
fe96802b | 1728 | } |
b9164398 | 1729 | #endif |
c23e8aee HZ |
1730 | |
1731 | static int get_double_write_ratio(struct VP9Decoder_s *pbi, | |
1732 | int dw_mode) | |
1733 | { | |
1734 | int ratio = 1; | |
1735 | if ((dw_mode == 2) || | |
1736 | (dw_mode == 3)) | |
1737 | ratio = 4; | |
1738 | else if (dw_mode == 4) | |
1739 | ratio = 2; | |
1740 | return ratio; | |
1741 | } | |
1742 | ||
df841122 | 1743 | //#define MAX_4K_NUM 0x1200 |
b7706e1e | 1744 | |
b9164398 NQ |
1745 | int vp9_alloc_mmu( |
1746 | struct VP9Decoder_s *pbi, | |
1747 | int cur_buf_idx, | |
1748 | int pic_width, | |
1749 | int pic_height, | |
1750 | unsigned short bit_depth, | |
1751 | unsigned int *mmu_index_adr) | |
1752 | { | |
1753 | int bit_depth_10 = (bit_depth == VPX_BITS_10); | |
1754 | int picture_size; | |
df841122 | 1755 | int cur_mmu_4k_number, max_frame_num; |
976f3376 HZ |
1756 | if (!pbi->mmu_box) { |
1757 | pr_err("error no mmu box!\n"); | |
1758 | return -1; | |
1759 | } | |
eb05f7cf | 1760 | if (get_double_write_mode(pbi) == 0x10) |
6276f4ff | 1761 | return 0; |
976f3376 HZ |
1762 | if (bit_depth >= VPX_BITS_12) { |
1763 | pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW; | |
1764 | pr_err("fatal_error, un support bit depth 12!\n\n"); | |
1765 | return -1; | |
1766 | } | |
b9164398 NQ |
1767 | picture_size = compute_losless_comp_body_size(pic_width, pic_height, |
1768 | bit_depth_10); | |
1769 | cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12); | |
df841122 | 1770 | |
6f5ee885 | 1771 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) |
df841122 | 1772 | max_frame_num = MAX_FRAME_8K_NUM; |
1773 | else | |
1774 | max_frame_num = MAX_FRAME_4K_NUM; | |
1775 | ||
1776 | if (cur_mmu_4k_number > max_frame_num) { | |
d481db31 NQ |
1777 | pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n", |
1778 | cur_mmu_4k_number, pic_width, pic_height); | |
1779 | return -1; | |
1780 | } | |
677ab50d | 1781 | |
b9164398 NQ |
1782 | return decoder_mmu_box_alloc_idx( |
1783 | pbi->mmu_box, | |
1784 | cur_buf_idx, | |
1785 | cur_mmu_4k_number, | |
1786 | mmu_index_adr); | |
1787 | } | |
b7706e1e | 1788 | |
fe96802b NQ |
1789 | |
1790 | #ifndef MV_USE_FIXED_BUF | |
1791 | static void dealloc_mv_bufs(struct VP9Decoder_s *pbi) | |
1792 | { | |
1793 | int i; | |
a6c89e96 | 1794 | for (i = 0; i < MV_BUFFER_NUM; i++) { |
fe96802b NQ |
1795 | if (pbi->m_mv_BUF[i].start_adr) { |
1796 | if (debug) | |
1797 | pr_info( | |
1798 | "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n", | |
1799 | i, pbi->m_mv_BUF[i].start_adr, | |
1800 | pbi->m_mv_BUF[i].size, | |
1801 | pbi->m_mv_BUF[i].used_flag); | |
1802 | decoder_bmmu_box_free_idx( | |
1803 | pbi->bmmu_box, | |
1804 | MV_BUFFER_IDX(i)); | |
1805 | pbi->m_mv_BUF[i].start_adr = 0; | |
1806 | pbi->m_mv_BUF[i].size = 0; | |
1807 | pbi->m_mv_BUF[i].used_flag = 0; | |
1808 | } | |
1809 | } | |
1810 | } | |
1811 | ||
1812 | static int alloc_mv_buf(struct VP9Decoder_s *pbi, | |
1813 | int i, int size) | |
1814 | { | |
1815 | int ret = 0; | |
49c06502 NQ |
1816 | |
1817 | if (pbi->m_mv_BUF[i].start_adr && | |
1818 | size > pbi->m_mv_BUF[i].size) { | |
1819 | dealloc_mv_bufs(pbi); | |
1820 | } else if (pbi->m_mv_BUF[i].start_adr) | |
1821 | return 0; | |
1822 | ||
fe96802b NQ |
1823 | if (decoder_bmmu_box_alloc_buf_phy |
1824 | (pbi->bmmu_box, | |
1825 | MV_BUFFER_IDX(i), size, | |
1826 | DRIVER_NAME, | |
1827 | &pbi->m_mv_BUF[i].start_adr) < 0) { | |
1828 | pbi->m_mv_BUF[i].start_adr = 0; | |
1829 | ret = -1; | |
1830 | } else { | |
1831 | pbi->m_mv_BUF[i].size = size; | |
1832 | pbi->m_mv_BUF[i].used_flag = 0; | |
1833 | ret = 0; | |
1834 | if (debug) { | |
1835 | pr_info( | |
1836 | "MV Buffer %d: start_adr %p size %x\n", | |
1837 | i, | |
1838 | (void *)pbi->m_mv_BUF[i].start_adr, | |
1839 | pbi->m_mv_BUF[i].size); | |
1840 | } | |
1841 | } | |
1842 | return ret; | |
1843 | } | |
1844 | ||
1845 | static int init_mv_buf_list(struct VP9Decoder_s *pbi) | |
1846 | { | |
1847 | int i; | |
1848 | int ret = 0; | |
a6c89e96 | 1849 | int count = MV_BUFFER_NUM; |
fe96802b NQ |
1850 | int pic_width = pbi->init_pic_w; |
1851 | int pic_height = pbi->init_pic_h; | |
1852 | int lcu_size = 64; /*fixed 64*/ | |
1853 | int pic_width_64 = (pic_width + 63) & (~0x3f); | |
1854 | int pic_height_32 = (pic_height + 31) & (~0x1f); | |
1855 | int pic_width_lcu = (pic_width_64 % lcu_size) ? | |
1856 | pic_width_64 / lcu_size + 1 | |
1857 | : pic_width_64 / lcu_size; | |
1858 | int pic_height_lcu = (pic_height_32 % lcu_size) ? | |
1859 | pic_height_32 / lcu_size + 1 | |
1860 | : pic_height_32 / lcu_size; | |
1861 | int lcu_total = pic_width_lcu * pic_height_lcu; | |
1862 | int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) & | |
1863 | (~0xffff); | |
dfe41deb RZ |
1864 | if (mv_buf_margin > 0) |
1865 | count = REF_FRAMES + mv_buf_margin; | |
a674e3cd | 1866 | |
dfe41deb RZ |
1867 | if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088) |
1868 | count = REF_FRAMES_4K + mv_buf_margin; | |
df841122 | 1869 | |
a674e3cd | 1870 | if (debug) { |
1871 | pr_info("%s w:%d, h:%d, count: %d\n", | |
1872 | __func__, pbi->init_pic_w, pbi->init_pic_h, count); | |
1873 | } | |
1874 | ||
a6c89e96 NQ |
1875 | for (i = 0; |
1876 | i < count && i < MV_BUFFER_NUM; i++) { | |
fe96802b NQ |
1877 | if (alloc_mv_buf(pbi, i, size) < 0) { |
1878 | ret = -1; | |
1879 | break; | |
1880 | } | |
1881 | } | |
1882 | return ret; | |
1883 | } | |
1884 | ||
1885 | static int get_mv_buf(struct VP9Decoder_s *pbi, | |
a6c89e96 NQ |
1886 | int *mv_buf_index, |
1887 | unsigned long *mpred_mv_wr_start_addr) | |
fe96802b NQ |
1888 | { |
1889 | int i; | |
1890 | int ret = -1; | |
a6c89e96 | 1891 | for (i = 0; i < MV_BUFFER_NUM; i++) { |
fe96802b NQ |
1892 | if (pbi->m_mv_BUF[i].start_adr && |
1893 | pbi->m_mv_BUF[i].used_flag == 0) { | |
1894 | pbi->m_mv_BUF[i].used_flag = 1; | |
1895 | ret = i; | |
1896 | break; | |
1897 | } | |
1898 | } | |
1899 | ||
1900 | if (ret >= 0) { | |
a6c89e96 NQ |
1901 | *mv_buf_index = ret; |
1902 | *mpred_mv_wr_start_addr = | |
fe96802b NQ |
1903 | (pbi->m_mv_BUF[ret].start_adr + 0xffff) & |
1904 | (~0xffff); | |
1905 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
1906 | pr_info( | |
1907 | "%s => %d (%ld) size 0x%x\n", | |
1908 | __func__, ret, | |
a6c89e96 | 1909 | *mpred_mv_wr_start_addr, |
fe96802b NQ |
1910 | pbi->m_mv_BUF[ret].size); |
1911 | } else { | |
1912 | pr_info( | |
1913 | "%s: Error, mv buf is not enough\n", | |
1914 | __func__); | |
1915 | } | |
1916 | return ret; | |
1917 | } | |
1918 | ||
1919 | static void put_mv_buf(struct VP9Decoder_s *pbi, | |
a6c89e96 | 1920 | int *mv_buf_index) |
fe96802b | 1921 | { |
a6c89e96 NQ |
1922 | int i = *mv_buf_index; |
1923 | if (i >= MV_BUFFER_NUM) { | |
fe96802b NQ |
1924 | if (debug & VP9_DEBUG_BUFMGR_MORE) |
1925 | pr_info( | |
1926 | "%s: index %d beyond range\n", | |
1927 | __func__, i); | |
1928 | return; | |
1929 | } | |
1930 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
1931 | pr_info( | |
1932 | "%s(%d): used_flag(%d)\n", | |
1933 | __func__, i, | |
1934 | pbi->m_mv_BUF[i].used_flag); | |
1935 | ||
a6c89e96 | 1936 | *mv_buf_index = -1; |
fe96802b NQ |
1937 | if (pbi->m_mv_BUF[i].start_adr && |
1938 | pbi->m_mv_BUF[i].used_flag) | |
1939 | pbi->m_mv_BUF[i].used_flag = 0; | |
1940 | } | |
1941 | ||
1942 | static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi) | |
1943 | { | |
1944 | struct VP9_Common_s *const cm = &pbi->common; | |
1945 | struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; | |
1946 | int i; | |
1947 | for (i = 0; i < pbi->used_buf_num; ++i) { | |
1948 | if ((frame_bufs[i].ref_count == 0) && | |
1949 | (frame_bufs[i].buf.index != -1) && | |
1950 | (frame_bufs[i].buf.mv_buf_index >= 0) | |
1951 | ) | |
a6c89e96 NQ |
1952 | put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index); |
1953 | } | |
1954 | } | |
1955 | ||
1956 | #ifdef SUPPORT_FB_DECODING | |
1957 | static bool mv_buf_available(struct VP9Decoder_s *pbi) | |
1958 | { | |
1959 | int i; | |
1960 | bool ret = 0; | |
1961 | for (i = 0; i < MV_BUFFER_NUM; i++) { | |
1962 | if (pbi->m_mv_BUF[i].start_adr && | |
1963 | pbi->m_mv_BUF[i].used_flag == 0) { | |
1964 | ret = 1; | |
1965 | break; | |
1966 | } | |
1967 | } | |
1968 | return ret; | |
1969 | } | |
1970 | #endif | |
1971 | #endif | |
1972 | ||
1973 | #ifdef SUPPORT_FB_DECODING | |
1974 | static void init_stage_buf(struct VP9Decoder_s *pbi) | |
1975 | { | |
1976 | uint i; | |
1977 | for (i = 0; i < STAGE_MAX_BUFFERS | |
1978 | && i < stage_buf_num; i++) { | |
1979 | pbi->stage_bufs[i] = | |
1980 | vmalloc(sizeof(struct stage_buf_s)); | |
1981 | if (pbi->stage_bufs[i] == NULL) { | |
1982 | vp9_print(pbi, | |
1983 | 0, "%s vmalloc fail\n", __func__); | |
1984 | break; | |
1985 | } | |
1986 | pbi->stage_bufs[i]->index = i; | |
1987 | } | |
1988 | pbi->used_stage_buf_num = i; | |
1989 | pbi->s1_pos = 0; | |
1990 | pbi->s2_pos = 0; | |
1991 | pbi->s1_buf = NULL; | |
1992 | pbi->s2_buf = NULL; | |
1993 | pbi->s1_mv_buf_index = FRAME_BUFFERS; | |
1994 | pbi->s1_mv_buf_index_pre = FRAME_BUFFERS; | |
1995 | pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS; | |
1996 | ||
1997 | if (pbi->used_stage_buf_num > 0) | |
1998 | vp9_print(pbi, | |
1999 | 0, "%s 2 stage decoding buf %d\n", | |
2000 | __func__, | |
2001 | pbi->used_stage_buf_num); | |
2002 | } | |
2003 | ||
2004 | static void uninit_stage_buf(struct VP9Decoder_s *pbi) | |
2005 | { | |
2006 | int i; | |
2007 | for (i = 0; i < pbi->used_stage_buf_num; i++) { | |
2008 | if (pbi->stage_bufs[i]) | |
2009 | vfree(pbi->stage_bufs[i]); | |
2010 | pbi->stage_bufs[i] = NULL; | |
2011 | } | |
2012 | pbi->used_stage_buf_num = 0; | |
2013 | pbi->s1_pos = 0; | |
2014 | pbi->s2_pos = 0; | |
2015 | pbi->s1_buf = NULL; | |
2016 | pbi->s2_buf = NULL; | |
2017 | } | |
2018 | ||
2019 | static int get_s1_buf( | |
2020 | struct VP9Decoder_s *pbi) | |
2021 | { | |
2022 | struct stage_buf_s *buf = NULL; | |
2023 | int ret = -1; | |
2024 | int buf_page_num = MAX_STAGE_PAGE_NUM; | |
2025 | int next_s1_pos = pbi->s1_pos + 1; | |
2026 | ||
2027 | if (next_s1_pos >= pbi->used_stage_buf_num) | |
2028 | next_s1_pos = 0; | |
2029 | if (next_s1_pos == pbi->s2_pos) { | |
2030 | pbi->s1_buf = NULL; | |
2031 | return ret; | |
2032 | } | |
2033 | ||
2034 | buf = pbi->stage_bufs[pbi->s1_pos]; | |
2035 | ret = decoder_mmu_box_alloc_idx( | |
2036 | pbi->mmu_box, | |
2037 | buf->index, | |
2038 | buf_page_num, | |
2039 | pbi->stage_mmu_map_addr); | |
2040 | if (ret < 0) { | |
2041 | vp9_print(pbi, 0, | |
2042 | "%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n", | |
2043 | __func__, buf->index, | |
2044 | pbi->s1_pos, pbi->s2_pos); | |
2045 | buf = NULL; | |
2046 | } else { | |
2047 | vp9_print(pbi, VP9_DEBUG_2_STAGE, | |
2048 | "%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n", | |
2049 | __func__, buf_page_num, buf->index, | |
2050 | pbi->s1_pos, pbi->s2_pos); | |
fe96802b | 2051 | } |
a6c89e96 NQ |
2052 | pbi->s1_buf = buf; |
2053 | return ret; | |
2054 | } | |
2055 | ||
2056 | static void inc_s1_pos(struct VP9Decoder_s *pbi) | |
2057 | { | |
2058 | struct stage_buf_s *buf = | |
2059 | pbi->stage_bufs[pbi->s1_pos]; | |
2060 | ||
2061 | int used_page_num = | |
2062 | #ifdef FB_DECODING_TEST_SCHEDULE | |
2063 | MAX_STAGE_PAGE_NUM/2; | |
2064 | #else | |
2065 | (READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16); | |
2066 | #endif | |
2067 | decoder_mmu_box_free_idx_tail(pbi->mmu_box, | |
2068 | FRAME_BUFFERS + buf->index, used_page_num); | |
2069 | ||
2070 | pbi->s1_pos++; | |
2071 | if (pbi->s1_pos >= pbi->used_stage_buf_num) | |
2072 | pbi->s1_pos = 0; | |
2073 | ||
2074 | vp9_print(pbi, VP9_DEBUG_2_STAGE, | |
2075 | "%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n", | |
2076 | __func__, used_page_num, buf->index, | |
2077 | pbi->s1_pos, pbi->s2_pos); | |
2078 | } | |
2079 | ||
2080 | #define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos) | |
2081 | ||
2082 | static int get_s2_buf( | |
2083 | struct VP9Decoder_s *pbi) | |
2084 | { | |
2085 | int ret = -1; | |
2086 | struct stage_buf_s *buf = NULL; | |
2087 | if (s2_buf_available(pbi)) { | |
2088 | buf = pbi->stage_bufs[pbi->s2_pos]; | |
2089 | vp9_print(pbi, VP9_DEBUG_2_STAGE, | |
2090 | "%s for index %d (s1_pos %d s2_pos %d)\n", | |
2091 | __func__, buf->index, | |
2092 | pbi->s1_pos, pbi->s2_pos); | |
2093 | pbi->s2_buf = buf; | |
2094 | ret = 0; | |
2095 | } | |
2096 | return ret; | |
2097 | } | |
2098 | ||
2099 | static void inc_s2_pos(struct VP9Decoder_s *pbi) | |
2100 | { | |
2101 | struct stage_buf_s *buf = | |
2102 | pbi->stage_bufs[pbi->s2_pos]; | |
2103 | decoder_mmu_box_free_idx(pbi->mmu_box, | |
2104 | FRAME_BUFFERS + buf->index); | |
2105 | pbi->s2_pos++; | |
2106 | if (pbi->s2_pos >= pbi->used_stage_buf_num) | |
2107 | pbi->s2_pos = 0; | |
2108 | vp9_print(pbi, VP9_DEBUG_2_STAGE, | |
2109 | "%s for index %d (s1_pos %d s2_pos %d)\n", | |
2110 | __func__, buf->index, | |
2111 | pbi->s1_pos, pbi->s2_pos); | |
2112 | } | |
2113 | ||
2114 | static int get_free_stage_buf_num(struct VP9Decoder_s *pbi) | |
2115 | { | |
2116 | int num; | |
2117 | if (pbi->s1_pos >= pbi->s2_pos) | |
2118 | num = pbi->used_stage_buf_num - | |
2119 | (pbi->s1_pos - pbi->s2_pos) - 1; | |
2120 | else | |
2121 | num = (pbi->s2_pos - pbi->s1_pos) - 1; | |
2122 | return num; | |
2123 | } | |
2124 | ||
2125 | #ifndef FB_DECODING_TEST_SCHEDULE | |
2126 | static DEFINE_SPINLOCK(fb_core_spin_lock); | |
2127 | ||
2128 | static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi) | |
2129 | { | |
2130 | /* to do: VLSI review | |
2131 | completion of last LCU decoding in BACK | |
2132 | */ | |
2133 | return 1; | |
2134 | } | |
2135 | ||
2136 | static void start_s1_decoding(struct VP9Decoder_s *pbi) | |
2137 | { | |
2138 | /* to do: VLSI review | |
2139 | after parser, how to start LCU decoding in BACK | |
2140 | */ | |
fe96802b | 2141 | } |
a6c89e96 NQ |
2142 | |
2143 | static void fb_reset_core(struct vdec_s *vdec, u32 mask) | |
2144 | { | |
2145 | /* to do: VLSI review | |
2146 | 1. how to disconnect DMC for FRONT and BACK | |
2147 | 2. reset bit 13, 24, FRONT or BACK ?? | |
2148 | */ | |
2149 | ||
2150 | unsigned long flags; | |
2151 | u32 reset_bits = 0; | |
2152 | if (mask & HW_MASK_FRONT) | |
2153 | WRITE_VREG(HEVC_STREAM_CONTROL, 0); | |
2154 | spin_lock_irqsave(&fb_core_spin_lock, flags); | |
2155 | codec_dmcbus_write(DMC_REQ_CTRL, | |
2156 | codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4))); | |
2157 | spin_unlock_irqrestore(&fb_core_spin_lock, flags); | |
2158 | ||
2159 | while (!(codec_dmcbus_read(DMC_CHAN_STS) | |
2160 | & (1 << 4))) | |
2161 | ; | |
2162 | ||
2163 | if ((mask & HW_MASK_FRONT) && | |
2164 | input_frame_based(vdec)) | |
2165 | WRITE_VREG(HEVC_STREAM_CONTROL, 0); | |
2166 | ||
2167 | /* | |
2168 | * 2: assist | |
2169 | * 3: parser | |
2170 | * 4: parser_state | |
2171 | * 8: dblk | |
2172 | * 11:mcpu | |
2173 | * 12:ccpu | |
2174 | * 13:ddr | |
2175 | * 14:iqit | |
2176 | * 15:ipp | |
2177 | * 17:qdct | |
2178 | * 18:mpred | |
2179 | * 19:sao | |
2180 | * 24:hevc_afifo | |
2181 | */ | |
2182 | if (mask & HW_MASK_FRONT) { | |
2183 | reset_bits = | |
2184 | (1<<3)|(1<<4)|(1<<11)| | |
2185 | (1<<12)|(1<<18); | |
2186 | } | |
2187 | if (mask & HW_MASK_BACK) { | |
2188 | reset_bits = | |
2189 | (1<<8)|(1<<13)|(1<<14)|(1<<15)| | |
2190 | (1<<17)|(1<<19)|(1<<24); | |
2191 | } | |
2192 | WRITE_VREG(DOS_SW_RESET3, reset_bits); | |
2193 | #if 0 | |
2194 | (1<<3)|(1<<4)|(1<<8)|(1<<11)| | |
2195 | (1<<12)|(1<<13)|(1<<14)|(1<<15)| | |
2196 | (1<<17)|(1<<18)|(1<<19)|(1<<24); | |
2197 | #endif | |
2198 | WRITE_VREG(DOS_SW_RESET3, 0); | |
2199 | ||
2200 | ||
2201 | spin_lock_irqsave(&fb_core_spin_lock, flags); | |
2202 | codec_dmcbus_write(DMC_REQ_CTRL, | |
2203 | codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4)); | |
2204 | spin_unlock_irqrestore(&fb_core_spin_lock, flags); | |
2205 | ||
2206 | } | |
2207 | #endif | |
2208 | ||
fe96802b NQ |
2209 | #endif |
2210 | ||
0fb7e163 | 2211 | static void init_pic_list_hw(struct VP9Decoder_s *pbi); |
a6c89e96 | 2212 | |
fe96802b NQ |
2213 | static int get_free_fb(struct VP9Decoder_s *pbi) |
2214 | { | |
2215 | struct VP9_Common_s *const cm = &pbi->common; | |
2216 | struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; | |
2217 | int i; | |
2218 | unsigned long flags; | |
2219 | ||
2220 | lock_buffer_pool(cm->buffer_pool, flags); | |
2221 | if (debug & VP9_DEBUG_BUFMGR_MORE) { | |
2222 | for (i = 0; i < pbi->used_buf_num; ++i) { | |
2223 | pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n", | |
2224 | __func__, i, frame_bufs[i].ref_count, | |
2225 | frame_bufs[i].buf.vf_ref, | |
2226 | frame_bufs[i].buf.index); | |
2227 | } | |
2228 | } | |
2229 | for (i = 0; i < pbi->used_buf_num; ++i) { | |
2230 | if ((frame_bufs[i].ref_count == 0) && | |
b9ff7233 NQ |
2231 | (frame_bufs[i].buf.vf_ref == 0) && |
2232 | (frame_bufs[i].buf.index != -1) | |
2233 | ) | |
fe96802b NQ |
2234 | break; |
2235 | } | |
2236 | if (i != pbi->used_buf_num) { | |
2237 | frame_bufs[i].ref_count = 1; | |
2238 | /*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n", | |
2239 | i, frame_bufs[i].ref_count);*/ | |
2240 | } else { | |
2241 | /* Reset i to be INVALID_IDX to indicate | |
2242 | no free buffer found*/ | |
2243 | i = INVALID_IDX; | |
2244 | } | |
2245 | ||
2246 | unlock_buffer_pool(cm->buffer_pool, flags); | |
2247 | return i; | |
2248 | } | |
2249 | ||
b9ff7233 NQ |
2250 | static int v4l_get_free_fb(struct VP9Decoder_s *pbi) |
2251 | { | |
2252 | struct VP9_Common_s *const cm = &pbi->common; | |
2253 | struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; | |
2254 | struct aml_vcodec_ctx * v4l = pbi->v4l2_ctx; | |
02515e2a | 2255 | struct v4l_buff_pool *pool = &v4l->cap_pool; |
b9ff7233 NQ |
2256 | struct PIC_BUFFER_CONFIG_s *pic = NULL; |
2257 | int i, idx = INVALID_IDX; | |
2258 | ulong flags; | |
2259 | ||
2260 | lock_buffer_pool(cm->buffer_pool, flags); | |
2261 | ||
02515e2a | 2262 | for (i = 0; i < pool->in; ++i) { |
b9ff7233 NQ |
2263 | u32 state = (pool->seq[i] >> 16); |
2264 | u32 index = (pool->seq[i] & 0xffff); | |
2265 | ||
2266 | switch (state) { | |
2267 | case V4L_CAP_BUFF_IN_DEC: | |
2268 | pic = &frame_bufs[i].buf; | |
2269 | if ((frame_bufs[i].ref_count == 0) && | |
2270 | (pic->vf_ref == 0) && | |
2271 | (pic->index != -1) && | |
2272 | pic->cma_alloc_addr) { | |
2273 | idx = i; | |
2274 | } | |
2275 | break; | |
2276 | case V4L_CAP_BUFF_IN_M2M: | |
2277 | pic = &frame_bufs[index].buf; | |
2278 | pic->y_crop_width = pbi->frame_width; | |
2279 | pic->y_crop_height = pbi->frame_height; | |
2280 | if (!v4l_alloc_and_config_pic(pbi, pic)) { | |
2281 | set_canvas(pbi, pic); | |
2282 | init_pic_list_hw(pbi); | |
2283 | idx = index; | |
2284 | } | |
2285 | break; | |
2286 | default: | |
2287 | pr_err("v4l buffer state err %d.\n", state); | |
2288 | break; | |
2289 | } | |
2290 | ||
2291 | if (idx != INVALID_IDX) { | |
2292 | frame_bufs[idx].ref_count = 1; | |
2293 | break; | |
2294 | } | |
2295 | } | |
2296 | ||
2297 | unlock_buffer_pool(cm->buffer_pool, flags); | |
2298 | ||
2299 | return idx; | |
2300 | } | |
2301 | ||
fe96802b NQ |
2302 | static int get_free_buf_count(struct VP9Decoder_s *pbi) |
2303 | { | |
2304 | struct VP9_Common_s *const cm = &pbi->common; | |
2305 | struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; | |
2306 | int i; | |
2307 | int free_buf_count = 0; | |
2308 | for (i = 0; i < pbi->used_buf_num; ++i) | |
2309 | if ((frame_bufs[i].ref_count == 0) && | |
2310 | (frame_bufs[i].buf.vf_ref == 0) && | |
2311 | (frame_bufs[i].buf.index != -1) | |
2312 | ) | |
2313 | free_buf_count++; | |
2314 | return free_buf_count; | |
2315 | } | |
2316 | ||
b9164398 NQ |
2317 | static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs, |
2318 | struct BufferPool_s *const pool) | |
2319 | { | |
2320 | if (idx >= 0) { | |
2321 | --frame_bufs[idx].ref_count; | |
2322 | /*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx, | |
e0614bf7 ZZ |
2323 | * frame_bufs[idx].ref_count); |
2324 | */ | |
b9164398 | 2325 | /*A worker may only get a free framebuffer index when |
e0614bf7 ZZ |
2326 | *calling get_free_fb. But the private buffer is not set up |
2327 | *until finish decoding header. So any error happens during | |
2328 | *decoding header, the frame_bufs will not have valid priv | |
2329 | *buffer. | |
2330 | */ | |
b9164398 NQ |
2331 | |
2332 | if (frame_bufs[idx].ref_count == 0 && | |
2333 | frame_bufs[idx].raw_frame_buffer.priv) | |
2334 | vp9_release_frame_buffer | |
2335 | (&frame_bufs[idx].raw_frame_buffer); | |
2336 | } | |
2337 | } | |
2338 | ||
2339 | static void generate_next_ref_frames(struct VP9Decoder_s *pbi) | |
2340 | { | |
2341 | struct VP9_Common_s *const cm = &pbi->common; | |
2342 | struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; | |
2343 | struct BufferPool_s *const pool = cm->buffer_pool; | |
2344 | int mask, ref_index = 0; | |
fe96802b | 2345 | unsigned long flags; |
b9164398 NQ |
2346 | |
2347 | /* Generate next_ref_frame_map.*/ | |
fe96802b | 2348 | lock_buffer_pool(pool, flags); |
b9164398 NQ |
2349 | for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) { |
2350 | if (mask & 1) { | |
2351 | cm->next_ref_frame_map[ref_index] = cm->new_fb_idx; | |
2352 | ++frame_bufs[cm->new_fb_idx].ref_count; | |
2353 | /*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n", | |
e0614bf7 ZZ |
2354 | *cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count); |
2355 | */ | |
b9164398 NQ |
2356 | } else |
2357 | cm->next_ref_frame_map[ref_index] = | |
2358 | cm->ref_frame_map[ref_index]; | |
2359 | /* Current thread holds the reference frame.*/ | |
2360 | if (cm->ref_frame_map[ref_index] >= 0) { | |
2361 | ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count; | |
2362 | /*pr_info | |
e0614bf7 ZZ |
2363 | *("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n", |
2364 | *cm->ref_frame_map[ref_index], | |
2365 | *frame_bufs[cm->ref_frame_map[ref_index]].ref_count); | |
2366 | */ | |
b9164398 NQ |
2367 | } |
2368 | ++ref_index; | |
2369 | } | |
2370 | ||
2371 | for (; ref_index < REF_FRAMES; ++ref_index) { | |
2372 | cm->next_ref_frame_map[ref_index] = | |
2373 | cm->ref_frame_map[ref_index]; | |
2374 | /* Current thread holds the reference frame.*/ | |
2375 | if (cm->ref_frame_map[ref_index] >= 0) { | |
2376 | ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count; | |
2377 | /*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n", | |
e0614bf7 ZZ |
2378 | *cm->ref_frame_map[ref_index], |
2379 | *frame_bufs[cm->ref_frame_map[ref_index]].ref_count); | |
2380 | */ | |
b9164398 NQ |
2381 | } |
2382 | } | |
fe96802b | 2383 | unlock_buffer_pool(pool, flags); |
b9164398 NQ |
2384 | return; |
2385 | } | |
2386 | ||
2387 | static void refresh_ref_frames(struct VP9Decoder_s *pbi) | |
2388 | ||
2389 | { | |
2390 | struct VP9_Common_s *const cm = &pbi->common; | |
2391 | struct BufferPool_s *pool = cm->buffer_pool; | |
2392 | struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; | |
2393 | int mask, ref_index = 0; | |
fe96802b | 2394 | unsigned long flags; |
b9164398 | 2395 | |
fe96802b | 2396 | lock_buffer_pool(pool, flags); |
b9164398 NQ |
2397 | for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) { |
2398 | const int old_idx = cm->ref_frame_map[ref_index]; | |
2399 | /*Current thread releases the holding of reference frame.*/ | |
2400 | decrease_ref_count(old_idx, frame_bufs, pool); | |
2401 | ||
2402 | /*Release the reference frame in reference map.*/ | |
2403 | if ((mask & 1) && old_idx >= 0) | |
2404 | decrease_ref_count(old_idx, frame_bufs, pool); | |
2405 | cm->ref_frame_map[ref_index] = | |
2406 | cm->next_ref_frame_map[ref_index]; | |
2407 | ++ref_index; | |
2408 | } | |
2409 | ||
2410 | /*Current thread releases the holding of reference frame.*/ | |
2411 | for (; ref_index < REF_FRAMES && !cm->show_existing_frame; | |
2412 | ++ref_index) { | |
2413 | const int old_idx = cm->ref_frame_map[ref_index]; | |
e0614bf7 | 2414 | |
b9164398 NQ |
2415 | decrease_ref_count(old_idx, frame_bufs, pool); |
2416 | cm->ref_frame_map[ref_index] = | |
2417 | cm->next_ref_frame_map[ref_index]; | |
2418 | } | |
fe96802b | 2419 | unlock_buffer_pool(pool, flags); |
b9164398 NQ |
2420 | return; |
2421 | } | |
b7706e1e | 2422 | |
b9164398 NQ |
2423 | int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params) |
2424 | { | |
2425 | struct VP9_Common_s *const cm = &pbi->common; | |
2426 | struct BufferPool_s *pool = cm->buffer_pool; | |
2427 | struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; | |
0fb7e163 | 2428 | struct PIC_BUFFER_CONFIG_s *pic = NULL; |
b9164398 NQ |
2429 | int i; |
2430 | int ret; | |
2431 | ||
2432 | pbi->ready_for_new_data = 0; | |
2433 | ||
2434 | if (pbi->has_keyframe == 0 && | |
2435 | params->p.frame_type != KEY_FRAME){ | |
2436 | on_no_keyframe_skiped++; | |
2437 | return -2; | |
2438 | } | |
2439 | pbi->has_keyframe = 1; | |
2440 | on_no_keyframe_skiped = 0; | |
b7706e1e | 2441 | #if 0 |
2442 | if (pbi->mmu_enable) { | |
2443 | if (!pbi->m_ins_flag) | |
2444 | pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); | |
2445 | if (cm->prev_fb_idx >= 0) { | |
2446 | decoder_mmu_box_free_idx_tail(pbi->mmu_box, | |
2447 | cm->prev_fb_idx, pbi->used_4k_num); | |
2448 | } | |
a6c89e96 NQ |
2449 | } |
2450 | #endif | |
b9164398 NQ |
2451 | if (cm->new_fb_idx >= 0 |
2452 | && frame_bufs[cm->new_fb_idx].ref_count == 0){ | |
2453 | vp9_release_frame_buffer | |
2454 | (&frame_bufs[cm->new_fb_idx].raw_frame_buffer); | |
2455 | } | |
2456 | /*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n", | |
2457 | cm->prev_fb_idx, cm->new_fb_idx);*/ | |
fe96802b NQ |
2458 | #ifndef MV_USE_FIXED_BUF |
2459 | put_un_used_mv_bufs(pbi); | |
2460 | if (debug & VP9_DEBUG_BUFMGR_DETAIL) | |
2461 | dump_pic_list(pbi); | |
2462 | #endif | |
b9ff7233 NQ |
2463 | cm->new_fb_idx = pbi->is_used_v4l ? |
2464 | v4l_get_free_fb(pbi) : | |
2465 | get_free_fb(pbi); | |
b9164398 NQ |
2466 | if (cm->new_fb_idx == INVALID_IDX) { |
2467 | pr_info("get_free_fb error\r\n"); | |
2468 | return -1; | |
2469 | } | |
677ab50d | 2470 | |
fe96802b | 2471 | #ifndef MV_USE_FIXED_BUF |
a6c89e96 NQ |
2472 | #ifdef SUPPORT_FB_DECODING |
2473 | if (pbi->used_stage_buf_num == 0) { | |
2474 | #endif | |
2475 | if (get_mv_buf(pbi, | |
2476 | &pool->frame_bufs[cm->new_fb_idx]. | |
2477 | buf.mv_buf_index, | |
2478 | &pool->frame_bufs[cm->new_fb_idx]. | |
2479 | buf.mpred_mv_wr_start_addr | |
2480 | ) < 0) { | |
2481 | pr_info("get_mv_buf fail\r\n"); | |
2482 | return -1; | |
2483 | } | |
2484 | if (debug & VP9_DEBUG_BUFMGR_DETAIL) | |
2485 | dump_pic_list(pbi); | |
2486 | #ifdef SUPPORT_FB_DECODING | |
fe96802b | 2487 | } |
a6c89e96 | 2488 | #endif |
fe96802b NQ |
2489 | #endif |
2490 | cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx]; | |
2491 | /*if (debug & VP9_DEBUG_BUFMGR) | |
2492 | pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__, | |
2493 | cm->new_fb_idx);*/ | |
2494 | ||
b9164398 | 2495 | pbi->cur_buf = &frame_bufs[cm->new_fb_idx]; |
b7706e1e | 2496 | if (pbi->mmu_enable) { |
2497 | /* moved to after picture size ready | |
2498 | *alloc_mmu(cm, params->p.width, params->p.height, | |
2499 | *params->p.bit_depth, pbi->frame_mmu_map_addr); | |
2500 | */ | |
2501 | cm->prev_fb_idx = cm->new_fb_idx; | |
2502 | } | |
b9164398 NQ |
2503 | /*read_uncompressed_header()*/ |
2504 | cm->last_frame_type = cm->frame_type; | |
2505 | cm->last_intra_only = cm->intra_only; | |
2506 | cm->profile = params->p.profile; | |
2507 | if (cm->profile >= MAX_PROFILES) { | |
2508 | pr_err("Error: Unsupported profile %d\r\n", cm->profile); | |
2509 | return -1; | |
2510 | } | |
2511 | cm->show_existing_frame = params->p.show_existing_frame; | |
2512 | if (cm->show_existing_frame) { | |
2513 | /* Show an existing frame directly.*/ | |
2514 | int frame_to_show_idx = params->p.frame_to_show_idx; | |
2515 | int frame_to_show; | |
fe96802b | 2516 | unsigned long flags; |
b9164398 NQ |
2517 | if (frame_to_show_idx >= REF_FRAMES) { |
2518 | pr_info("frame_to_show_idx %d exceed max index\r\n", | |
2519 | frame_to_show_idx); | |
2520 | return -1; | |
2521 | } | |
2522 | ||
2523 | frame_to_show = cm->ref_frame_map[frame_to_show_idx]; | |
2524 | /*pr_info("frame_to_show %d\r\n", frame_to_show);*/ | |
fe96802b | 2525 | lock_buffer_pool(pool, flags); |
b9164398 NQ |
2526 | if (frame_to_show < 0 || |
2527 | frame_bufs[frame_to_show].ref_count < 1) { | |
fe96802b | 2528 | unlock_buffer_pool(pool, flags); |
b9164398 NQ |
2529 | pr_err |
2530 | ("Error:Buffer %d does not contain a decoded frame", | |
2531 | frame_to_show); | |
2532 | return -1; | |
2533 | } | |
2534 | ||
2535 | ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show); | |
fe96802b | 2536 | unlock_buffer_pool(pool, flags); |
b9164398 NQ |
2537 | pbi->refresh_frame_flags = 0; |
2538 | /*cm->lf.filter_level = 0;*/ | |
2539 | cm->show_frame = 1; | |
2540 | ||
2541 | /* | |
e0614bf7 ZZ |
2542 | *if (pbi->frame_parallel_decode) { |
2543 | * for (i = 0; i < REF_FRAMES; ++i) | |
2544 | * cm->next_ref_frame_map[i] = | |
2545 | * cm->ref_frame_map[i]; | |
2546 | *} | |
2547 | */ | |
b9164398 NQ |
2548 | /* do not decode, search next start code */ |
2549 | return 1; | |
2550 | } | |
2551 | cm->frame_type = params->p.frame_type; | |
2552 | cm->show_frame = params->p.show_frame; | |
677ab50d | 2553 | cm->bit_depth = params->p.bit_depth; |
b9164398 NQ |
2554 | cm->error_resilient_mode = params->p.error_resilient_mode; |
2555 | ||
2556 | ||
2557 | if (cm->frame_type == KEY_FRAME) { | |
2558 | pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1; | |
2559 | ||
2560 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
2561 | cm->frame_refs[i].idx = INVALID_IDX; | |
2562 | cm->frame_refs[i].buf = NULL; | |
2563 | } | |
2564 | ||
2565 | ret = setup_frame_size(pbi, | |
2566 | cm, params, pbi->frame_mmu_map_addr, | |
2567 | print_header_info); | |
2568 | if (ret) | |
2569 | return -1; | |
2570 | if (pbi->need_resync) { | |
2571 | memset(&cm->ref_frame_map, -1, | |
2572 | sizeof(cm->ref_frame_map)); | |
2573 | pbi->need_resync = 0; | |
2574 | } | |
2575 | } else { | |
2576 | cm->intra_only = cm->show_frame ? 0 : params->p.intra_only; | |
2577 | /*if (print_header_info) { | |
e0614bf7 ZZ |
2578 | * if (cm->show_frame) |
2579 | * pr_info | |
2580 | * ("intra_only set to 0 because of show_frame\n"); | |
2581 | * else | |
2582 | * pr_info | |
2583 | * ("1-bit intra_only read: %d\n", cm->intra_only); | |
2584 | *} | |
2585 | */ | |
b9164398 NQ |
2586 | |
2587 | ||
2588 | cm->reset_frame_context = cm->error_resilient_mode ? | |
2589 | 0 : params->p.reset_frame_context; | |
2590 | if (print_header_info) { | |
2591 | if (cm->error_resilient_mode) | |
2592 | pr_info | |
2593 | ("reset to 0 error_resilient_mode\n"); | |
2594 | else | |
2595 | pr_info | |
2596 | (" * 2-bits reset_frame_context read : %d\n", | |
2597 | cm->reset_frame_context); | |
2598 | } | |
2599 | ||
2600 | if (cm->intra_only) { | |
2601 | if (cm->profile > PROFILE_0) { | |
2602 | /*read_bitdepth_colorspace_sampling(cm, | |
e0614bf7 ZZ |
2603 | * rb, print_header_info); |
2604 | */ | |
b9164398 NQ |
2605 | } else { |
2606 | /*NOTE: The intra-only frame header | |
e0614bf7 ZZ |
2607 | *does not include the specification |
2608 | *of either the color format or | |
2609 | *color sub-sampling | |
2610 | *in profile 0. VP9 specifies that the default | |
2611 | *color format should be YUV 4:2:0 in this | |
2612 | *case (normative). | |
2613 | */ | |
b9164398 NQ |
2614 | cm->color_space = VPX_CS_BT_601; |
2615 | cm->subsampling_y = cm->subsampling_x = 1; | |
2616 | cm->bit_depth = VPX_BITS_8; | |
2617 | cm->use_highbitdepth = 0; | |
2618 | } | |
2619 | ||
2620 | pbi->refresh_frame_flags = | |
2621 | params->p.refresh_frame_flags; | |
2622 | /*if (print_header_info) | |
e0614bf7 ZZ |
2623 | * pr_info("*%d-bits refresh_frame read:0x%x\n", |
2624 | * REF_FRAMES, pbi->refresh_frame_flags); | |
2625 | */ | |
b9164398 NQ |
2626 | ret = setup_frame_size(pbi, |
2627 | cm, | |
2628 | params, | |
2629 | pbi->frame_mmu_map_addr, | |
2630 | print_header_info); | |
e0614bf7 | 2631 | if (ret) |
b9164398 | 2632 | return -1; |
b9164398 NQ |
2633 | if (pbi->need_resync) { |
2634 | memset(&cm->ref_frame_map, -1, | |
2635 | sizeof(cm->ref_frame_map)); | |
2636 | pbi->need_resync = 0; | |
2637 | } | |
2638 | } else if (pbi->need_resync != 1) { /* Skip if need resync */ | |
e0614bf7 ZZ |
2639 | pbi->refresh_frame_flags = |
2640 | params->p.refresh_frame_flags; | |
2641 | if (print_header_info) | |
2642 | pr_info | |
2643 | ("*%d-bits refresh_frame read:0x%x\n", | |
2644 | REF_FRAMES, pbi->refresh_frame_flags); | |
2645 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
2646 | const int ref = | |
2647 | (params->p.ref_info >> | |
2648 | (((REFS_PER_FRAME-i-1)*4)+1)) | |
2649 | & 0x7; | |
2650 | const int idx = | |
2651 | cm->ref_frame_map[ref]; | |
2652 | struct RefBuffer_s * const ref_frame = | |
2653 | &cm->frame_refs[i]; | |
b9164398 | 2654 | if (print_header_info) |
e0614bf7 | 2655 | pr_info("*%d-bits ref[%d]read:%d\n", |
b9164398 | 2656 | REF_FRAMES_LOG2, i, ref); |
e0614bf7 ZZ |
2657 | ref_frame->idx = idx; |
2658 | ref_frame->buf = &frame_bufs[idx].buf; | |
2659 | cm->ref_frame_sign_bias[LAST_FRAME + i] | |
2660 | = (params->p.ref_info >> | |
2661 | ((REFS_PER_FRAME-i-1)*4)) & 0x1; | |
2662 | if (print_header_info) | |
2663 | pr_info("1bit ref_frame_sign_bias"); | |
2664 | /*pr_info | |
2665 | *("%dread: %d\n", | |
2666 | *LAST_FRAME+i, | |
2667 | *cm->ref_frame_sign_bias | |
2668 | *[LAST_FRAME + i]); | |
2669 | */ | |
2670 | /*pr_info | |
2671 | *("[VP9 DEBUG]%s(get ref):%d\r\n", | |
2672 | *__func__, ref_frame->idx); | |
2673 | */ | |
b9164398 | 2674 | |
e0614bf7 | 2675 | } |
b9164398 | 2676 | |
e0614bf7 ZZ |
2677 | ret = setup_frame_size_with_refs( |
2678 | pbi, | |
2679 | cm, | |
2680 | params, | |
2681 | pbi->frame_mmu_map_addr, | |
2682 | print_header_info); | |
2683 | if (ret) | |
2684 | return -1; | |
2685 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
2686 | /*struct RefBuffer_s *const ref_buf = | |
2687 | *&cm->frame_refs[i]; | |
2688 | */ | |
2689 | /* to do: | |
2690 | *vp9_setup_scale_factors_for_frame | |
2691 | */ | |
2692 | } | |
b9164398 NQ |
2693 | } |
2694 | } | |
2695 | ||
0fb7e163 NQ |
2696 | pic = get_frame_new_buffer(cm); |
2697 | if (!pic) | |
2698 | return -1; | |
2699 | ||
2700 | pic->bit_depth = cm->bit_depth; | |
2701 | pic->color_space = cm->color_space; | |
2702 | pic->slice_type = cm->frame_type; | |
b9164398 | 2703 | |
fe96802b | 2704 | if (pbi->need_resync) { |
b9164398 NQ |
2705 | pr_err |
2706 | ("Error: Keyframe/intra-only frame required to reset\r\n"); | |
fe96802b NQ |
2707 | return -1; |
2708 | } | |
b9164398 NQ |
2709 | generate_next_ref_frames(pbi); |
2710 | pbi->hold_ref_buf = 1; | |
2711 | ||
2712 | #if 0 | |
2713 | if (frame_is_intra_only(cm) || cm->error_resilient_mode) | |
2714 | vp9_setup_past_independence(cm); | |
2715 | setup_loopfilter(&cm->lf, rb, print_header_info); | |
2716 | setup_quantization(cm, &pbi->mb, rb, print_header_info); | |
2717 | setup_segmentation(&cm->seg, rb, print_header_info); | |
2718 | setup_segmentation_dequant(cm, print_header_info); | |
2719 | ||
2720 | setup_tile_info(cm, rb, print_header_info); | |
2721 | sz = vp9_rb_read_literal(rb, 16); | |
2722 | if (print_header_info) | |
2723 | pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz); | |
2724 | ||
2725 | if (sz == 0) | |
2726 | vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME, | |
2727 | "Invalid header size"); | |
2728 | #endif | |
2729 | /*end read_uncompressed_header()*/ | |
2730 | cm->use_prev_frame_mvs = !cm->error_resilient_mode && | |
2731 | cm->width == cm->last_width && | |
2732 | cm->height == cm->last_height && | |
2733 | !cm->last_intra_only && | |
2734 | cm->last_show_frame && | |
2735 | (cm->last_frame_type != KEY_FRAME); | |
2736 | ||
2737 | /*pr_info | |
e0614bf7 ZZ |
2738 | *("set use_prev_frame_mvs to %d (last_width %d last_height %d", |
2739 | *cm->use_prev_frame_mvs, cm->last_width, cm->last_height); | |
2740 | *pr_info | |
2741 | *(" last_intra_only %d last_show_frame %d last_frame_type %d)\n", | |
2742 | *cm->last_intra_only, cm->last_show_frame, cm->last_frame_type); | |
2743 | */ | |
677ab50d NQ |
2744 | |
2745 | if (pbi->enable_fence && cm->show_frame) { | |
2746 | struct PIC_BUFFER_CONFIG_s *pic = &cm->cur_frame->buf; | |
2747 | struct vdec_s *vdec = hw_to_vdec(pbi); | |
2748 | ||
2749 | /* create fence for each buffers. */ | |
2750 | ret = vdec_timeline_create_fence(&vdec->sync); | |
2751 | if (ret < 0) | |
2752 | return ret; | |
2753 | ||
2754 | pic->fence = vdec->sync.fence; | |
2755 | pic->bit_depth = cm->bit_depth; | |
2756 | pic->slice_type = cm->frame_type; | |
2757 | pic->stream_offset = pbi->pre_stream_offset; | |
2758 | ||
2759 | if (pbi->chunk) { | |
2760 | pic->pts = pbi->chunk->pts; | |
2761 | pic->pts64 = pbi->chunk->pts64; | |
2762 | pic->timestamp = pbi->chunk->timestamp; | |
2763 | } | |
2764 | ||
2765 | /* post video vframe. */ | |
2766 | prepare_display_buf(pbi, pic); | |
2767 | } | |
2768 | ||
b9164398 NQ |
2769 | return 0; |
2770 | } | |
2771 | ||
2772 | ||
2773 | void swap_frame_buffers(struct VP9Decoder_s *pbi) | |
2774 | { | |
2775 | int ref_index = 0; | |
2776 | struct VP9_Common_s *const cm = &pbi->common; | |
2777 | struct BufferPool_s *const pool = cm->buffer_pool; | |
2778 | struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; | |
fe96802b | 2779 | unsigned long flags; |
b9164398 NQ |
2780 | refresh_ref_frames(pbi); |
2781 | pbi->hold_ref_buf = 0; | |
2782 | cm->frame_to_show = get_frame_new_buffer(cm); | |
2783 | ||
0fb7e163 NQ |
2784 | if (cm->frame_to_show) { |
2785 | /*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/ | |
2786 | lock_buffer_pool(pool, flags); | |
2787 | --frame_bufs[cm->new_fb_idx].ref_count; | |
2788 | /*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx, | |
2789 | * frame_bufs[cm->new_fb_idx].ref_count); | |
2790 | */ | |
2791 | unlock_buffer_pool(pool, flags); | |
2792 | /*}*/ | |
2793 | } | |
b9164398 NQ |
2794 | |
2795 | /*Invalidate these references until the next frame starts.*/ | |
2796 | for (ref_index = 0; ref_index < 3; ref_index++) | |
2797 | cm->frame_refs[ref_index].idx = -1; | |
2798 | } | |
2799 | ||
2800 | #if 0 | |
2801 | static void check_resync(vpx_codec_alg_priv_t *const ctx, | |
2802 | const struct VP9Decoder_s *const pbi) | |
2803 | { | |
2804 | /* Clear resync flag if worker got a key frame or intra only frame.*/ | |
2805 | if (ctx->need_resync == 1 && pbi->need_resync == 0 && | |
2806 | (pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME)) | |
2807 | ctx->need_resync = 0; | |
2808 | } | |
2809 | #endif | |
2810 | ||
2811 | int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd) | |
2812 | { | |
2813 | struct VP9_Common_s *const cm = &pbi->common; | |
2814 | int ret = -1; | |
2815 | ||
2816 | if (pbi->ready_for_new_data == 1) | |
2817 | return ret; | |
2818 | ||
2819 | pbi->ready_for_new_data = 1; | |
2820 | ||
2821 | /* no raw frame to show!!! */ | |
2822 | if (!cm->show_frame) | |
2823 | return ret; | |
2824 | ||
0fb7e163 NQ |
2825 | /* may not be get buff in v4l2 */ |
2826 | if (!cm->frame_to_show) | |
2827 | return ret; | |
2828 | ||
b9164398 NQ |
2829 | pbi->ready_for_new_data = 1; |
2830 | ||
2831 | *sd = *cm->frame_to_show; | |
2832 | ret = 0; | |
2833 | ||
2834 | return ret; | |
2835 | } | |
2836 | ||
2837 | int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i, | |
2838 | struct buff_s *mc_buf_i) { | |
2839 | struct VP9_Common_s *cm = &pbi->common; | |
2840 | ||
a674e3cd | 2841 | /*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/ |
b9164398 NQ |
2842 | pbi->frame_count = 0; |
2843 | pbi->pic_count = 0; | |
2844 | pbi->pre_stream_offset = 0; | |
2845 | cm->buffer_pool = &pbi->vp9_buffer_pool; | |
2846 | spin_lock_init(&cm->buffer_pool->lock); | |
2847 | cm->prev_fb_idx = INVALID_IDX; | |
2848 | cm->new_fb_idx = INVALID_IDX; | |
fe96802b NQ |
2849 | pbi->used_4k_num = -1; |
2850 | cm->cur_fb_idx_mmu = INVALID_IDX; | |
5b851ff9 | 2851 | pr_debug |
b9164398 NQ |
2852 | ("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n", |
2853 | cm->prev_fb_idx, cm->new_fb_idx); | |
2854 | pbi->need_resync = 1; | |
2855 | /* Initialize the references to not point to any frame buffers.*/ | |
2856 | memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map)); | |
2857 | memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map)); | |
2858 | cm->current_video_frame = 0; | |
2859 | pbi->ready_for_new_data = 1; | |
2860 | ||
2861 | /* private init */ | |
2862 | pbi->work_space_buf = buf_spec_i; | |
b7706e1e | 2863 | if (!pbi->mmu_enable) |
2864 | pbi->mc_buf = mc_buf_i; | |
2865 | ||
b9164398 NQ |
2866 | pbi->rpm_addr = NULL; |
2867 | pbi->lmem_addr = NULL; | |
2868 | ||
2869 | pbi->use_cma_flag = 0; | |
2870 | pbi->decode_idx = 0; | |
2871 | pbi->slice_idx = 0; | |
2872 | /*int m_uiMaxCUWidth = 1<<7;*/ | |
2873 | /*int m_uiMaxCUHeight = 1<<7;*/ | |
2874 | pbi->has_keyframe = 0; | |
2875 | pbi->skip_flag = 0; | |
2876 | pbi->wait_buf = 0; | |
2877 | pbi->error_flag = 0; | |
2878 | ||
2879 | pbi->pts_mode = PTS_NORMAL; | |
2880 | pbi->last_pts = 0; | |
2881 | pbi->last_lookup_pts = 0; | |
2882 | pbi->last_pts_us64 = 0; | |
2883 | pbi->last_lookup_pts_us64 = 0; | |
2884 | pbi->shift_byte_count = 0; | |
2885 | pbi->shift_byte_count_lo = 0; | |
2886 | pbi->shift_byte_count_hi = 0; | |
2887 | pbi->pts_mode_switching_count = 0; | |
2888 | pbi->pts_mode_recovery_count = 0; | |
2889 | ||
2890 | pbi->buf_num = 0; | |
2891 | pbi->pic_num = 0; | |
2892 | ||
2893 | return 0; | |
2894 | } | |
2895 | ||
b9164398 NQ |
2896 | int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi) |
2897 | { | |
677ab50d | 2898 | struct vdec_s *vdec = hw_to_vdec(pbi); |
b9164398 NQ |
2899 | struct VP9_Common_s *cm = &pbi->common; |
2900 | struct PIC_BUFFER_CONFIG_s sd; | |
e0614bf7 | 2901 | |
187af067 | 2902 | if (pbi->postproc_done) |
2903 | return 0; | |
2904 | pbi->postproc_done = 1; | |
b9164398 NQ |
2905 | swap_frame_buffers(pbi); |
2906 | if (!cm->show_existing_frame) { | |
2907 | cm->last_show_frame = cm->show_frame; | |
2908 | cm->prev_frame = cm->cur_frame; | |
2909 | #if 0 | |
2910 | if (cm->seg.enabled && !pbi->frame_parallel_decode) | |
2911 | vp9_swap_current_and_last_seg_map(cm); | |
2912 | #endif | |
2913 | } | |
2914 | cm->last_width = cm->width; | |
2915 | cm->last_height = cm->height; | |
2916 | if (cm->show_frame) | |
2917 | cm->current_video_frame++; | |
2918 | ||
2919 | if (vp9_get_raw_frame(pbi, &sd) == 0) { | |
2920 | /*pr_info("Display frame index %d\r\n", sd.index);*/ | |
2921 | sd.stream_offset = pbi->pre_stream_offset; | |
677ab50d NQ |
2922 | |
2923 | if (pbi->enable_fence) { | |
2924 | /* notify signal to wake up wq of fence. */ | |
2925 | vdec_timeline_increase(&vdec->sync, 1); | |
2926 | } else { | |
2927 | prepare_display_buf(pbi, &sd); | |
2928 | } | |
2929 | ||
b9164398 | 2930 | pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT); |
e0614bf7 ZZ |
2931 | } |
2932 | ||
2933 | /* else | |
2934 | * pr_info | |
2935 | * ("Not display this frame,ready_for_new_data%d show_frame%d\r\n", | |
2936 | * pbi->ready_for_new_data, cm->show_frame); | |
2937 | */ | |
b9164398 NQ |
2938 | return 0; |
2939 | } | |
2940 | ||
b9164398 | 2941 | /************************************************** |
e0614bf7 ZZ |
2942 | * |
2943 | *VP9 buffer management end | |
2944 | * | |
2945 | *************************************************** | |
2946 | */ | |
b9164398 NQ |
2947 | |
2948 | ||
2949 | #define HEVC_CM_BODY_START_ADDR 0x3626 | |
2950 | #define HEVC_CM_BODY_LENGTH 0x3627 | |
2951 | #define HEVC_CM_HEADER_LENGTH 0x3629 | |
2952 | #define HEVC_CM_HEADER_OFFSET 0x362b | |
2953 | ||
2954 | #define LOSLESS_COMPRESS_MODE | |
b9164398 NQ |
2955 | |
2956 | /*#define DECOMP_HEADR_SURGENT*/ | |
3a5df697 | 2957 | #ifdef VP9_10B_NV21 |
2958 | static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/ | |
2959 | #else | |
b9164398 | 2960 | static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */ |
3a5df697 | 2961 | #endif |
b9164398 NQ |
2962 | static u32 enable_mem_saving = 1; |
2963 | static u32 force_w_h; | |
2964 | ||
2965 | static u32 force_fps; | |
2966 | ||
2967 | ||
2968 | const u32 vp9_version = 201602101; | |
2969 | static u32 debug; | |
2970 | static u32 radr; | |
2971 | static u32 rval; | |
2972 | static u32 pop_shorts; | |
2973 | static u32 dbg_cmd; | |
2974 | static u32 dbg_skip_decode_index; | |
2975 | static u32 endian = 0xff0; | |
2976 | #ifdef ERROR_HANDLE_DEBUG | |
2977 | static u32 dbg_nal_skip_flag; | |
2978 | /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */ | |
2979 | static u32 dbg_nal_skip_count; | |
2980 | #endif | |
2981 | /*for debug*/ | |
b9164398 NQ |
2982 | static u32 decode_pic_begin; |
2983 | static uint slice_parse_begin; | |
2984 | static u32 step; | |
2985 | #ifdef MIX_STREAM_SUPPORT | |
b9164398 NQ |
2986 | static u32 buf_alloc_width = 4096; |
2987 | static u32 buf_alloc_height = 2304; | |
a6c89e96 NQ |
2988 | static u32 vp9_max_pic_w = 4096; |
2989 | static u32 vp9_max_pic_h = 2304; | |
a6c89e96 | 2990 | |
b9164398 NQ |
2991 | static u32 dynamic_buf_num_margin; |
2992 | #else | |
2993 | static u32 buf_alloc_width; | |
2994 | static u32 buf_alloc_height; | |
2995 | static u32 dynamic_buf_num_margin = 7; | |
2996 | #endif | |
2997 | static u32 buf_alloc_depth = 10; | |
2998 | static u32 buf_alloc_size; | |
2999 | /* | |
e0614bf7 ZZ |
3000 | *bit[0]: 0, |
3001 | * bit[1]: 0, always release cma buffer when stop | |
3002 | * bit[1]: 1, never release cma buffer when stop | |
3003 | *bit[0]: 1, when stop, release cma buffer if blackout is 1; | |
3004 | *do not release cma buffer is blackout is not 1 | |
3005 | * | |
3006 | *bit[2]: 0, when start decoding, check current displayed buffer | |
3007 | * (only for buffer decoded by vp9) if blackout is 0 | |
3008 | * 1, do not check current displayed buffer | |
3009 | * | |
3010 | *bit[3]: 1, if blackout is not 1, do not release current | |
3011 | * displayed cma buffer always. | |
3012 | */ | |
b9164398 | 3013 | /* set to 1 for fast play; |
e0614bf7 ZZ |
3014 | * set to 8 for other case of "keep last frame" |
3015 | */ | |
b9164398 NQ |
3016 | static u32 buffer_mode = 1; |
3017 | /* buffer_mode_dbg: debug only*/ | |
3018 | static u32 buffer_mode_dbg = 0xffff0000; | |
3019 | /**/ | |
3020 | ||
3021 | /* | |
e0614bf7 ZZ |
3022 | *bit 0, 1: only display I picture; |
3023 | *bit 1, 1: only decode I picture; | |
3024 | */ | |
b9164398 NQ |
3025 | static u32 i_only_flag; |
3026 | ||
187af067 | 3027 | static u32 low_latency_flag; |
b9164398 | 3028 | |
0eb79ad7 RZ |
3029 | static u32 no_head; |
3030 | ||
b9164398 NQ |
3031 | static u32 max_decoding_time; |
3032 | /* | |
e0614bf7 ZZ |
3033 | *error handling |
3034 | */ | |
b9164398 | 3035 | /*error_handle_policy: |
e0614bf7 ZZ |
3036 | *bit 0: 0, auto skip error_skip_nal_count nals before error recovery; |
3037 | *1, skip error_skip_nal_count nals before error recovery; | |
3038 | *bit 1 (valid only when bit0 == 1): | |
3039 | *1, wait vps/sps/pps after error recovery; | |
3040 | *bit 2 (valid only when bit0 == 0): | |
3041 | *0, auto search after error recovery (vp9_recover() called); | |
3042 | *1, manual search after error recovery | |
3043 | *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2)) | |
3044 | * | |
3045 | *bit 4: 0, set error_mark after reset/recover | |
3046 | * 1, do not set error_mark after reset/recover | |
3047 | *bit 5: 0, check total lcu for every picture | |
3048 | * 1, do not check total lcu | |
3049 | * | |
3050 | */ | |
b9164398 NQ |
3051 | |
3052 | static u32 error_handle_policy; | |
3053 | /*static u32 parser_sei_enable = 1;*/ | |
dfe41deb RZ |
3054 | #define MAX_BUF_NUM_NORMAL 12 |
3055 | #define MAX_BUF_NUM_LESS 10 | |
3056 | static u32 max_buf_num = MAX_BUF_NUM_NORMAL; | |
3057 | #define MAX_BUF_NUM_SAVE_BUF 8 | |
b9164398 | 3058 | |
fe96802b | 3059 | static u32 run_ready_min_buf_num = 2; |
b9164398 | 3060 | |
a5c5bec0 | 3061 | |
b9164398 NQ |
3062 | static DEFINE_MUTEX(vvp9_mutex); |
3063 | #ifndef MULTI_INSTANCE_SUPPORT | |
3064 | static struct device *cma_dev; | |
3065 | #endif | |
3066 | ||
3067 | #define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0 | |
3068 | #define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1 | |
3069 | #define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2 | |
3070 | #define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3 | |
3071 | #define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4 | |
3072 | #define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5 | |
3073 | #define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6 | |
3074 | #define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7 | |
3075 | #define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8 | |
3076 | #define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9 | |
3077 | #define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A | |
3078 | #define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B | |
3079 | #define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D | |
3080 | #define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E | |
3081 | #define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F | |
3082 | #define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F | |
3083 | #define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L | |
3084 | #ifdef MULTI_INSTANCE_SUPPORT | |
3085 | #define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M | |
3086 | #define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N | |
3087 | #else | |
3088 | #define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M | |
3089 | #define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N | |
3090 | #endif | |
3091 | #define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G | |
3092 | #define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H | |
3093 | ||
3094 | ||
3095 | /* | |
e0614bf7 ZZ |
3096 | *ucode parser/search control |
3097 | *bit 0: 0, header auto parse; 1, header manual parse | |
3098 | *bit 1: 0, auto skip for noneseamless stream; 1, no skip | |
3099 | *bit [3:2]: valid when bit1==0; | |
3100 | *0, auto skip nal before first vps/sps/pps/idr; | |
3101 | *1, auto skip nal before first vps/sps/pps | |
3102 | *2, auto skip nal before first vps/sps/pps, | |
3103 | * and not decode until the first I slice (with slice address of 0) | |
3104 | * | |
3105 | *3, auto skip before first I slice (nal_type >=16 && nal_type<=21) | |
3106 | *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) ) | |
3107 | *bit [16]: for NAL_UNIT_EOS when bit0 is 0: | |
3108 | * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm | |
3109 | *bit [17]: for NAL_SEI when bit0 is 0: | |
3110 | * 0, do not parse SEI in ucode; 1, parse SEI in ucode | |
3111 | *bit [31:20]: used by ucode for debug purpose | |
3112 | */ | |
b9164398 | 3113 | #define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I |
a6c89e96 NQ |
3114 | /*[31:24] chip feature |
3115 | 31: 0, use MBOX1; 1, use MBOX0 | |
3116 | */ | |
b9164398 NQ |
3117 | #define DECODE_MODE HEVC_ASSIST_SCRATCH_J |
3118 | #define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K | |
3119 | ||
3120 | #ifdef MULTI_INSTANCE_SUPPORT | |
3121 | #define RPM_BUF_SIZE (0x400 * 2) | |
3122 | #else | |
3123 | #define RPM_BUF_SIZE (0x80*2) | |
3124 | #endif | |
3125 | #define LMEM_BUF_SIZE (0x400 * 2) | |
3126 | ||
df841122 | 3127 | #define WORK_BUF_SPEC_NUM 3 |
b9164398 NQ |
3128 | static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = { |
3129 | { | |
3130 | /* 8M bytes */ | |
3131 | .max_width = 1920, | |
3132 | .max_height = 1088, | |
3133 | .ipp = { | |
3134 | /* IPP work space calculation : | |
e0614bf7 ZZ |
3135 | * 4096 * (Y+CbCr+Flags) = 12k, round to 16k |
3136 | */ | |
b9164398 NQ |
3137 | .buf_size = 0x4000, |
3138 | }, | |
3139 | .sao_abv = { | |
3140 | .buf_size = 0x30000, | |
3141 | }, | |
3142 | .sao_vb = { | |
3143 | .buf_size = 0x30000, | |
3144 | }, | |
3145 | .short_term_rps = { | |
3146 | /* SHORT_TERM_RPS - Max 64 set, 16 entry every set, | |
e0614bf7 ZZ |
3147 | * total 64x16x2 = 2048 bytes (0x800) |
3148 | */ | |
b9164398 NQ |
3149 | .buf_size = 0x800, |
3150 | }, | |
3151 | .vps = { | |
3152 | /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
3153 | * total 0x0800 bytes |
3154 | */ | |
b9164398 NQ |
3155 | .buf_size = 0x800, |
3156 | }, | |
3157 | .sps = { | |
3158 | /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
3159 | * total 0x0800 bytes |
3160 | */ | |
b9164398 NQ |
3161 | .buf_size = 0x800, |
3162 | }, | |
3163 | .pps = { | |
3164 | /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
3165 | * total 0x2000 bytes |
3166 | */ | |
b9164398 NQ |
3167 | .buf_size = 0x2000, |
3168 | }, | |
3169 | .sao_up = { | |
3170 | /* SAO UP STORE AREA - Max 640(10240/16) LCU, | |
e0614bf7 ZZ |
3171 | * each has 16 bytes total 0x2800 bytes |
3172 | */ | |
b9164398 NQ |
3173 | .buf_size = 0x2800, |
3174 | }, | |
3175 | .swap_buf = { | |
3176 | /* 256cyclex64bit = 2K bytes 0x800 | |
e0614bf7 ZZ |
3177 | * (only 144 cycles valid) |
3178 | */ | |
b9164398 NQ |
3179 | .buf_size = 0x800, |
3180 | }, | |
3181 | .swap_buf2 = { | |
3182 | .buf_size = 0x800, | |
3183 | }, | |
3184 | .scalelut = { | |
3185 | /* support up to 32 SCALELUT 1024x32 = | |
e0614bf7 ZZ |
3186 | * 32Kbytes (0x8000) |
3187 | */ | |
b9164398 NQ |
3188 | .buf_size = 0x8000, |
3189 | }, | |
3190 | .dblk_para = { | |
3191 | /* DBLK -> Max 256(4096/16) LCU, | |
e0614bf7 ZZ |
3192 | *each para 1024bytes(total:0x40000), |
3193 | *data 1024bytes(total:0x40000) | |
3194 | */ | |
b9164398 NQ |
3195 | .buf_size = 0x80000, |
3196 | }, | |
3197 | .dblk_data = { | |
3198 | .buf_size = 0x80000, | |
3199 | }, | |
3200 | .seg_map = { | |
3201 | /*4096x2304/64/64 *24 = 0xd800 Bytes*/ | |
3202 | .buf_size = 0xd800, | |
3203 | }, | |
b9164398 NQ |
3204 | .mmu_vbh = { |
3205 | .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/ | |
3206 | }, | |
fe96802b | 3207 | #if 0 |
b9164398 NQ |
3208 | .cm_header = { |
3209 | /*add one for keeper.*/ | |
3210 | .buf_size = MMU_COMPRESS_HEADER_SIZE * | |
3211 | (FRAME_BUFFERS + 1), | |
3212 | /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */ | |
3213 | }, | |
3214 | #endif | |
3215 | .mpred_above = { | |
3216 | .buf_size = 0x10000, /* 2 * size of hevc*/ | |
3217 | }, | |
fe96802b | 3218 | #ifdef MV_USE_FIXED_BUF |
b9164398 NQ |
3219 | .mpred_mv = {/* 1080p, 0x40000 per buffer */ |
3220 | .buf_size = 0x40000 * FRAME_BUFFERS, | |
3221 | }, | |
fe96802b | 3222 | #endif |
b9164398 NQ |
3223 | .rpm = { |
3224 | .buf_size = RPM_BUF_SIZE, | |
3225 | }, | |
3226 | .lmem = { | |
3227 | .buf_size = 0x400 * 2, | |
3228 | } | |
3229 | }, | |
3230 | { | |
3231 | .max_width = 4096, | |
3232 | .max_height = 2304, | |
3233 | .ipp = { | |
3234 | /* IPP work space calculation : | |
e0614bf7 ZZ |
3235 | * 4096 * (Y+CbCr+Flags) = 12k, round to 16k |
3236 | */ | |
b9164398 NQ |
3237 | .buf_size = 0x4000, |
3238 | }, | |
3239 | .sao_abv = { | |
3240 | .buf_size = 0x30000, | |
3241 | }, | |
3242 | .sao_vb = { | |
3243 | .buf_size = 0x30000, | |
3244 | }, | |
3245 | .short_term_rps = { | |
3246 | /* SHORT_TERM_RPS - Max 64 set, 16 entry every set, | |
e0614bf7 ZZ |
3247 | * total 64x16x2 = 2048 bytes (0x800) |
3248 | */ | |
b9164398 NQ |
3249 | .buf_size = 0x800, |
3250 | }, | |
3251 | .vps = { | |
3252 | /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
3253 | * total 0x0800 bytes |
3254 | */ | |
b9164398 NQ |
3255 | .buf_size = 0x800, |
3256 | }, | |
3257 | .sps = { | |
3258 | /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
3259 | * total 0x0800 bytes |
3260 | */ | |
b9164398 NQ |
3261 | .buf_size = 0x800, |
3262 | }, | |
3263 | .pps = { | |
3264 | /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, | |
e0614bf7 ZZ |
3265 | * total 0x2000 bytes |
3266 | */ | |
b9164398 NQ |
3267 | .buf_size = 0x2000, |
3268 | }, | |
3269 | .sao_up = { | |
3270 | /* SAO UP STORE AREA - Max 640(10240/16) LCU, | |
e0614bf7 ZZ |
3271 | * each has 16 bytes total 0x2800 bytes |
3272 | */ | |
b9164398 NQ |
3273 | .buf_size = 0x2800, |
3274 | }, | |
3275 | .swap_buf = { | |
3276 | /* 256cyclex64bit = 2K bytes 0x800 | |
e0614bf7 ZZ |
3277 | * (only 144 cycles valid) |
3278 | */ | |
b9164398 NQ |
3279 | .buf_size = 0x800, |
3280 | }, | |
3281 | .swap_buf2 = { | |
3282 | .buf_size = 0x800, | |
3283 | }, | |
3284 | .scalelut = { | |
3285 | /* support up to 32 SCALELUT 1024x32 = 32Kbytes | |
e0614bf7 ZZ |
3286 | * (0x8000) |
3287 | */ | |
b9164398 NQ |
3288 | .buf_size = 0x8000, |
3289 | }, | |
3290 | .dblk_para = { | |
3291 | /* DBLK -> Max 256(4096/16) LCU, | |
e0614bf7 ZZ |
3292 | *each para 1024bytes(total:0x40000), |
3293 | *data 1024bytes(total:0x40000) | |
3294 | */ | |
b9164398 NQ |
3295 | .buf_size = 0x80000, |
3296 | }, | |
3297 | .dblk_data = { | |
3298 | .buf_size = 0x80000, | |
3299 | }, | |
3300 | .seg_map = { | |
3301 | /*4096x2304/64/64 *24 = 0xd800 Bytes*/ | |
3302 | .buf_size = 0xd800, | |
3303 | }, | |
b9164398 NQ |
3304 | .mmu_vbh = { |
3305 | .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/ | |
3306 | }, | |
fe96802b | 3307 | #if 0 |
b9164398 NQ |
3308 | .cm_header = { |
3309 | /*add one for keeper.*/ | |
3310 | .buf_size = MMU_COMPRESS_HEADER_SIZE * | |
3311 | (FRAME_BUFFERS + 1), | |
3312 | /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */ | |
3313 | }, | |
3314 | #endif | |
3315 | .mpred_above = { | |
3316 | .buf_size = 0x10000, /* 2 * size of hevc*/ | |
3317 | }, | |
fe96802b | 3318 | #ifdef MV_USE_FIXED_BUF |
b9164398 NQ |
3319 | .mpred_mv = { |
3320 | /* .buf_size = 0x100000*16, | |
e0614bf7 ZZ |
3321 | * //4k2k , 0x100000 per buffer |
3322 | */ | |
b9164398 NQ |
3323 | /* 4096x2304 , 0x120000 per buffer */ |
3324 | .buf_size = 0x120000 * FRAME_BUFFERS, | |
3325 | }, | |
fe96802b | 3326 | #endif |
b9164398 NQ |
3327 | .rpm = { |
3328 | .buf_size = RPM_BUF_SIZE, | |
3329 | }, | |
3330 | .lmem = { | |
3331 | .buf_size = 0x400 * 2, | |
3332 | } | |
df841122 | 3333 | }, |
3334 | { | |
3335 | .max_width = 4096*2, | |
3336 | .max_height = 2304*2, | |
3337 | .ipp = { | |
3338 | // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k | |
3339 | .buf_size = 0x4000*2, | |
3340 | }, | |
3341 | .sao_abv = { | |
3342 | .buf_size = 0x30000*2, | |
3343 | }, | |
3344 | .sao_vb = { | |
3345 | .buf_size = 0x30000*2, | |
3346 | }, | |
3347 | .short_term_rps = { | |
3348 | // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800) | |
3349 | .buf_size = 0x800, | |
3350 | }, | |
3351 | .vps = { | |
3352 | // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes | |
3353 | .buf_size = 0x800, | |
3354 | }, | |
3355 | .sps = { | |
3356 | // SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes | |
3357 | .buf_size = 0x800, | |
3358 | }, | |
3359 | .pps = { | |
3360 | // PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes | |
3361 | .buf_size = 0x2000, | |
3362 | }, | |
3363 | .sao_up = { | |
3364 | // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes | |
3365 | .buf_size = 0x2800*2, | |
3366 | }, | |
3367 | .swap_buf = { | |
3368 | // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid) | |
3369 | .buf_size = 0x800, | |
3370 | }, | |
3371 | .swap_buf2 = { | |
3372 | .buf_size = 0x800, | |
3373 | }, | |
3374 | .scalelut = { | |
3375 | // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000) | |
3376 | .buf_size = 0x8000*2, | |
3377 | }, | |
3378 | .dblk_para = { | |
3379 | // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000) | |
3380 | .buf_size = 0x80000*2, | |
3381 | }, | |
3382 | .dblk_data = { | |
3383 | .buf_size = 0x80000*2, | |
3384 | }, | |
8deb3449 NQ |
3385 | .seg_map = { |
3386 | /*4096x2304/64/64 *24 = 0xd800 Bytes*/ | |
3387 | .buf_size = 0xd800*4, | |
3388 | }, | |
df841122 | 3389 | .mmu_vbh = { |
3390 | .buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K | |
3391 | }, | |
e0e39311 | 3392 | #if 0 |
df841122 | 3393 | .cm_header = { |
3394 | //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) | |
3395 | .buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) | |
3396 | }, | |
e0e39311 | 3397 | #endif |
df841122 | 3398 | .mpred_above = { |
3399 | .buf_size = 0x10000*2, /* 2 * size of hevc*/ | |
3400 | }, | |
3401 | #ifdef MV_USE_FIXED_BUF | |
3402 | .mpred_mv = { | |
3403 | //4k2k , 0x100000 per buffer */ | |
3404 | /* 4096x2304 , 0x120000 per buffer */ | |
e0e39311 | 3405 | .buf_size = 0x120000 * FRAME_BUFFERS * 4, |
df841122 | 3406 | }, |
3407 | #endif | |
3408 | .rpm = { | |
e0e39311 | 3409 | .buf_size = RPM_BUF_SIZE, |
3410 | }, | |
3411 | .lmem = { | |
3412 | .buf_size = 0x400 * 2, | |
df841122 | 3413 | } |
b9164398 NQ |
3414 | } |
3415 | }; | |
3416 | ||
3417 | ||
3418 | /*Losless compression body buffer size 4K per 64x32 (jt)*/ | |
3419 | int compute_losless_comp_body_size(int width, int height, | |
3420 | uint8_t is_bit_depth_10) | |
3421 | { | |
3422 | int width_x64; | |
3423 | int height_x32; | |
3424 | int bsize; | |
e0614bf7 | 3425 | |
b9164398 NQ |
3426 | width_x64 = width + 63; |
3427 | width_x64 >>= 6; | |
3428 | height_x32 = height + 31; | |
3429 | height_x32 >>= 5; | |
b7706e1e | 3430 | bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32; |
b9164398 NQ |
3431 | if (debug & VP9_DEBUG_BUFMGR_MORE) |
3432 | pr_info("%s(%d,%d,%d)=>%d\n", | |
3433 | __func__, width, height, | |
3434 | is_bit_depth_10, bsize); | |
3435 | ||
3436 | return bsize; | |
3437 | } | |
3438 | ||
3439 | /* Losless compression header buffer size 32bytes per 128x64 (jt)*/ | |
3440 | static int compute_losless_comp_header_size(int width, int height) | |
3441 | { | |
3442 | int width_x128; | |
3443 | int height_x64; | |
3444 | int hsize; | |
e0614bf7 | 3445 | |
b9164398 NQ |
3446 | width_x128 = width + 127; |
3447 | width_x128 >>= 7; | |
3448 | height_x64 = height + 63; | |
3449 | height_x64 >>= 6; | |
3450 | ||
3451 | hsize = 32 * width_x128 * height_x64; | |
3452 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
3453 | pr_info("%s(%d,%d)=>%d\n", | |
3454 | __func__, width, height, | |
3455 | hsize); | |
3456 | ||
3457 | return hsize; | |
3458 | } | |
3459 | ||
3460 | static void init_buff_spec(struct VP9Decoder_s *pbi, | |
3461 | struct BuffInfo_s *buf_spec) | |
3462 | { | |
3463 | void *mem_start_virt; | |
e0614bf7 | 3464 | |
b9164398 NQ |
3465 | buf_spec->ipp.buf_start = buf_spec->start_adr; |
3466 | buf_spec->sao_abv.buf_start = | |
3467 | buf_spec->ipp.buf_start + buf_spec->ipp.buf_size; | |
3468 | ||
3469 | buf_spec->sao_vb.buf_start = | |
3470 | buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size; | |
3471 | buf_spec->short_term_rps.buf_start = | |
3472 | buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size; | |
3473 | buf_spec->vps.buf_start = | |
3474 | buf_spec->short_term_rps.buf_start + | |
3475 | buf_spec->short_term_rps.buf_size; | |
3476 | buf_spec->sps.buf_start = | |
3477 | buf_spec->vps.buf_start + buf_spec->vps.buf_size; | |
3478 | buf_spec->pps.buf_start = | |
3479 | buf_spec->sps.buf_start + buf_spec->sps.buf_size; | |
3480 | buf_spec->sao_up.buf_start = | |
3481 | buf_spec->pps.buf_start + buf_spec->pps.buf_size; | |
3482 | buf_spec->swap_buf.buf_start = | |
3483 | buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size; | |
3484 | buf_spec->swap_buf2.buf_start = | |
3485 | buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size; | |
3486 | buf_spec->scalelut.buf_start = | |
3487 | buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size; | |
3488 | buf_spec->dblk_para.buf_start = | |
3489 | buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size; | |
3490 | buf_spec->dblk_data.buf_start = | |
3491 | buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size; | |
3492 | buf_spec->seg_map.buf_start = | |
3493 | buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size; | |
b7706e1e | 3494 | if (pbi == NULL || pbi->mmu_enable) { |
3495 | buf_spec->mmu_vbh.buf_start = | |
3496 | buf_spec->seg_map.buf_start + | |
3497 | buf_spec->seg_map.buf_size; | |
3498 | buf_spec->mpred_above.buf_start = | |
3499 | buf_spec->mmu_vbh.buf_start + | |
3500 | buf_spec->mmu_vbh.buf_size; | |
3501 | } else { | |
3502 | buf_spec->mpred_above.buf_start = | |
a6c89e96 | 3503 | buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size; |
b7706e1e | 3504 | } |
fe96802b | 3505 | #ifdef MV_USE_FIXED_BUF |
b9164398 NQ |
3506 | buf_spec->mpred_mv.buf_start = |
3507 | buf_spec->mpred_above.buf_start + | |
3508 | buf_spec->mpred_above.buf_size; | |
fe96802b NQ |
3509 | |
3510 | buf_spec->rpm.buf_start = | |
3511 | buf_spec->mpred_mv.buf_start + | |
3512 | buf_spec->mpred_mv.buf_size; | |
3513 | #else | |
3514 | buf_spec->rpm.buf_start = | |
3515 | buf_spec->mpred_above.buf_start + | |
3516 | buf_spec->mpred_above.buf_size; | |
3517 | ||
3518 | #endif | |
3519 | buf_spec->lmem.buf_start = | |
3520 | buf_spec->rpm.buf_start + | |
3521 | buf_spec->rpm.buf_size; | |
3522 | buf_spec->end_adr = | |
3523 | buf_spec->lmem.buf_start + | |
3524 | buf_spec->lmem.buf_size; | |
3525 | ||
7d2e7e17 NQ |
3526 | if (!pbi) |
3527 | return; | |
3528 | ||
3529 | if (!vdec_secure(hw_to_vdec(pbi))) { | |
fe96802b NQ |
3530 | mem_start_virt = |
3531 | codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start); | |
3532 | if (mem_start_virt) { | |
7d2e7e17 NQ |
3533 | memset(mem_start_virt, 0, |
3534 | buf_spec->dblk_para.buf_size); | |
fe96802b NQ |
3535 | codec_mm_dma_flush(mem_start_virt, |
3536 | buf_spec->dblk_para.buf_size, | |
3537 | DMA_TO_DEVICE); | |
b9164398 | 3538 | } else { |
7d2e7e17 NQ |
3539 | mem_start_virt = codec_mm_vmap( |
3540 | buf_spec->dblk_para.buf_start, | |
3541 | buf_spec->dblk_para.buf_size); | |
3542 | if (mem_start_virt) { | |
3543 | memset(mem_start_virt, 0, | |
3544 | buf_spec->dblk_para.buf_size); | |
3545 | codec_mm_dma_flush(mem_start_virt, | |
3546 | buf_spec->dblk_para.buf_size, | |
3547 | DMA_TO_DEVICE); | |
3548 | codec_mm_unmap_phyaddr(mem_start_virt); | |
3549 | } else { | |
3550 | /*not virt for tvp playing, | |
3551 | may need clear on ucode.*/ | |
3552 | pr_err("mem_start_virt failed\n"); | |
3553 | } | |
b7706e1e | 3554 | } |
7d2e7e17 NQ |
3555 | } |
3556 | ||
3557 | if (debug) { | |
3558 | pr_info("%s workspace (%x %x) size = %x\n", __func__, | |
3559 | buf_spec->start_adr, buf_spec->end_adr, | |
3560 | buf_spec->end_adr - buf_spec->start_adr); | |
3561 | } | |
3562 | ||
3563 | if (debug) { | |
3564 | pr_info("ipp.buf_start :%x\n", | |
3565 | buf_spec->ipp.buf_start); | |
3566 | pr_info("sao_abv.buf_start :%x\n", | |
3567 | buf_spec->sao_abv.buf_start); | |
3568 | pr_info("sao_vb.buf_start :%x\n", | |
3569 | buf_spec->sao_vb.buf_start); | |
3570 | pr_info("short_term_rps.buf_start :%x\n", | |
3571 | buf_spec->short_term_rps.buf_start); | |
3572 | pr_info("vps.buf_start :%x\n", | |
3573 | buf_spec->vps.buf_start); | |
3574 | pr_info("sps.buf_start :%x\n", | |
3575 | buf_spec->sps.buf_start); | |
3576 | pr_info("pps.buf_start :%x\n", | |
3577 | buf_spec->pps.buf_start); | |
3578 | pr_info("sao_up.buf_start :%x\n", | |
3579 | buf_spec->sao_up.buf_start); | |
3580 | pr_info("swap_buf.buf_start :%x\n", | |
3581 | buf_spec->swap_buf.buf_start); | |
3582 | pr_info("swap_buf2.buf_start :%x\n", | |
3583 | buf_spec->swap_buf2.buf_start); | |
3584 | pr_info("scalelut.buf_start :%x\n", | |
3585 | buf_spec->scalelut.buf_start); | |
3586 | pr_info("dblk_para.buf_start :%x\n", | |
3587 | buf_spec->dblk_para.buf_start); | |
3588 | pr_info("dblk_data.buf_start :%x\n", | |
3589 | buf_spec->dblk_data.buf_start); | |
3590 | pr_info("seg_map.buf_start :%x\n", | |
3591 | buf_spec->seg_map.buf_start); | |
3592 | if (pbi->mmu_enable) { | |
3593 | pr_info("mmu_vbh.buf_start :%x\n", | |
3594 | buf_spec->mmu_vbh.buf_start); | |
3595 | } | |
3596 | pr_info("mpred_above.buf_start :%x\n", | |
3597 | buf_spec->mpred_above.buf_start); | |
fe96802b | 3598 | #ifdef MV_USE_FIXED_BUF |
7d2e7e17 NQ |
3599 | pr_info("mpred_mv.buf_start :%x\n", |
3600 | buf_spec->mpred_mv.buf_start); | |
fe96802b | 3601 | #endif |
7d2e7e17 NQ |
3602 | if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) { |
3603 | pr_info("rpm.buf_start :%x\n", | |
3604 | buf_spec->rpm.buf_start); | |
b9164398 NQ |
3605 | } |
3606 | } | |
b9164398 NQ |
3607 | } |
3608 | ||
c23e8aee HZ |
3609 | /* cache_util.c */ |
3610 | #define THODIYIL_MCRCC_CANVAS_ALGX 4 | |
3611 | ||
3612 | static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX; | |
3613 | ||
3614 | static void mcrcc_perfcount_reset(void) | |
3615 | { | |
3616 | if (debug & VP9_DEBUG_CACHE) | |
3617 | pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n"); | |
3618 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1); | |
3619 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0); | |
3620 | return; | |
3621 | } | |
3622 | ||
3623 | static unsigned raw_mcr_cnt_total_prev; | |
3624 | static unsigned hit_mcr_0_cnt_total_prev; | |
3625 | static unsigned hit_mcr_1_cnt_total_prev; | |
3626 | static unsigned byp_mcr_cnt_nchcanv_total_prev; | |
3627 | static unsigned byp_mcr_cnt_nchoutwin_total_prev; | |
3628 | ||
3629 | static void mcrcc_get_hitrate(unsigned reset_pre) | |
3630 | { | |
3631 | unsigned delta_hit_mcr_0_cnt; | |
3632 | unsigned delta_hit_mcr_1_cnt; | |
3633 | unsigned delta_raw_mcr_cnt; | |
3634 | unsigned delta_mcr_cnt_nchcanv; | |
3635 | unsigned delta_mcr_cnt_nchoutwin; | |
3636 | ||
3637 | unsigned tmp; | |
3638 | unsigned raw_mcr_cnt; | |
3639 | unsigned hit_mcr_cnt; | |
3640 | unsigned byp_mcr_cnt_nchoutwin; | |
3641 | unsigned byp_mcr_cnt_nchcanv; | |
3642 | int hitrate; | |
3643 | if (reset_pre) { | |
3644 | raw_mcr_cnt_total_prev = 0; | |
3645 | hit_mcr_0_cnt_total_prev = 0; | |
3646 | hit_mcr_1_cnt_total_prev = 0; | |
3647 | byp_mcr_cnt_nchcanv_total_prev = 0; | |
3648 | byp_mcr_cnt_nchoutwin_total_prev = 0; | |
3649 | } | |
3650 | if (debug & VP9_DEBUG_CACHE) | |
3651 | pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n"); | |
3652 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1)); | |
3653 | raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3654 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1)); | |
3655 | hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3656 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1)); | |
3657 | byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3658 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1)); | |
3659 | byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3660 | ||
3661 | if (debug & VP9_DEBUG_CACHE) | |
3662 | pr_info("raw_mcr_cnt_total: %d\n", | |
3663 | raw_mcr_cnt); | |
3664 | if (debug & VP9_DEBUG_CACHE) | |
3665 | pr_info("hit_mcr_cnt_total: %d\n", | |
3666 | hit_mcr_cnt); | |
3667 | if (debug & VP9_DEBUG_CACHE) | |
3668 | pr_info("byp_mcr_cnt_nchoutwin_total: %d\n", | |
3669 | byp_mcr_cnt_nchoutwin); | |
3670 | if (debug & VP9_DEBUG_CACHE) | |
3671 | pr_info("byp_mcr_cnt_nchcanv_total: %d\n", | |
3672 | byp_mcr_cnt_nchcanv); | |
3673 | ||
3674 | delta_raw_mcr_cnt = raw_mcr_cnt - | |
3675 | raw_mcr_cnt_total_prev; | |
3676 | delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv - | |
3677 | byp_mcr_cnt_nchcanv_total_prev; | |
3678 | delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin - | |
3679 | byp_mcr_cnt_nchoutwin_total_prev; | |
3680 | raw_mcr_cnt_total_prev = raw_mcr_cnt; | |
3681 | byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv; | |
3682 | byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin; | |
3683 | ||
3684 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1)); | |
3685 | tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3686 | if (debug & VP9_DEBUG_CACHE) | |
3687 | pr_info("miss_mcr_0_cnt_total: %d\n", tmp); | |
3688 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1)); | |
3689 | tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3690 | if (debug & VP9_DEBUG_CACHE) | |
3691 | pr_info("miss_mcr_1_cnt_total: %d\n", tmp); | |
3692 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1)); | |
3693 | tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3694 | if (debug & VP9_DEBUG_CACHE) | |
3695 | pr_info("hit_mcr_0_cnt_total: %d\n", tmp); | |
3696 | delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev; | |
3697 | hit_mcr_0_cnt_total_prev = tmp; | |
3698 | WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1)); | |
3699 | tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); | |
3700 | if (debug & VP9_DEBUG_CACHE) | |
3701 | pr_info("hit_mcr_1_cnt_total: %d\n", tmp); | |
3702 | delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev; | |
3703 | hit_mcr_1_cnt_total_prev = tmp; | |
3704 | ||
3705 | if (delta_raw_mcr_cnt != 0) { | |
3706 | hitrate = 100 * delta_hit_mcr_0_cnt | |
3707 | / delta_raw_mcr_cnt; | |
3708 | if (debug & VP9_DEBUG_CACHE) | |
3709 | pr_info("CANV0_HIT_RATE : %d\n", hitrate); | |
3710 | hitrate = 100 * delta_hit_mcr_1_cnt | |
3711 | / delta_raw_mcr_cnt; | |
3712 | if (debug & VP9_DEBUG_CACHE) | |
3713 | pr_info("CANV1_HIT_RATE : %d\n", hitrate); | |
3714 | hitrate = 100 * delta_mcr_cnt_nchcanv | |
3715 | / delta_raw_mcr_cnt; | |
3716 | if (debug & VP9_DEBUG_CACHE) | |
3717 | pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate); | |
3718 | hitrate = 100 * delta_mcr_cnt_nchoutwin | |
3719 | / delta_raw_mcr_cnt; | |
3720 | if (debug & VP9_DEBUG_CACHE) | |
3721 | pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate); | |
3722 | } | |
3723 | ||
3724 | ||
3725 | if (raw_mcr_cnt != 0) { | |
3726 | hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt; | |
3727 | if (debug & VP9_DEBUG_CACHE) | |
3728 | pr_info("MCRCC_HIT_RATE : %d\n", hitrate); | |
3729 | hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv) | |
3730 | / raw_mcr_cnt; | |
3731 | if (debug & VP9_DEBUG_CACHE) | |
3732 | pr_info("MCRCC_BYP_RATE : %d\n", hitrate); | |
3733 | } else { | |
3734 | if (debug & VP9_DEBUG_CACHE) | |
3735 | pr_info("MCRCC_HIT_RATE : na\n"); | |
3736 | if (debug & VP9_DEBUG_CACHE) | |
3737 | pr_info("MCRCC_BYP_RATE : na\n"); | |
3738 | } | |
3739 | return; | |
3740 | } | |
3741 | ||
3742 | ||
3743 | static void decomp_perfcount_reset(void) | |
3744 | { | |
3745 | if (debug & VP9_DEBUG_CACHE) | |
3746 | pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n"); | |
3747 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1); | |
3748 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0); | |
3749 | return; | |
3750 | } | |
3751 | ||
3752 | static void decomp_get_hitrate(void) | |
3753 | { | |
3754 | unsigned raw_mcr_cnt; | |
3755 | unsigned hit_mcr_cnt; | |
3756 | int hitrate; | |
3757 | if (debug & VP9_DEBUG_CACHE) | |
3758 | pr_info("[cache_util.c] Entered decomp_get_hitrate...\n"); | |
3759 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1)); | |
3760 | raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3761 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1)); | |
3762 | hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3763 | ||
3764 | if (debug & VP9_DEBUG_CACHE) | |
3765 | pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt); | |
3766 | if (debug & VP9_DEBUG_CACHE) | |
3767 | pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt); | |
3768 | ||
3769 | if (raw_mcr_cnt != 0) { | |
3770 | hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt; | |
3771 | if (debug & VP9_DEBUG_CACHE) | |
3772 | pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate); | |
3773 | } else { | |
3774 | if (debug & VP9_DEBUG_CACHE) | |
3775 | pr_info("DECOMP_HCACHE_HIT_RATE : na\n"); | |
3776 | } | |
3777 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1)); | |
3778 | raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3779 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1)); | |
3780 | hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3781 | ||
3782 | if (debug & VP9_DEBUG_CACHE) | |
3783 | pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt); | |
3784 | if (debug & VP9_DEBUG_CACHE) | |
3785 | pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt); | |
3786 | ||
3787 | if (raw_mcr_cnt != 0) { | |
3788 | hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt; | |
3789 | if (debug & VP9_DEBUG_CACHE) | |
3790 | pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate); | |
3791 | } else { | |
3792 | if (debug & VP9_DEBUG_CACHE) | |
3793 | pr_info("DECOMP_DCACHE_HIT_RATE : na\n"); | |
3794 | } | |
3795 | return; | |
3796 | } | |
3797 | ||
3798 | static void decomp_get_comprate(void) | |
3799 | { | |
3800 | unsigned raw_ucomp_cnt; | |
3801 | unsigned fast_comp_cnt; | |
3802 | unsigned slow_comp_cnt; | |
3803 | int comprate; | |
3804 | ||
3805 | if (debug & VP9_DEBUG_CACHE) | |
3806 | pr_info("[cache_util.c] Entered decomp_get_comprate...\n"); | |
3807 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1)); | |
3808 | fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3809 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1)); | |
3810 | slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3811 | WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1)); | |
3812 | raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); | |
3813 | ||
3814 | if (debug & VP9_DEBUG_CACHE) | |
3815 | pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt); | |
3816 | if (debug & VP9_DEBUG_CACHE) | |
3817 | pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt); | |
3818 | if (debug & VP9_DEBUG_CACHE) | |
3819 | pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt); | |
3820 | ||
3821 | if (raw_ucomp_cnt != 0) { | |
3822 | comprate = (fast_comp_cnt + slow_comp_cnt) | |
3823 | * 100 / raw_ucomp_cnt; | |
3824 | if (debug & VP9_DEBUG_CACHE) | |
3825 | pr_info("DECOMP_COMP_RATIO : %d\n", comprate); | |
3826 | } else { | |
3827 | if (debug & VP9_DEBUG_CACHE) | |
3828 | pr_info("DECOMP_COMP_RATIO : na\n"); | |
3829 | } | |
3830 | return; | |
3831 | } | |
3832 | /* cache_util.c end */ | |
3833 | ||
b9164398 | 3834 | /*==================================================== |
e0614bf7 ZZ |
3835 | *======================================================================== |
3836 | *vp9_prob define | |
3837 | *======================================================================== | |
3838 | */ | |
b9164398 NQ |
3839 | #define VP9_PARTITION_START 0 |
3840 | #define VP9_PARTITION_SIZE_STEP (3 * 4) | |
3841 | #define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP) | |
3842 | #define VP9_PARTITION_KEY_START 0 | |
3843 | #define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE | |
3844 | #define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE) | |
3845 | #define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE) | |
3846 | #define VP9_SKIP_SIZE 4 /* only use 3*/ | |
3847 | #define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE) | |
3848 | #define VP9_TX_MODE_8_0_OFFSET 0 | |
3849 | #define VP9_TX_MODE_8_1_OFFSET 1 | |
3850 | #define VP9_TX_MODE_16_0_OFFSET 2 | |
3851 | #define VP9_TX_MODE_16_1_OFFSET 4 | |
3852 | #define VP9_TX_MODE_32_0_OFFSET 6 | |
3853 | #define VP9_TX_MODE_32_1_OFFSET 9 | |
3854 | #define VP9_TX_MODE_SIZE 12 | |
3855 | #define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE) | |
3856 | #define VP9_COEF_BAND_0_OFFSET 0 | |
3857 | #define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1) | |
3858 | #define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3) | |
3859 | #define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3) | |
3860 | #define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3) | |
3861 | #define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3) | |
3862 | #define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/ | |
3863 | #define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET) | |
3864 | #define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET) | |
3865 | #define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET) | |
3866 | #define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET) | |
3867 | #define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET) | |
3868 | #define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET) | |
3869 | #define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE) | |
3870 | #define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/ | |
3871 | #define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE) | |
3872 | #define VP9_INTERP_SIZE 8 | |
3873 | #define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE) | |
3874 | #define VP9_INTRA_INTER_SIZE 4 | |
3875 | #define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START | |
3876 | #define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE) | |
3877 | #define VP9_COMP_INTER_START \ | |
3878 | (VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE) | |
3879 | #define VP9_COMP_INTER_SIZE 5 | |
3880 | #define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE) | |
3881 | #define VP9_COMP_REF_SIZE 5 | |
3882 | #define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE) | |
3883 | #define VP9_SINGLE_REF_SIZE 10 | |
3884 | #define VP9_REF_MODE_START VP9_COMP_INTER_START | |
3885 | #define VP9_REF_MODE_SIZE \ | |
3886 | (VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE) | |
3887 | #define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE) | |
3888 | #define VP9_IF_Y_MODE_SIZE 36 | |
3889 | #define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE) | |
3890 | #define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/ | |
3891 | #define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE) | |
3892 | #define VP9_MV_JOINTS_SIZE 3 | |
3893 | #define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE) | |
3894 | #define VP9_MV_SIGN_0_SIZE 1 | |
3895 | #define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE) | |
3896 | #define VP9_MV_CLASSES_0_SIZE 10 | |
3897 | #define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE) | |
3898 | #define VP9_MV_CLASS0_0_SIZE 1 | |
3899 | #define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE) | |
3900 | #define VP9_MV_BITS_0_SIZE 10 | |
3901 | #define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE) | |
3902 | #define VP9_MV_SIGN_1_SIZE 1 | |
3903 | #define VP9_MV_CLASSES_1_START \ | |
3904 | (VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE) | |
3905 | #define VP9_MV_CLASSES_1_SIZE 10 | |
3906 | #define VP9_MV_CLASS0_1_START \ | |
3907 | (VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE) | |
3908 | #define VP9_MV_CLASS0_1_SIZE 1 | |
3909 | #define VP9_MV_BITS_1_START \ | |
3910 | (VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE) | |
3911 | #define VP9_MV_BITS_1_SIZE 10 | |
3912 | #define VP9_MV_CLASS0_FP_0_START \ | |
3913 | (VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE) | |
3914 | #define VP9_MV_CLASS0_FP_0_SIZE 9 | |
3915 | #define VP9_MV_CLASS0_FP_1_START \ | |
3916 | (VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE) | |
3917 | #define VP9_MV_CLASS0_FP_1_SIZE 9 | |
3918 | #define VP9_MV_CLASS0_HP_0_START \ | |
3919 | (VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE) | |
3920 | #define VP9_MV_CLASS0_HP_0_SIZE 2 | |
3921 | #define VP9_MV_CLASS0_HP_1_START \ | |
3922 | (VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE) | |
3923 | #define VP9_MV_CLASS0_HP_1_SIZE 2 | |
3924 | #define VP9_MV_START VP9_MV_JOINTS_START | |
3925 | #define VP9_MV_SIZE 72 /*only use 69*/ | |
3926 | ||
3927 | #define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE) | |
3928 | ||
3929 | ||
3930 | /*======================================================================== | |
e0614bf7 ZZ |
3931 | * vp9_count_mem define |
3932 | *======================================================================== | |
3933 | */ | |
b9164398 NQ |
3934 | #define VP9_COEF_COUNT_START 0 |
3935 | #define VP9_COEF_COUNT_BAND_0_OFFSET 0 | |
3936 | #define VP9_COEF_COUNT_BAND_1_OFFSET \ | |
3937 | (VP9_COEF_COUNT_BAND_0_OFFSET + 3*5) | |
3938 | #define VP9_COEF_COUNT_BAND_2_OFFSET \ | |
3939 | (VP9_COEF_COUNT_BAND_1_OFFSET + 6*5) | |
3940 | #define VP9_COEF_COUNT_BAND_3_OFFSET \ | |
3941 | (VP9_COEF_COUNT_BAND_2_OFFSET + 6*5) | |
3942 | #define VP9_COEF_COUNT_BAND_4_OFFSET \ | |
3943 | (VP9_COEF_COUNT_BAND_3_OFFSET + 6*5) | |
3944 | #define VP9_COEF_COUNT_BAND_5_OFFSET \ | |
3945 | (VP9_COEF_COUNT_BAND_4_OFFSET + 6*5) | |
3946 | #define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */ | |
3947 | #define VP9_COEF_COUNT_4X4_START \ | |
3948 | (VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET) | |
3949 | #define VP9_COEF_COUNT_8X8_START \ | |
3950 | (VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET) | |
3951 | #define VP9_COEF_COUNT_16X16_START \ | |
3952 | (VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET) | |
3953 | #define VP9_COEF_COUNT_32X32_START \ | |
3954 | (VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET) | |
3955 | #define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET) | |
3956 | #define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET) | |
3957 | ||
3958 | #define VP9_INTRA_INTER_COUNT_START \ | |
3959 | (VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE) | |
3960 | #define VP9_INTRA_INTER_COUNT_SIZE (4*2) | |
3961 | #define VP9_COMP_INTER_COUNT_START \ | |
3962 | (VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE) | |
3963 | #define VP9_COMP_INTER_COUNT_SIZE (5*2) | |
3964 | #define VP9_COMP_REF_COUNT_START \ | |
3965 | (VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE) | |
3966 | #define VP9_COMP_REF_COUNT_SIZE (5*2) | |
3967 | #define VP9_SINGLE_REF_COUNT_START \ | |
3968 | (VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE) | |
3969 | #define VP9_SINGLE_REF_COUNT_SIZE (10*2) | |
3970 | #define VP9_TX_MODE_COUNT_START \ | |
3971 | (VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE) | |
3972 | #define VP9_TX_MODE_COUNT_SIZE (12*2) | |
3973 | #define VP9_SKIP_COUNT_START \ | |
3974 | (VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE) | |
3975 | #define VP9_SKIP_COUNT_SIZE (3*2) | |
3976 | #define VP9_MV_SIGN_0_COUNT_START \ | |
3977 | (VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE) | |
3978 | #define VP9_MV_SIGN_0_COUNT_SIZE (1*2) | |
3979 | #define VP9_MV_SIGN_1_COUNT_START \ | |
3980 | (VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE) | |
3981 | #define VP9_MV_SIGN_1_COUNT_SIZE (1*2) | |
3982 | #define VP9_MV_BITS_0_COUNT_START \ | |
3983 | (VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE) | |
3984 | #define VP9_MV_BITS_0_COUNT_SIZE (10*2) | |
3985 | #define VP9_MV_BITS_1_COUNT_START \ | |
3986 | (VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE) | |
3987 | #define VP9_MV_BITS_1_COUNT_SIZE (10*2) | |
3988 | #define VP9_MV_CLASS0_HP_0_COUNT_START \ | |
3989 | (VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE) | |
3990 | #define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2) | |
3991 | #define VP9_MV_CLASS0_HP_1_COUNT_START \ | |
3992 | (VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE) | |
3993 | #define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2) | |
3994 | /* Start merge_tree*/ | |
3995 | #define VP9_INTER_MODE_COUNT_START \ | |
3996 | (VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE) | |
3997 | #define VP9_INTER_MODE_COUNT_SIZE (7*4) | |
3998 | #define VP9_IF_Y_MODE_COUNT_START \ | |
3999 | (VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE) | |
4000 | #define VP9_IF_Y_MODE_COUNT_SIZE (10*4) | |
4001 | #define VP9_IF_UV_MODE_COUNT_START \ | |
4002 | (VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE) | |
4003 | #define VP9_IF_UV_MODE_COUNT_SIZE (10*10) | |
4004 | #define VP9_PARTITION_P_COUNT_START \ | |
4005 | (VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE) | |
4006 | #define VP9_PARTITION_P_COUNT_SIZE (4*4*4) | |
4007 | #define VP9_INTERP_COUNT_START \ | |
4008 | (VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE) | |
4009 | #define VP9_INTERP_COUNT_SIZE (4*3) | |
4010 | #define VP9_MV_JOINTS_COUNT_START \ | |
4011 | (VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE) | |
4012 | #define VP9_MV_JOINTS_COUNT_SIZE (1 * 4) | |
4013 | #define VP9_MV_CLASSES_0_COUNT_START \ | |
4014 | (VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE) | |
4015 | #define VP9_MV_CLASSES_0_COUNT_SIZE (1*11) | |
4016 | #define VP9_MV_CLASS0_0_COUNT_START \ | |
4017 | (VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE) | |
4018 | #define VP9_MV_CLASS0_0_COUNT_SIZE (1*2) | |
4019 | #define VP9_MV_CLASSES_1_COUNT_START \ | |
4020 | (VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE) | |
4021 | #define VP9_MV_CLASSES_1_COUNT_SIZE (1*11) | |
4022 | #define VP9_MV_CLASS0_1_COUNT_START \ | |
4023 | (VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE) | |
4024 | #define VP9_MV_CLASS0_1_COUNT_SIZE (1*2) | |
4025 | #define VP9_MV_CLASS0_FP_0_COUNT_START \ | |
4026 | (VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE) | |
4027 | #define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4) | |
4028 | #define VP9_MV_CLASS0_FP_1_COUNT_START \ | |
4029 | (VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE) | |
4030 | #define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4) | |
4031 | ||
4032 | ||
4033 | #define DC_PRED 0 /* Average of above and left pixels*/ | |
4034 | #define V_PRED 1 /* Vertical*/ | |
4035 | #define H_PRED 2 /* Horizontal*/ | |
4036 | #define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/ | |
4037 | #define D135_PRED 4 /* Directional 135 deg = 180 - 45*/ | |
4038 | #define D117_PRED 5 /* Directional 117 deg = 180 - 63*/ | |
4039 | #define D153_PRED 6 /* Directional 153 deg = 180 - 27*/ | |
4040 | #define D207_PRED 7 /* Directional 207 deg = 180 + 27*/ | |
4041 | #define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/ | |
4042 | #define TM_PRED 9 /*True-motion*/ | |
4043 | ||
4044 | int clip_prob(int p) | |
4045 | { | |
4046 | return (p > 255) ? 255 : (p < 1) ? 1 : p; | |
4047 | } | |
4048 | ||
4049 | #define ROUND_POWER_OF_TWO(value, n) \ | |
4050 | (((value) + (1 << ((n) - 1))) >> (n)) | |
4051 | ||
4052 | #define MODE_MV_COUNT_SAT 20 | |
4053 | static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = { | |
4054 | 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64, | |
4055 | 70, 76, 83, 89, 96, 102, 108, 115, 121, 128 | |
4056 | }; | |
4057 | ||
4058 | void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob, | |
4059 | int coef_node_start, int tree_left, int tree_right, int tree_i, | |
4060 | int node) { | |
4061 | ||
4062 | int prob_32, prob_res, prob_shift; | |
4063 | int pre_prob, new_prob; | |
4064 | int den, m_count, get_prob, factor; | |
e0614bf7 | 4065 | |
b9164398 NQ |
4066 | prob_32 = prev_prob[coef_node_start / 4 * 2]; |
4067 | prob_res = coef_node_start & 3; | |
4068 | prob_shift = prob_res * 8; | |
4069 | pre_prob = (prob_32 >> prob_shift) & 0xff; | |
4070 | ||
4071 | den = tree_left + tree_right; | |
4072 | ||
4073 | if (den == 0) | |
4074 | new_prob = pre_prob; | |
4075 | else { | |
4076 | m_count = (den < MODE_MV_COUNT_SAT) ? | |
4077 | den : MODE_MV_COUNT_SAT; | |
4078 | get_prob = clip_prob( | |
4079 | div_r32(((int64_t)tree_left * 256 + (den >> 1)), | |
4080 | den)); | |
4081 | /*weighted_prob*/ | |
4082 | factor = count_to_update_factor[m_count]; | |
4083 | new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor) | |
4084 | + get_prob * factor, 8); | |
4085 | } | |
4086 | cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2] | |
4087 | & (~(0xff << prob_shift))) | (new_prob << prob_shift); | |
4088 | ||
4089 | /*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n", | |
e0614bf7 ZZ |
4090 | *tree_i, node, pre_prob, new_prob, tree_left, tree_right, |
4091 | *cur_prob[coef_node_start/4*2]); | |
4092 | */ | |
b9164398 NQ |
4093 | } |
4094 | ||
4095 | ||
4096 | /*void adapt_coef_probs(void)*/ | |
4097 | void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc, | |
4098 | unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count) | |
4099 | { | |
4100 | /* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes) | |
e0614bf7 ZZ |
4101 | *unsigned int prev_prob[496*2]; |
4102 | *unsigned int cur_prob[496*2]; | |
4103 | *0x300 * 128bits = 0x3000 (32K Bytes) | |
4104 | *unsigned int count[0x300*4]; | |
4105 | */ | |
b9164398 NQ |
4106 | |
4107 | int tx_size, coef_tx_size_start, coef_count_tx_size_start; | |
4108 | int plane, coef_plane_start, coef_count_plane_start; | |
4109 | int type, coef_type_start, coef_count_type_start; | |
4110 | int band, coef_band_start, coef_count_band_start; | |
4111 | int cxt_num; | |
4112 | int cxt, coef_cxt_start, coef_count_cxt_start; | |
4113 | int node, coef_node_start, coef_count_node_start; | |
4114 | ||
4115 | int tree_i, tree_left, tree_right; | |
4116 | int mvd_i; | |
4117 | ||
4118 | int count_sat = 24; | |
4119 | /*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, | |
e0614bf7 ZZ |
4120 | *use 128 |
4121 | */ | |
b9164398 NQ |
4122 | /* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/ |
4123 | /*int update_factor = (pic_count == 1) ? 128 : 112;*/ | |
4124 | int update_factor = cur_kf ? 112 : | |
4125 | prev_kf ? 128 : 112; | |
4126 | ||
4127 | int prob_32; | |
4128 | int prob_res; | |
4129 | int prob_shift; | |
4130 | int pre_prob; | |
4131 | ||
4132 | int num, den; | |
4133 | int get_prob; | |
4134 | int m_count; | |
4135 | int factor; | |
4136 | ||
4137 | int new_prob; | |
4138 | ||
4139 | if (debug & VP9_DEBUG_MERGE) | |
4140 | pr_info | |
4141 | ("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n", | |
4142 | pre_fc, prev_kf, cur_kf); | |
4143 | ||
4144 | /*adapt_coef_probs*/ | |
4145 | for (tx_size = 0; tx_size < 4; tx_size++) { | |
4146 | coef_tx_size_start = VP9_COEF_START | |
4147 | + tx_size * 4 * VP9_COEF_SIZE_ONE_SET; | |
4148 | coef_count_tx_size_start = VP9_COEF_COUNT_START | |
4149 | + tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET; | |
4150 | coef_plane_start = coef_tx_size_start; | |
4151 | coef_count_plane_start = coef_count_tx_size_start; | |
4152 | for (plane = 0; plane < 2; plane++) { | |
4153 | coef_type_start = coef_plane_start; | |
4154 | coef_count_type_start = coef_count_plane_start; | |
4155 | for (type = 0; type < 2; type++) { | |
4156 | coef_band_start = coef_type_start; | |
4157 | coef_count_band_start = coef_count_type_start; | |
4158 | for (band = 0; band < 6; band++) { | |
4159 | if (band == 0) | |
4160 | cxt_num = 3; | |
4161 | else | |
4162 | cxt_num = 6; | |
4163 | coef_cxt_start = coef_band_start; | |
4164 | coef_count_cxt_start = | |
4165 | coef_count_band_start; | |
4166 | for (cxt = 0; cxt < cxt_num; cxt++) { | |
4167 | const int n0 = | |
4168 | count[coef_count_cxt_start]; | |
4169 | const int n1 = | |
4170 | count[coef_count_cxt_start + 1]; | |
4171 | const int n2 = | |
4172 | count[coef_count_cxt_start + 2]; | |
4173 | const int neob = | |
4174 | count[coef_count_cxt_start + 3]; | |
4175 | const int nneob = | |
4176 | count[coef_count_cxt_start + 4]; | |
4177 | const unsigned int | |
4178 | branch_ct[3][2] = { | |
4179 | { neob, nneob }, | |
4180 | { n0, n1 + n2 }, | |
4181 | { n1, n2 } | |
4182 | }; | |
4183 | coef_node_start = | |
4184 | coef_cxt_start; | |
4185 | for | |
4186 | (node = 0; node < 3; node++) { | |
4187 | prob_32 = | |
4188 | prev_prob[ | |
4189 | coef_node_start | |
4190 | / 4 * 2]; | |
4191 | prob_res = | |
4192 | coef_node_start & 3; | |
4193 | prob_shift = | |
4194 | prob_res * 8; | |
4195 | pre_prob = | |
4196 | (prob_32 >> prob_shift) | |
4197 | & 0xff; | |
4198 | ||
4199 | /*get_binary_prob*/ | |
4200 | num = | |
4201 | branch_ct[node][0]; | |
4202 | den = | |
4203 | branch_ct[node][0] + | |
4204 | branch_ct[node][1]; | |
4205 | m_count = (den < | |
4206 | count_sat) | |
4207 | ? den : count_sat; | |
4208 | ||
4209 | get_prob = | |
4210 | (den == 0) ? 128u : | |
4211 | clip_prob( | |
4212 | div_r32(((int64_t) | |
4213 | num * 256 | |
4214 | + (den >> 1)), | |
4215 | den)); | |
4216 | ||
4217 | factor = | |
4218 | update_factor * m_count | |
4219 | / count_sat; | |
4220 | new_prob = | |
4221 | ROUND_POWER_OF_TWO | |
4222 | (pre_prob * | |
4223 | (256 - factor) + | |
4224 | get_prob * factor, 8); | |
4225 | ||
4226 | cur_prob[coef_node_start | |
4227 | / 4 * 2] = | |
4228 | (cur_prob | |
4229 | [coef_node_start | |
4230 | / 4 * 2] & (~(0xff << | |
4231 | prob_shift))) | | |
4232 | (new_prob << | |
4233 | prob_shift); | |
4234 | ||
4235 | coef_node_start += 1; | |
4236 | } | |
4237 | ||
4238 | coef_cxt_start = | |
4239 | coef_cxt_start + 3; | |
4240 | coef_count_cxt_start = | |
4241 | coef_count_cxt_start | |
4242 | + 5; | |
4243 | } | |
4244 | if (band == 0) { | |
4245 | coef_band_start += 10; | |
4246 | coef_count_band_start += 15; | |
4247 | } else { | |
4248 | coef_band_start += 18; | |
4249 | coef_count_band_start += 30; | |
4250 | } | |
4251 | } | |
4252 | coef_type_start += VP9_COEF_SIZE_ONE_SET; | |
4253 | coef_count_type_start += | |
4254 | VP9_COEF_COUNT_SIZE_ONE_SET; | |
4255 | } | |
4256 | coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET; | |
4257 | coef_count_plane_start += | |
4258 | 2 * VP9_COEF_COUNT_SIZE_ONE_SET; | |
4259 | } | |
4260 | } | |
4261 | ||
e0614bf7 | 4262 | if (cur_kf == 0) { |
b9164398 NQ |
4263 | /*mode_mv_merge_probs - merge_intra_inter_prob*/ |
4264 | for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START; | |
4265 | coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START + | |
4266 | VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) { | |
4267 | ||
4268 | if (coef_count_node_start == | |
4269 | VP9_INTRA_INTER_COUNT_START) { | |
4270 | if (debug & VP9_DEBUG_MERGE) | |
4271 | pr_info(" # merge_intra_inter_prob\n"); | |
4272 | coef_node_start = VP9_INTRA_INTER_START; | |
4273 | } else if (coef_count_node_start == | |
4274 | VP9_COMP_INTER_COUNT_START) { | |
4275 | if (debug & VP9_DEBUG_MERGE) | |
4276 | pr_info(" # merge_comp_inter_prob\n"); | |
4277 | coef_node_start = VP9_COMP_INTER_START; | |
4278 | } | |
4279 | /* | |
e0614bf7 ZZ |
4280 | *else if (coef_count_node_start == |
4281 | * VP9_COMP_REF_COUNT_START) { | |
4282 | * pr_info(" # merge_comp_inter_prob\n"); | |
4283 | * coef_node_start = VP9_COMP_REF_START; | |
4284 | *} | |
4285 | *else if (coef_count_node_start == | |
4286 | * VP9_SINGLE_REF_COUNT_START) { | |
4287 | * pr_info(" # merge_comp_inter_prob\n"); | |
4288 | * coef_node_start = VP9_SINGLE_REF_START; | |
4289 | *} | |
4290 | */ | |
b9164398 NQ |
4291 | else if (coef_count_node_start == |
4292 | VP9_TX_MODE_COUNT_START) { | |
4293 | if (debug & VP9_DEBUG_MERGE) | |
4294 | pr_info(" # merge_tx_mode_probs\n"); | |
4295 | coef_node_start = VP9_TX_MODE_START; | |
4296 | } else if (coef_count_node_start == | |
4297 | VP9_SKIP_COUNT_START) { | |
4298 | if (debug & VP9_DEBUG_MERGE) | |
4299 | pr_info(" # merge_skip_probs\n"); | |
4300 | coef_node_start = VP9_SKIP_START; | |
4301 | } else if (coef_count_node_start == | |
4302 | VP9_MV_SIGN_0_COUNT_START) { | |
4303 | if (debug & VP9_DEBUG_MERGE) | |
4304 | pr_info(" # merge_sign_0\n"); | |
4305 | coef_node_start = VP9_MV_SIGN_0_START; | |
4306 | } else if (coef_count_node_start == | |
4307 | VP9_MV_SIGN_1_COUNT_START) { | |
4308 | if (debug & VP9_DEBUG_MERGE) | |
4309 | pr_info(" # merge_sign_1\n"); | |
4310 | coef_node_start = VP9_MV_SIGN_1_START; | |
4311 | } else if (coef_count_node_start == | |
4312 | VP9_MV_BITS_0_COUNT_START) { | |
4313 | if (debug & VP9_DEBUG_MERGE) | |
4314 | pr_info(" # merge_bits_0\n"); | |
4315 | coef_node_start = VP9_MV_BITS_0_START; | |
4316 | } else if (coef_count_node_start == | |
4317 | VP9_MV_BITS_1_COUNT_START) { | |
4318 | if (debug & VP9_DEBUG_MERGE) | |
4319 | pr_info(" # merge_bits_1\n"); | |
4320 | coef_node_start = VP9_MV_BITS_1_START; | |
4321 | } else if (coef_count_node_start == | |
4322 | VP9_MV_CLASS0_HP_0_COUNT_START) { | |
4323 | if (debug & VP9_DEBUG_MERGE) | |
4324 | pr_info(" # merge_class0_hp\n"); | |
4325 | coef_node_start = VP9_MV_CLASS0_HP_0_START; | |
4326 | } | |
4327 | ||
4328 | ||
4329 | den = count[coef_count_node_start] + | |
4330 | count[coef_count_node_start + 1]; | |
4331 | ||
4332 | prob_32 = prev_prob[coef_node_start / 4 * 2]; | |
4333 | prob_res = coef_node_start & 3; | |
4334 | prob_shift = prob_res * 8; | |
4335 | pre_prob = (prob_32 >> prob_shift) & 0xff; | |
4336 | ||
4337 | if (den == 0) | |
4338 | new_prob = pre_prob; | |
4339 | else { | |
4340 | m_count = (den < MODE_MV_COUNT_SAT) ? | |
4341 | den : MODE_MV_COUNT_SAT; | |
4342 | get_prob = | |
4343 | clip_prob( | |
4344 | div_r32(((int64_t)count[coef_count_node_start] | |
4345 | * 256 + (den >> 1)), | |
4346 | den)); | |
4347 | /*weighted_prob*/ | |
4348 | factor = count_to_update_factor[m_count]; | |
4349 | new_prob = | |
4350 | ROUND_POWER_OF_TWO(pre_prob * (256 - factor) | |
4351 | + get_prob * factor, 8); | |
4352 | } | |
4353 | cur_prob[coef_node_start / 4 * 2] = | |
4354 | (cur_prob[coef_node_start / 4 * 2] & | |
4355 | (~(0xff << prob_shift))) | |
4356 | | (new_prob << prob_shift); | |
4357 | ||
4358 | coef_node_start = coef_node_start + 1; | |
4359 | } | |
4360 | if (debug & VP9_DEBUG_MERGE) | |
4361 | pr_info(" # merge_vp9_inter_mode_tree\n"); | |
4362 | coef_node_start = VP9_INTER_MODE_START; | |
4363 | coef_count_node_start = VP9_INTER_MODE_COUNT_START; | |
4364 | for (tree_i = 0; tree_i < 7; tree_i++) { | |
4365 | for (node = 0; node < 3; node++) { | |
4366 | switch (node) { | |
4367 | case 2: | |
4368 | tree_left = | |
4369 | count[coef_count_node_start + 1]; | |
4370 | tree_right = | |
4371 | count[coef_count_node_start + 3]; | |
4372 | break; | |
4373 | case 1: | |
4374 | tree_left = | |
4375 | count[coef_count_node_start + 0]; | |
4376 | tree_right = | |
4377 | count[coef_count_node_start + 1] | |
4378 | + count[coef_count_node_start + 3]; | |
4379 | break; | |
4380 | default: | |
4381 | tree_left = | |
4382 | count[coef_count_node_start + 2]; | |
4383 | tree_right = | |
4384 | count[coef_count_node_start + 0] | |
4385 | + count[coef_count_node_start + 1] | |
4386 | + count[coef_count_node_start + 3]; | |
4387 | break; | |
4388 | ||
4389 | } | |
4390 | ||
4391 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4392 | coef_node_start, tree_left, tree_right, | |
4393 | tree_i, node); | |
4394 | ||
4395 | coef_node_start = coef_node_start + 1; | |
4396 | } | |
4397 | coef_count_node_start = coef_count_node_start + 4; | |
4398 | } | |
4399 | if (debug & VP9_DEBUG_MERGE) | |
4400 | pr_info(" # merge_vp9_intra_mode_tree\n"); | |
4401 | coef_node_start = VP9_IF_Y_MODE_START; | |
4402 | coef_count_node_start = VP9_IF_Y_MODE_COUNT_START; | |
4403 | for (tree_i = 0; tree_i < 14; tree_i++) { | |
4404 | for (node = 0; node < 9; node++) { | |
4405 | switch (node) { | |
4406 | case 8: | |
4407 | tree_left = | |
4408 | count[coef_count_node_start+D153_PRED]; | |
4409 | tree_right = | |
4410 | count[coef_count_node_start+D207_PRED]; | |
4411 | break; | |
4412 | case 7: | |
4413 | tree_left = | |
4414 | count[coef_count_node_start+D63_PRED]; | |
4415 | tree_right = | |
4416 | count[coef_count_node_start+D207_PRED] + | |
4417 | count[coef_count_node_start+D153_PRED]; | |
4418 | break; | |
4419 | case 6: | |
4420 | tree_left = | |
4421 | count[coef_count_node_start + D45_PRED]; | |
4422 | tree_right = | |
4423 | count[coef_count_node_start+D207_PRED] + | |
4424 | count[coef_count_node_start+D153_PRED] + | |
4425 | count[coef_count_node_start+D63_PRED]; | |
4426 | break; | |
4427 | case 5: | |
4428 | tree_left = | |
4429 | count[coef_count_node_start+D135_PRED]; | |
4430 | tree_right = | |
4431 | count[coef_count_node_start+D117_PRED]; | |
4432 | break; | |
4433 | case 4: | |
4434 | tree_left = | |
4435 | count[coef_count_node_start+H_PRED]; | |
4436 | tree_right = | |
4437 | count[coef_count_node_start+D117_PRED] + | |
4438 | count[coef_count_node_start+D135_PRED]; | |
4439 | break; | |
4440 | case 3: | |
4441 | tree_left = | |
4442 | count[coef_count_node_start+H_PRED] + | |
4443 | count[coef_count_node_start+D117_PRED] + | |
4444 | count[coef_count_node_start+D135_PRED]; | |
4445 | tree_right = | |
4446 | count[coef_count_node_start+D45_PRED] + | |
4447 | count[coef_count_node_start+D207_PRED] + | |
4448 | count[coef_count_node_start+D153_PRED] + | |
4449 | count[coef_count_node_start+D63_PRED]; | |
4450 | break; | |
4451 | case 2: | |
4452 | tree_left = | |
4453 | count[coef_count_node_start+V_PRED]; | |
4454 | tree_right = | |
4455 | count[coef_count_node_start+H_PRED] + | |
4456 | count[coef_count_node_start+D117_PRED] + | |
4457 | count[coef_count_node_start+D135_PRED] + | |
4458 | count[coef_count_node_start+D45_PRED] + | |
4459 | count[coef_count_node_start+D207_PRED] + | |
4460 | count[coef_count_node_start+D153_PRED] + | |
4461 | count[coef_count_node_start+D63_PRED]; | |
4462 | break; | |
4463 | case 1: | |
4464 | tree_left = | |
4465 | count[coef_count_node_start+TM_PRED]; | |
4466 | tree_right = | |
4467 | count[coef_count_node_start+V_PRED] + | |
4468 | count[coef_count_node_start+H_PRED] + | |
4469 | count[coef_count_node_start+D117_PRED] + | |
4470 | count[coef_count_node_start+D135_PRED] + | |
4471 | count[coef_count_node_start+D45_PRED] + | |
4472 | count[coef_count_node_start+D207_PRED] + | |
4473 | count[coef_count_node_start+D153_PRED] + | |
4474 | count[coef_count_node_start+D63_PRED]; | |
4475 | break; | |
4476 | default: | |
4477 | tree_left = | |
4478 | count[coef_count_node_start+DC_PRED]; | |
4479 | tree_right = | |
4480 | count[coef_count_node_start+TM_PRED] + | |
4481 | count[coef_count_node_start+V_PRED] + | |
4482 | count[coef_count_node_start+H_PRED] + | |
4483 | count[coef_count_node_start+D117_PRED] + | |
4484 | count[coef_count_node_start+D135_PRED] + | |
4485 | count[coef_count_node_start+D45_PRED] + | |
4486 | count[coef_count_node_start+D207_PRED] + | |
4487 | count[coef_count_node_start+D153_PRED] + | |
4488 | count[coef_count_node_start+D63_PRED]; | |
4489 | break; | |
4490 | ||
4491 | } | |
4492 | ||
4493 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4494 | coef_node_start, tree_left, tree_right, | |
4495 | tree_i, node); | |
4496 | ||
4497 | coef_node_start = coef_node_start + 1; | |
4498 | } | |
4499 | coef_count_node_start = coef_count_node_start + 10; | |
4500 | } | |
4501 | ||
4502 | if (debug & VP9_DEBUG_MERGE) | |
4503 | pr_info(" # merge_vp9_partition_tree\n"); | |
4504 | coef_node_start = VP9_PARTITION_P_START; | |
4505 | coef_count_node_start = VP9_PARTITION_P_COUNT_START; | |
4506 | for (tree_i = 0; tree_i < 16; tree_i++) { | |
4507 | for (node = 0; node < 3; node++) { | |
4508 | switch (node) { | |
4509 | case 2: | |
4510 | tree_left = | |
4511 | count[coef_count_node_start + 2]; | |
4512 | tree_right = | |
4513 | count[coef_count_node_start + 3]; | |
4514 | break; | |
4515 | case 1: | |
4516 | tree_left = | |
4517 | count[coef_count_node_start + 1]; | |
4518 | tree_right = | |
4519 | count[coef_count_node_start + 2] + | |
4520 | count[coef_count_node_start + 3]; | |
4521 | break; | |
4522 | default: | |
4523 | tree_left = | |
4524 | count[coef_count_node_start + 0]; | |
4525 | tree_right = | |
4526 | count[coef_count_node_start + 1] + | |
4527 | count[coef_count_node_start + 2] + | |
4528 | count[coef_count_node_start + 3]; | |
4529 | break; | |
4530 | ||
4531 | } | |
4532 | ||
4533 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4534 | coef_node_start, | |
4535 | tree_left, tree_right, tree_i, node); | |
4536 | ||
4537 | coef_node_start = coef_node_start + 1; | |
4538 | } | |
4539 | coef_count_node_start = coef_count_node_start + 4; | |
4540 | } | |
4541 | ||
4542 | if (debug & VP9_DEBUG_MERGE) | |
4543 | pr_info(" # merge_vp9_switchable_interp_tree\n"); | |
4544 | coef_node_start = VP9_INTERP_START; | |
4545 | coef_count_node_start = VP9_INTERP_COUNT_START; | |
4546 | for (tree_i = 0; tree_i < 4; tree_i++) { | |
4547 | for (node = 0; node < 2; node++) { | |
4548 | switch (node) { | |
4549 | case 1: | |
4550 | tree_left = | |
4551 | count[coef_count_node_start + 1]; | |
4552 | tree_right = | |
4553 | count[coef_count_node_start + 2]; | |
4554 | break; | |
4555 | default: | |
4556 | tree_left = | |
4557 | count[coef_count_node_start + 0]; | |
4558 | tree_right = | |
4559 | count[coef_count_node_start + 1] + | |
4560 | count[coef_count_node_start + 2]; | |
4561 | break; | |
4562 | ||
4563 | } | |
4564 | ||
4565 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4566 | coef_node_start, | |
4567 | tree_left, tree_right, tree_i, node); | |
4568 | ||
4569 | coef_node_start = coef_node_start + 1; | |
4570 | } | |
4571 | coef_count_node_start = coef_count_node_start + 3; | |
4572 | } | |
4573 | ||
4574 | if (debug & VP9_DEBUG_MERGE) | |
4575 | pr_info("# merge_vp9_mv_joint_tree\n"); | |
4576 | coef_node_start = VP9_MV_JOINTS_START; | |
4577 | coef_count_node_start = VP9_MV_JOINTS_COUNT_START; | |
4578 | for (tree_i = 0; tree_i < 1; tree_i++) { | |
4579 | for (node = 0; node < 3; node++) { | |
4580 | switch (node) { | |
4581 | case 2: | |
4582 | tree_left = | |
4583 | count[coef_count_node_start + 2]; | |
4584 | tree_right = | |
4585 | count[coef_count_node_start + 3]; | |
4586 | break; | |
4587 | case 1: | |
4588 | tree_left = | |
4589 | count[coef_count_node_start + 1]; | |
4590 | tree_right = | |
4591 | count[coef_count_node_start + 2] + | |
4592 | count[coef_count_node_start + 3]; | |
4593 | break; | |
4594 | default: | |
4595 | tree_left = | |
4596 | count[coef_count_node_start + 0]; | |
4597 | tree_right = | |
4598 | count[coef_count_node_start + 1] + | |
4599 | count[coef_count_node_start + 2] + | |
4600 | count[coef_count_node_start + 3]; | |
4601 | break; | |
4602 | } | |
4603 | ||
4604 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4605 | coef_node_start, | |
4606 | tree_left, tree_right, tree_i, node); | |
4607 | ||
4608 | coef_node_start = coef_node_start + 1; | |
4609 | } | |
4610 | coef_count_node_start = coef_count_node_start + 4; | |
4611 | } | |
4612 | ||
4613 | for (mvd_i = 0; mvd_i < 2; mvd_i++) { | |
4614 | if (debug & VP9_DEBUG_MERGE) | |
4615 | pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i); | |
4616 | coef_node_start = | |
4617 | mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START; | |
4618 | coef_count_node_start = | |
4619 | mvd_i ? VP9_MV_CLASSES_1_COUNT_START | |
4620 | : VP9_MV_CLASSES_0_COUNT_START; | |
4621 | tree_i = 0; | |
4622 | for (node = 0; node < 10; node++) { | |
4623 | switch (node) { | |
4624 | case 9: | |
4625 | tree_left = | |
4626 | count[coef_count_node_start + 9]; | |
4627 | tree_right = | |
4628 | count[coef_count_node_start + 10]; | |
4629 | break; | |
4630 | case 8: | |
4631 | tree_left = | |
4632 | count[coef_count_node_start + 7]; | |
4633 | tree_right = | |
4634 | count[coef_count_node_start + 8]; | |
4635 | break; | |
4636 | case 7: | |
4637 | tree_left = | |
4638 | count[coef_count_node_start + 7] + | |
4639 | count[coef_count_node_start + 8]; | |
4640 | tree_right = | |
4641 | count[coef_count_node_start + 9] + | |
4642 | count[coef_count_node_start + 10]; | |
4643 | break; | |
4644 | case 6: | |
4645 | tree_left = | |
4646 | count[coef_count_node_start + 6]; | |
4647 | tree_right = | |
4648 | count[coef_count_node_start + 7] + | |
4649 | count[coef_count_node_start + 8] + | |
4650 | count[coef_count_node_start + 9] + | |
4651 | count[coef_count_node_start + 10]; | |
4652 | break; | |
4653 | case 5: | |
4654 | tree_left = | |
4655 | count[coef_count_node_start + 4]; | |
4656 | tree_right = | |
4657 | count[coef_count_node_start + 5]; | |
4658 | break; | |
4659 | case 4: | |
4660 | tree_left = | |
4661 | count[coef_count_node_start + 4] + | |
4662 | count[coef_count_node_start + 5]; | |
4663 | tree_right = | |
4664 | count[coef_count_node_start + 6] + | |
4665 | count[coef_count_node_start + 7] + | |
4666 | count[coef_count_node_start + 8] + | |
4667 | count[coef_count_node_start + 9] + | |
4668 | count[coef_count_node_start + 10]; | |
4669 | break; | |
4670 | case 3: | |
4671 | tree_left = | |
4672 | count[coef_count_node_start + 2]; | |
4673 | tree_right = | |
4674 | count[coef_count_node_start + 3]; | |
4675 | break; | |
4676 | case 2: | |
4677 | tree_left = | |
4678 | count[coef_count_node_start + 2] + | |
4679 | count[coef_count_node_start + 3]; | |
4680 | tree_right = | |
4681 | count[coef_count_node_start + 4] + | |
4682 | count[coef_count_node_start + 5] + | |
4683 | count[coef_count_node_start + 6] + | |
4684 | count[coef_count_node_start + 7] + | |
4685 | count[coef_count_node_start + 8] + | |
4686 | count[coef_count_node_start + 9] + | |
4687 | count[coef_count_node_start + 10]; | |
4688 | break; | |
4689 | case 1: | |
4690 | tree_left = | |
4691 | count[coef_count_node_start + 1]; | |
4692 | tree_right = | |
4693 | count[coef_count_node_start + 2] + | |
4694 | count[coef_count_node_start + 3] + | |
4695 | count[coef_count_node_start + 4] + | |
4696 | count[coef_count_node_start + 5] + | |
4697 | count[coef_count_node_start + 6] + | |
4698 | count[coef_count_node_start + 7] + | |
4699 | count[coef_count_node_start + 8] + | |
4700 | count[coef_count_node_start + 9] + | |
4701 | count[coef_count_node_start + 10]; | |
4702 | break; | |
4703 | default: | |
4704 | tree_left = | |
4705 | count[coef_count_node_start + 0]; | |
4706 | tree_right = | |
4707 | count[coef_count_node_start + 1] + | |
4708 | count[coef_count_node_start + 2] + | |
4709 | count[coef_count_node_start + 3] + | |
4710 | count[coef_count_node_start + 4] + | |
4711 | count[coef_count_node_start + 5] + | |
4712 | count[coef_count_node_start + 6] + | |
4713 | count[coef_count_node_start + 7] + | |
4714 | count[coef_count_node_start + 8] + | |
4715 | count[coef_count_node_start + 9] + | |
4716 | count[coef_count_node_start + 10]; | |
4717 | break; | |
4718 | ||
4719 | } | |
4720 | ||
4721 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4722 | coef_node_start, tree_left, tree_right, | |
4723 | tree_i, node); | |
4724 | ||
4725 | coef_node_start = coef_node_start + 1; | |
4726 | } | |
4727 | ||
4728 | if (debug & VP9_DEBUG_MERGE) | |
4729 | pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i); | |
4730 | coef_node_start = | |
4731 | mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START; | |
4732 | coef_count_node_start = | |
4733 | mvd_i ? VP9_MV_CLASS0_1_COUNT_START : | |
4734 | VP9_MV_CLASS0_0_COUNT_START; | |
4735 | tree_i = 0; | |
4736 | node = 0; | |
4737 | tree_left = count[coef_count_node_start + 0]; | |
4738 | tree_right = count[coef_count_node_start + 1]; | |
4739 | ||
4740 | vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start, | |
4741 | tree_left, tree_right, tree_i, node); | |
4742 | if (debug & VP9_DEBUG_MERGE) | |
4743 | pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n", | |
4744 | mvd_i); | |
4745 | coef_node_start = | |
4746 | mvd_i ? VP9_MV_CLASS0_FP_1_START : | |
4747 | VP9_MV_CLASS0_FP_0_START; | |
4748 | coef_count_node_start = | |
4749 | mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START : | |
4750 | VP9_MV_CLASS0_FP_0_COUNT_START; | |
4751 | for (tree_i = 0; tree_i < 3; tree_i++) { | |
4752 | for (node = 0; node < 3; node++) { | |
4753 | switch (node) { | |
4754 | case 2: | |
4755 | tree_left = | |
4756 | count[coef_count_node_start + 2]; | |
4757 | tree_right = | |
4758 | count[coef_count_node_start + 3]; | |
4759 | break; | |
4760 | case 1: | |
4761 | tree_left = | |
4762 | count[coef_count_node_start + 1]; | |
4763 | tree_right = | |
4764 | count[coef_count_node_start + 2] | |
4765 | + count[coef_count_node_start + 3]; | |
4766 | break; | |
4767 | default: | |
4768 | tree_left = | |
4769 | count[coef_count_node_start + 0]; | |
4770 | tree_right = | |
4771 | count[coef_count_node_start + 1] | |
4772 | + count[coef_count_node_start + 2] | |
4773 | + count[coef_count_node_start + 3]; | |
4774 | break; | |
4775 | ||
4776 | } | |
4777 | ||
4778 | vp9_tree_merge_probs(prev_prob, cur_prob, | |
4779 | coef_node_start, tree_left, tree_right, | |
4780 | tree_i, node); | |
4781 | ||
4782 | coef_node_start = coef_node_start + 1; | |
4783 | } | |
4784 | coef_count_node_start = coef_count_node_start + 4; | |
4785 | } | |
4786 | ||
4787 | } /* for mvd_i (mvd_y or mvd_x)*/ | |
4788 | } | |
4789 | ||
4790 | } | |
4791 | ||
75803959 NQ |
4792 | static bool v4l_is_there_vframe_bound(struct VP9Decoder_s *pbi) |
4793 | { | |
4794 | int i; | |
4795 | struct VP9_Common_s *const cm = &pbi->common; | |
4796 | struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; | |
4797 | ||
4798 | for (i = 0; i < pbi->used_buf_num; ++i) { | |
4799 | if (frame_bufs[i].buf.vframe_bound) | |
4800 | return true; | |
4801 | } | |
4802 | ||
4803 | return false; | |
4804 | } | |
4805 | ||
4806 | static void v4l_mmu_buffer_release(struct VP9Decoder_s *pbi) | |
4807 | { | |
4808 | struct VP9_Common_s *const cm = &pbi->common; | |
4809 | struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; | |
4810 | int i; | |
4811 | ||
4812 | /* release workspace */ | |
4813 | if (pbi->bmmu_box) | |
4814 | decoder_bmmu_box_free_idx(pbi->bmmu_box, | |
4815 | WORK_SPACE_BUF_ID); | |
4816 | /* | |
4817 | * it's only when vframe get back to driver, right now we can be sure | |
4818 | * that vframe and fd are related. if the playback exits, the capture | |
4819 | * requires the upper app to release when the fd is closed, and others | |
4820 | * buffers drivers are released by driver. | |
4821 | */ | |
4822 | for (i = 0; i < pbi->used_buf_num; ++i) { | |
4823 | if (!frame_bufs[i].buf.vframe_bound) { | |
4824 | if (pbi->bmmu_box) | |
4825 | decoder_bmmu_box_free_idx(pbi->bmmu_box, | |
4826 | HEADER_BUFFER_IDX(i)); | |
4827 | if (pbi->mmu_box) | |
4828 | decoder_mmu_box_free_idx(pbi->mmu_box, i); | |
4829 | ||
4830 | vp9_print(pbi, PRINT_FLAG_V4L_DETAIL, | |
4831 | "%s free buffer[%d], bmmu_box: %p, mmu_box: %p\n", | |
4832 | __func__, i, pbi->bmmu_box, pbi->mmu_box); | |
4833 | } | |
4834 | } | |
4835 | } | |
b9164398 NQ |
4836 | |
4837 | static void uninit_mmu_buffers(struct VP9Decoder_s *pbi) | |
4838 | { | |
fe96802b NQ |
4839 | #ifndef MV_USE_FIXED_BUF |
4840 | dealloc_mv_bufs(pbi); | |
4841 | #endif | |
75803959 NQ |
4842 | if (pbi->is_used_v4l && |
4843 | v4l_is_there_vframe_bound(pbi)) { | |
4844 | if (get_double_write_mode(pbi) != 0x10) { | |
4845 | v4l_mmu_buffer_release(pbi); | |
4846 | return; | |
4847 | } | |
4848 | } | |
4849 | ||
b7706e1e | 4850 | if (pbi->mmu_box) |
4851 | decoder_mmu_box_free(pbi->mmu_box); | |
b9164398 NQ |
4852 | pbi->mmu_box = NULL; |
4853 | ||
4854 | if (pbi->bmmu_box) | |
4855 | decoder_bmmu_box_free(pbi->bmmu_box); | |
4856 | pbi->bmmu_box = NULL; | |
4857 | } | |
4858 | ||
75803959 NQ |
4859 | static int calc_luc_quantity(u32 w, u32 h) |
4860 | { | |
4861 | int lcu_size = 64; /*fixed 64*/ | |
4862 | int pic_width_64 = (w + 63) & (~0x3f); | |
4863 | int pic_height_32 = (h + 31) & (~0x1f); | |
4864 | int pic_width_lcu = (pic_width_64 % lcu_size) ? | |
4865 | pic_width_64 / lcu_size + 1 : pic_width_64 / lcu_size; | |
4866 | int pic_height_lcu = (pic_height_32 % lcu_size) ? | |
4867 | pic_height_32 / lcu_size + 1 : pic_height_32 / lcu_size; | |
4868 | ||
4869 | return pic_width_lcu * pic_height_lcu; | |
4870 | } | |
4871 | ||
4872 | static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi, | |
4873 | struct PIC_BUFFER_CONFIG_s *pic) | |
4874 | { | |
4875 | int ret = -1; | |
4876 | int i = pic->index; | |
4877 | int dw_mode = get_double_write_mode_init(pbi); | |
4878 | int lcu_total = calc_luc_quantity(pbi->frame_width, pbi->frame_height); | |
4879 | #ifdef MV_USE_FIXED_BUF | |
4880 | u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start + | |
4881 | pbi->work_space_buf->mpred_mv.buf_size; | |
4882 | #endif | |
4883 | struct vdec_v4l2_buffer *fb = NULL; | |
4884 | ||
5c405a1b | 4885 | if (i < 0) |
4886 | return ret; | |
4887 | ||
75803959 NQ |
4888 | ret = vdec_v4l_get_buffer(pbi->v4l2_ctx, &fb); |
4889 | if (ret < 0) { | |
4890 | vp9_print(pbi, 0, "[%d] VP9 get buffer fail.\n", | |
4891 | ((struct aml_vcodec_ctx *) (pbi->v4l2_ctx))->id); | |
4892 | return ret; | |
4893 | } | |
4894 | ||
4895 | if (pbi->mmu_enable) { | |
4896 | pbi->m_BUF[i].header_addr = decoder_bmmu_box_get_phy_addr( | |
4897 | pbi->bmmu_box, HEADER_BUFFER_IDX(i)); | |
4898 | if (debug & VP9_DEBUG_BUFMGR_MORE) { | |
4899 | pr_info("MMU header_adr %d: %ld\n", | |
4900 | i, pbi->m_BUF[i].header_addr); | |
4901 | } | |
4902 | } | |
4903 | ||
4904 | #ifdef MV_USE_FIXED_BUF | |
4905 | if ((pbi->work_space_buf->mpred_mv.buf_start + | |
4906 | (((i + 1) * lcu_total) * MV_MEM_UNIT)) | |
4907 | <= mpred_mv_end) { | |
4908 | #endif | |
4909 | pbi->m_BUF[i].v4l_ref_buf_addr = (ulong)fb; | |
4910 | pic->cma_alloc_addr = fb->m.mem[0].addr; | |
4911 | if (fb->num_planes == 1) { | |
4912 | pbi->m_BUF[i].start_adr = fb->m.mem[0].addr; | |
75803959 | 4913 | pbi->m_BUF[i].luma_size = fb->m.mem[0].offset; |
307badab | 4914 | pbi->m_BUF[i].size = fb->m.mem[0].size; |
75803959 | 4915 | fb->m.mem[0].bytes_used = fb->m.mem[0].size; |
307badab NQ |
4916 | pic->dw_y_adr = pbi->m_BUF[i].start_adr; |
4917 | pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size; | |
75803959 NQ |
4918 | } else if (fb->num_planes == 2) { |
4919 | pbi->m_BUF[i].start_adr = fb->m.mem[0].addr; | |
307badab NQ |
4920 | pbi->m_BUF[i].size = fb->m.mem[0].size; |
4921 | pbi->m_BUF[i].chroma_addr = fb->m.mem[1].addr; | |
4922 | pbi->m_BUF[i].chroma_size = fb->m.mem[1].size; | |
75803959 NQ |
4923 | fb->m.mem[0].bytes_used = fb->m.mem[0].size; |
4924 | fb->m.mem[1].bytes_used = fb->m.mem[1].size; | |
307badab NQ |
4925 | pic->dw_y_adr = pbi->m_BUF[i].start_adr; |
4926 | pic->dw_u_v_adr = pbi->m_BUF[i].chroma_addr; | |
75803959 NQ |
4927 | } |
4928 | ||
4929 | /* config frame buffer */ | |
4930 | if (pbi->mmu_enable) | |
4931 | pic->header_adr = pbi->m_BUF[i].header_addr; | |
4932 | ||
4933 | pic->BUF_index = i; | |
4934 | pic->lcu_total = lcu_total; | |
4935 | pic->mc_canvas_y = pic->index; | |
4936 | pic->mc_canvas_u_v = pic->index; | |
4937 | ||
4938 | if (dw_mode & 0x10) { | |
75803959 NQ |
4939 | pic->mc_canvas_y = (pic->index << 1); |
4940 | pic->mc_canvas_u_v = (pic->index << 1) + 1; | |
75803959 NQ |
4941 | } |
4942 | ||
4943 | #ifdef MV_USE_FIXED_BUF | |
4944 | pic->mpred_mv_wr_start_addr = | |
4945 | pbi->work_space_buf->mpred_mv.buf_start + | |
4946 | ((pic->index * lcu_total) * MV_MEM_UNIT); | |
4947 | #endif | |
4948 | if (debug) { | |
4949 | pr_info("%s index %d BUF_index %d ", | |
4950 | __func__, pic->index, | |
4951 | pic->BUF_index); | |
4952 | pr_info("comp_body_size %x comp_buf_size %x ", | |
4953 | pic->comp_body_size, | |
4954 | pic->buf_size); | |
4955 | pr_info("mpred_mv_wr_start_adr %ld\n", | |
4956 | pic->mpred_mv_wr_start_addr); | |
4957 | pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n", | |
4958 | pic->dw_y_adr, | |
4959 | pic->dw_u_v_adr); | |
4960 | } | |
4961 | #ifdef MV_USE_FIXED_BUF | |
4962 | } | |
4963 | #endif | |
4964 | return ret; | |
4965 | } | |
a6c89e96 NQ |
4966 | |
4967 | static int config_pic(struct VP9Decoder_s *pbi, | |
4968 | struct PIC_BUFFER_CONFIG_s *pic_config) | |
4969 | { | |
4970 | int ret = -1; | |
4971 | int i; | |
75803959 NQ |
4972 | int pic_width = pbi->init_pic_w; |
4973 | int pic_height = pbi->init_pic_h; | |
a6c89e96 NQ |
4974 | int lcu_size = 64; /*fixed 64*/ |
4975 | int pic_width_64 = (pic_width + 63) & (~0x3f); | |
4976 | int pic_height_32 = (pic_height + 31) & (~0x1f); | |
4977 | int pic_width_lcu = (pic_width_64 % lcu_size) ? | |
4978 | pic_width_64 / lcu_size + 1 | |
4979 | : pic_width_64 / lcu_size; | |
4980 | int pic_height_lcu = (pic_height_32 % lcu_size) ? | |
4981 | pic_height_32 / lcu_size + 1 | |
4982 | : pic_height_32 / lcu_size; | |
4983 | int lcu_total = pic_width_lcu * pic_height_lcu; | |
4984 | #ifdef MV_USE_FIXED_BUF | |
4985 | u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start + | |
4986 | pbi->work_space_buf->mpred_mv.buf_size; | |
4987 | #endif | |
4988 | u32 y_adr = 0; | |
4989 | int buf_size = 0; | |
4990 | ||
4991 | int losless_comp_header_size = | |
4992 | compute_losless_comp_header_size(pic_width, | |
4993 | pic_height); | |
4994 | int losless_comp_body_size = compute_losless_comp_body_size(pic_width, | |
4995 | pic_height, buf_alloc_depth == 10); | |
4996 | int mc_buffer_size = losless_comp_header_size + losless_comp_body_size; | |
4997 | int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16; | |
4998 | int mc_buffer_size_u_v = 0; | |
4999 | int mc_buffer_size_u_v_h = 0; | |
5000 | int dw_mode = get_double_write_mode_init(pbi); | |
5001 | ||
5002 | pbi->lcu_total = lcu_total; | |
5003 | ||
5004 | if (dw_mode) { | |
5005 | int pic_width_dw = pic_width / | |
5006 | get_double_write_ratio(pbi, dw_mode); | |
5007 | int pic_height_dw = pic_height / | |
5008 | get_double_write_ratio(pbi, dw_mode); | |
5009 | ||
5010 | int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f); | |
5011 | int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f); | |
5012 | int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ? | |
5013 | pic_width_64_dw / lcu_size + 1 | |
5014 | : pic_width_64_dw / lcu_size; | |
5015 | int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ? | |
b9164398 NQ |
5016 | pic_height_32_dw / lcu_size + 1 |
5017 | : pic_height_32_dw / lcu_size; | |
5018 | int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw; | |
b9164398 NQ |
5019 | mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2; |
5020 | mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16; | |
5021 | /*64k alignment*/ | |
5022 | buf_size = ((mc_buffer_size_u_v_h << 16) * 3); | |
5023 | buf_size = ((buf_size + 0xffff) >> 16) << 16; | |
5024 | } | |
b34d6d3e | 5025 | |
b9164398 NQ |
5026 | if (mc_buffer_size & 0xffff) /*64k alignment*/ |
5027 | mc_buffer_size_h += 1; | |
b7706e1e | 5028 | if ((!pbi->mmu_enable) && ((dw_mode & 0x10) == 0)) |
b9164398 | 5029 | buf_size += (mc_buffer_size_h << 16); |
b9164398 | 5030 | |
b7706e1e | 5031 | if (pbi->mmu_enable) { |
5032 | pic_config->header_adr = decoder_bmmu_box_get_phy_addr( | |
a6c89e96 | 5033 | pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index)); |
b9164398 | 5034 | |
b7706e1e | 5035 | if (debug & VP9_DEBUG_BUFMGR_MORE) { |
5036 | pr_info("MMU header_adr %d: %ld\n", | |
5037 | pic_config->index, pic_config->header_adr); | |
5038 | } | |
b9164398 | 5039 | } |
b9164398 NQ |
5040 | |
5041 | i = pic_config->index; | |
fe96802b | 5042 | #ifdef MV_USE_FIXED_BUF |
b9164398 NQ |
5043 | if ((pbi->work_space_buf->mpred_mv.buf_start + |
5044 | (((i + 1) * lcu_total) * MV_MEM_UNIT)) | |
5045 | <= mpred_mv_end | |
b9164398 | 5046 | ) { |
fe96802b | 5047 | #endif |
a6c89e96 | 5048 | if (buf_size > 0) { |
75803959 NQ |
5049 | ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, |
5050 | VF_BUFFER_IDX(i), | |
5051 | buf_size, DRIVER_NAME, | |
5052 | &pic_config->cma_alloc_addr); | |
5053 | if (ret < 0) { | |
5054 | pr_info( | |
5055 | "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n", | |
5056 | VF_BUFFER_IDX(i), | |
5057 | buf_size | |
5058 | ); | |
5059 | return ret; | |
a6c89e96 NQ |
5060 | } |
5061 | ||
5062 | if (pic_config->cma_alloc_addr) | |
5063 | y_adr = pic_config->cma_alloc_addr; | |
5064 | else { | |
5065 | pr_info( | |
5066 | "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n", | |
5067 | VF_BUFFER_IDX(i), | |
5068 | buf_size | |
5069 | ); | |
5070 | return -1; | |
5071 | } | |
b34d6d3e | 5072 | } |
a6c89e96 NQ |
5073 | { |
5074 | /*ensure get_pic_by_POC() | |
5075 | not get the buffer not decoded*/ | |
5076 | pic_config->BUF_index = i; | |
5077 | pic_config->lcu_total = lcu_total; | |
5078 | ||
5079 | pic_config->comp_body_size = losless_comp_body_size; | |
5080 | pic_config->buf_size = buf_size; | |
b7706e1e | 5081 | |
a6c89e96 NQ |
5082 | pic_config->mc_canvas_y = pic_config->index; |
5083 | pic_config->mc_canvas_u_v = pic_config->index; | |
a6c89e96 | 5084 | if (dw_mode & 0x10) { |
75803959 NQ |
5085 | pic_config->dw_y_adr = y_adr; |
5086 | pic_config->dw_u_v_adr = y_adr + | |
5087 | ((mc_buffer_size_u_v_h << 16) << 1); | |
a6c89e96 NQ |
5088 | |
5089 | pic_config->mc_canvas_y = | |
5090 | (pic_config->index << 1); | |
5091 | pic_config->mc_canvas_u_v = | |
5092 | (pic_config->index << 1) + 1; | |
b7706e1e | 5093 | } else if (dw_mode) { |
a6c89e96 | 5094 | pic_config->dw_y_adr = y_adr; |
a6c89e96 | 5095 | pic_config->dw_u_v_adr = pic_config->dw_y_adr + |
b7706e1e | 5096 | ((mc_buffer_size_u_v_h << 16) << 1); |
a6c89e96 | 5097 | } |
fe96802b | 5098 | #ifdef MV_USE_FIXED_BUF |
a6c89e96 NQ |
5099 | pic_config->mpred_mv_wr_start_addr = |
5100 | pbi->work_space_buf->mpred_mv.buf_start + | |
5101 | ((pic_config->index * lcu_total) | |
5102 | * MV_MEM_UNIT); | |
fe96802b | 5103 | #endif |
a6c89e96 NQ |
5104 | if (debug) { |
5105 | pr_info | |
b7706e1e | 5106 | ("%s index %d BUF_index %d ", |
a6c89e96 | 5107 | __func__, pic_config->index, |
b7706e1e | 5108 | pic_config->BUF_index); |
a6c89e96 NQ |
5109 | pr_info |
5110 | ("comp_body_size %x comp_buf_size %x ", | |
5111 | pic_config->comp_body_size, | |
5112 | pic_config->buf_size); | |
5113 | pr_info | |
5114 | ("mpred_mv_wr_start_adr %ld\n", | |
5115 | pic_config->mpred_mv_wr_start_addr); | |
5116 | pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n", | |
5117 | pic_config->dw_y_adr, | |
5118 | pic_config->dw_u_v_adr); | |
5119 | } | |
5120 | ret = 0; | |
b9164398 | 5121 | } |
fe96802b | 5122 | #ifdef MV_USE_FIXED_BUF |
b9164398 | 5123 | } |
fe96802b | 5124 | #endif |
b9164398 NQ |
5125 | return ret; |
5126 | } | |
5127 | ||
e0e39311 | 5128 | static int vvp9_mmu_compress_header_size(struct VP9Decoder_s *pbi) |
5129 | { | |
6f5ee885 | 5130 | if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) && |
e0e39311 | 5131 | IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h)) |
5132 | return (MMU_COMPRESS_8K_HEADER_SIZE); | |
5133 | ||
5134 | return (MMU_COMPRESS_HEADER_SIZE); | |
5135 | } | |
5136 | ||
5137 | /*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/ | |
5138 | static int vvp9_frame_mmu_map_size(struct VP9Decoder_s *pbi) | |
5139 | { | |
6f5ee885 | 5140 | if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) && |
e0e39311 | 5141 | IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h)) |
5142 | return (MAX_FRAME_8K_NUM * 4); | |
5143 | ||
5144 | return (MAX_FRAME_4K_NUM * 4); | |
5145 | } | |
5146 | ||
b9164398 NQ |
5147 | static void init_pic_list(struct VP9Decoder_s *pbi) |
5148 | { | |
5149 | int i; | |
5150 | struct VP9_Common_s *cm = &pbi->common; | |
5151 | struct PIC_BUFFER_CONFIG_s *pic_config; | |
df841122 | 5152 | u32 header_size; |
05afa03d | 5153 | struct vdec_s *vdec = hw_to_vdec(pbi); |
2cd6815e | 5154 | |
6276f4ff | 5155 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
e0e39311 | 5156 | header_size = vvp9_mmu_compress_header_size(pbi); |
b7706e1e | 5157 | /*alloc VP9 compress header first*/ |
5158 | for (i = 0; i < pbi->used_buf_num; i++) { | |
5159 | unsigned long buf_addr; | |
5160 | if (decoder_bmmu_box_alloc_buf_phy | |
a6c89e96 | 5161 | (pbi->bmmu_box, |
df841122 | 5162 | HEADER_BUFFER_IDX(i), header_size, |
a6c89e96 | 5163 | DRIVER_HEADER_NAME, |
b7706e1e | 5164 | &buf_addr) < 0) { |
5165 | pr_info("%s malloc compress header failed %d\n", | |
a6c89e96 | 5166 | DRIVER_HEADER_NAME, i); |
b7706e1e | 5167 | pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM; |
5168 | return; | |
5169 | } | |
b9164398 NQ |
5170 | } |
5171 | } | |
fe96802b | 5172 | for (i = 0; i < pbi->used_buf_num; i++) { |
b9164398 NQ |
5173 | pic_config = &cm->buffer_pool->frame_bufs[i].buf; |
5174 | pic_config->index = i; | |
5175 | pic_config->BUF_index = -1; | |
fe96802b | 5176 | pic_config->mv_buf_index = -1; |
05afa03d PY |
5177 | if (vdec->parallel_dec == 1) { |
5178 | pic_config->y_canvas_index = -1; | |
5179 | pic_config->uv_canvas_index = -1; | |
5180 | } | |
b9164398 NQ |
5181 | pic_config->y_crop_width = pbi->init_pic_w; |
5182 | pic_config->y_crop_height = pbi->init_pic_h; | |
b7706e1e | 5183 | pic_config->double_write_mode = get_double_write_mode(pbi); |
2cd6815e | 5184 | |
0fb7e163 NQ |
5185 | if (!pbi->is_used_v4l) { |
5186 | if (config_pic(pbi, pic_config) < 0) { | |
5187 | if (debug) | |
5188 | pr_info("Config_pic %d fail\n", | |
5189 | pic_config->index); | |
5190 | pic_config->index = -1; | |
5191 | break; | |
5192 | } | |
5193 | ||
5194 | if (pic_config->double_write_mode) { | |
5195 | set_canvas(pbi, pic_config); | |
5196 | } | |
b7706e1e | 5197 | } |
b9164398 | 5198 | } |
fe96802b | 5199 | for (; i < pbi->used_buf_num; i++) { |
b9164398 NQ |
5200 | pic_config = &cm->buffer_pool->frame_bufs[i].buf; |
5201 | pic_config->index = -1; | |
5202 | pic_config->BUF_index = -1; | |
fe96802b | 5203 | pic_config->mv_buf_index = -1; |
05afa03d PY |
5204 | if (vdec->parallel_dec == 1) { |
5205 | pic_config->y_canvas_index = -1; | |
5206 | pic_config->uv_canvas_index = -1; | |
5207 | } | |
b9164398 | 5208 | } |
fe96802b NQ |
5209 | pr_info("%s ok, used_buf_num = %d\n", |
5210 | __func__, pbi->used_buf_num); | |
b9164398 NQ |
5211 | } |
5212 | ||
b9164398 NQ |
5213 | static void init_pic_list_hw(struct VP9Decoder_s *pbi) |
5214 | { | |
5215 | int i; | |
5216 | struct VP9_Common_s *cm = &pbi->common; | |
5217 | struct PIC_BUFFER_CONFIG_s *pic_config; | |
5218 | /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/ | |
5219 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, | |
5220 | (0x1 << 1) | (0x1 << 2)); | |
5221 | ||
5222 | ||
fe96802b | 5223 | for (i = 0; i < pbi->used_buf_num; i++) { |
b9164398 NQ |
5224 | pic_config = &cm->buffer_pool->frame_bufs[i].buf; |
5225 | if (pic_config->index < 0) | |
5226 | break; | |
5227 | ||
6276f4ff HZ |
5228 | if (pbi->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) { |
5229 | ||
b7706e1e | 5230 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, |
5231 | pic_config->header_adr >> 5); | |
5232 | } else { | |
5233 | /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, | |
5234 | * pic_config->mc_y_adr | |
5235 | * | (pic_config->mc_canvas_y << 8) | 0x1); | |
5236 | */ | |
5237 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, | |
5238 | pic_config->dw_y_adr >> 5); | |
5239 | } | |
a6c89e96 | 5240 | #ifndef LOSLESS_COMPRESS_MODE |
b7706e1e | 5241 | /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, |
5242 | * pic_config->mc_u_v_adr | |
5243 | * | (pic_config->mc_canvas_u_v << 8)| 0x1); | |
5244 | */ | |
6276f4ff | 5245 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, |
b7706e1e | 5246 | pic_config->header_adr >> 5); |
5247 | #else | |
5248 | if (pic_config->double_write_mode & 0x10) { | |
b7706e1e | 5249 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, |
5250 | pic_config->dw_u_v_adr >> 5); | |
5251 | } | |
b9164398 NQ |
5252 | #endif |
5253 | } | |
5254 | WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1); | |
5255 | ||
5256 | /*Zero out canvas registers in IPP -- avoid simulation X*/ | |
5257 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, | |
5258 | (0 << 8) | (0 << 1) | 1); | |
5259 | for (i = 0; i < 32; i++) | |
5260 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0); | |
5261 | } | |
5262 | ||
5263 | ||
5264 | static void dump_pic_list(struct VP9Decoder_s *pbi) | |
5265 | { | |
fe96802b NQ |
5266 | struct VP9_Common_s *const cm = &pbi->common; |
5267 | struct PIC_BUFFER_CONFIG_s *pic_config; | |
5268 | int i; | |
5269 | for (i = 0; i < FRAME_BUFFERS; i++) { | |
5270 | pic_config = &cm->buffer_pool->frame_bufs[i].buf; | |
5271 | vp9_print(pbi, 0, | |
a6c89e96 | 5272 | "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n", |
fe96802b NQ |
5273 | i, |
5274 | pic_config->index, | |
5275 | #ifndef MV_USE_FIXED_BUF | |
5276 | pic_config->mv_buf_index, | |
5277 | #else | |
5278 | -1, | |
5279 | #endif | |
a6c89e96 NQ |
5280 | cm->buffer_pool-> |
5281 | frame_bufs[i].ref_count, | |
fe96802b NQ |
5282 | pic_config->vf_ref, |
5283 | pic_config->decode_idx, | |
5284 | pic_config->slice_type, | |
5285 | pic_config->y_crop_width, | |
5286 | pic_config->y_crop_height, | |
5287 | pic_config->cma_alloc_addr | |
5288 | ); | |
5289 | } | |
b9164398 NQ |
5290 | return; |
5291 | } | |
5292 | ||
5293 | static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth) | |
5294 | { | |
5295 | #ifdef LOSLESS_COMPRESS_MODE | |
5296 | unsigned int data32; | |
5297 | #endif | |
5298 | int losless_comp_header_size, losless_comp_body_size; | |
5299 | struct VP9_Common_s *cm = &pbi->common; | |
5300 | struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf; | |
e0614bf7 | 5301 | |
b9164398 NQ |
5302 | frame_width = cur_pic_config->y_crop_width; |
5303 | frame_height = cur_pic_config->y_crop_height; | |
5304 | cur_pic_config->bit_depth = bit_depth; | |
c23e8aee | 5305 | cur_pic_config->double_write_mode = get_double_write_mode(pbi); |
b9164398 NQ |
5306 | losless_comp_header_size = |
5307 | compute_losless_comp_header_size(cur_pic_config->y_crop_width, | |
5308 | cur_pic_config->y_crop_height); | |
5309 | losless_comp_body_size = | |
5310 | compute_losless_comp_body_size(cur_pic_config->y_crop_width, | |
5311 | cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10)); | |
5312 | cur_pic_config->comp_body_size = losless_comp_body_size; | |
5313 | #ifdef LOSLESS_COMPRESS_MODE | |
5314 | data32 = READ_VREG(HEVC_SAO_CTRL5); | |
5315 | if (bit_depth == VPX_BITS_10) | |
5316 | data32 &= ~(1 << 9); | |
5317 | else | |
5318 | data32 |= (1 << 9); | |
5319 | ||
5320 | WRITE_VREG(HEVC_SAO_CTRL5, data32); | |
5321 | ||
b7706e1e | 5322 | if (pbi->mmu_enable) { |
5323 | /*bit[4] : paged_mem_mode*/ | |
5324 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4)); | |
5325 | } else { | |
b9164398 | 5326 | /*bit[3] smem mdoe*/ |
b7706e1e | 5327 | if (bit_depth == VPX_BITS_10) |
5328 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3)); | |
5329 | else | |
5330 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3)); | |
5331 | } | |
6f5ee885 | 5332 | if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1) |
df841122 | 5333 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5)); |
b9164398 NQ |
5334 | /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/ |
5335 | WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size); | |
5336 | WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size); | |
5337 | WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size); | |
b7706e1e | 5338 | if (get_double_write_mode(pbi) & 0x10) |
5339 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); | |
b9164398 NQ |
5340 | #else |
5341 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); | |
5342 | #endif | |
5343 | return 0; | |
5344 | } | |
5345 | ||
5346 | static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth) | |
5347 | { | |
5348 | int i; | |
5349 | struct VP9_Common_s *cm = &pbi->common; | |
5350 | struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf; | |
5351 | uint8_t scale_enable = 0; | |
5352 | ||
fe96802b | 5353 | if (debug&VP9_DEBUG_BUFMGR_MORE) |
b9164398 NQ |
5354 | pr_info("config_mc_buffer entered .....\n"); |
5355 | ||
5356 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, | |
5357 | (0 << 8) | (0 << 1) | 1); | |
5358 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
5359 | struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf; | |
fe96802b NQ |
5360 | if (!pic_config) |
5361 | continue; | |
b9164398 NQ |
5362 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, |
5363 | (pic_config->mc_canvas_u_v << 16) | |
5364 | | (pic_config->mc_canvas_u_v << 8) | |
5365 | | pic_config->mc_canvas_y); | |
5366 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
5367 | pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n", | |
5368 | i, pic_config->mc_canvas_u_v, | |
5369 | pic_config->mc_canvas_y); | |
5370 | } | |
5371 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, | |
5372 | (16 << 8) | (0 << 1) | 1); | |
5373 | for (i = 0; i < REFS_PER_FRAME; ++i) { | |
5374 | struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf; | |
fe96802b NQ |
5375 | if (!pic_config) |
5376 | continue; | |
b9164398 NQ |
5377 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, |
5378 | (pic_config->mc_canvas_u_v << 16) | |
5379 | | (pic_config->mc_canvas_u_v << 8) | |
5380 | | pic_config->mc_canvas_y); | |
5381 | } | |
5382 | ||
5383 | /*auto_inc start index:0 field:0*/ | |
5384 | WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2); | |
5385 | /*index 0:last 1:golden 2:altref*/ | |
5386 | for (i = 0; i < REFS_PER_FRAME; i++) { | |
5387 | int ref_pic_body_size; | |
5388 | struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf; | |
fe96802b NQ |
5389 | if (!pic_config) |
5390 | continue; | |
b9164398 NQ |
5391 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width); |
5392 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height); | |
5393 | ||
5394 | if (pic_config->y_crop_width != cur_pic_config->y_crop_width || | |
5395 | pic_config->y_crop_height != cur_pic_config->y_crop_height) { | |
5396 | scale_enable |= (1 << i); | |
5397 | } | |
5398 | ref_pic_body_size = | |
5399 | compute_losless_comp_body_size(pic_config->y_crop_width, | |
5400 | pic_config->y_crop_height, (bit_depth == VPX_BITS_10)); | |
5401 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, | |
5402 | (pic_config->y_crop_width << 14) | |
5403 | / cur_pic_config->y_crop_width); | |
5404 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, | |
5405 | (pic_config->y_crop_height << 14) | |
5406 | / cur_pic_config->y_crop_height); | |
b7706e1e | 5407 | if (pbi->mmu_enable) |
5408 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0); | |
5409 | else | |
5410 | WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5); | |
b9164398 NQ |
5411 | } |
5412 | WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable); | |
5413 | return 0; | |
5414 | } | |
5415 | ||
5416 | static void clear_mpred_hw(struct VP9Decoder_s *pbi) | |
5417 | { | |
5418 | unsigned int data32; | |
e0614bf7 | 5419 | |
b9164398 NQ |
5420 | data32 = READ_VREG(HEVC_MPRED_CTRL4); |
5421 | data32 &= (~(1 << 6)); | |
5422 | WRITE_VREG(HEVC_MPRED_CTRL4, data32); | |
5423 | } | |
5424 | ||
5425 | static void config_mpred_hw(struct VP9Decoder_s *pbi) | |
5426 | { | |
5427 | struct VP9_Common_s *cm = &pbi->common; | |
5428 | struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf; | |
5429 | struct PIC_BUFFER_CONFIG_s *last_frame_pic_config = | |
5430 | &cm->prev_frame->buf; | |
5431 | ||
5432 | unsigned int data32; | |
5433 | int mpred_curr_lcu_x; | |
5434 | int mpred_curr_lcu_y; | |
5435 | int mpred_mv_rd_end_addr; | |
b9164398 NQ |
5436 | |
5437 | ||
5438 | mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr | |
5439 | + (last_frame_pic_config->lcu_total * MV_MEM_UNIT); | |
5440 | ||
5441 | data32 = READ_VREG(HEVC_MPRED_CURR_LCU); | |
5442 | mpred_curr_lcu_x = data32 & 0xffff; | |
5443 | mpred_curr_lcu_y = (data32 >> 16) & 0xffff; | |
5444 | ||
5445 | if (debug & VP9_DEBUG_BUFMGR) | |
5446 | pr_info("cur pic_config index %d col pic_config index %d\n", | |
5447 | cur_pic_config->index, last_frame_pic_config->index); | |
5448 | WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412); | |
5449 | WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, | |
5450 | pbi->work_space_buf->mpred_above.buf_start); | |
5451 | ||
5452 | data32 = READ_VREG(HEVC_MPRED_CTRL4); | |
5453 | ||
5454 | data32 &= (~(1 << 6)); | |
5455 | data32 |= (cm->use_prev_frame_mvs << 6); | |
5456 | WRITE_VREG(HEVC_MPRED_CTRL4, data32); | |
5457 | ||
5458 | WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR, | |
5459 | cur_pic_config->mpred_mv_wr_start_addr); | |
5460 | WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr); | |
5461 | ||
5462 | WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR, | |
5463 | last_frame_pic_config->mpred_mv_wr_start_addr); | |
5464 | WRITE_VREG(HEVC_MPRED_MV_RPTR, | |
5465 | last_frame_pic_config->mpred_mv_wr_start_addr); | |
5466 | /*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/ | |
5467 | /*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/ | |
5468 | /*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/ | |
5469 | WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr); | |
5470 | ||
5471 | } | |
5472 | ||
5473 | static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params) | |
5474 | { | |
5475 | struct VP9_Common_s *cm = &pbi->common; | |
5476 | struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf; | |
5477 | ||
5478 | unsigned int data32; | |
5479 | int lcu_size = 64; | |
5480 | int mc_buffer_size_u_v = | |
5481 | pic_config->lcu_total * lcu_size*lcu_size/2; | |
5482 | int mc_buffer_size_u_v_h = | |
5483 | (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/ | |
0fb7e163 | 5484 | struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx; |
b7706e1e | 5485 | |
fe96802b | 5486 | if (get_double_write_mode(pbi)) { |
b9164398 NQ |
5487 | WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr); |
5488 | WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr); | |
5489 | WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr); | |
5490 | WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr); | |
5491 | } else { | |
5492 | WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff); | |
5493 | WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff); | |
5494 | } | |
b7706e1e | 5495 | if (pbi->mmu_enable) |
5496 | WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr); | |
5497 | ||
b9164398 NQ |
5498 | data32 = (mc_buffer_size_u_v_h << 16) << 1; |
5499 | /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n", | |
e0614bf7 ZZ |
5500 | * data32, mc_buffer_size_u_v_h, pic_config->lcu_total); |
5501 | */ | |
b9164398 NQ |
5502 | WRITE_VREG(HEVC_SAO_Y_LENGTH, data32); |
5503 | ||
5504 | data32 = (mc_buffer_size_u_v_h << 16); | |
5505 | WRITE_VREG(HEVC_SAO_C_LENGTH, data32); | |
5506 | ||
5507 | #ifdef VP9_10B_NV21 | |
5508 | #ifdef DOS_PROJECT | |
5509 | data32 = READ_VREG(HEVC_SAO_CTRL1); | |
5510 | data32 &= (~0x3000); | |
5511 | /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/ | |
0fb7e163 | 5512 | data32 |= (pbi->mem_map_mode << 12); |
b9164398 NQ |
5513 | data32 &= (~0x3); |
5514 | data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/ | |
5515 | WRITE_VREG(HEVC_SAO_CTRL1, data32); | |
5516 | /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl | |
e0614bf7 ZZ |
5517 | * [17:16] dw_h0_ctrl |
5518 | */ | |
b9164398 NQ |
5519 | data32 = READ_VREG(HEVC_SAO_CTRL5); |
5520 | /*set them all 0 for H265_NV21 (no down-scale)*/ | |
5521 | data32 &= ~(0xff << 16); | |
5522 | WRITE_VREG(HEVC_SAO_CTRL5, data32); | |
976f3376 | 5523 | data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); |
b9164398 NQ |
5524 | data32 &= (~0x30); |
5525 | /*[5:4] address_format 00:linear 01:32x32 10:64x32*/ | |
0fb7e163 | 5526 | data32 |= (pbi->mem_map_mode << 4); |
b9164398 NQ |
5527 | WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); |
5528 | #else | |
5529 | /*m8baby test1902*/ | |
5530 | data32 = READ_VREG(HEVC_SAO_CTRL1); | |
5531 | data32 &= (~0x3000); | |
5532 | /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/ | |
0fb7e163 | 5533 | data32 |= (pbi->mem_map_mode << 12); |
b9164398 NQ |
5534 | data32 &= (~0xff0); |
5535 | /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/ | |
5536 | data32 |= 0x880; /*.Big-Endian per 64-bit */ | |
5537 | data32 &= (~0x3); | |
5538 | data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/ | |
5539 | WRITE_VREG(HEVC_SAO_CTRL1, data32); | |
5540 | /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl | |
e0614bf7 ZZ |
5541 | *[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl |
5542 | */ | |
b9164398 NQ |
5543 | data32 = READ_VREG(HEVC_SAO_CTRL5); |
5544 | /* set them all 0 for H265_NV21 (no down-scale)*/ | |
5545 | data32 &= ~(0xff << 16); | |
5546 | WRITE_VREG(HEVC_SAO_CTRL5, data32); | |
5547 | ||
5548 | data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); | |
5549 | data32 &= (~0x30); | |
5550 | /*[5:4] address_format 00:linear 01:32x32 10:64x32*/ | |
0fb7e163 | 5551 | data32 |= (pbi->mem_map_mode << 4); |
b9164398 NQ |
5552 | data32 &= (~0xF); |
5553 | data32 |= 0x8; /*Big-Endian per 64-bit*/ | |
5554 | WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); | |
5555 | #endif | |
5556 | #else | |
5557 | data32 = READ_VREG(HEVC_SAO_CTRL1); | |
5558 | data32 &= (~0x3000); | |
0fb7e163 | 5559 | data32 |= (pbi->mem_map_mode << |
e0614bf7 ZZ |
5560 | 12); |
5561 | ||
5562 | /* [13:12] axi_aformat, 0-Linear, | |
5563 | * 1-32x32, 2-64x32 | |
5564 | */ | |
b9164398 NQ |
5565 | data32 &= (~0xff0); |
5566 | /* data32 |= 0x670; // Big-Endian per 64-bit */ | |
5567 | data32 |= endian; /* Big-Endian per 64-bit */ | |
9f1b18f7 HZ |
5568 | data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/ |
5569 | if (get_double_write_mode(pbi) == 0) | |
5570 | data32 |= 0x2; /*disable double write*/ | |
6276f4ff | 5571 | else if (get_double_write_mode(pbi) & 0x10) |
b9164398 | 5572 | data32 |= 0x1; /*disable cm*/ |
9f1b18f7 | 5573 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { /* >= G12A dw write control */ |
a6c89e96 NQ |
5574 | unsigned int data; |
5575 | data = READ_VREG(HEVC_DBLK_CFGB); | |
5576 | data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/ | |
5577 | if (get_double_write_mode(pbi) == 0) | |
5578 | data |= (0x1 << 8); /*enable first write*/ | |
6276f4ff | 5579 | else if (get_double_write_mode(pbi) & 0x10) |
a6c89e96 NQ |
5580 | data |= (0x1 << 9); /*double write only*/ |
5581 | else | |
5582 | data |= ((0x1 << 8) |(0x1 << 9)); | |
5583 | WRITE_VREG(HEVC_DBLK_CFGB, data); | |
5584 | } | |
0fb7e163 NQ |
5585 | |
5586 | /* swap uv */ | |
5587 | if (pbi->is_used_v4l) { | |
5588 | if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) || | |
5589 | (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M)) | |
5590 | data32 &= ~(1 << 8); /* NV21 */ | |
5591 | else | |
5592 | data32 |= (1 << 8); /* NV12 */ | |
5593 | } | |
5594 | ||
5595 | /* | |
5596 | * [31:24] ar_fifo1_axi_thred | |
5597 | * [23:16] ar_fifo0_axi_thred | |
5598 | * [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes | |
5599 | * [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32 | |
5600 | * [11:08] axi_lendian_C | |
5601 | * [07:04] axi_lendian_Y | |
5602 | * [3] reserved | |
5603 | * [2] clk_forceon | |
5604 | * [1] dw_disable:disable double write output | |
5605 | * [0] cm_disable:disable compress output | |
5606 | */ | |
b9164398 NQ |
5607 | WRITE_VREG(HEVC_SAO_CTRL1, data32); |
5608 | ||
fe96802b | 5609 | if (get_double_write_mode(pbi) & 0x10) { |
b9164398 | 5610 | /* [23:22] dw_v1_ctrl |
e0614bf7 ZZ |
5611 | *[21:20] dw_v0_ctrl |
5612 | *[19:18] dw_h1_ctrl | |
5613 | *[17:16] dw_h0_ctrl | |
5614 | */ | |
b9164398 NQ |
5615 | data32 = READ_VREG(HEVC_SAO_CTRL5); |
5616 | /*set them all 0 for H265_NV21 (no down-scale)*/ | |
5617 | data32 &= ~(0xff << 16); | |
5618 | WRITE_VREG(HEVC_SAO_CTRL5, data32); | |
5619 | } else { | |
5620 | data32 = READ_VREG(HEVC_SAO_CTRL5); | |
5621 | data32 &= (~(0xff << 16)); | |
c23e8aee HZ |
5622 | if (get_double_write_mode(pbi) == 2 || |
5623 | get_double_write_mode(pbi) == 3) | |
b9164398 | 5624 | data32 |= (0xff<<16); |
c23e8aee HZ |
5625 | else if (get_double_write_mode(pbi) == 4) |
5626 | data32 |= (0x33<<16); | |
b9164398 NQ |
5627 | WRITE_VREG(HEVC_SAO_CTRL5, data32); |
5628 | } | |
5629 | ||
5630 | data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); | |
5631 | data32 &= (~0x30); | |
5632 | /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */ | |
0fb7e163 | 5633 | data32 |= (pbi->mem_map_mode << |
b9164398 NQ |
5634 | 4); |
5635 | data32 &= (~0xF); | |
5636 | data32 |= 0xf; /* valid only when double write only */ | |
5637 | /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */ | |
0fb7e163 NQ |
5638 | |
5639 | /* swap uv */ | |
5640 | if (pbi->is_used_v4l) { | |
5641 | if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) || | |
5642 | (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M)) | |
5643 | data32 |= (1 << 12); /* NV21 */ | |
5644 | else | |
5645 | data32 &= ~(1 << 12); /* NV12 */ | |
5646 | } | |
5647 | ||
5648 | /* | |
5649 | * [3:0] little_endian | |
5650 | * [5:4] address_format 00:linear 01:32x32 10:64x32 | |
5651 | * [7:6] reserved | |
5652 | * [9:8] Linear_LineAlignment 00:16byte 01:32byte 10:64byte | |
5653 | * [11:10] reserved | |
5654 | * [12] CbCr_byte_swap | |
5655 | * [31:13] reserved | |
5656 | */ | |
b9164398 NQ |
5657 | WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); |
5658 | #endif | |
5659 | } | |
5660 | ||
a6c89e96 | 5661 | static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask) |
b9164398 NQ |
5662 | { |
5663 | struct BuffInfo_s *buf_spec = pbi->work_space_buf; | |
b9164398 | 5664 | unsigned int data32; |
b7706e1e | 5665 | |
fe96802b | 5666 | if (debug && pbi->init_flag == 0) |
b9164398 NQ |
5667 | pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n", |
5668 | __func__, | |
5669 | buf_spec->ipp.buf_start, | |
5670 | buf_spec->start_adr, | |
5671 | buf_spec->short_term_rps.buf_start, | |
5672 | buf_spec->vps.buf_start, | |
5673 | buf_spec->sps.buf_start, | |
5674 | buf_spec->pps.buf_start, | |
5675 | buf_spec->sao_up.buf_start, | |
5676 | buf_spec->swap_buf.buf_start, | |
5677 | buf_spec->swap_buf2.buf_start, | |
5678 | buf_spec->scalelut.buf_start, | |
5679 | buf_spec->dblk_para.buf_start, | |
5680 | buf_spec->dblk_data.buf_start); | |
b9164398 | 5681 | |
a6c89e96 NQ |
5682 | if (mask & HW_MASK_FRONT) { |
5683 | if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) | |
5684 | WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr); | |
5685 | ||
5686 | WRITE_VREG(HEVC_SHORT_TERM_RPS, | |
5687 | buf_spec->short_term_rps.buf_start); | |
5688 | /*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/ | |
5689 | /*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/ | |
5690 | WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start); | |
5691 | WRITE_VREG(HEVC_STREAM_SWAP_BUFFER, | |
5692 | buf_spec->swap_buf.buf_start); | |
5693 | WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, | |
5694 | buf_spec->swap_buf2.buf_start); | |
5695 | WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr); | |
5696 | ||
5697 | } | |
5698 | ||
5699 | if (mask & HW_MASK_BACK) { | |
b9164398 | 5700 | #ifdef LOSLESS_COMPRESS_MODE |
a6c89e96 NQ |
5701 | int losless_comp_header_size = |
5702 | compute_losless_comp_header_size(pbi->init_pic_w, | |
5703 | pbi->init_pic_h); | |
5704 | int losless_comp_body_size = | |
5705 | compute_losless_comp_body_size(pbi->init_pic_w, | |
5706 | pbi->init_pic_h, buf_alloc_depth == 10); | |
5707 | #endif | |
5708 | WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, | |
5709 | buf_spec->ipp.buf_start); | |
5710 | WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start); | |
5711 | WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start); | |
63e810c0 | 5712 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { |
a6c89e96 NQ |
5713 | /* cfg_addr_adp*/ |
5714 | WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start); | |
5715 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
5716 | pr_info("Write HEVC_DBLK_CFGE\n"); | |
a6c89e96 | 5717 | } |
4c9ec3c3 HZ |
5718 | /* cfg_p_addr */ |
5719 | WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start); | |
a6c89e96 NQ |
5720 | /* cfg_d_addr */ |
5721 | WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start); | |
5722 | ||
6f5ee885 | 5723 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
df841122 | 5724 | /* |
5725 | * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40 | |
5726 | * data32 = data32 * 2; | |
5727 | * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040 | |
5728 | * data32 = data32 * 2; | |
5729 | */ | |
5730 | WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k] | |
5731 | } | |
a6c89e96 | 5732 | #ifdef LOSLESS_COMPRESS_MODE |
b7706e1e | 5733 | if (pbi->mmu_enable) { |
b34d6d3e ZZ |
5734 | /*bit[4] : paged_mem_mode*/ |
5735 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4)); | |
6f5ee885 | 5736 | if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1) |
df841122 | 5737 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0); |
b7706e1e | 5738 | } else { |
b34d6d3e ZZ |
5739 | /*if(cur_pic_config->bit_depth == VPX_BITS_10) |
5740 | * WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3)); | |
5741 | */ | |
5742 | /*bit[3] smem mdoe*/ | |
5743 | /*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/ | |
5744 | /*bit[3] smem mdoe*/ | |
a6c89e96 NQ |
5745 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, |
5746 | (losless_comp_body_size >> 5)); | |
b7706e1e | 5747 | } |
5748 | /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, | |
5749 | (losless_comp_body_size >> 5));*/ | |
5750 | /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3, | |
5751 | (0xff<<20) | (0xff<<10) | 0xff);*/ | |
5752 | /*8-bit mode */ | |
5753 | WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size); | |
5754 | WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size); | |
5755 | WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size); | |
5756 | if (get_double_write_mode(pbi) & 0x10) | |
5757 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); | |
b9164398 NQ |
5758 | #else |
5759 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); | |
5760 | #endif | |
5761 | ||
b7706e1e | 5762 | if (pbi->mmu_enable) { |
b34d6d3e ZZ |
5763 | WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start); |
5764 | WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start | |
5765 | + buf_spec->mmu_vbh.buf_size/2); | |
5766 | /*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/ | |
5767 | /*data32 |= 0x1;*/ | |
5768 | /*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/ | |
b9164398 | 5769 | |
b34d6d3e ZZ |
5770 | /* use HEVC_CM_HEADER_START_ADDR */ |
5771 | data32 = READ_VREG(HEVC_SAO_CTRL5); | |
5772 | data32 |= (1<<10); | |
5773 | WRITE_VREG(HEVC_SAO_CTRL5, data32); | |
b7706e1e | 5774 | } |
5775 | ||
a6c89e96 NQ |
5776 | WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start); |
5777 | ||
b7706e1e | 5778 | WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr); |
a6c89e96 NQ |
5779 | /**/ |
5780 | WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr); | |
5781 | WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr); | |
b7706e1e | 5782 | if (pbi->mmu_enable) { |
5783 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) | |
5784 | WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr); | |
5785 | else | |
5786 | WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr); | |
5787 | } | |
b34d6d3e | 5788 | } |
b9164398 NQ |
5789 | } |
5790 | ||
5791 | ||
5792 | #ifdef VP9_LPF_LVL_UPDATE | |
5793 | /* | |
5794 | * Defines, declarations, sub-functions for vp9 de-block loop | |
5795 | filter Thr/Lvl table update | |
5796 | * - struct segmentation is for loop filter only (removed something) | |
5797 | * - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will | |
5798 | be instantiated in C_Entry | |
5799 | * - vp9_loop_filter_init run once before decoding start | |
5800 | * - vp9_loop_filter_frame_init run before every frame decoding start | |
5801 | * - set video format to VP9 is in vp9_loop_filter_init | |
5802 | */ | |
5803 | #define MAX_LOOP_FILTER 63 | |
5804 | #define MAX_REF_LF_DELTAS 4 | |
5805 | #define MAX_MODE_LF_DELTAS 2 | |
5806 | /*#define INTRA_FRAME 0*/ | |
5807 | /*#define LAST_FRAME 1*/ | |
5808 | /*#define MAX_REF_FRAMES 4*/ | |
5809 | #define SEGMENT_DELTADATA 0 | |
5810 | #define SEGMENT_ABSDATA 1 | |
5811 | #define MAX_SEGMENTS 8 | |
5812 | /*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/ | |
5813 | /*no use for loop filter, if this struct for common use, pls add it back*/ | |
5814 | /*#define PREDICTION_PROBS 3*/ | |
5815 | /* no use for loop filter, if this struct for common use, pls add it back*/ | |
5816 | ||
5817 | enum SEG_LVL_FEATURES { | |
5818 | SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/ | |
5819 | SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/ | |
5820 | SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/ | |
5821 | SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/ | |
5822 | SEG_LVL_MAX = 4 /*Number of features supported*/ | |
5823 | }; | |
5824 | ||
5825 | struct segmentation { | |
5826 | uint8_t enabled; | |
5827 | uint8_t update_map; | |
5828 | uint8_t update_data; | |
5829 | uint8_t abs_delta; | |
5830 | uint8_t temporal_update; | |
5831 | ||
5832 | /*no use for loop filter, if this struct | |
e0614bf7 ZZ |
5833 | *for common use, pls add it back |
5834 | */ | |
b9164398 NQ |
5835 | /*vp9_prob tree_probs[SEG_TREE_PROBS]; */ |
5836 | /* no use for loop filter, if this struct | |
e0614bf7 ZZ |
5837 | * for common use, pls add it back |
5838 | */ | |
b9164398 NQ |
5839 | /*vp9_prob pred_probs[PREDICTION_PROBS];*/ |
5840 | ||
5841 | int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX]; | |
5842 | unsigned int feature_mask[MAX_SEGMENTS]; | |
5843 | }; | |
5844 | ||
5845 | struct loop_filter_thresh { | |
5846 | uint8_t mblim; | |
5847 | uint8_t lim; | |
5848 | uint8_t hev_thr; | |
5849 | }; | |
5850 | ||
5851 | struct loop_filter_info_n { | |
5852 | struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1]; | |
5853 | uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS]; | |
5854 | }; | |
5855 | ||
5856 | struct loopfilter { | |
5857 | int filter_level; | |
5858 | ||
5859 | int sharpness_level; | |
5860 | int last_sharpness_level; | |
5861 | ||
5862 | uint8_t mode_ref_delta_enabled; | |
5863 | uint8_t mode_ref_delta_update; | |
5864 | ||
5865 | /*0 = Intra, Last, GF, ARF*/ | |
5866 | signed char ref_deltas[MAX_REF_LF_DELTAS]; | |
5867 | signed char last_ref_deltas[MAX_REF_LF_DELTAS]; | |
5868 | ||
5869 | /*0 = ZERO_MV, MV*/ | |
5870 | signed char mode_deltas[MAX_MODE_LF_DELTAS]; | |
5871 | signed char last_mode_deltas[MAX_MODE_LF_DELTAS]; | |
5872 | }; | |
5873 | ||
5874 | static int vp9_clamp(int value, int low, int high) | |
5875 | { | |
5876 | return value < low ? low : (value > high ? high : value); | |
5877 | } | |
5878 | ||
5879 | int segfeature_active(struct segmentation *seg, | |
5880 | int segment_id, | |
5881 | enum SEG_LVL_FEATURES feature_id) { | |
5882 | return seg->enabled && | |
5883 | (seg->feature_mask[segment_id] & (1 << feature_id)); | |
5884 | } | |
5885 | ||
5886 | int get_segdata(struct segmentation *seg, int segment_id, | |
5887 | enum SEG_LVL_FEATURES feature_id) { | |
5888 | return seg->feature_data[segment_id][feature_id]; | |
5889 | } | |
5890 | ||
5891 | static void vp9_update_sharpness(struct loop_filter_info_n *lfi, | |
5892 | int sharpness_lvl) | |
5893 | { | |
5894 | int lvl; | |
5895 | /*For each possible value for the loop filter fill out limits*/ | |
5896 | for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) { | |
5897 | /*Set loop filter parameters that control sharpness.*/ | |
5898 | int block_inside_limit = lvl >> ((sharpness_lvl > 0) + | |
5899 | (sharpness_lvl > 4)); | |
5900 | ||
5901 | if (sharpness_lvl > 0) { | |
5902 | if (block_inside_limit > (9 - sharpness_lvl)) | |
5903 | block_inside_limit = (9 - sharpness_lvl); | |
5904 | } | |
5905 | ||
5906 | if (block_inside_limit < 1) | |
5907 | block_inside_limit = 1; | |
5908 | ||
5909 | lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit; | |
5910 | lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) + | |
5911 | block_inside_limit); | |
5912 | } | |
5913 | } | |
5914 | ||
b9164398 | 5915 | /*instantiate this function once when decode is started*/ |
fe96802b | 5916 | void vp9_loop_filter_init(struct VP9Decoder_s *pbi) |
b9164398 | 5917 | { |
fe96802b NQ |
5918 | struct loop_filter_info_n *lfi = pbi->lfi; |
5919 | struct loopfilter *lf = pbi->lf; | |
5920 | struct segmentation *seg_4lf = pbi->seg_4lf; | |
b9164398 | 5921 | int i; |
df841122 | 5922 | unsigned int data32; |
fe96802b | 5923 | |
b9164398 NQ |
5924 | memset(lfi, 0, sizeof(struct loop_filter_info_n)); |
5925 | memset(lf, 0, sizeof(struct loopfilter)); | |
5926 | memset(seg_4lf, 0, sizeof(struct segmentation)); | |
5927 | lf->sharpness_level = 0; /*init to 0 */ | |
5928 | /*init limits for given sharpness*/ | |
5929 | vp9_update_sharpness(lfi, lf->sharpness_level); | |
5930 | lf->last_sharpness_level = lf->sharpness_level; | |
5931 | /*init hev threshold const vectors (actually no use) | |
e0614bf7 ZZ |
5932 | *for (i = 0; i <= MAX_LOOP_FILTER; i++) |
5933 | * lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4); | |
5934 | */ | |
b9164398 NQ |
5935 | |
5936 | /*Write to register*/ | |
5937 | for (i = 0; i < 32; i++) { | |
5938 | unsigned int thr; | |
e0614bf7 | 5939 | |
b9164398 NQ |
5940 | thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) | |
5941 | (lfi->lfthr[i * 2 + 1].mblim & 0xff); | |
5942 | thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) | | |
5943 | (lfi->lfthr[i * 2].mblim & 0xff); | |
5944 | WRITE_VREG(HEVC_DBLK_CFG9, thr); | |
5945 | } | |
5946 | ||
5947 | /*video format is VP9*/ | |
6f5ee885 | 5948 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
df841122 | 5949 | data32 = (0x3 << 14) | // (dw fifo thres r and b) |
5950 | (0x3 << 12) | // (dw fifo thres r or b) | |
5951 | (0x3 << 10) | // (dw fifo thres not r/b) | |
5952 | (0x3 << 8) | // 1st/2nd write both enable | |
5953 | (0x1 << 0); // vp9 video format | |
9f1b18f7 HZ |
5954 | if (get_double_write_mode(pbi) == 0x10) |
5955 | data32 &= (~0x100); | |
df841122 | 5956 | } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { |
a6c89e96 | 5957 | data32 = (0x57 << 8) | /*1st/2nd write both enable*/ |
df841122 | 5958 | (0x1 << 0); /*vp9 video format*/ |
9f1b18f7 HZ |
5959 | if (get_double_write_mode(pbi) == 0x10) |
5960 | data32 &= (~0x100); | |
a6c89e96 | 5961 | } else |
df841122 | 5962 | data32 = 0x40400001; |
5963 | ||
5964 | WRITE_VREG(HEVC_DBLK_CFGB, data32); | |
5965 | if (debug & VP9_DEBUG_BUFMGR_MORE) | |
5966 | pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32); | |
b9164398 NQ |
5967 | } |
5968 | /* perform this function per frame*/ | |
5969 | void vp9_loop_filter_frame_init(struct segmentation *seg, | |
5970 | struct loop_filter_info_n *lfi, struct loopfilter *lf, | |
5971 | int default_filt_lvl) { | |
5972 | int i; | |
5973 | int seg_id; | |
5974 | /*n_shift is the multiplier for lf_deltas | |
e0614bf7 ZZ |
5975 | *the multiplier is 1 for when filter_lvl is between 0 and 31; |
5976 | *2 when filter_lvl is between 32 and 63 | |
5977 | */ | |
b9164398 NQ |
5978 | const int scale = 1 << (default_filt_lvl >> 5); |
5979 | ||
5980 | /*update limits if sharpness has changed*/ | |
5981 | if (lf->last_sharpness_level != lf->sharpness_level) { | |
5982 | vp9_update_sharpness(lfi, lf->sharpness_level); | |
5983 | lf->last_sharpness_level = lf->sharpness_level; | |
5984 | ||
5985 | /*Write to register*/ | |
5986 | for (i = 0; i < 32; i++) { | |
5987 | unsigned int thr; | |
e0614bf7 | 5988 | |
b9164398 NQ |
5989 | thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8) |
5990 | | (lfi->lfthr[i * 2 + 1].mblim & 0xff); | |
5991 | thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8) | |
5992 | | (lfi->lfthr[i * 2].mblim & 0xff); | |
5993 | WRITE_VREG(HEVC_DBLK_CFG9, thr); | |
5994 | } | |
5995 | } | |
5996 | ||
5997 | for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/ | |
5998 | int lvl_seg = default_filt_lvl; | |
e0614bf7 | 5999 | |
b9164398 NQ |
6000 | if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) { |
6001 | const int data = get_segdata(seg, seg_id, | |
6002 | SEG_LVL_ALT_LF); | |
6003 | lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ? | |
6004 | data : default_filt_lvl + data, | |
6005 | 0, MAX_LOOP_FILTER); | |
6006 | #ifdef DBG_LF_PRINT | |
6007 | pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg); | |
6008 | #endif | |
6009 | } | |
6010 | ||
6011 | if (!lf->mode_ref_delta_enabled) { | |
6012 | /*we could get rid of this if we assume that deltas are set to | |
e0614bf7 ZZ |
6013 | *zero when not in use; encoder always uses deltas |
6014 | */ | |
b9164398 NQ |
6015 | memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id])); |
6016 | } else { | |
6017 | int ref, mode; | |
6018 | const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME] | |
6019 | * scale; | |
6020 | #ifdef DBG_LF_PRINT | |
6021 | pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id); | |
6022 | pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]); | |
6023 | #endif | |
6024 | lfi->lvl[seg_id][INTRA_FRAME][0] = | |
6025 | vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER); | |
6026 | ||
6027 | for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) { | |
6028 | /* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/ | |
6029 | for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) { | |
6030 | /*MAX_MODE_LF_DELTAS = 2*/ | |
6031 | const int inter_lvl = | |
6032 | lvl_seg + lf->ref_deltas[ref] * scale | |
6033 | + lf->mode_deltas[mode] * scale; | |
6034 | #ifdef DBG_LF_PRINT | |
6035 | #endif | |
6036 | lfi->lvl[seg_id][ref][mode] = | |
6037 | vp9_clamp(inter_lvl, 0, | |
6038 | MAX_LOOP_FILTER); | |
6039 | } | |
6040 | } | |
6041 | } | |
6042 | } | |
6043 | ||
6044 | #ifdef DBG_LF_PRINT | |
6045 | /*print out thr/lvl table per frame*/ | |
6046 | for (i = 0; i <= MAX_LOOP_FILTER; i++) { | |
6047 | pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n", | |
6048 | i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim, | |
6049 | lfi->lfthr[i].lim); | |
6050 | } | |
6051 | for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) { | |
6052 | pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n", | |
6053 | seg_id, lfi->lvl[seg_id][0][0], | |
6054 | lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0], | |
6055 | lfi->lvl[seg_id][3][0]); | |
6056 | pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1], | |
6057 | lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1], | |
6058 | lfi->lvl[seg_id][3][1]); | |
6059 | } | |
6060 | #endif | |
6061 | ||
6062 | /*Write to register */ | |
6063 | for (i = 0; i < 16; i++) { | |
6064 | unsigned int level; | |
e0614bf7 | 6065 | |
b9164398 NQ |
6066 | level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) | |
6067 | ((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) | | |
6068 | ((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) | | |
6069 | (lfi->lvl[i >> 1][0][i & 1] & 0x3f); | |
6070 | if (!default_filt_lvl) | |
6071 | level = 0; | |
6072 | WRITE_VREG(HEVC_DBLK_CFGA, level); | |
6073 | } | |
6074 | } | |
6075 | /* VP9_LPF_LVL_UPDATE */ | |
6076 | #endif | |
6077 | ||
a6c89e96 | 6078 | static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask) |
b9164398 NQ |
6079 | { |
6080 | unsigned int data32; | |
6081 | int i; | |
a674e3cd | 6082 | const unsigned short parser_cmd[PARSER_CMD_NUMBER] = { |
6083 | 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423, | |
6084 | 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE, | |
6085 | 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A, | |
6086 | 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408, | |
6087 | 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D, | |
6088 | 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00, | |
6089 | 0x7C00 | |
6090 | }; | |
a6c89e96 | 6091 | #if 0 |
df841122 | 6092 | if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) { |
a6c89e96 NQ |
6093 | /* Set MCR fetch priorities*/ |
6094 | data32 = 0x1 | (0x1 << 2) | (0x1 <<3) | | |
6095 | (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25); | |
6096 | WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32); | |
6097 | } | |
6098 | #endif | |
fe96802b NQ |
6099 | /*if (debug & VP9_DEBUG_BUFMGR_MORE) |
6100 | pr_info("%s\n", __func__);*/ | |
a6c89e96 | 6101 | if (mask & HW_MASK_FRONT) { |
b9164398 NQ |
6102 | data32 = READ_VREG(HEVC_PARSER_INT_CONTROL); |
6103 | #if 1 | |
6104 | /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */ | |
6105 | data32 &= ~(7 << 29); | |
6106 | data32 |= (3 << 29); | |
6107 | #endif | |
6108 | data32 = data32 | | |
6109 | (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/ | |
6110 | (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/ | |
6111 | (1 << 7) |/*dec_done_int_cpu_enable*/ | |
6112 | (1 << 4) |/*startcode_found_int_cpu_enable*/ | |
6113 | (0 << 3) |/*startcode_found_int_amrisc_enable*/ | |
6114 | (1 << 0) /*parser_int_enable*/ | |
6115 | ; | |
a6c89e96 NQ |
6116 | #ifdef SUPPORT_FB_DECODING |
6117 | #ifndef FB_DECODING_TEST_SCHEDULE | |
6118 | /*fed_fb_slice_done_int_cpu_enable*/ | |
6119 | if (pbi->used_stage_buf_num > 0) | |
6120 | data32 |= (1 << 10); | |
6121 | #endif | |
6122 | #endif | |
6123 | WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32); | |
b9164398 | 6124 | |
fe96802b NQ |
6125 | data32 = READ_VREG(HEVC_SHIFT_STATUS); |
6126 | data32 = data32 | | |
6127 | (0 << 1) |/*emulation_check_off VP9 | |
6128 | do not have emulation*/ | |
6129 | (1 << 0)/*startcode_check_on*/ | |
6130 | ; | |
6131 | WRITE_VREG(HEVC_SHIFT_STATUS, data32); | |
6132 | WRITE_VREG(HEVC_SHIFT_CONTROL, | |
6133 | (0 << 14) | /*disable_start_code_protect*/ | |
6134 | (1 << 10) | /*length_zero_startcode_en for VP9*/ | |
6135 | (1 << 9) | /*length_valid_startcode_en for VP9*/ | |
6136 | (3 << 6) | /*sft_valid_wr_position*/ | |
6137 | (2 << 4) | /*emulate_code_length_sub_1*/ | |
6138 | (3 << 1) | /*start_code_length_sub_1 | |
6139 | VP9 use 0x00000001 as startcode (4 Bytes)*/ | |
6140 | (1 << 0) /*stream_shift_enable*/ | |
6141 | ); | |
b9164398 NQ |
6142 | |
6143 | WRITE_VREG(HEVC_CABAC_CONTROL, | |
6144 | (1 << 0)/*cabac_enable*/ | |
6145 | ); | |
6146 | ||
6147 | WRITE_VREG(HEVC_PARSER_CORE_CONTROL, | |
6148 | (1 << 0)/* hevc_parser_core_clk_en*/ | |
6149 | ); | |
6150 | ||
6151 | ||
6152 | WRITE_VREG(HEVC_DEC_STATUS_REG, 0); | |
6153 | ||
a6c89e96 NQ |
6154 | } |
6155 | ||
6156 | if (mask & HW_MASK_BACK) { | |
6157 | /*Initial IQIT_SCALELUT memory | |
6158 | -- just to avoid X in simulation*/ | |
b9164398 | 6159 | |
a6c89e96 NQ |
6160 | WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/ |
6161 | for (i = 0; i < 1024; i++) | |
6162 | WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0); | |
6163 | } | |
6164 | ||
6165 | if (mask & HW_MASK_FRONT) { | |
6166 | u32 decode_mode; | |
b9164398 NQ |
6167 | #ifdef ENABLE_SWAP_TEST |
6168 | WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100); | |
6169 | #else | |
6170 | WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0); | |
6171 | #endif | |
6172 | #ifdef MULTI_INSTANCE_SUPPORT | |
187af067 | 6173 | if (!pbi->m_ins_flag) { |
6174 | if (pbi->low_latency_flag) | |
6175 | decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY; | |
6176 | else | |
6177 | decode_mode = DECODE_MODE_SINGLE; | |
6178 | } else if (vdec_frame_based(hw_to_vdec(pbi))) | |
0eb79ad7 RZ |
6179 | decode_mode = pbi->no_head ? |
6180 | DECODE_MODE_MULTI_FRAMEBASE_NOHEAD : | |
6181 | DECODE_MODE_MULTI_FRAMEBASE; | |
a6c89e96 NQ |
6182 | else |
6183 | decode_mode = DECODE_MODE_MULTI_STREAMBASE; | |
6184 | #ifdef SUPPORT_FB_DECODING | |
6185 | #ifndef FB_DECODING_TEST_SCHEDULE | |
6186 | if (pbi->used_stage_buf_num > 0) | |
6187 | decode_mode |= (0x01 << 24); | |
6188 | #endif | |
6189 | #endif | |
6190 | WRITE_VREG(DECODE_MODE, decode_mode); | |
6191 | WRITE_VREG(HEVC_DECODE_SIZE, 0); | |
6192 | WRITE_VREG(HEVC_DECODE_COUNT, 0); | |
b9164398 NQ |
6193 | #else |
6194 | WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE); | |
6195 | WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0); | |
6196 | WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/ | |
6197 | #endif | |
6198 | /*Send parser_cmd*/ | |
b9164398 NQ |
6199 | WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0)); |
6200 | for (i = 0; i < PARSER_CMD_NUMBER; i++) | |
6201 | WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]); | |
6202 | WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0); | |
6203 | WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1); | |
6204 | WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2); | |
6205 | ||
6206 | ||
a6c89e96 NQ |
6207 | WRITE_VREG(HEVC_PARSER_IF_CONTROL, |
6208 | /* (1 << 8) |*/ /*sao_sw_pred_enable*/ | |
6209 | (1 << 5) | /*parser_sao_if_en*/ | |
6210 | (1 << 2) | /*parser_mpred_if_en*/ | |
6211 | (1 << 0) /*parser_scaler_if_en*/ | |
6212 | ); | |
6213 | } | |
6214 | ||
6215 | if (mask & HW_MASK_BACK) { | |
6216 | /*Changed to Start MPRED in microcode*/ | |
6217 | /* | |
6218 | pr_info("[test.c] Start MPRED\n"); | |
6219 | WRITE_VREG(HEVC_MPRED_INT_STATUS, | |
6220 | (1<<31) | |
6221 | ); | |
6222 | */ | |
6223 | WRITE_VREG(HEVCD_IPP_TOP_CNTL, | |
6224 | (0 << 1) | /*enable ipp*/ | |
6225 | (1 << 0) /*software reset ipp and mpp*/ | |
6226 | ); | |
6227 | WRITE_VREG(HEVCD_IPP_TOP_CNTL, | |
6228 | (1 << 1) | /*enable ipp*/ | |
6229 | (0 << 0) /*software reset ipp and mpp*/ | |
6230 | ); | |
b7706e1e | 6231 | if (get_double_write_mode(pbi) & 0x10) { |
b34d6d3e ZZ |
6232 | /*Enable NV21 reference read mode for MC*/ |
6233 | WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); | |
b7706e1e | 6234 | } |
b34d6d3e | 6235 | |
a6c89e96 NQ |
6236 | /*Initialize mcrcc and decomp perf counters*/ |
6237 | if (mcrcc_cache_alg_flag && | |
6238 | pbi->init_flag == 0) { | |
6239 | mcrcc_perfcount_reset(); | |
6240 | decomp_perfcount_reset(); | |
6241 | } | |
c23e8aee | 6242 | } |
b9164398 NQ |
6243 | return; |
6244 | } | |
6245 | ||
6246 | ||
6247 | #ifdef CONFIG_HEVC_CLK_FORCED_ON | |
6248 | static void config_vp9_clk_forced_on(void) | |
6249 | { | |
6250 | unsigned int rdata32; | |
6251 | /*IQIT*/ | |
6252 | rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL); | |
6253 | WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2)); | |
6254 | ||
6255 | /* DBLK*/ | |
6256 | rdata32 = READ_VREG(HEVC_DBLK_CFG0); | |
6257 | WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2)); | |
6258 | ||
6259 | /* SAO*/ | |
6260 | rdata32 = READ_VREG(HEVC_SAO_CTRL1); | |
6261 | WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2)); | |
6262 | ||
6263 | /*MPRED*/ | |
6264 | rdata32 = READ_VREG(HEVC_MPRED_CTRL1); | |
6265 | WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24)); | |
6266 | ||
6267 | /* PARSER*/ | |
6268 | rdata32 = READ_VREG(HEVC_STREAM_CONTROL); | |
6269 | WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15)); | |
6270 | rdata32 = READ_VREG(HEVC_SHIFT_CONTROL); | |
6271 | WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15)); | |
6272 | rdata32 = READ_VREG(HEVC_CABAC_CONTROL); | |
6273 | WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13)); | |
6274 | rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL); | |
6275 | WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15)); | |
6276 | rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL); | |
6277 | WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15)); | |
6278 | rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL); | |
6279 | WRITE_VREG(HEVC_PARSER_IF_CONTROL, | |
6280 | rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1)); | |
6281 | ||
6282 | /*IPP*/ | |
6283 | rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG); | |
6284 | WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff); | |
6285 | ||
6286 | /* MCRCC*/ | |
6287 | rdata32 = READ_VREG(HEVCD_MCRCC_CTL1); | |
6288 | WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3)); | |
6289 | } | |
6290 | #endif | |
6291 | ||
6292 | ||
6293 | #ifdef MCRCC_ENABLE | |
c23e8aee HZ |
6294 | static void dump_hit_rate(struct VP9Decoder_s *pbi) |
6295 | { | |
6296 | if (debug & VP9_DEBUG_CACHE_HIT_RATE) { | |
6297 | mcrcc_get_hitrate(pbi->m_ins_flag); | |
6298 | decomp_get_hitrate(); | |
6299 | decomp_get_comprate(); | |
6300 | } | |
6301 | } | |
6302 | ||
b9164398 NQ |
6303 | static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi) |
6304 | { | |
6305 | unsigned int rdata32; | |
6306 | unsigned short is_inter; | |
6307 | /*pr_info("Entered config_mcrcc_axi_hw...\n");*/ | |
6308 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/ | |
6309 | is_inter = ((pbi->common.frame_type != KEY_FRAME) && | |
6310 | (!pbi->common.intra_only)) ? 1 : 0; | |
6311 | if (!is_inter) { /* I-PIC*/ | |
6312 | /*remove reset -- disables clock*/ | |
6313 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0); | |
6314 | return; | |
6315 | } | |
6316 | ||
6f5ee885 | 6317 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
df841122 | 6318 | mcrcc_get_hitrate(pbi->m_ins_flag); |
6319 | decomp_get_hitrate(); | |
6320 | decomp_get_comprate(); | |
6321 | } | |
b9164398 NQ |
6322 | |
6323 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, | |
6324 | (0 << 8) | (1 << 1) | 0); | |
6325 | rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6326 | rdata32 = rdata32 & 0xffff; | |
6327 | rdata32 = rdata32 | (rdata32 << 16); | |
6328 | WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); | |
6329 | /*Programme canvas1 */ | |
6330 | rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6331 | rdata32 = rdata32 & 0xffff; | |
6332 | rdata32 = rdata32 | (rdata32 << 16); | |
6333 | WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); | |
6334 | /*enable mcrcc progressive-mode*/ | |
6335 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); | |
b9164398 | 6336 | } |
c23e8aee HZ |
6337 | |
6338 | static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi) | |
6339 | { | |
6340 | u32 curr_picnum = -1; | |
6341 | u32 lastref_picnum = -1; | |
6342 | u32 goldenref_picnum = -1; | |
6343 | u32 altref_picnum = -1; | |
6344 | ||
6345 | u32 lastref_delta_picnum; | |
6346 | u32 goldenref_delta_picnum; | |
6347 | u32 altref_delta_picnum; | |
6348 | ||
6349 | u32 rdata32; | |
6350 | ||
6351 | u32 lastcanvas; | |
6352 | u32 goldencanvas; | |
6353 | u32 altrefcanvas; | |
6354 | ||
6355 | u16 is_inter; | |
6356 | u16 lastref_inref; | |
6357 | u16 goldenref_inref; | |
6358 | u16 altref_inref; | |
6359 | ||
6360 | u32 refcanvas_array[3], utmp; | |
6361 | int deltapicnum_array[3], tmp; | |
6362 | ||
6363 | struct VP9_Common_s *cm = &pbi->common; | |
6364 | struct PIC_BUFFER_CONFIG_s *cur_pic_config | |
6365 | = &cm->cur_frame->buf; | |
6366 | curr_picnum = cur_pic_config->decode_idx; | |
6367 | if (cm->frame_refs[0].buf) | |
6368 | lastref_picnum = cm->frame_refs[0].buf->decode_idx; | |
6369 | if (cm->frame_refs[1].buf) | |
6370 | goldenref_picnum = cm->frame_refs[1].buf->decode_idx; | |
6371 | if (cm->frame_refs[2].buf) | |
6372 | altref_picnum = cm->frame_refs[2].buf->decode_idx; | |
6373 | ||
6374 | lastref_delta_picnum = (lastref_picnum >= curr_picnum) ? | |
6375 | (lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum); | |
6376 | goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ? | |
6377 | (goldenref_picnum - curr_picnum) : | |
6378 | (curr_picnum - goldenref_picnum); | |
6379 | altref_delta_picnum = | |
6380 | (altref_picnum >= curr_picnum) ? | |
6381 | (altref_picnum - curr_picnum) : (curr_picnum - altref_picnum); | |
6382 | ||
6383 | lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0; | |
6384 | goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0; | |
6385 | altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0; | |
6386 | ||
6387 | if (debug & VP9_DEBUG_CACHE) | |
6388 | pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n", | |
6389 | __func__, lastref_inref, goldenref_inref, altref_inref); | |
6390 | ||
6391 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */ | |
6392 | ||
6393 | is_inter = ((pbi->common.frame_type != KEY_FRAME) | |
6394 | && (!pbi->common.intra_only)) ? 1 : 0; | |
6395 | ||
6396 | if (!is_inter) { /* I-PIC */ | |
6397 | /* remove reset -- disables clock */ | |
6398 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0); | |
6399 | return; | |
6400 | } | |
6401 | ||
6402 | if (!pbi->m_ins_flag) | |
6403 | dump_hit_rate(pbi); | |
6404 | ||
6405 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0); | |
6406 | lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6407 | goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6408 | altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6409 | ||
6410 | if (debug & VP9_DEBUG_CACHE) | |
6411 | pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n", | |
6412 | lastcanvas, goldencanvas, altrefcanvas); | |
6413 | ||
6414 | altref_inref = ((altref_inref == 1) && | |
6415 | (altrefcanvas != (goldenref_inref | |
6416 | ? goldencanvas : 0xffffffff)) && | |
6417 | (altrefcanvas != (lastref_inref ? | |
6418 | lastcanvas : 0xffffffff))) ? 1 : 0; | |
6419 | goldenref_inref = ((goldenref_inref == 1) && | |
6420 | (goldencanvas != (lastref_inref ? | |
6421 | lastcanvas : 0xffffffff))) ? 1 : 0; | |
6422 | if (debug & VP9_DEBUG_CACHE) | |
6423 | pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n", | |
6424 | lastref_inref, goldenref_inref, altref_inref); | |
6425 | ||
6426 | altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff; | |
6427 | goldenref_delta_picnum = goldenref_inref ? | |
6428 | goldenref_delta_picnum : 0x7fffffff; | |
6429 | lastref_delta_picnum = lastref_inref ? | |
6430 | lastref_delta_picnum : 0x7fffffff; | |
6431 | if (debug & VP9_DEBUG_CACHE) | |
6432 | pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n", | |
6433 | lastref_delta_picnum, goldenref_delta_picnum, | |
6434 | altref_delta_picnum); | |
6435 | /*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/ | |
6436 | ||
6437 | refcanvas_array[0] = lastcanvas; | |
6438 | refcanvas_array[1] = goldencanvas; | |
6439 | refcanvas_array[2] = altrefcanvas; | |
6440 | ||
6441 | deltapicnum_array[0] = lastref_delta_picnum; | |
6442 | deltapicnum_array[1] = goldenref_delta_picnum; | |
6443 | deltapicnum_array[2] = altref_delta_picnum; | |
6444 | ||
6445 | /* sort0 : 2-to-1 */ | |
6446 | if (deltapicnum_array[2] < deltapicnum_array[1]) { | |
6447 | utmp = refcanvas_array[2]; | |
6448 | refcanvas_array[2] = refcanvas_array[1]; | |
6449 | refcanvas_array[1] = utmp; | |
6450 | tmp = deltapicnum_array[2]; | |
6451 | deltapicnum_array[2] = deltapicnum_array[1]; | |
6452 | deltapicnum_array[1] = tmp; | |
6453 | } | |
6454 | /* sort1 : 1-to-0 */ | |
6455 | if (deltapicnum_array[1] < deltapicnum_array[0]) { | |
6456 | utmp = refcanvas_array[1]; | |
6457 | refcanvas_array[1] = refcanvas_array[0]; | |
6458 | refcanvas_array[0] = utmp; | |
6459 | tmp = deltapicnum_array[1]; | |
6460 | deltapicnum_array[1] = deltapicnum_array[0]; | |
6461 | deltapicnum_array[0] = tmp; | |
6462 | } | |
6463 | /* sort2 : 2-to-1 */ | |
6464 | if (deltapicnum_array[2] < deltapicnum_array[1]) { | |
6465 | utmp = refcanvas_array[2]; refcanvas_array[2] = | |
6466 | refcanvas_array[1]; refcanvas_array[1] = utmp; | |
6467 | tmp = deltapicnum_array[2]; deltapicnum_array[2] = | |
6468 | deltapicnum_array[1]; deltapicnum_array[1] = tmp; | |
6469 | } | |
6470 | if (mcrcc_cache_alg_flag == | |
6471 | THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/ | |
6472 | /* lowest delta_picnum */ | |
6473 | rdata32 = refcanvas_array[0]; | |
6474 | rdata32 = rdata32 & 0xffff; | |
6475 | rdata32 = rdata32 | (rdata32 << 16); | |
6476 | WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); | |
6477 | ||
6478 | /* 2nd-lowest delta_picnum */ | |
6479 | rdata32 = refcanvas_array[1]; | |
6480 | rdata32 = rdata32 & 0xffff; | |
6481 | rdata32 = rdata32 | (rdata32 << 16); | |
6482 | WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); | |
6483 | } else { | |
6484 | /* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/ | |
6485 | WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, | |
6486 | (0 << 8) | (1<<1) | 0); | |
6487 | rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6488 | rdata32 = rdata32 & 0xffff; | |
6489 | rdata32 = rdata32 | (rdata32 << 16); | |
6490 | WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); | |
6491 | ||
6492 | /* Programme canvas1 */ | |
6493 | rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); | |
6494 | rdata32 = rdata32 & 0xffff; | |
6495 | rdata32 = rdata32 | (rdata32 << 16); | |
6496 | WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); | |
6497 | } | |
6498 | ||
6499 | WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */ | |
6500 | return; | |
6501 | } | |
6502 | ||
b9164398 NQ |
6503 | #endif |
6504 | ||
6505 | ||
fe96802b NQ |
6506 | static void free_lf_buf(struct VP9Decoder_s *pbi) |
6507 | { | |
6508 | if (pbi->lfi) | |
6509 | vfree(pbi->lfi); | |
6510 | if (pbi->lf) | |
6511 | vfree(pbi->lf); | |
6512 | if (pbi->seg_4lf) | |
6513 | vfree(pbi->seg_4lf); | |
6514 | pbi->lfi = NULL; | |
6515 | pbi->lf = NULL; | |
6516 | pbi->seg_4lf = NULL; | |
6517 | } | |
6518 | ||
6519 | static int alloc_lf_buf(struct VP9Decoder_s *pbi) | |
6520 | { | |
6521 | pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n)); | |
6522 | pbi->lf = vmalloc(sizeof(struct loopfilter)); | |
6523 | pbi->seg_4lf = vmalloc(sizeof(struct segmentation)); | |
6524 | if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) { | |
6525 | free_lf_buf(pbi); | |
6526 | pr_err("[test.c] vp9_loop_filter init malloc error!!!\n"); | |
6527 | return -1; | |
6528 | } | |
6529 | return 0; | |
6530 | } | |
6531 | ||
b9164398 NQ |
6532 | static void vp9_local_uninit(struct VP9Decoder_s *pbi) |
6533 | { | |
6534 | pbi->rpm_ptr = NULL; | |
6535 | pbi->lmem_ptr = NULL; | |
6536 | if (pbi->rpm_addr) { | |
5f165f39 HZ |
6537 | dma_free_coherent(amports_get_dma_device(), |
6538 | RPM_BUF_SIZE, | |
6539 | pbi->rpm_addr, | |
6540 | pbi->rpm_phy_addr); | |
b9164398 NQ |
6541 | pbi->rpm_addr = NULL; |
6542 | } | |
6543 | if (pbi->lmem_addr) { | |
e0614bf7 ZZ |
6544 | if (pbi->lmem_phy_addr) |
6545 | dma_free_coherent(amports_get_dma_device(), | |
6546 | LMEM_BUF_SIZE, pbi->lmem_addr, | |
6547 | pbi->lmem_phy_addr); | |
6548 | pbi->lmem_addr = NULL; | |
b9164398 NQ |
6549 | } |
6550 | if (pbi->prob_buffer_addr) { | |
6551 | if (pbi->prob_buffer_phy_addr) | |
6552 | dma_free_coherent(amports_get_dma_device(), | |
6553 | PROB_BUF_SIZE, pbi->prob_buffer_addr, | |
6554 | pbi->prob_buffer_phy_addr); | |
6555 | ||
6556 | pbi->prob_buffer_addr = NULL; | |
6557 | } | |
6558 | if (pbi->count_buffer_addr) { | |
6559 | if (pbi->count_buffer_phy_addr) | |
6560 | dma_free_coherent(amports_get_dma_device(), | |
6561 | COUNT_BUF_SIZE, pbi->count_buffer_addr, | |
6562 | pbi->count_buffer_phy_addr); | |
6563 | ||
6564 | pbi->count_buffer_addr = NULL; | |
6565 | } | |
b7706e1e | 6566 | if (pbi->mmu_enable) { |
e0e39311 | 6567 | u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi); |
b7706e1e | 6568 | if (pbi->frame_mmu_map_addr) { |
6569 | if (pbi->frame_mmu_map_phy_addr) | |
6570 | dma_free_coherent(amports_get_dma_device(), | |
df841122 | 6571 | mmu_map_size, |
b7706e1e | 6572 | pbi->frame_mmu_map_addr, |
a6c89e96 | 6573 | pbi->frame_mmu_map_phy_addr); |
b7706e1e | 6574 | pbi->frame_mmu_map_addr = NULL; |
6575 | } | |
a6c89e96 | 6576 | } |
a6c89e96 NQ |
6577 | #ifdef SUPPORT_FB_DECODING |
6578 | if (pbi->stage_mmu_map_addr) { | |
6579 | if (pbi->stage_mmu_map_phy_addr) | |
6580 | dma_free_coherent(amports_get_dma_device(), | |
6581 | STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS, | |
6582 | pbi->stage_mmu_map_addr, | |
6583 | pbi->stage_mmu_map_phy_addr); | |
6584 | pbi->stage_mmu_map_addr = NULL; | |
b9164398 | 6585 | } |
b9164398 | 6586 | |
a6c89e96 NQ |
6587 | uninit_stage_buf(pbi); |
6588 | #endif | |
6589 | ||
b9164398 | 6590 | #ifdef VP9_LPF_LVL_UPDATE |
fe96802b | 6591 | free_lf_buf(pbi); |
b9164398 | 6592 | #endif |
fe96802b NQ |
6593 | if (pbi->gvs) |
6594 | vfree(pbi->gvs); | |
6595 | pbi->gvs = NULL; | |
b9164398 NQ |
6596 | } |
6597 | ||
6598 | static int vp9_local_init(struct VP9Decoder_s *pbi) | |
6599 | { | |
6600 | int ret = -1; | |
6601 | /*int losless_comp_header_size, losless_comp_body_size;*/ | |
6602 | ||
6603 | struct BuffInfo_s *cur_buf_info = NULL; | |
e0614bf7 | 6604 | |
b9164398 NQ |
6605 | memset(&pbi->param, 0, sizeof(union param_u)); |
6606 | memset(&pbi->common, 0, sizeof(struct VP9_Common_s)); | |
6607 | #ifdef MULTI_INSTANCE_SUPPORT | |
6608 | cur_buf_info = &pbi->work_space_buf_store; | |
df841122 | 6609 | |
6610 | if (vdec_is_support_4k()) { | |
6f5ee885 | 6611 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
3a5df697 | 6612 | memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */ |
df841122 | 6613 | sizeof(struct BuffInfo_s)); |
6614 | } else | |
6615 | memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */ | |
6616 | sizeof(struct BuffInfo_s)); | |
6617 | } else | |
c23e8aee | 6618 | memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */ |
b9164398 | 6619 | sizeof(struct BuffInfo_s)); |
df841122 | 6620 | |
b9164398 | 6621 | cur_buf_info->start_adr = pbi->buf_start; |
b7706e1e | 6622 | if (!pbi->mmu_enable) |
6623 | pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size; | |
6624 | ||
b9164398 NQ |
6625 | #else |
6626 | /*! MULTI_INSTANCE_SUPPORT*/ | |
df841122 | 6627 | if (vdec_is_support_4k()) { |
6f5ee885 | 6628 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) |
df841122 | 6629 | cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */ |
6630 | else | |
6631 | cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */ | |
6632 | } else | |
c23e8aee | 6633 | cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */ |
df841122 | 6634 | |
b9164398 NQ |
6635 | #endif |
6636 | ||
6637 | init_buff_spec(pbi, cur_buf_info); | |
fe96802b | 6638 | vp9_bufmgr_init(pbi, cur_buf_info, NULL); |
b9164398 | 6639 | |
c23e8aee HZ |
6640 | if (!vdec_is_support_4k() |
6641 | && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) { | |
6642 | buf_alloc_width = 1920; | |
6643 | buf_alloc_height = 1088; | |
a6c89e96 NQ |
6644 | if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) { |
6645 | pbi->max_pic_w = 1920; | |
6646 | pbi->max_pic_h = 1088; | |
6647 | } | |
6f5ee885 | 6648 | } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
df841122 | 6649 | buf_alloc_width = 8192; |
6650 | buf_alloc_height = 4608; | |
c23e8aee | 6651 | } |
a6c89e96 NQ |
6652 | pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w : |
6653 | (buf_alloc_width ? buf_alloc_width : | |
b9164398 NQ |
6654 | (pbi->vvp9_amstream_dec_info.width ? |
6655 | pbi->vvp9_amstream_dec_info.width : | |
0be1523d | 6656 | pbi->work_space_buf->max_width)); |
a6c89e96 NQ |
6657 | pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h : |
6658 | (buf_alloc_height ? buf_alloc_height : | |
b9164398 NQ |
6659 | (pbi->vvp9_amstream_dec_info.height ? |
6660 | pbi->vvp9_amstream_dec_info.height : | |
0be1523d | 6661 | pbi->work_space_buf->max_height)); |
3a5df697 | 6662 | |
e3b2152e | 6663 | /* video is not support unaligned with 64 in tl1 |
6664 | ** vdec canvas mode will be linear when dump yuv is set | |
6665 | */ | |
21d9caac | 6666 | if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) && |
3a5df697 | 6667 | (pbi->double_write_mode != 0) && |
6668 | (((pbi->max_pic_w % 64) != 0) || | |
e3b2152e | 6669 | (pbi->vvp9_amstream_dec_info.width % 64) != 0)) { |
6670 | if (hw_to_vdec(pbi)->canvas_mode != | |
6671 | CANVAS_BLKMODE_LINEAR) | |
0fb7e163 | 6672 | pbi->mem_map_mode = 2; |
e3b2152e | 6673 | else { |
0fb7e163 | 6674 | pbi->mem_map_mode = 0; |
e3b2152e | 6675 | pr_info("vdec blkmod linear, force mem_map_mode 0\n"); |
6676 | } | |
6677 | } | |
3a5df697 | 6678 | |
fe96802b NQ |
6679 | #ifndef MV_USE_FIXED_BUF |
6680 | if (init_mv_buf_list(pbi) < 0) { | |
6681 | pr_err("%s: init_mv_buf_list fail\n", __func__); | |
6682 | return -1; | |
6683 | } | |
6684 | #endif | |
dfe41deb RZ |
6685 | if (pbi->save_buffer_mode) |
6686 | pbi->used_buf_num = MAX_BUF_NUM_SAVE_BUF; | |
75803959 NQ |
6687 | else { |
6688 | if (pbi->is_used_v4l) | |
6689 | pbi->used_buf_num = 5 + pbi->dynamic_buf_num_margin; | |
6690 | else | |
6691 | pbi->used_buf_num = max_buf_num; | |
6692 | } | |
b7706e1e | 6693 | |
fe96802b NQ |
6694 | if (pbi->used_buf_num > MAX_BUF_NUM) |
6695 | pbi->used_buf_num = MAX_BUF_NUM; | |
6696 | if (pbi->used_buf_num > FRAME_BUFFERS) | |
6697 | pbi->used_buf_num = FRAME_BUFFERS; | |
b9164398 | 6698 | |
976f3376 | 6699 | pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param) |
b9164398 NQ |
6700 | & 0x40) >> 6; |
6701 | ||
b9164398 | 6702 | if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) { |
5f165f39 HZ |
6703 | pbi->rpm_addr = dma_alloc_coherent(amports_get_dma_device(), |
6704 | RPM_BUF_SIZE, | |
6705 | &pbi->rpm_phy_addr, GFP_KERNEL); | |
b9164398 NQ |
6706 | if (pbi->rpm_addr == NULL) { |
6707 | pr_err("%s: failed to alloc rpm buffer\n", __func__); | |
6708 | return -1; | |
6709 | } | |
6710 | ||
b9164398 NQ |
6711 | pbi->rpm_ptr = pbi->rpm_addr; |
6712 | } | |
6713 | ||
fe96802b NQ |
6714 | pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(), |
6715 | LMEM_BUF_SIZE, | |
6716 | &pbi->lmem_phy_addr, GFP_KERNEL); | |
6717 | if (pbi->lmem_addr == NULL) { | |
6718 | pr_err("%s: failed to alloc lmem buffer\n", __func__); | |
6719 | return -1; | |
6720 | } | |
e0614bf7 | 6721 | pbi->lmem_ptr = pbi->lmem_addr; |
fe96802b | 6722 | |
b9164398 NQ |
6723 | pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(), |
6724 | PROB_BUF_SIZE, | |
6725 | &pbi->prob_buffer_phy_addr, GFP_KERNEL); | |
6726 | if (pbi->prob_buffer_addr == NULL) { | |
6727 | pr_err("%s: failed to alloc prob_buffer\n", __func__); | |
6728 | return -1; | |
6729 | } | |
6730 | memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE); | |
b9164398 NQ |
6731 | pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(), |
6732 | COUNT_BUF_SIZE, | |
6733 | &pbi->count_buffer_phy_addr, GFP_KERNEL); | |
6734 | if (pbi->count_buffer_addr == NULL) { | |
6735 | pr_err("%s: failed to alloc count_buffer\n", __func__); | |
6736 | return -1; | |
6737 | } | |
6738 | memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE); | |
5f165f39 | 6739 | |
b7706e1e | 6740 | if (pbi->mmu_enable) { |
e0e39311 | 6741 | u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi); |
b7706e1e | 6742 | pbi->frame_mmu_map_addr = |
6743 | dma_alloc_coherent(amports_get_dma_device(), | |
df841122 | 6744 | mmu_map_size, |
a6c89e96 | 6745 | &pbi->frame_mmu_map_phy_addr, GFP_KERNEL); |
b7706e1e | 6746 | if (pbi->frame_mmu_map_addr == NULL) { |
6747 | pr_err("%s: failed to alloc count_buffer\n", __func__); | |
6748 | return -1; | |
6749 | } | |
6750 | memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE); | |
a6c89e96 | 6751 | } |
a6c89e96 NQ |
6752 | #ifdef SUPPORT_FB_DECODING |
6753 | if (pbi->m_ins_flag && stage_buf_num > 0) { | |
6754 | pbi->stage_mmu_map_addr = | |
6755 | dma_alloc_coherent(amports_get_dma_device(), | |
6756 | STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS, | |
6757 | &pbi->stage_mmu_map_phy_addr, GFP_KERNEL); | |
6758 | if (pbi->stage_mmu_map_addr == NULL) { | |
b34d6d3e ZZ |
6759 | pr_err("%s: failed to alloc count_buffer\n", __func__); |
6760 | return -1; | |
6761 | } | |
a6c89e96 NQ |
6762 | memset(pbi->stage_mmu_map_addr, |
6763 | 0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS); | |
b34d6d3e | 6764 | |
a6c89e96 NQ |
6765 | init_stage_buf(pbi); |
6766 | } | |
6767 | #endif | |
b9164398 NQ |
6768 | |
6769 | ret = 0; | |
6770 | return ret; | |
6771 | } | |
6772 | ||
6773 | /******************************************** | |
6774 | * Mailbox command | |
6775 | ********************************************/ | |
6776 | #define CMD_FINISHED 0 | |
6777 | #define CMD_ALLOC_VIEW 1 | |
6778 | #define CMD_FRAME_DISPLAY 3 | |
6779 | #define CMD_DEBUG 10 | |
6780 | ||
6781 | ||
6782 | #define DECODE_BUFFER_NUM_MAX 32 | |
6783 | #define DISPLAY_BUFFER_NUM 6 | |
6784 | ||
6785 | #define video_domain_addr(adr) (adr&0x7fffffff) | |
6786 | #define DECODER_WORK_SPACE_SIZE 0x800000 | |
6787 | ||
6788 | #define spec2canvas(x) \ | |
6789 | (((x)->uv_canvas_index << 16) | \ | |
6790 | ((x)->uv_canvas_index << 8) | \ | |
6791 | ((x)->y_canvas_index << 0)) | |
6792 | ||
6793 | ||
fe96802b NQ |
6794 | static void set_canvas(struct VP9Decoder_s *pbi, |
6795 | struct PIC_BUFFER_CONFIG_s *pic_config) | |
b9164398 | 6796 | { |
05afa03d | 6797 | struct vdec_s *vdec = hw_to_vdec(pbi); |
b9164398 NQ |
6798 | int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4; |
6799 | int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4; | |
0fb7e163 | 6800 | int blkmode = pbi->mem_map_mode; |
b9164398 | 6801 | /*CANVAS_BLKMODE_64X32*/ |
c23e8aee HZ |
6802 | if (pic_config->double_write_mode) { |
6803 | canvas_w = pic_config->y_crop_width / | |
6804 | get_double_write_ratio(pbi, | |
6805 | pic_config->double_write_mode); | |
6806 | canvas_h = pic_config->y_crop_height / | |
6807 | get_double_write_ratio(pbi, | |
6808 | pic_config->double_write_mode); | |
b9164398 | 6809 | |
0fb7e163 | 6810 | if (pbi->mem_map_mode == 0) |
b9164398 NQ |
6811 | canvas_w = ALIGN(canvas_w, 32); |
6812 | else | |
6813 | canvas_w = ALIGN(canvas_w, 64); | |
6814 | canvas_h = ALIGN(canvas_h, 32); | |
6815 | ||
05afa03d PY |
6816 | if (vdec->parallel_dec == 1) { |
6817 | if (pic_config->y_canvas_index == -1) | |
6818 | pic_config->y_canvas_index = | |
6819 | vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id); | |
6820 | if (pic_config->uv_canvas_index == -1) | |
6821 | pic_config->uv_canvas_index = | |
6822 | vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id); | |
6823 | } else { | |
6824 | pic_config->y_canvas_index = 128 + pic_config->index * 2; | |
6825 | pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1; | |
6826 | } | |
b9164398 NQ |
6827 | |
6828 | canvas_config_ex(pic_config->y_canvas_index, | |
6829 | pic_config->dw_y_adr, canvas_w, canvas_h, | |
75803959 | 6830 | CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7); |
b9164398 NQ |
6831 | canvas_config_ex(pic_config->uv_canvas_index, |
6832 | pic_config->dw_u_v_adr, canvas_w, canvas_h, | |
75803959 | 6833 | CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7); |
6276f4ff | 6834 | |
b9164398 NQ |
6835 | #ifdef MULTI_INSTANCE_SUPPORT |
6836 | pic_config->canvas_config[0].phy_addr = | |
6837 | pic_config->dw_y_adr; | |
6838 | pic_config->canvas_config[0].width = | |
6839 | canvas_w; | |
6840 | pic_config->canvas_config[0].height = | |
6841 | canvas_h; | |
6842 | pic_config->canvas_config[0].block_mode = | |
6843 | blkmode; | |
75803959 | 6844 | pic_config->canvas_config[0].endian = pbi->is_used_v4l ? 0 : 7; |
b9164398 NQ |
6845 | |
6846 | pic_config->canvas_config[1].phy_addr = | |
6847 | pic_config->dw_u_v_adr; | |
6848 | pic_config->canvas_config[1].width = | |
6849 | canvas_w; | |
6850 | pic_config->canvas_config[1].height = | |
6851 | canvas_h; | |
6852 | pic_config->canvas_config[1].block_mode = | |
6853 | blkmode; | |
75803959 | 6854 | pic_config->canvas_config[1].endian = pbi->is_used_v4l ? 0 : 7; |
b9164398 | 6855 | #endif |
b9164398 | 6856 | } |
b9164398 NQ |
6857 | } |
6858 | ||
6859 | ||
6860 | static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf) | |
6861 | { | |
6862 | unsigned int ar; | |
b9164398 NQ |
6863 | vf->duration = pbi->frame_dur; |
6864 | vf->duration_pulldown = 0; | |
6865 | vf->flag = 0; | |
d481db31 NQ |
6866 | vf->prop.master_display_colour = pbi->vf_dp; |
6867 | vf->signal_type = pbi->video_signal_type; | |
9edb8e76 HZ |
6868 | if (vf->compWidth && vf->compHeight) |
6869 | pbi->frame_ar = vf->compHeight * 0x100 / vf->compWidth; | |
b9164398 NQ |
6870 | ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX); |
6871 | vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); | |
6872 | ||
75803959 NQ |
6873 | if (pbi->is_used_v4l && pbi->vf_dp.present_flag) { |
6874 | struct aml_vdec_hdr_infos hdr; | |
6875 | struct aml_vcodec_ctx *ctx = | |
6876 | (struct aml_vcodec_ctx *)(pbi->v4l2_ctx); | |
6877 | ||
6878 | memset(&hdr, 0, sizeof(hdr)); | |
6879 | hdr.signal_type = vf->signal_type; | |
6880 | hdr.color_parms = pbi->vf_dp; | |
6881 | vdec_v4l_set_hdr_infos(ctx, &hdr); | |
6882 | } | |
ae727791 | 6883 | |
8654f7f2 | 6884 | if ((pbi->chunk != NULL) && (pbi->chunk->hdr10p_data_buf != NULL) |
6885 | && (pbi->chunk->hdr10p_data_size != 0)) { | |
6886 | char *new_buf; | |
6887 | int i = 0; | |
6888 | new_buf = vzalloc(pbi->chunk->hdr10p_data_size); | |
6889 | ||
6890 | if (new_buf) { | |
6891 | memcpy(new_buf, pbi->chunk->hdr10p_data_buf, pbi->chunk->hdr10p_data_size); | |
6892 | if (debug & VP9_DEBUG_BUFMGR_MORE) { | |
6893 | vp9_print(pbi, VP9_DEBUG_BUFMGR_MORE, | |
6894 | "hdr10p data: (size %d)\n", | |
6895 | pbi->chunk->hdr10p_data_size); | |
6896 | for (i = 0; i < pbi->chunk->hdr10p_data_size; i++) { | |
6897 | vp9_print(pbi, VP9_DEBUG_BUFMGR_MORE, | |
6898 | "%02x ", pbi->chunk->hdr10p_data_buf[i]); | |
6899 | if (((i + 1) & 0xf) == 0) | |
6900 | vp9_print(pbi, VP9_DEBUG_BUFMGR_MORE, "\n"); | |
6901 | } | |
6902 | vp9_print(pbi, VP9_DEBUG_BUFMGR_MORE, "\n"); | |
6903 | } | |
6904 | ||
6905 | vf->hdr10p_data_size = pbi->chunk->hdr10p_data_size; | |
6906 | vf->hdr10p_data_buf = new_buf; | |
6907 | } else { | |
6908 | vp9_print(pbi, 0, "%s:hdr10p data vzalloc size(%d) fail\n", | |
6909 | __func__, pbi->chunk->hdr10p_data_size); | |
6910 | vf->hdr10p_data_size = pbi->chunk->hdr10p_data_size; | |
6911 | vf->hdr10p_data_buf = new_buf; | |
6912 | } | |
6913 | ||
6914 | vfree(pbi->chunk->hdr10p_data_buf); | |
6915 | pbi->chunk->hdr10p_data_buf = NULL; | |
6916 | pbi->chunk->hdr10p_data_size = 0; | |
6917 | } | |
6918 | ||
ae727791 | 6919 | vf->sidebind_type = pbi->sidebind_type; |
6920 | vf->sidebind_channel_id = pbi->sidebind_channel_id; | |
b9164398 NQ |
6921 | } |
6922 | ||
6923 | static int vvp9_vf_states(struct vframe_states *states, void *op_arg) | |
6924 | { | |
6925 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; | |
6926 | ||
6927 | states->vf_pool_size = VF_POOL_SIZE; | |
6928 | states->buf_free_num = kfifo_len(&pbi->newframe_q); | |
6929 | states->buf_avail_num = kfifo_len(&pbi->display_q); | |
6930 | ||
6931 | if (step == 2) | |
6932 | states->buf_avail_num = 0; | |
6933 | return 0; | |
6934 | } | |
6935 | ||
6936 | static struct vframe_s *vvp9_vf_peek(void *op_arg) | |
6937 | { | |
c64ff275 | 6938 | struct vframe_s *vf[2] = {0, 0}; |
b9164398 | 6939 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; |
e0614bf7 | 6940 | |
b9164398 NQ |
6941 | if (step == 2) |
6942 | return NULL; | |
6943 | ||
c64ff275 | 6944 | if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) { |
6945 | if (vf[1]) { | |
6946 | vf[0]->next_vf_pts_valid = true; | |
6947 | vf[0]->next_vf_pts = vf[1]->pts; | |
6948 | } else | |
6949 | vf[0]->next_vf_pts_valid = false; | |
6950 | return vf[0]; | |
6951 | } | |
b9164398 NQ |
6952 | |
6953 | return NULL; | |
6954 | } | |
6955 | ||
6956 | static struct vframe_s *vvp9_vf_get(void *op_arg) | |
6957 | { | |
6958 | struct vframe_s *vf; | |
6959 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; | |
e0614bf7 | 6960 | |
b9164398 NQ |
6961 | if (step == 2) |
6962 | return NULL; | |
6963 | else if (step == 1) | |
6964 | step = 2; | |
6965 | ||
6966 | if (kfifo_get(&pbi->display_q, &vf)) { | |
c64ff275 | 6967 | struct vframe_s *next_vf; |
b9164398 | 6968 | uint8_t index = vf->index & 0xff; |
0fb7e163 NQ |
6969 | if (index < pbi->used_buf_num || |
6970 | (vf->type & VIDTYPE_V4L_EOS)) { | |
e341185c | 6971 | vf->index_disp = pbi->vf_get_count; |
fe96802b NQ |
6972 | pbi->vf_get_count++; |
6973 | if (debug & VP9_DEBUG_BUFMGR) | |
6974 | pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n", | |
6975 | __func__, vf->type, | |
6976 | vf->width, vf->height, | |
6977 | vf->pts, | |
6978 | vf->pts_us64); | |
c64ff275 | 6979 | |
6980 | if (kfifo_peek(&pbi->display_q, &next_vf)) { | |
6981 | vf->next_vf_pts_valid = true; | |
6982 | vf->next_vf_pts = next_vf->pts; | |
6983 | } else | |
6984 | vf->next_vf_pts_valid = false; | |
6985 | ||
b9164398 | 6986 | return vf; |
fe96802b | 6987 | } |
b9164398 NQ |
6988 | } |
6989 | return NULL; | |
6990 | } | |
6991 | ||
6992 | static void vvp9_vf_put(struct vframe_s *vf, void *op_arg) | |
6993 | { | |
6994 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; | |
6995 | uint8_t index = vf->index & 0xff; | |
6996 | ||
8e9fb312 NQ |
6997 | if (vf == (&pbi->vframe_dummy)) |
6998 | return; | |
6999 | ||
677ab50d NQ |
7000 | if (pbi->enable_fence && vf->fence) { |
7001 | vdec_fence_put(vf->fence); | |
7002 | vf->fence = NULL; | |
7003 | } | |
7004 | ||
8654f7f2 | 7005 | if (vf->hdr10p_data_buf) { |
7006 | vfree(vf->hdr10p_data_buf); | |
7007 | vf->hdr10p_data_buf = NULL; | |
7008 | vf->hdr10p_data_size = 0; | |
7009 | } | |
7010 | ||
b9164398 | 7011 | kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf); |
fe96802b | 7012 | pbi->vf_put_count++; |
a35da9f0 | 7013 | if (index < pbi->used_buf_num) { |
b9164398 NQ |
7014 | struct VP9_Common_s *cm = &pbi->common; |
7015 | struct BufferPool_s *pool = cm->buffer_pool; | |
fe96802b NQ |
7016 | unsigned long flags; |
7017 | ||
7018 | lock_buffer_pool(pool, flags); | |
b9164398 NQ |
7019 | if (pool->frame_bufs[index].buf.vf_ref > 0) |
7020 | pool->frame_bufs[index].buf.vf_ref--; | |
7021 | ||
75803959 NQ |
7022 | if (pbi->is_used_v4l) |
7023 | pool->frame_bufs[index].buf.vframe_bound = true; | |
7024 | ||
b9164398 | 7025 | if (pbi->wait_buf) |
a6c89e96 | 7026 | WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, |
b9164398 NQ |
7027 | 0x1); |
7028 | pbi->last_put_idx = index; | |
7029 | pbi->new_frame_displayed++; | |
fe96802b | 7030 | unlock_buffer_pool(pool, flags); |
a6c89e96 NQ |
7031 | #ifdef SUPPORT_FB_DECODING |
7032 | if (pbi->used_stage_buf_num > 0 && | |
7033 | pbi->back_not_run_ready) | |
7034 | trigger_schedule(pbi); | |
7035 | #endif | |
b9164398 NQ |
7036 | } |
7037 | ||
7038 | } | |
7039 | ||
7040 | static int vvp9_event_cb(int type, void *data, void *private_data) | |
7041 | { | |
7042 | if (type & VFRAME_EVENT_RECEIVER_RESET) { | |
7043 | #if 0 | |
7044 | unsigned long flags; | |
e0614bf7 | 7045 | |
b9164398 NQ |
7046 | amhevc_stop(); |
7047 | #ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER | |
7048 | vf_light_unreg_provider(&vvp9_vf_prov); | |
7049 | #endif | |
7050 | spin_lock_irqsave(&pbi->lock, flags); | |
7051 | vvp9_local_init(); | |
7052 | vvp9_prot_init(); | |
7053 | spin_unlock_irqrestore(&pbi->lock, flags); | |
7054 | #ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER | |
7055 | vf_reg_provider(&vvp9_vf_prov); | |
7056 | #endif | |
7057 | amhevc_start(); | |
7058 | #endif | |
7059 | } | |
7060 | ||
7061 | return 0; | |
7062 | } | |
7063 | ||
7064 | void inc_vf_ref(struct VP9Decoder_s *pbi, int index) | |
7065 | { | |
7066 | struct VP9_Common_s *cm = &pbi->common; | |
e0614bf7 | 7067 | |
b9164398 NQ |
7068 | cm->buffer_pool->frame_bufs[index].buf.vf_ref++; |
7069 | ||
fe96802b | 7070 | if (debug & VP9_DEBUG_BUFMGR_MORE) |
b9164398 NQ |
7071 | pr_info("%s index = %d new vf_ref = %d\r\n", |
7072 | __func__, index, | |
7073 | cm->buffer_pool->frame_bufs[index].buf.vf_ref); | |
7074 | } | |
7075 | ||
c20e6c85 | 7076 | static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid) |
7077 | { | |
7078 | u32 old_duration, pts_duration = 0; | |
7079 | u32 pts = vf->pts; | |
7080 | ||
7081 | if (pbi->get_frame_dur == true) | |
7082 | return true; | |
7083 | ||
7084 | pbi->frame_cnt_window++; | |
7085 | if (!(pbi->vp9_first_pts_ready == 1)) { | |
7086 | if (valid) { | |
7087 | pbi->pts1 = pts; | |
7088 | pbi->frame_cnt_window = 0; | |
7089 | pbi->duration_from_pts_done = 0; | |
7090 | pbi->vp9_first_pts_ready = 1; | |
7091 | } else { | |
7092 | return false; | |
7093 | } | |
7094 | } else { | |
7095 | if (pts < pbi->pts1) { | |
7096 | if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) { | |
7097 | pbi->pts1 = pts; | |
7098 | pbi->frame_cnt_window = 0; | |
7099 | } | |
7100 | } | |
7101 | ||
7102 | if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) && | |
7103 | (pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) { | |
7104 | old_duration = pbi->frame_dur; | |
7105 | pbi->pts2 = pts; | |
7106 | pts_duration = (((pbi->pts2 - pbi->pts1) * 16) / | |
7107 | (pbi->frame_cnt_window * 15)); | |
7108 | ||
7109 | if (close_to(pts_duration, old_duration, 2000)) { | |
7110 | pbi->frame_dur = pts_duration; | |
7111 | if ((debug & VP9_DEBUG_OUT_PTS) != 0) | |
7112 | pr_info("use calc duration %d\n", pts_duration); | |
7113 | } | |
7114 | ||
7115 | if (pbi->duration_from_pts_done == 0) { | |
7116 | if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) { | |
7117 | pbi->duration_from_pts_done = 1; | |
7118 | } else { | |
7119 | if (!close_to(pts_duration, | |
7120 | old_duration, 1000) && | |
7121 | !close_to(pts_duration, | |
7122 | pbi->frame_dur, 1000) && | |
7123 | close_to(pts_duration, | |
7124 | pbi->last_duration, 200)) { | |
7125 | /* frame_dur must | |
7126 | * wrong,recover it. | |
7127 | */ | |
7128 | pbi->frame_dur = pts_duration; | |
7129 | } | |
7130 | pbi->pts1 = pbi->pts2; | |
7131 | pbi->frame_cnt_window = 0; | |
7132 | pbi->duration_from_pts_done = 0; | |
7133 | } | |
7134 | } | |
7135 | pbi->last_duration = pts_duration; | |
7136 | } | |
7137 | } | |
7138 | return true; | |
7139 | } | |
7140 | ||
b7706e1e | 7141 | static void update_vf_memhandle(struct VP9Decoder_s *pbi, |
7142 | struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic) | |
7143 | { | |
7144 | if (pic->index < 0) { | |
7145 | vf->mem_handle = NULL; | |
7146 | vf->mem_head_handle = NULL; | |
f7a80758 | 7147 | vf->mem_dw_handle = NULL; |
b7706e1e | 7148 | } else if (vf->type & VIDTYPE_SCATTER) { |
7149 | vf->mem_handle = | |
7150 | decoder_mmu_box_get_mem_handle( | |
7151 | pbi->mmu_box, pic->index); | |
7152 | vf->mem_head_handle = | |
7153 | decoder_bmmu_box_get_mem_handle( | |
7154 | pbi->bmmu_box, | |
d20f4d9e | 7155 | HEADER_BUFFER_IDX(pic->BUF_index)); |
f7a80758 GZ |
7156 | if (pbi->double_write_mode == 3) |
7157 | vf->mem_dw_handle = | |
7158 | decoder_bmmu_box_get_mem_handle( | |
7159 | pbi->bmmu_box, | |
7160 | VF_BUFFER_IDX(pic->BUF_index)); | |
7161 | else | |
7162 | vf->mem_dw_handle = NULL; | |
b7706e1e | 7163 | } else { |
7164 | vf->mem_handle = | |
7165 | decoder_bmmu_box_get_mem_handle( | |
7166 | pbi->bmmu_box, VF_BUFFER_IDX(pic->BUF_index)); | |
7167 | vf->mem_head_handle = NULL; | |
f7a80758 | 7168 | vf->mem_dw_handle = NULL; |
b7706e1e | 7169 | /*vf->mem_head_handle = |
7170 | *decoder_bmmu_box_get_mem_handle( | |
7171 | *hevc->bmmu_box, VF_BUFFER_IDX(BUF_index)); | |
7172 | */ | |
7173 | } | |
7174 | } | |
ac678990 | 7175 | |
cc41710a | 7176 | static inline void pbi_update_gvs(struct VP9Decoder_s *pbi) |
7177 | { | |
7178 | if (pbi->gvs->frame_height != frame_height) { | |
7179 | pbi->gvs->frame_width = frame_width; | |
7180 | pbi->gvs->frame_height = frame_height; | |
7181 | } | |
7182 | if (pbi->gvs->frame_dur != pbi->frame_dur) { | |
7183 | pbi->gvs->frame_dur = pbi->frame_dur; | |
7184 | if (pbi->frame_dur != 0) | |
4cd99df0 | 7185 | pbi->gvs->frame_rate = ((96000 * 10 / pbi->frame_dur) % 10) < 5 ? |
7186 | 96000 / pbi->frame_dur : (96000 / pbi->frame_dur +1); | |
cc41710a | 7187 | else |
7188 | pbi->gvs->frame_rate = -1; | |
7189 | } | |
7190 | pbi->gvs->status = pbi->stat | pbi->fatal_error; | |
7191 | } | |
7192 | ||
b9164398 NQ |
7193 | static int prepare_display_buf(struct VP9Decoder_s *pbi, |
7194 | struct PIC_BUFFER_CONFIG_s *pic_config) | |
7195 | { | |
7196 | struct vframe_s *vf = NULL; | |
cc41710a | 7197 | struct vdec_s *pvdec = hw_to_vdec(pbi); |
b9164398 NQ |
7198 | int stream_offset = pic_config->stream_offset; |
7199 | unsigned short slice_type = pic_config->slice_type; | |
5652b4fc NQ |
7200 | struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx; |
7201 | ulong nv_order = VIDTYPE_VIU_NV21; | |
5f2400c0 | 7202 | u32 pts_valid = 0, pts_us64_valid = 0; |
7203 | u32 pts_save; | |
7204 | u64 pts_us64_save; | |
cc41710a | 7205 | u32 frame_size = 0; |
65ad8202 | 7206 | int i = 0; |
c20e6c85 | 7207 | |
5652b4fc | 7208 | |
b9164398 NQ |
7209 | if (debug & VP9_DEBUG_BUFMGR) |
7210 | pr_info("%s index = %d\r\n", __func__, pic_config->index); | |
7211 | if (kfifo_get(&pbi->newframe_q, &vf) == 0) { | |
7212 | pr_info("fatal error, no available buffer slot."); | |
7213 | return -1; | |
7214 | } | |
7215 | ||
5652b4fc NQ |
7216 | /* swap uv */ |
7217 | if (pbi->is_used_v4l) { | |
7218 | if ((v4l2_ctx->cap_pix_fmt == V4L2_PIX_FMT_NV12) || | |
7219 | (v4l2_ctx->cap_pix_fmt == V4L2_PIX_FMT_NV12M)) | |
7220 | nv_order = VIDTYPE_VIU_NV12; | |
7221 | } | |
7222 | ||
c23e8aee | 7223 | if (pic_config->double_write_mode) |
fe96802b | 7224 | set_canvas(pbi, pic_config); |
c23e8aee | 7225 | |
fe96802b | 7226 | display_frame_count[pbi->index]++; |
b9164398 | 7227 | if (vf) { |
65ad8202 GZ |
7228 | if (!force_pts_unstable) { |
7229 | if ((pic_config->pts == 0) || (pic_config->pts <= pbi->last_pts)) { | |
7230 | for (i = (FRAME_BUFFERS - 1); i > 0; i--) { | |
7231 | if ((pbi->last_pts == pbi->frame_mode_pts_save[i]) || | |
7232 | (pbi->last_pts_us64 == pbi->frame_mode_pts64_save[i])) { | |
7233 | pic_config->pts = pbi->frame_mode_pts_save[i - 1]; | |
7234 | pic_config->pts64 = pbi->frame_mode_pts64_save[i - 1]; | |
7235 | break; | |
7236 | } | |
7237 | } | |
7238 | if ((i == 0) || (pic_config->pts <= pbi->last_pts)) { | |
7239 | vp9_print(pbi, VP9_DEBUG_OUT_PTS, | |
7240 | "no found pts %d, set 0. %d, %d\n", | |
7241 | i, pic_config->pts, pbi->last_pts); | |
7242 | pic_config->pts = 0; | |
7243 | pic_config->pts64 = 0; | |
7244 | } | |
7245 | } | |
7246 | } | |
7247 | ||
2cd6815e NQ |
7248 | if (pbi->is_used_v4l) { |
7249 | vf->v4l_mem_handle | |
7250 | = pbi->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr; | |
0fb7e163 | 7251 | if (pbi->mmu_enable) { |
75803959 NQ |
7252 | vf->mm_box.bmmu_box = pbi->bmmu_box; |
7253 | vf->mm_box.bmmu_idx = HEADER_BUFFER_IDX(pic_config->BUF_index); | |
7254 | vf->mm_box.mmu_box = pbi->mmu_box; | |
7255 | vf->mm_box.mmu_idx = pic_config->index; | |
0fb7e163 | 7256 | } |
2cd6815e NQ |
7257 | } |
7258 | ||
677ab50d NQ |
7259 | if (pbi->enable_fence) { |
7260 | /* fill fence information. */ | |
7261 | if (pbi->fence_usage == FENCE_USE_FOR_DRIVER) | |
7262 | vf->fence = pic_config->fence; | |
7263 | } | |
7264 | ||
fe96802b | 7265 | #ifdef MULTI_INSTANCE_SUPPORT |
cc41710a | 7266 | if (vdec_frame_based(pvdec)) { |
fe96802b NQ |
7267 | vf->pts = pic_config->pts; |
7268 | vf->pts_us64 = pic_config->pts64; | |
0fb7e163 | 7269 | vf->timestamp = pic_config->timestamp; |
c20e6c85 | 7270 | if (vf->pts != 0 || vf->pts_us64 != 0) { |
7271 | pts_valid = 1; | |
7272 | pts_us64_valid = 1; | |
7273 | } else { | |
7274 | pts_valid = 0; | |
7275 | pts_us64_valid = 0; | |
7276 | } | |
fe96802b NQ |
7277 | } else |
7278 | #endif | |
b9164398 | 7279 | /* if (pts_lookup_offset(PTS_TYPE_VIDEO, |
e0614bf7 ZZ |
7280 | * stream_offset, &vf->pts, 0) != 0) { |
7281 | */ | |
36114cbd | 7282 | if ((pvdec->vbuf.no_parser == 0) || (pvdec->vbuf.use_ptsserv)) { |
7283 | if (pts_lookup_offset_us64 | |
7284 | (PTS_TYPE_VIDEO, stream_offset, &vf->pts, | |
7285 | &frame_size, 0, | |
7286 | &vf->pts_us64) != 0) { | |
b9164398 | 7287 | #ifdef DEBUG_PTS |
36114cbd | 7288 | pbi->pts_missed++; |
b9164398 | 7289 | #endif |
36114cbd | 7290 | vf->pts = 0; |
7291 | vf->pts_us64 = 0; | |
7292 | pts_valid = 0; | |
7293 | pts_us64_valid = 0; | |
7294 | } else { | |
b9164398 | 7295 | #ifdef DEBUG_PTS |
36114cbd | 7296 | pbi->pts_hit++; |
b9164398 | 7297 | #endif |
36114cbd | 7298 | pts_valid = 1; |
7299 | pts_us64_valid = 1; | |
7300 | } | |
c20e6c85 | 7301 | } |
7302 | ||
ac678990 NQ |
7303 | fill_frame_info(pbi, pic_config, frame_size, vf->pts); |
7304 | ||
5f2400c0 | 7305 | pts_save = vf->pts; |
7306 | pts_us64_save = vf->pts_us64; | |
c20e6c85 | 7307 | if (pbi->pts_unstable) { |
7308 | frame_duration_adapt(pbi, vf, pts_valid); | |
7309 | if (pbi->duration_from_pts_done) { | |
7310 | pbi->pts_mode = PTS_NONE_REF_USE_DURATION; | |
7311 | } else { | |
7312 | if (pts_valid || pts_us64_valid) | |
7313 | pbi->pts_mode = PTS_NORMAL; | |
7314 | } | |
7315 | } | |
b9164398 NQ |
7316 | |
7317 | if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0) | |
7318 | && pbi->get_frame_dur) { | |
7319 | int pts_diff = (int)vf->pts - pbi->last_lookup_pts; | |
7320 | ||
7321 | if (pts_diff < 0) { | |
7322 | pbi->pts_mode_switching_count++; | |
7323 | pbi->pts_mode_recovery_count = 0; | |
7324 | ||
7325 | if (pbi->pts_mode_switching_count >= | |
7326 | PTS_MODE_SWITCHING_THRESHOLD) { | |
7327 | pbi->pts_mode = | |
7328 | PTS_NONE_REF_USE_DURATION; | |
7329 | pr_info | |
7330 | ("HEVC: switch to n_d mode.\n"); | |
7331 | } | |
7332 | ||
7333 | } else { | |
7334 | int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD; | |
e0614bf7 | 7335 | |
b9164398 NQ |
7336 | pbi->pts_mode_recovery_count++; |
7337 | if (pbi->pts_mode_recovery_count > p) { | |
7338 | pbi->pts_mode_switching_count = 0; | |
7339 | pbi->pts_mode_recovery_count = 0; | |
7340 | } | |
7341 | } | |
7342 | } | |
7343 | ||
7344 | if (vf->pts != 0) | |
7345 | pbi->last_lookup_pts = vf->pts; | |
7346 | ||
7347 | if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION) | |
7348 | && (slice_type != KEY_FRAME)) | |
7349 | vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur); | |
7350 | pbi->last_pts = vf->pts; | |
7351 | ||
7352 | if (vf->pts_us64 != 0) | |
7353 | pbi->last_lookup_pts_us64 = vf->pts_us64; | |
7354 | ||
7355 | if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION) | |
7356 | && (slice_type != KEY_FRAME)) { | |
7357 | vf->pts_us64 = | |
7358 | pbi->last_pts_us64 + | |
7359 | (DUR2PTS(pbi->frame_dur) * 100 / 9); | |
7360 | } | |
7361 | pbi->last_pts_us64 = vf->pts_us64; | |
7362 | if ((debug & VP9_DEBUG_OUT_PTS) != 0) { | |
7363 | pr_info | |
546484c5 | 7364 | ("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n", |
7365 | pbi->pts_mode, pbi->frame_dur, vf->pts, | |
7366 | vf->pts_us64, pts_save, pts_us64_save); | |
b9164398 NQ |
7367 | } |
7368 | ||
5f2400c0 | 7369 | if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) { |
7370 | vf->disp_pts = vf->pts; | |
7371 | vf->disp_pts_us64 = vf->pts_us64; | |
7372 | vf->pts = pts_save; | |
7373 | vf->pts_us64 = pts_us64_save; | |
7374 | } else { | |
7375 | vf->disp_pts = 0; | |
7376 | vf->disp_pts_us64 = 0; | |
7377 | } | |
7378 | ||
b9164398 | 7379 | vf->index = 0xff00 | pic_config->index; |
fe96802b | 7380 | |
c23e8aee | 7381 | if (pic_config->double_write_mode & 0x10) { |
b9164398 NQ |
7382 | /* double write only */ |
7383 | vf->compBodyAddr = 0; | |
7384 | vf->compHeadAddr = 0; | |
7385 | } else { | |
b7706e1e | 7386 | if (pbi->mmu_enable) { |
7387 | vf->compBodyAddr = 0; | |
7388 | vf->compHeadAddr = pic_config->header_adr; | |
7389 | } else { | |
7390 | /*vf->compBodyAddr = pic_config->mc_y_adr; | |
7391 | *vf->compHeadAddr = pic_config->mc_y_adr + | |
7392 | *pic_config->comp_body_size; */ | |
7393 | /*head adr*/ | |
7394 | } | |
7395 | vf->canvas0Addr = vf->canvas1Addr = 0; | |
b9164398 | 7396 | } |
c23e8aee | 7397 | if (pic_config->double_write_mode) { |
b9164398 NQ |
7398 | vf->type = VIDTYPE_PROGRESSIVE | |
7399 | VIDTYPE_VIU_FIELD; | |
5652b4fc | 7400 | vf->type |= nv_order; |
e0e39311 | 7401 | if ((pic_config->double_write_mode == 3) && |
7402 | (!IS_8K_SIZE(pic_config->y_crop_width, | |
7403 | pic_config->y_crop_height))) { | |
fe96802b | 7404 | vf->type |= VIDTYPE_COMPRESS; |
b7706e1e | 7405 | if (pbi->mmu_enable) |
7406 | vf->type |= VIDTYPE_SCATTER; | |
fe96802b | 7407 | } |
b9164398 NQ |
7408 | #ifdef MULTI_INSTANCE_SUPPORT |
7409 | if (pbi->m_ins_flag) { | |
e0614bf7 ZZ |
7410 | vf->canvas0Addr = vf->canvas1Addr = -1; |
7411 | vf->plane_num = 2; | |
7412 | vf->canvas0_config[0] = | |
7413 | pic_config->canvas_config[0]; | |
7414 | vf->canvas0_config[1] = | |
7415 | pic_config->canvas_config[1]; | |
7416 | vf->canvas1_config[0] = | |
7417 | pic_config->canvas_config[0]; | |
7418 | vf->canvas1_config[1] = | |
7419 | pic_config->canvas_config[1]; | |
b9164398 NQ |
7420 | |
7421 | } else | |
7422 | #endif | |
7423 | vf->canvas0Addr = vf->canvas1Addr = | |
7424 | spec2canvas(pic_config); | |
7425 | } else { | |
7426 | vf->canvas0Addr = vf->canvas1Addr = 0; | |
7427 | vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD; | |
b7706e1e | 7428 | if (pbi->mmu_enable) |
7429 | vf->type |= VIDTYPE_SCATTER; | |
fe96802b NQ |
7430 | } |
7431 | ||
7432 | switch (pic_config->bit_depth) { | |
7433 | case VPX_BITS_8: | |
7434 | vf->bitdepth = BITDEPTH_Y8 | | |
7435 | BITDEPTH_U8 | BITDEPTH_V8; | |
7436 | break; | |
7437 | case VPX_BITS_10: | |
7438 | case VPX_BITS_12: | |
7439 | vf->bitdepth = BITDEPTH_Y10 | | |
7440 | BITDEPTH_U10 | BITDEPTH_V10; | |
7441 | break; | |
7442 | default: | |
7443 | vf->bitdepth = BITDEPTH_Y10 | | |
7444 | BITDEPTH_U10 | BITDEPTH_V10; | |
7445 | break; | |
7446 | } | |
7447 | if ((vf->type & VIDTYPE_COMPRESS) == 0) | |
7448 | vf->bitdepth = | |
7449 | BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8; | |
7450 | if (pic_config->bit_depth == VPX_BITS_8) | |
7451 | vf->bitdepth |= BITDEPTH_SAVING_MODE; | |
7452 | ||
b9164398 | 7453 | /* if((vf->width!=pic_config->width)| |
e0614bf7 ZZ |
7454 | * (vf->height!=pic_config->height)) |
7455 | */ | |
b9164398 NQ |
7456 | /* pr_info("aaa: %d/%d, %d/%d\n", |
7457 | vf->width,vf->height, pic_config->width, | |
7458 | pic_config->height); */ | |
c23e8aee HZ |
7459 | vf->width = pic_config->y_crop_width / |
7460 | get_double_write_ratio(pbi, | |
7461 | pic_config->double_write_mode); | |
7462 | vf->height = pic_config->y_crop_height / | |
7463 | get_double_write_ratio(pbi, | |
7464 | pic_config->double_write_mode); | |
b9164398 NQ |
7465 | if (force_w_h != 0) { |
7466 | vf->width = (force_w_h >> 16) & 0xffff; | |
7467 | vf->height = force_w_h & 0xffff; | |
7468 | } | |
7469 | vf->compWidth = pic_config->y_crop_width; | |
7470 | vf->compHeight = pic_config->y_crop_height; | |
9edb8e76 | 7471 | set_frame_info(pbi, vf); |
b9164398 NQ |
7472 | if (force_fps & 0x100) { |
7473 | u32 rate = force_fps & 0xff; | |
e0614bf7 | 7474 | |
b9164398 NQ |
7475 | if (rate) |
7476 | vf->duration = 96000/rate; | |
7477 | else | |
7478 | vf->duration = 0; | |
7479 | } | |
b7706e1e | 7480 | update_vf_memhandle(pbi, vf, pic_config); |
36114cbd | 7481 | if (vdec_stream_based(pvdec) && (!pvdec->vbuf.use_ptsserv)) { |
7482 | vf->pts_us64 = stream_offset; | |
7483 | vf->pts = 0; | |
7484 | } | |
c23e8aee | 7485 | if (!(pic_config->y_crop_width == 196 |
e3b2152e | 7486 | && pic_config->y_crop_height == 196 |
7487 | && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0 | |
7488 | && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) { | |
3be38e55 | 7489 | struct vdec_info tmp4x; |
7490 | ||
e3b2152e | 7491 | inc_vf_ref(pbi, pic_config->index); |
85193e3c | 7492 | vdec_vframe_ready(pvdec, vf); |
e3b2152e | 7493 | kfifo_put(&pbi->display_q, (const struct vframe_s *)vf); |
7494 | ATRACE_COUNTER(MODULE_NAME, vf->pts); | |
7495 | pbi->vf_pre_count++; | |
cc41710a | 7496 | pbi_update_gvs(pbi); |
e3b2152e | 7497 | /*count info*/ |
cc41710a | 7498 | vdec_count_info(pbi->gvs, 0, stream_offset); |
4cd99df0 | 7499 | if (stream_offset) { |
7500 | if (slice_type == KEY_FRAME) { | |
7501 | pbi->gvs->i_decoded_frames++; | |
7502 | } else if (slice_type == INTER_FRAME) { | |
7503 | pbi->gvs->p_decoded_frames++; | |
7504 | } else if (slice_type == FRAME_TYPES) { | |
7505 | pbi->gvs->b_decoded_frames++; | |
7506 | } | |
7507 | } | |
3be38e55 | 7508 | memcpy(&tmp4x, pbi->gvs, sizeof(struct vdec_info)); |
7509 | tmp4x.bit_depth_luma = pbi->vp9_param.p.bit_depth; | |
7510 | tmp4x.bit_depth_chroma = pbi->vp9_param.p.bit_depth; | |
7511 | tmp4x.double_write_mode = get_double_write_mode(pbi); | |
7512 | vdec_fill_vdec_frame(pvdec, &pbi->vframe_qos, &tmp4x, | |
cc41710a | 7513 | vf, pic_config->hw_decode_time); |
7514 | pvdec->vdec_fps_detec(pvdec->id); | |
7c2956be PY |
7515 | if (without_display_mode == 0) { |
7516 | vf_notify_receiver(pbi->provider_name, | |
7517 | VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); | |
7518 | } else | |
7519 | vvp9_vf_put(vvp9_vf_get(pbi), pbi); | |
c23e8aee HZ |
7520 | } else { |
7521 | pbi->stat |= VP9_TRIGGER_FRAME_DONE; | |
7522 | hevc_source_changed(VFORMAT_VP9, 196, 196, 30); | |
7523 | pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n", | |
7524 | __func__, __LINE__, vf->width, | |
7525 | vf->height, pbi->stat); | |
7526 | } | |
b9164398 NQ |
7527 | } |
7528 | ||
7529 | return 0; | |
7530 | } | |
7531 | ||
2cd6815e NQ |
7532 | static int notify_v4l_eos(struct vdec_s *vdec) |
7533 | { | |
7534 | struct VP9Decoder_s *hw = (struct VP9Decoder_s *)vdec->private; | |
7535 | struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx); | |
8e9fb312 NQ |
7536 | struct vframe_s *vf = &hw->vframe_dummy; |
7537 | struct vdec_v4l2_buffer *fb = NULL; | |
75803959 NQ |
7538 | int index = INVALID_IDX; |
7539 | ulong expires; | |
2cd6815e | 7540 | |
b4a59a5a | 7541 | if (hw->eos) { |
7542 | if (hw->is_used_v4l) { | |
7543 | expires = jiffies + msecs_to_jiffies(2000); | |
7544 | while (INVALID_IDX == (index = v4l_get_free_fb(hw))) { | |
7545 | if (time_after(jiffies, expires) || | |
7546 | v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) | |
7547 | break; | |
7548 | } | |
75803959 | 7549 | |
b4a59a5a | 7550 | if (index == INVALID_IDX) { |
7551 | if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) { | |
7552 | pr_err("[%d] EOS get free buff fail.\n", ctx->id); | |
7553 | return -1; | |
7554 | } | |
8e9fb312 | 7555 | } |
2cd6815e NQ |
7556 | } |
7557 | ||
75803959 NQ |
7558 | vf->type |= VIDTYPE_V4L_EOS; |
7559 | vf->timestamp = ULONG_MAX; | |
75803959 | 7560 | vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L; |
8e9fb312 NQ |
7561 | vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb : |
7562 | hw->m_BUF[index].v4l_ref_buf_addr; | |
2cd6815e NQ |
7563 | |
7564 | kfifo_put(&hw->display_q, (const struct vframe_s *)vf); | |
7565 | vf_notify_receiver(vdec->vf_provider_name, | |
7566 | VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); | |
7567 | ||
b4a59a5a | 7568 | pr_info("[%d] VP9 EOS notify.\n", (hw->is_used_v4l)?ctx->id:vdec->id); |
2cd6815e NQ |
7569 | } |
7570 | ||
7571 | return 0; | |
7572 | } | |
7573 | ||
b9164398 NQ |
7574 | static void get_rpm_param(union param_u *params) |
7575 | { | |
7576 | int i; | |
7577 | unsigned int data32; | |
e0614bf7 | 7578 | |
b9164398 NQ |
7579 | if (debug & VP9_DEBUG_BUFMGR) |
7580 | pr_info("enter %s\r\n", __func__); | |
7581 | for (i = 0; i < 128; i++) { | |
7582 | do { | |
7583 | data32 = READ_VREG(RPM_CMD_REG); | |
7584 | /*pr_info("%x\n", data32);*/ | |
7585 | } while ((data32 & 0x10000) == 0); | |
7586 | params->l.data[i] = data32&0xffff; | |
7587 | /*pr_info("%x\n", data32);*/ | |
7588 | WRITE_VREG(RPM_CMD_REG, 0); | |
7589 | } | |
7590 | if (debug & VP9_DEBUG_BUFMGR) | |
7591 | pr_info("leave %s\r\n", __func__); | |
7592 | } | |
7593 | static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi) | |
7594 | { | |
7595 | int i; | |
e0614bf7 | 7596 | |
b9164398 NQ |
7597 | if (!(debug & VP9_DEBUG_BUFMGR_MORE)) |
7598 | return; | |
7599 | pr_info("vp9_param: (%d)\n", pbi->slice_idx); | |
7600 | for (i = 0; i < (RPM_END-RPM_BEGIN); i++) { | |
3be38e55 | 7601 | pr_info("%04x ", pbi->vp9_param.l.data[i]); |
b9164398 NQ |
7602 | if (((i + 1) & 0xf) == 0) |
7603 | pr_info("\n"); | |
7604 | } | |
7605 | pr_info("=============param==========\r\n"); | |
3be38e55 | 7606 | pr_info("profile %x\r\n", pbi->vp9_param.p.profile); |
b9164398 | 7607 | pr_info("show_existing_frame %x\r\n", |
3be38e55 | 7608 | pbi->vp9_param.p.show_existing_frame); |
b9164398 | 7609 | pr_info("frame_to_show_idx %x\r\n", |
3be38e55 | 7610 | pbi->vp9_param.p.frame_to_show_idx); |
7611 | pr_info("frame_type %x\r\n", pbi->vp9_param.p.frame_type); | |
7612 | pr_info("show_frame %x\r\n", pbi->vp9_param.p.show_frame); | |
b9164398 | 7613 | pr_info("e.r.r.o.r_resilient_mode %x\r\n", |
3be38e55 | 7614 | pbi->vp9_param.p.error_resilient_mode); |
7615 | pr_info("intra_only %x\r\n", pbi->vp9_param.p.intra_only); | |
b9164398 | 7616 | pr_info("display_size_present %x\r\n", |
3be38e55 | 7617 | pbi->vp9_param.p.display_size_present); |
b9164398 | 7618 | pr_info("reset_frame_context %x\r\n", |
3be38e55 | 7619 | pbi->vp9_param.p.reset_frame_context); |
b9164398 | 7620 | pr_info("refresh_frame_flags %x\r\n", |
3be38e55 | 7621 | pbi->vp9_param.p.refresh_frame_flags); |
7622 | pr_info("bit_depth %x\r\n", pbi->vp9_param.p.bit_depth); | |
7623 | pr_info("width %x\r\n", pbi->vp9_param.p.width); | |
7624 | pr_info("height %x\r\n", pbi->vp9_param.p.height); | |
7625 | pr_info("display_width %x\r\n", pbi->vp9_param.p.display_width); | |
7626 | pr_info("display_height %x\r\n", pbi->vp9_param.p.display_height); | |
7627 | pr_info("ref_info %x\r\n", pbi->vp9_param.p.ref_info); | |
7628 | pr_info("same_frame_size %x\r\n", pbi->vp9_param.p.same_frame_size); | |
b9164398 NQ |
7629 | if (!(debug & VP9_DEBUG_DBG_LF_PRINT)) |
7630 | return; | |
7631 | pr_info("mode_ref_delta_enabled: 0x%x\r\n", | |
3be38e55 | 7632 | pbi->vp9_param.p.mode_ref_delta_enabled); |
b9164398 | 7633 | pr_info("sharpness_level: 0x%x\r\n", |
3be38e55 | 7634 | pbi->vp9_param.p.sharpness_level); |
b9164398 | 7635 | pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n", |
3be38e55 | 7636 | pbi->vp9_param.p.ref_deltas[0], pbi->vp9_param.p.ref_deltas[1], |
7637 | pbi->vp9_param.p.ref_deltas[2], pbi->vp9_param.p.ref_deltas[3]); | |
7638 | pr_info("mode_deltas: 0x%x, 0x%x\r\n", pbi->vp9_param.p.mode_deltas[0], | |
7639 | pbi->vp9_param.p.mode_deltas[1]); | |
7640 | pr_info("filter_level: 0x%x\r\n", pbi->vp9_param.p.filter_level); | |
7641 | pr_info("seg_enabled: 0x%x\r\n", pbi->vp9_param.p.seg_enabled); | |
7642 | pr_info("seg_abs_delta: 0x%x\r\n", pbi->vp9_param.p.seg_abs_delta); | |
b9164398 | 7643 | pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n", |
3be38e55 | 7644 | (pbi->vp9_param.p.seg_lf_info[0]>>15 & 1), |
7645 | (pbi->vp9_param.p.seg_lf_info[1]>>15 & 1), | |
7646 | (pbi->vp9_param.p.seg_lf_info[2]>>15 & 1), | |
7647 | (pbi->vp9_param.p.seg_lf_info[3]>>15 & 1), | |
7648 | (pbi->vp9_param.p.seg_lf_info[4]>>15 & 1), | |
7649 | (pbi->vp9_param.p.seg_lf_info[5]>>15 & 1), | |
7650 | (pbi->vp9_param.p.seg_lf_info[6]>>15 & 1), | |
7651 | (pbi->vp9_param.p.seg_lf_info[7]>>15 & 1)); | |
b9164398 | 7652 | pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n", |
3be38e55 | 7653 | (pbi->vp9_param.p.seg_lf_info[0] & 0x13f), |
7654 | (pbi->vp9_param.p.seg_lf_info[1] & 0x13f), | |
7655 | (pbi->vp9_param.p.seg_lf_info[2] & 0x13f), | |
7656 | (pbi->vp9_param.p.seg_lf_info[3] & 0x13f), | |
7657 | (pbi->vp9_param.p.seg_lf_info[4] & 0x13f), | |
7658 | (pbi->vp9_param.p.seg_lf_info[5] & 0x13f), | |
7659 | (pbi->vp9_param.p.seg_lf_info[6] & 0x13f), | |
7660 | (pbi->vp9_param.p.seg_lf_info[7] & 0x13f)); | |
b9164398 NQ |
7661 | |
7662 | } | |
7663 | ||
b7706e1e | 7664 | |
fe96802b NQ |
7665 | static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi) |
7666 | { | |
7667 | struct VP9_Common_s *const cm = &pbi->common; | |
6276f4ff HZ |
7668 | if (pbi->double_write_mode & 0x10) |
7669 | return; | |
fe96802b | 7670 | if (cm->cur_fb_idx_mmu != INVALID_IDX) { |
144f5ee8 | 7671 | if (pbi->used_4k_num == -1) { |
fe96802b NQ |
7672 | pbi->used_4k_num = |
7673 | (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); | |
144f5ee8 HZ |
7674 | if (pbi->m_ins_flag) |
7675 | hevc_mmu_dma_check(hw_to_vdec(pbi)); | |
7676 | } | |
fe96802b NQ |
7677 | decoder_mmu_box_free_idx_tail(pbi->mmu_box, |
7678 | cm->cur_fb_idx_mmu, pbi->used_4k_num); | |
fe96802b NQ |
7679 | cm->cur_fb_idx_mmu = INVALID_IDX; |
7680 | pbi->used_4k_num = -1; | |
7681 | } | |
7682 | } | |
7683 | ||
7684 | #ifdef MULTI_INSTANCE_SUPPORT | |
7685 | static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi) | |
7686 | { | |
7687 | struct VP9_Common_s *const cm = &pbi->common; | |
6276f4ff HZ |
7688 | if (pbi->double_write_mode & 0x10) |
7689 | return; | |
fe96802b NQ |
7690 | if (cm->cur_fb_idx_mmu != INVALID_IDX) { |
7691 | decoder_mmu_box_free_idx(pbi->mmu_box, | |
7692 | cm->cur_fb_idx_mmu); | |
7693 | ||
7694 | cm->cur_fb_idx_mmu = INVALID_IDX; | |
7695 | pbi->used_4k_num = -1; | |
7696 | } | |
7697 | } | |
dc4a2edc | 7698 | |
7699 | void vp9_recycle_mmu_work(struct work_struct *work) | |
7700 | { | |
7701 | struct VP9Decoder_s *pbi = container_of(work, | |
7702 | struct VP9Decoder_s, recycle_mmu_work); | |
7703 | ||
eacf45ec SZ |
7704 | if (pbi) |
7705 | vp9_recycle_mmu_buf(pbi); | |
dc4a2edc | 7706 | } |
fe96802b | 7707 | #endif |
b7706e1e | 7708 | |
fe96802b NQ |
7709 | |
7710 | static void dec_again_process(struct VP9Decoder_s *pbi) | |
7711 | { | |
7712 | amhevc_stop(); | |
7713 | pbi->dec_result = DEC_RESULT_AGAIN; | |
7714 | if (pbi->process_state == | |
7715 | PROC_STATE_DECODESLICE) { | |
7716 | pbi->process_state = | |
7717 | PROC_STATE_SENDAGAIN; | |
dc4a2edc | 7718 | if (pbi->mmu_enable) { |
7719 | /* | |
7720 | * Because vp9_recycle_mmu_buf has sleep function,we can't | |
7721 | * call it directly. Use a recycle_mmu_work to substitude it. | |
7722 | */ | |
7723 | vdec_schedule_work(&pbi->recycle_mmu_work); | |
7724 | } | |
fe96802b NQ |
7725 | } |
7726 | reset_process_time(pbi); | |
7727 | vdec_schedule_work(&pbi->work); | |
7728 | } | |
7729 | ||
a6c89e96 NQ |
7730 | int continue_decoding(struct VP9Decoder_s *pbi) |
7731 | { | |
7732 | int ret; | |
7733 | int i; | |
7734 | struct VP9_Common_s *const cm = &pbi->common; | |
d9a28922 | 7735 | struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(pbi->v4l2_ctx); |
a6c89e96 NQ |
7736 | debug_buffer_mgr_more(pbi); |
7737 | ||
d9a28922 YP |
7738 | if (pbi->is_used_v4l && ctx->param_sets_from_ucode) |
7739 | pbi->res_ch_flag = 0; | |
0baa899d | 7740 | |
3be38e55 | 7741 | bit_depth_luma = pbi->vp9_param.p.bit_depth; |
7742 | bit_depth_chroma = pbi->vp9_param.p.bit_depth; | |
a6c89e96 | 7743 | |
3be38e55 | 7744 | if ((pbi->vp9_param.p.bit_depth >= VPX_BITS_10) && |
21d9caac | 7745 | (get_double_write_mode(pbi) == 0x10)) { |
7746 | pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; | |
7747 | pr_err("fatal err, bit_depth %d, unsupport dw 0x10\n", | |
3be38e55 | 7748 | pbi->vp9_param.p.bit_depth); |
21d9caac | 7749 | return -1; |
7750 | } | |
7751 | ||
a6c89e96 | 7752 | if (pbi->process_state != PROC_STATE_SENDAGAIN) { |
3be38e55 | 7753 | ret = vp9_bufmgr_process(pbi, &pbi->vp9_param); |
a6c89e96 NQ |
7754 | if (!pbi->m_ins_flag) |
7755 | pbi->slice_idx++; | |
7756 | } else { | |
3be38e55 | 7757 | union param_u *params = &pbi->vp9_param; |
6276f4ff | 7758 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
b7706e1e | 7759 | ret = vp9_alloc_mmu(pbi, |
a6c89e96 | 7760 | cm->new_fb_idx, |
b7706e1e | 7761 | params->p.width, |
7762 | params->p.height, | |
7763 | params->p.bit_depth, | |
7764 | pbi->frame_mmu_map_addr); | |
7765 | if (ret >= 0) | |
7766 | cm->cur_fb_idx_mmu = cm->new_fb_idx; | |
7767 | else | |
7768 | pr_err("can't alloc need mmu1,idx %d ret =%d\n", | |
7769 | cm->new_fb_idx, | |
7770 | ret); | |
7771 | } else { | |
7772 | ret = 0; | |
7773 | } | |
a6c89e96 NQ |
7774 | WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, |
7775 | (params->p.height << 16) | params->p.width); | |
7776 | } | |
7777 | if (ret < 0) { | |
7778 | pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n", | |
7779 | ret); | |
7780 | WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL); | |
7781 | cm->show_frame = 0; | |
b7706e1e | 7782 | if (pbi->mmu_enable) |
7783 | vp9_recycle_mmu_buf(pbi); | |
a6c89e96 NQ |
7784 | #ifdef MULTI_INSTANCE_SUPPORT |
7785 | if (pbi->m_ins_flag) { | |
7786 | pbi->dec_result = DEC_RESULT_DONE; | |
7787 | #ifdef SUPPORT_FB_DECODING | |
7788 | if (pbi->used_stage_buf_num == 0) | |
7789 | #endif | |
7790 | amhevc_stop(); | |
7791 | vdec_schedule_work(&pbi->work); | |
7792 | } | |
7793 | #endif | |
7794 | return ret; | |
7795 | } else if (ret == 0) { | |
7796 | struct PIC_BUFFER_CONFIG_s *cur_pic_config | |
7797 | = &cm->cur_frame->buf; | |
7798 | cur_pic_config->decode_idx = pbi->frame_count; | |
7799 | ||
7800 | if (pbi->process_state != PROC_STATE_SENDAGAIN) { | |
7801 | if (!pbi->m_ins_flag) { | |
7802 | pbi->frame_count++; | |
7803 | decode_frame_count[pbi->index] | |
7804 | = pbi->frame_count; | |
7805 | } | |
7806 | #ifdef MULTI_INSTANCE_SUPPORT | |
7807 | if (pbi->chunk) { | |
7808 | cur_pic_config->pts = pbi->chunk->pts; | |
7809 | cur_pic_config->pts64 = pbi->chunk->pts64; | |
0fb7e163 | 7810 | cur_pic_config->timestamp = pbi->chunk->timestamp; |
a6c89e96 NQ |
7811 | } |
7812 | #endif | |
7813 | } | |
7814 | /*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/ | |
3be38e55 | 7815 | config_pic_size(pbi, pbi->vp9_param.p.bit_depth); |
a6c89e96 NQ |
7816 | |
7817 | if ((pbi->common.frame_type != KEY_FRAME) | |
7818 | && (!pbi->common.intra_only)) { | |
3be38e55 | 7819 | config_mc_buffer(pbi, pbi->vp9_param.p.bit_depth); |
a6c89e96 NQ |
7820 | #ifdef SUPPORT_FB_DECODING |
7821 | if (pbi->used_stage_buf_num == 0) | |
7822 | #endif | |
7823 | config_mpred_hw(pbi); | |
7824 | } else { | |
7825 | #ifdef SUPPORT_FB_DECODING | |
7826 | if (pbi->used_stage_buf_num == 0) | |
7827 | #endif | |
7828 | clear_mpred_hw(pbi); | |
7829 | } | |
7830 | #ifdef MCRCC_ENABLE | |
7831 | if (mcrcc_cache_alg_flag) | |
7832 | config_mcrcc_axi_hw_new(pbi); | |
7833 | else | |
7834 | config_mcrcc_axi_hw(pbi); | |
7835 | #endif | |
3be38e55 | 7836 | config_sao_hw(pbi, &pbi->vp9_param); |
a6c89e96 NQ |
7837 | |
7838 | #ifdef VP9_LPF_LVL_UPDATE | |
b7706e1e | 7839 | /* |
7840 | * Get loop filter related picture level parameters from Parser | |
7841 | */ | |
3be38e55 | 7842 | pbi->lf->mode_ref_delta_enabled = pbi->vp9_param.p.mode_ref_delta_enabled; |
7843 | pbi->lf->sharpness_level = pbi->vp9_param.p.sharpness_level; | |
b7706e1e | 7844 | for (i = 0; i < 4; i++) |
3be38e55 | 7845 | pbi->lf->ref_deltas[i] = pbi->vp9_param.p.ref_deltas[i]; |
b7706e1e | 7846 | for (i = 0; i < 2; i++) |
3be38e55 | 7847 | pbi->lf->mode_deltas[i] = pbi->vp9_param.p.mode_deltas[i]; |
7848 | pbi->default_filt_lvl = pbi->vp9_param.p.filter_level; | |
7849 | pbi->seg_4lf->enabled = pbi->vp9_param.p.seg_enabled; | |
7850 | pbi->seg_4lf->abs_delta = pbi->vp9_param.p.seg_abs_delta; | |
b7706e1e | 7851 | for (i = 0; i < MAX_SEGMENTS; i++) |
3be38e55 | 7852 | pbi->seg_4lf->feature_mask[i] = (pbi->vp9_param.p.seg_lf_info[i] & |
b7706e1e | 7853 | 0x8000) ? (1 << SEG_LVL_ALT_LF) : 0; |
7854 | for (i = 0; i < MAX_SEGMENTS; i++) | |
7855 | pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF] | |
3be38e55 | 7856 | = (pbi->vp9_param.p.seg_lf_info[i] |
7857 | & 0x100) ? -(pbi->vp9_param.p.seg_lf_info[i] | |
7858 | & 0x3f) : (pbi->vp9_param.p.seg_lf_info[i] & 0x3f); | |
b7706e1e | 7859 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { |
7860 | /*Set pipeline mode*/ | |
7861 | uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB); | |
7862 | /*dblk pipeline mode=1 for performance*/ | |
3be38e55 | 7863 | if (pbi->vp9_param.p.width >= 1280) |
b7706e1e | 7864 | lpf_data32 |= (0x1 << 4); |
7865 | else | |
7866 | lpf_data32 &= ~(0x3 << 4); | |
7867 | WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32); | |
7868 | } | |
7869 | /* | |
7870 | * Update loop filter Thr/Lvl table for every frame | |
7871 | */ | |
7872 | /*pr_info | |
7873 | ("vp9_loop_filter (run before every frame decoding start)\n");*/ | |
7874 | vp9_loop_filter_frame_init(pbi->seg_4lf, | |
7875 | pbi->lfi, pbi->lf, pbi->default_filt_lvl); | |
a6c89e96 | 7876 | #endif |
b7706e1e | 7877 | /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/ |
7878 | WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE); | |
a6c89e96 NQ |
7879 | } else { |
7880 | pr_info("Skip search next start code\n"); | |
7881 | cm->prev_fb_idx = INVALID_IDX; | |
7882 | /*skip, search next start code*/ | |
7883 | WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE); | |
7884 | } | |
7885 | pbi->process_state = PROC_STATE_DECODESLICE; | |
6276f4ff | 7886 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
87046a60 | 7887 | if (pbi->last_put_idx < pbi->used_buf_num) { |
b7706e1e | 7888 | struct RefCntBuffer_s *frame_bufs = |
7889 | cm->buffer_pool->frame_bufs; | |
7890 | int i = pbi->last_put_idx; | |
7891 | /*free not used buffers.*/ | |
7892 | if ((frame_bufs[i].ref_count == 0) && | |
7893 | (frame_bufs[i].buf.vf_ref == 0) && | |
7894 | (frame_bufs[i].buf.index != -1)) { | |
7895 | decoder_mmu_box_free_idx(pbi->mmu_box, i); | |
7896 | } | |
7897 | pbi->last_put_idx = -1; | |
a6c89e96 | 7898 | } |
a6c89e96 | 7899 | } |
a6c89e96 NQ |
7900 | return ret; |
7901 | } | |
7902 | ||
ac678990 NQ |
7903 | static void fill_frame_info(struct VP9Decoder_s *pbi, |
7904 | struct PIC_BUFFER_CONFIG_s *frame, | |
7905 | unsigned int framesize, | |
7906 | unsigned int pts) | |
7907 | { | |
7908 | struct vframe_qos_s *vframe_qos = &pbi->vframe_qos; | |
7909 | ||
7910 | if (frame->slice_type == KEY_FRAME) | |
7911 | vframe_qos->type = 1; | |
7912 | else if (frame->slice_type == INTER_FRAME) | |
7913 | vframe_qos->type = 2; | |
7914 | /* | |
7915 | #define SHOW_QOS_INFO | |
7916 | */ | |
cc41710a | 7917 | if (input_frame_based(hw_to_vdec(pbi))) |
7918 | vframe_qos->size = frame->frame_size2; | |
7919 | else | |
7920 | vframe_qos->size = framesize; | |
ac678990 NQ |
7921 | vframe_qos->pts = pts; |
7922 | #ifdef SHOW_QOS_INFO | |
7923 | vp9_print(pbi, 0, "slice:%d\n", frame->slice_type); | |
7924 | #endif | |
7925 | vframe_qos->max_mv = frame->max_mv; | |
7926 | vframe_qos->avg_mv = frame->avg_mv; | |
7927 | vframe_qos->min_mv = frame->min_mv; | |
7928 | #ifdef SHOW_QOS_INFO | |
7929 | vp9_print(pbi, 0, "mv: max:%d, avg:%d, min:%d\n", | |
7930 | vframe_qos->max_mv, | |
7931 | vframe_qos->avg_mv, | |
7932 | vframe_qos->min_mv); | |
7933 | #endif | |
7934 | vframe_qos->max_qp = frame->max_qp; | |
7935 | vframe_qos->avg_qp = frame->avg_qp; | |
7936 | vframe_qos->min_qp = frame->min_qp; | |
7937 | #ifdef SHOW_QOS_INFO | |
7938 | vp9_print(pbi, 0, "qp: max:%d, avg:%d, min:%d\n", | |
7939 | vframe_qos->max_qp, | |
7940 | vframe_qos->avg_qp, | |
7941 | vframe_qos->min_qp); | |
7942 | #endif | |
7943 | vframe_qos->max_skip = frame->max_skip; | |
7944 | vframe_qos->avg_skip = frame->avg_skip; | |
7945 | vframe_qos->min_skip = frame->min_skip; | |
7946 | #ifdef SHOW_QOS_INFO | |
7947 | vp9_print(pbi, 0, "skip: max:%d, avg:%d, min:%d\n", | |
7948 | vframe_qos->max_skip, | |
7949 | vframe_qos->avg_skip, | |
7950 | vframe_qos->min_skip); | |
7951 | #endif | |
7952 | vframe_qos->num++; | |
ac678990 NQ |
7953 | } |
7954 | ||
7955 | /* only when we decoded one field or one frame, | |
7956 | we can call this function to get qos info*/ | |
7957 | static void get_picture_qos_info(struct VP9Decoder_s *pbi) | |
7958 | { | |
7959 | struct PIC_BUFFER_CONFIG_s *frame = &pbi->cur_buf->buf; | |
cc41710a | 7960 | struct vdec_s *vdec = hw_to_vdec(pbi); |
ac678990 NQ |
7961 | |
7962 | if (!frame) | |
7963 | return; | |
cc41710a | 7964 | if (vdec->mvfrm) { |
7965 | frame->frame_size2 = vdec->mvfrm->frame_size; | |
7966 | frame->hw_decode_time = | |
7967 | local_clock() - vdec->mvfrm->hw_decode_start; | |
7968 | } | |
ac678990 NQ |
7969 | |
7970 | if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) { | |
7971 | unsigned char a[3]; | |
7972 | unsigned char i, j, t; | |
7973 | unsigned long data; | |
7974 | ||
7975 | data = READ_VREG(HEVC_MV_INFO); | |
7976 | if (frame->slice_type == KEY_FRAME) | |
7977 | data = 0; | |
7978 | a[0] = data & 0xff; | |
7979 | a[1] = (data >> 8) & 0xff; | |
7980 | a[2] = (data >> 16) & 0xff; | |
7981 | ||
7982 | for (i = 0; i < 3; i++) { | |
7983 | for (j = i+1; j < 3; j++) { | |
7984 | if (a[j] < a[i]) { | |
7985 | t = a[j]; | |
7986 | a[j] = a[i]; | |
7987 | a[i] = t; | |
7988 | } else if (a[j] == a[i]) { | |
7989 | a[i]++; | |
7990 | t = a[j]; | |
7991 | a[j] = a[i]; | |
7992 | a[i] = t; | |
7993 | } | |
7994 | } | |
7995 | } | |
7996 | frame->max_mv = a[2]; | |
7997 | frame->avg_mv = a[1]; | |
7998 | frame->min_mv = a[0]; | |
7999 | ||
8000 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8001 | "mv data %x a[0]= %x a[1]= %x a[2]= %x\n", | |
8002 | data, a[0], a[1], a[2]); | |
8003 | ||
8004 | data = READ_VREG(HEVC_QP_INFO); | |
8005 | a[0] = data & 0x1f; | |
8006 | a[1] = (data >> 8) & 0x3f; | |
8007 | a[2] = (data >> 16) & 0x7f; | |
8008 | ||
8009 | for (i = 0; i < 3; i++) { | |
8010 | for (j = i+1; j < 3; j++) { | |
8011 | if (a[j] < a[i]) { | |
8012 | t = a[j]; | |
8013 | a[j] = a[i]; | |
8014 | a[i] = t; | |
8015 | } else if (a[j] == a[i]) { | |
8016 | a[i]++; | |
8017 | t = a[j]; | |
8018 | a[j] = a[i]; | |
8019 | a[i] = t; | |
8020 | } | |
8021 | } | |
8022 | } | |
8023 | frame->max_qp = a[2]; | |
8024 | frame->avg_qp = a[1]; | |
8025 | frame->min_qp = a[0]; | |
8026 | ||
8027 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8028 | "qp data %x a[0]= %x a[1]= %x a[2]= %x\n", | |
8029 | data, a[0], a[1], a[2]); | |
8030 | ||
8031 | data = READ_VREG(HEVC_SKIP_INFO); | |
8032 | a[0] = data & 0x1f; | |
8033 | a[1] = (data >> 8) & 0x3f; | |
8034 | a[2] = (data >> 16) & 0x7f; | |
8035 | ||
8036 | for (i = 0; i < 3; i++) { | |
8037 | for (j = i+1; j < 3; j++) { | |
8038 | if (a[j] < a[i]) { | |
8039 | t = a[j]; | |
8040 | a[j] = a[i]; | |
8041 | a[i] = t; | |
8042 | } else if (a[j] == a[i]) { | |
8043 | a[i]++; | |
8044 | t = a[j]; | |
8045 | a[j] = a[i]; | |
8046 | a[i] = t; | |
8047 | } | |
8048 | } | |
8049 | } | |
8050 | frame->max_skip = a[2]; | |
8051 | frame->avg_skip = a[1]; | |
8052 | frame->min_skip = a[0]; | |
8053 | ||
8054 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8055 | "skip data %x a[0]= %x a[1]= %x a[2]= %x\n", | |
8056 | data, a[0], a[1], a[2]); | |
8057 | } else { | |
8058 | uint32_t blk88_y_count; | |
8059 | uint32_t blk88_c_count; | |
8060 | uint32_t blk22_mv_count; | |
8061 | uint32_t rdata32; | |
8062 | int32_t mv_hi; | |
8063 | int32_t mv_lo; | |
8064 | uint32_t rdata32_l; | |
8065 | uint32_t mvx_L0_hi; | |
8066 | uint32_t mvy_L0_hi; | |
8067 | uint32_t mvx_L1_hi; | |
8068 | uint32_t mvy_L1_hi; | |
8069 | int64_t value; | |
8070 | uint64_t temp_value; | |
8071 | int pic_number = frame->decode_idx; | |
8072 | ||
8073 | frame->max_mv = 0; | |
8074 | frame->avg_mv = 0; | |
8075 | frame->min_mv = 0; | |
8076 | ||
8077 | frame->max_skip = 0; | |
8078 | frame->avg_skip = 0; | |
8079 | frame->min_skip = 0; | |
8080 | ||
8081 | frame->max_qp = 0; | |
8082 | frame->avg_qp = 0; | |
8083 | frame->min_qp = 0; | |
8084 | ||
8085 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n", | |
8086 | frame->slice_type, | |
8087 | pic_number); | |
8088 | ||
8089 | /* set rd_idx to 0 */ | |
8090 | WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0); | |
8091 | ||
8092 | blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8093 | if (blk88_y_count == 0) { | |
8094 | ||
8095 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8096 | "[Picture %d Quality] NO Data yet.\n", | |
8097 | pic_number); | |
8098 | ||
8099 | /* reset all counts */ | |
8100 | WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8)); | |
8101 | return; | |
8102 | } | |
8103 | /* qp_y_sum */ | |
8104 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8105 | ||
8106 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8107 | "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n", | |
8108 | pic_number, rdata32/blk88_y_count, | |
8109 | rdata32, blk88_y_count); | |
8110 | ||
8111 | frame->avg_qp = rdata32/blk88_y_count; | |
8112 | /* intra_y_count */ | |
8113 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8114 | ||
8115 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8116 | "[Picture %d Quality] Y intra rate : %d%c (%d)\n", | |
8117 | pic_number, rdata32*100/blk88_y_count, | |
8118 | '%', rdata32); | |
8119 | ||
8120 | /* skipped_y_count */ | |
8121 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8122 | ||
8123 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8124 | "[Picture %d Quality] Y skipped rate : %d%c (%d)\n", | |
8125 | pic_number, rdata32*100/blk88_y_count, | |
8126 | '%', rdata32); | |
8127 | ||
8128 | frame->avg_skip = rdata32*100/blk88_y_count; | |
8129 | /* coeff_non_zero_y_count */ | |
8130 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8131 | ||
8132 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8133 | "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n", | |
8134 | pic_number, (100 - rdata32*100/(blk88_y_count*1)), | |
8135 | '%', rdata32); | |
8136 | ||
8137 | /* blk66_c_count */ | |
8138 | blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8139 | if (blk88_c_count == 0) { | |
8140 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8141 | "[Picture %d Quality] NO Data yet.\n", | |
8142 | pic_number); | |
8143 | /* reset all counts */ | |
8144 | WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8)); | |
8145 | return; | |
8146 | } | |
8147 | /* qp_c_sum */ | |
8148 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8149 | ||
8150 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8151 | "[Picture %d Quality] C QP AVG : %d (%d/%d)\n", | |
8152 | pic_number, rdata32/blk88_c_count, | |
8153 | rdata32, blk88_c_count); | |
8154 | ||
8155 | /* intra_c_count */ | |
8156 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8157 | ||
8158 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8159 | "[Picture %d Quality] C intra rate : %d%c (%d)\n", | |
8160 | pic_number, rdata32*100/blk88_c_count, | |
8161 | '%', rdata32); | |
8162 | ||
8163 | /* skipped_cu_c_count */ | |
8164 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8165 | ||
8166 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8167 | "[Picture %d Quality] C skipped rate : %d%c (%d)\n", | |
8168 | pic_number, rdata32*100/blk88_c_count, | |
8169 | '%', rdata32); | |
8170 | ||
8171 | /* coeff_non_zero_c_count */ | |
8172 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8173 | ||
8174 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8175 | "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n", | |
8176 | pic_number, (100 - rdata32*100/(blk88_c_count*1)), | |
8177 | '%', rdata32); | |
8178 | ||
8179 | /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0], | |
8180 | 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */ | |
8181 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8182 | ||
8183 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8184 | "[Picture %d Quality] Y QP min : %d\n", | |
8185 | pic_number, (rdata32>>0)&0xff); | |
8186 | ||
8187 | frame->min_qp = (rdata32>>0)&0xff; | |
8188 | ||
8189 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8190 | "[Picture %d Quality] Y QP max : %d\n", | |
8191 | pic_number, (rdata32>>8)&0xff); | |
8192 | ||
8193 | frame->max_qp = (rdata32>>8)&0xff; | |
8194 | ||
8195 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8196 | "[Picture %d Quality] C QP min : %d\n", | |
8197 | pic_number, (rdata32>>16)&0xff); | |
8198 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8199 | "[Picture %d Quality] C QP max : %d\n", | |
8200 | pic_number, (rdata32>>24)&0xff); | |
8201 | ||
8202 | /* blk22_mv_count */ | |
8203 | blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8204 | if (blk22_mv_count == 0) { | |
8205 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8206 | "[Picture %d Quality] NO MV Data yet.\n", | |
8207 | pic_number); | |
8208 | /* reset all counts */ | |
8209 | WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8)); | |
8210 | return; | |
8211 | } | |
8212 | /* mvy_L1_count[39:32], mvx_L1_count[39:32], | |
8213 | mvy_L0_count[39:32], mvx_L0_count[39:32] */ | |
8214 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8215 | /* should all be 0x00 or 0xff */ | |
8216 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8217 | "[Picture %d Quality] MV AVG High Bits: 0x%X\n", | |
8218 | pic_number, rdata32); | |
8219 | ||
8220 | mvx_L0_hi = ((rdata32>>0)&0xff); | |
8221 | mvy_L0_hi = ((rdata32>>8)&0xff); | |
8222 | mvx_L1_hi = ((rdata32>>16)&0xff); | |
8223 | mvy_L1_hi = ((rdata32>>24)&0xff); | |
8224 | ||
8225 | /* mvx_L0_count[31:0] */ | |
8226 | rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8227 | temp_value = mvx_L0_hi; | |
8228 | temp_value = (temp_value << 32) | rdata32_l; | |
8229 | ||
8230 | if (mvx_L0_hi & 0x80) | |
8231 | value = 0xFFFFFFF000000000 | temp_value; | |
8232 | else | |
8233 | value = temp_value; | |
8234 | ||
8235 | value = div_s64(value, blk22_mv_count); | |
8236 | ||
8237 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8238 | "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n", | |
8239 | pic_number, (int)value, | |
8240 | value, blk22_mv_count); | |
8241 | ||
8242 | frame->avg_mv = value; | |
8243 | ||
8244 | /* mvy_L0_count[31:0] */ | |
8245 | rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8246 | temp_value = mvy_L0_hi; | |
8247 | temp_value = (temp_value << 32) | rdata32_l; | |
8248 | ||
8249 | if (mvy_L0_hi & 0x80) | |
8250 | value = 0xFFFFFFF000000000 | temp_value; | |
8251 | else | |
8252 | value = temp_value; | |
8253 | ||
8254 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8255 | "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n", | |
8256 | pic_number, rdata32_l/blk22_mv_count, | |
8257 | value, blk22_mv_count); | |
8258 | ||
8259 | /* mvx_L1_count[31:0] */ | |
8260 | rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8261 | temp_value = mvx_L1_hi; | |
8262 | temp_value = (temp_value << 32) | rdata32_l; | |
8263 | if (mvx_L1_hi & 0x80) | |
8264 | value = 0xFFFFFFF000000000 | temp_value; | |
8265 | else | |
8266 | value = temp_value; | |
8267 | ||
8268 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8269 | "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n", | |
8270 | pic_number, rdata32_l/blk22_mv_count, | |
8271 | value, blk22_mv_count); | |
8272 | ||
8273 | /* mvy_L1_count[31:0] */ | |
8274 | rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8275 | temp_value = mvy_L1_hi; | |
8276 | temp_value = (temp_value << 32) | rdata32_l; | |
8277 | if (mvy_L1_hi & 0x80) | |
8278 | value = 0xFFFFFFF000000000 | temp_value; | |
8279 | else | |
8280 | value = temp_value; | |
8281 | ||
8282 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8283 | "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n", | |
8284 | pic_number, rdata32_l/blk22_mv_count, | |
8285 | value, blk22_mv_count); | |
8286 | ||
8287 | /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */ | |
8288 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8289 | mv_hi = (rdata32>>16)&0xffff; | |
8290 | if (mv_hi & 0x8000) | |
8291 | mv_hi = 0x8000 - mv_hi; | |
8292 | ||
8293 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8294 | "[Picture %d Quality] MVX_L0 MAX : %d\n", | |
8295 | pic_number, mv_hi); | |
8296 | ||
8297 | frame->max_mv = mv_hi; | |
8298 | ||
8299 | mv_lo = (rdata32>>0)&0xffff; | |
8300 | if (mv_lo & 0x8000) | |
8301 | mv_lo = 0x8000 - mv_lo; | |
8302 | ||
8303 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8304 | "[Picture %d Quality] MVX_L0 MIN : %d\n", | |
8305 | pic_number, mv_lo); | |
8306 | ||
8307 | frame->min_mv = mv_lo; | |
8308 | ||
8309 | /* {mvy_L0_max, mvy_L0_min} */ | |
8310 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8311 | mv_hi = (rdata32>>16)&0xffff; | |
8312 | if (mv_hi & 0x8000) | |
8313 | mv_hi = 0x8000 - mv_hi; | |
8314 | ||
8315 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8316 | "[Picture %d Quality] MVY_L0 MAX : %d\n", | |
8317 | pic_number, mv_hi); | |
8318 | ||
8319 | mv_lo = (rdata32>>0)&0xffff; | |
8320 | if (mv_lo & 0x8000) | |
8321 | mv_lo = 0x8000 - mv_lo; | |
8322 | ||
8323 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8324 | "[Picture %d Quality] MVY_L0 MIN : %d\n", | |
8325 | pic_number, mv_lo); | |
8326 | ||
8327 | /* {mvx_L1_max, mvx_L1_min} */ | |
8328 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8329 | mv_hi = (rdata32>>16)&0xffff; | |
8330 | if (mv_hi & 0x8000) | |
8331 | mv_hi = 0x8000 - mv_hi; | |
8332 | ||
8333 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8334 | "[Picture %d Quality] MVX_L1 MAX : %d\n", | |
8335 | pic_number, mv_hi); | |
8336 | ||
8337 | mv_lo = (rdata32>>0)&0xffff; | |
8338 | if (mv_lo & 0x8000) | |
8339 | mv_lo = 0x8000 - mv_lo; | |
8340 | ||
8341 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8342 | "[Picture %d Quality] MVX_L1 MIN : %d\n", | |
8343 | pic_number, mv_lo); | |
8344 | ||
8345 | /* {mvy_L1_max, mvy_L1_min} */ | |
8346 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA); | |
8347 | mv_hi = (rdata32>>16)&0xffff; | |
8348 | if (mv_hi & 0x8000) | |
8349 | mv_hi = 0x8000 - mv_hi; | |
8350 | ||
8351 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8352 | "[Picture %d Quality] MVY_L1 MAX : %d\n", | |
8353 | pic_number, mv_hi); | |
8354 | ||
8355 | mv_lo = (rdata32>>0)&0xffff; | |
8356 | if (mv_lo & 0x8000) | |
8357 | mv_lo = 0x8000 - mv_lo; | |
8358 | ||
8359 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8360 | "[Picture %d Quality] MVY_L1 MIN : %d\n", | |
8361 | pic_number, mv_lo); | |
8362 | ||
8363 | rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL); | |
8364 | ||
8365 | vp9_print(pbi, VP9_DEBUG_QOS_INFO, | |
8366 | "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n", | |
8367 | pic_number, rdata32); | |
8368 | ||
8369 | /* reset all counts */ | |
8370 | WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8)); | |
8371 | } | |
8372 | } | |
8373 | ||
d9a28922 YP |
8374 | static int vvp9_get_ps_info(struct VP9Decoder_s *pbi, struct aml_vdec_ps_infos *ps) |
8375 | { | |
8376 | int dw_mode = v4l_parser_get_double_write_mode(pbi); | |
8377 | ||
8378 | ps->visible_width = pbi->frame_width / get_double_write_ratio(pbi, dw_mode); | |
8379 | ps->visible_height = pbi->frame_height / get_double_write_ratio(pbi, dw_mode); | |
8380 | ps->coded_width = ALIGN(pbi->frame_width, 32) / get_double_write_ratio(pbi, dw_mode); | |
8381 | ps->coded_height = ALIGN(pbi->frame_height, 32) / get_double_write_ratio(pbi, dw_mode); | |
8382 | ps->dpb_size = pbi->used_buf_num; | |
8383 | ||
8384 | return 0; | |
8385 | } | |
8386 | ||
8387 | ||
8388 | static int v4l_res_change(struct VP9Decoder_s *pbi) | |
8389 | { | |
8390 | struct aml_vcodec_ctx *ctx = | |
8391 | (struct aml_vcodec_ctx *)(pbi->v4l2_ctx); | |
8392 | struct VP9_Common_s *const cm = &pbi->common; | |
8393 | int ret = 0; | |
8394 | ||
8395 | if (ctx->param_sets_from_ucode && | |
8396 | pbi->res_ch_flag == 0) { | |
8397 | struct aml_vdec_ps_infos ps; | |
8398 | if ((cm->width != 0 && | |
8399 | cm->height != 0) && | |
8400 | (pbi->frame_width != cm->width || | |
8401 | pbi->frame_height != cm->height)) { | |
8402 | ||
8403 | vp9_print(pbi, 0, "%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width, | |
8404 | cm->height, pbi->frame_width, pbi->frame_height); | |
8405 | vvp9_get_ps_info(pbi, &ps); | |
8406 | vdec_v4l_set_ps_infos(ctx, &ps); | |
8407 | vdec_v4l_res_ch_event(ctx); | |
8408 | pbi->v4l_params_parsed = false; | |
8409 | pbi->res_ch_flag = 1; | |
0baa899d | 8410 | ctx->v4l_resolution_change = 1; |
d9a28922 YP |
8411 | pbi->eos = 1; |
8412 | vp9_bufmgr_postproc(pbi); | |
8413 | //del_timer_sync(&pbi->timer); | |
8414 | notify_v4l_eos(hw_to_vdec(pbi)); | |
8415 | ret = 1; | |
8416 | } | |
8417 | } | |
8418 | ||
8419 | return ret; | |
8420 | } | |
8421 | ||
8422 | ||
b9164398 NQ |
8423 | static irqreturn_t vvp9_isr_thread_fn(int irq, void *data) |
8424 | { | |
8425 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data; | |
8426 | unsigned int dec_status = pbi->dec_status; | |
a6c89e96 | 8427 | int i; |
b9164398 NQ |
8428 | |
8429 | /*if (pbi->wait_buf) | |
e0614bf7 ZZ |
8430 | * pr_info("set wait_buf to 0\r\n"); |
8431 | */ | |
fe96802b NQ |
8432 | if (pbi->eos) |
8433 | return IRQ_HANDLED; | |
b9164398 | 8434 | pbi->wait_buf = 0; |
fe96802b | 8435 | #ifdef MULTI_INSTANCE_SUPPORT |
a6c89e96 NQ |
8436 | #ifdef SUPPORT_FB_DECODING |
8437 | #ifdef FB_DECODING_TEST_SCHEDULE | |
8438 | if (pbi->s1_test_cmd == TEST_SET_PIC_DONE) | |
8439 | dec_status = HEVC_DECPIC_DATA_DONE; | |
8440 | else if (pbi->s1_test_cmd == TEST_SET_S2_DONE | |
8441 | && dec_status == HEVC_DECPIC_DATA_DONE) | |
8442 | dec_status = HEVC_S2_DECODING_DONE; | |
8443 | pbi->s1_test_cmd = TEST_SET_NONE; | |
8444 | #else | |
8445 | /*if (irq != VDEC_IRQ_0) | |
8446 | dec_status = HEVC_S2_DECODING_DONE;*/ | |
8447 | #endif | |
8448 | if (dec_status == HEVC_S2_DECODING_DONE) { | |
8449 | pbi->dec_result = DEC_RESULT_DONE; | |
8450 | vdec_schedule_work(&pbi->work); | |
8451 | #ifdef FB_DECODING_TEST_SCHEDULE | |
8452 | amhevc_stop(); | |
8453 | pbi->dec_s1_result = DEC_S1_RESULT_DONE; | |
8454 | vdec_schedule_work(&pbi->s1_work); | |
8455 | #endif | |
8456 | } else | |
8457 | #endif | |
fe96802b NQ |
8458 | if ((dec_status == HEVC_NAL_DECODE_DONE) || |
8459 | (dec_status == HEVC_SEARCH_BUFEMPTY) || | |
8460 | (dec_status == HEVC_DECODE_BUFEMPTY) | |
8461 | ) { | |
8462 | if (pbi->m_ins_flag) { | |
8463 | reset_process_time(pbi); | |
8464 | if (!vdec_frame_based(hw_to_vdec(pbi))) | |
8465 | dec_again_process(pbi); | |
8466 | else { | |
8467 | pbi->dec_result = DEC_RESULT_GET_DATA; | |
8468 | vdec_schedule_work(&pbi->work); | |
8469 | } | |
8470 | } | |
8471 | pbi->process_busy = 0; | |
8472 | return IRQ_HANDLED; | |
8473 | } else if (dec_status == HEVC_DECPIC_DATA_DONE) { | |
8474 | if (pbi->m_ins_flag) { | |
ac678990 | 8475 | get_picture_qos_info(pbi); |
a6c89e96 NQ |
8476 | #ifdef SUPPORT_FB_DECODING |
8477 | if (pbi->used_stage_buf_num > 0) { | |
8478 | reset_process_time(pbi); | |
8479 | inc_s1_pos(pbi); | |
8480 | trigger_schedule(pbi); | |
8481 | #ifdef FB_DECODING_TEST_SCHEDULE | |
8482 | pbi->s1_test_cmd = TEST_SET_S2_DONE; | |
8483 | #else | |
8484 | amhevc_stop(); | |
8485 | pbi->dec_s1_result = DEC_S1_RESULT_DONE; | |
8486 | vdec_schedule_work(&pbi->s1_work); | |
8487 | #endif | |
8488 | } else | |
8489 | #endif | |
8490 | { | |
8491 | reset_process_time(pbi); | |
187af067 | 8492 | if (pbi->vf_pre_count == 0 || pbi->low_latency_flag) |
fd6875e8 PY |
8493 | vp9_bufmgr_postproc(pbi); |
8494 | ||
a6c89e96 NQ |
8495 | pbi->dec_result = DEC_RESULT_DONE; |
8496 | amhevc_stop(); | |
8497 | if (mcrcc_cache_alg_flag) | |
8498 | dump_hit_rate(pbi); | |
8499 | vdec_schedule_work(&pbi->work); | |
8500 | } | |
187af067 | 8501 | } else { |
8502 | if (pbi->low_latency_flag) { | |
8503 | vp9_bufmgr_postproc(pbi); | |
8504 | WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); | |
8505 | #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC | |
8506 | vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_CB); | |
8507 | if (debug & PRINT_FLAG_VDEC_DETAIL) | |
8508 | pr_info("%s VP9 frame done \n", __func__); | |
8509 | #endif | |
8510 | } | |
fe96802b NQ |
8511 | } |
8512 | ||
8513 | pbi->process_busy = 0; | |
8514 | return IRQ_HANDLED; | |
8515 | } | |
8516 | #endif | |
b9164398 NQ |
8517 | |
8518 | if (dec_status == VP9_EOS) { | |
fe96802b NQ |
8519 | #ifdef MULTI_INSTANCE_SUPPORT |
8520 | if (pbi->m_ins_flag) | |
8521 | reset_process_time(pbi); | |
8522 | #endif | |
8523 | ||
b9164398 NQ |
8524 | pr_info("VP9_EOS, flush buffer\r\n"); |
8525 | ||
8526 | vp9_bufmgr_postproc(pbi); | |
8527 | ||
8528 | pr_info("send VP9_10B_DISCARD_NAL\r\n"); | |
8529 | WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL); | |
8530 | pbi->process_busy = 0; | |
fe96802b NQ |
8531 | #ifdef MULTI_INSTANCE_SUPPORT |
8532 | if (pbi->m_ins_flag) { | |
8533 | pbi->dec_result = DEC_RESULT_DONE; | |
8534 | amhevc_stop(); | |
8535 | vdec_schedule_work(&pbi->work); | |
8536 | } | |
8537 | #endif | |
8538 | return IRQ_HANDLED; | |
8539 | } else if (dec_status == HEVC_DECODE_OVER_SIZE) { | |
8540 | pr_info("vp9 decode oversize !!\n"); | |
8541 | debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC | | |
8542 | VP9_DEBUG_DIS_SYS_ERROR_PROC); | |
8543 | pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; | |
8544 | #ifdef MULTI_INSTANCE_SUPPORT | |
8545 | if (pbi->m_ins_flag) | |
8546 | reset_process_time(pbi); | |
8547 | #endif | |
b9164398 NQ |
8548 | return IRQ_HANDLED; |
8549 | } | |
8550 | ||
8551 | if (dec_status != VP9_HEAD_PARSER_DONE) { | |
8552 | pbi->process_busy = 0; | |
8553 | return IRQ_HANDLED; | |
8554 | } | |
fe96802b | 8555 | |
65ad8202 GZ |
8556 | if (pbi->m_ins_flag && |
8557 | !get_free_buf_count(pbi)) { | |
8558 | pbi->run_ready_min_buf_num = pbi->one_package_frame_cnt + 1; | |
8559 | pr_err("need buffer, one package frame count = %d\n", pbi->one_package_frame_cnt + 1); | |
8560 | pbi->dec_result = DEC_RESULT_NEED_MORE_BUFFER; | |
8561 | vdec_schedule_work(&pbi->work); | |
8562 | return IRQ_HANDLED; | |
8563 | } | |
8564 | ||
8565 | pbi->one_package_frame_cnt++; | |
187af067 | 8566 | |
fe96802b | 8567 | #ifdef MULTI_INSTANCE_SUPPORT |
187af067 | 8568 | #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC |
8569 | if (pbi->m_ins_flag ==0 && pbi->low_latency_flag) { | |
8570 | vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_RUN); | |
8571 | if (debug & PRINT_FLAG_VDEC_DETAIL) | |
8572 | pr_info("%s VP9 frame header found \n", __func__); | |
8573 | } | |
8574 | #endif | |
fe96802b NQ |
8575 | if (pbi->m_ins_flag) |
8576 | reset_process_time(pbi); | |
8577 | #endif | |
a6c89e96 NQ |
8578 | if (pbi->process_state != PROC_STATE_SENDAGAIN |
8579 | #ifdef SUPPORT_FB_DECODING | |
8580 | && pbi->used_stage_buf_num == 0 | |
8581 | #endif | |
8582 | ) { | |
b7706e1e | 8583 | if (pbi->mmu_enable) |
8584 | vp9_recycle_mmu_buf_tail(pbi); | |
8585 | ||
fe96802b NQ |
8586 | |
8587 | if (pbi->frame_count > 0) | |
8588 | vp9_bufmgr_postproc(pbi); | |
8589 | } | |
b9164398 NQ |
8590 | |
8591 | if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) { | |
3be38e55 | 8592 | get_rpm_param(&pbi->vp9_param); |
b9164398 | 8593 | } else { |
a6c89e96 NQ |
8594 | #ifdef SUPPORT_FB_DECODING |
8595 | if (pbi->used_stage_buf_num > 0) { | |
8596 | reset_process_time(pbi); | |
8597 | get_s1_buf(pbi); | |
8598 | ||
8599 | if (get_mv_buf(pbi, | |
8600 | &pbi->s1_mv_buf_index, | |
8601 | &pbi->s1_mpred_mv_wr_start_addr | |
8602 | ) < 0) { | |
8603 | vp9_print(pbi, 0, | |
8604 | "%s: Error get_mv_buf fail\n", | |
8605 | __func__); | |
8606 | } | |
b9164398 | 8607 | |
a6c89e96 NQ |
8608 | if (pbi->s1_buf == NULL) { |
8609 | vp9_print(pbi, 0, | |
8610 | "%s: Error get_s1_buf fail\n", | |
8611 | __func__); | |
8612 | pbi->process_busy = 0; | |
8613 | return IRQ_HANDLED; | |
fe96802b | 8614 | } |
a6c89e96 NQ |
8615 | |
8616 | for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { | |
8617 | int ii; | |
8618 | for (ii = 0; ii < 4; ii++) { | |
8619 | pbi->s1_buf->rpm[i + 3 - ii] = | |
8620 | pbi->rpm_ptr[i + 3 - ii]; | |
8621 | pbi->s1_param.l.data[i + ii] = | |
8622 | pbi->rpm_ptr[i + 3 - ii]; | |
8623 | } | |
fe96802b | 8624 | } |
a6c89e96 NQ |
8625 | |
8626 | mpred_process(pbi); | |
8627 | #ifdef FB_DECODING_TEST_SCHEDULE | |
8628 | pbi->dec_s1_result = | |
8629 | DEC_S1_RESULT_TEST_TRIGGER_DONE; | |
8630 | vdec_schedule_work(&pbi->s1_work); | |
8631 | #else | |
8632 | WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR, | |
8633 | pbi->stage_mmu_map_phy_addr + | |
8634 | pbi->s1_buf->index * STAGE_MMU_MAP_SIZE); | |
8635 | ||
8636 | start_s1_decoding(pbi); | |
fe96802b | 8637 | #endif |
a6c89e96 NQ |
8638 | start_process_time(pbi); |
8639 | pbi->process_busy = 0; | |
8640 | return IRQ_HANDLED; | |
8641 | } else | |
8642 | #endif | |
b7706e1e | 8643 | { |
8644 | for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { | |
8645 | int ii; | |
8646 | for (ii = 0; ii < 4; ii++) | |
3be38e55 | 8647 | pbi->vp9_param.l.data[i + ii] = |
b7706e1e | 8648 | pbi->rpm_ptr[i + 3 - ii]; |
8649 | } | |
fe96802b | 8650 | } |
b9164398 | 8651 | } |
b9164398 | 8652 | |
0fb7e163 NQ |
8653 | if (pbi->is_used_v4l) { |
8654 | struct aml_vcodec_ctx *ctx = | |
8655 | (struct aml_vcodec_ctx *)(pbi->v4l2_ctx); | |
8656 | ||
3be38e55 | 8657 | pbi->frame_width = pbi->vp9_param.p.width; |
8658 | pbi->frame_height = pbi->vp9_param.p.height; | |
d9a28922 YP |
8659 | |
8660 | if (!v4l_res_change(pbi)) { | |
8661 | if (ctx->param_sets_from_ucode && !pbi->v4l_params_parsed) { | |
8662 | struct aml_vdec_ps_infos ps; | |
8663 | ||
8664 | pr_debug("set ucode parse\n"); | |
8665 | vvp9_get_ps_info(pbi, &ps); | |
8666 | /*notice the v4l2 codec.*/ | |
8667 | vdec_v4l_set_ps_infos(ctx, &ps); | |
8668 | pbi->v4l_params_parsed = true; | |
8669 | pbi->postproc_done = 0; | |
8670 | pbi->process_busy = 0; | |
8671 | dec_again_process(pbi); | |
8672 | return IRQ_HANDLED; | |
8673 | } | |
8674 | } else { | |
8675 | pbi->postproc_done = 0; | |
8676 | pbi->process_busy = 0; | |
8677 | dec_again_process(pbi); | |
8678 | return IRQ_HANDLED; | |
0fb7e163 NQ |
8679 | } |
8680 | } | |
8681 | ||
d9a28922 YP |
8682 | continue_decoding(pbi); |
8683 | pbi->postproc_done = 0; | |
8684 | pbi->process_busy = 0; | |
a6c89e96 | 8685 | |
fe96802b NQ |
8686 | #ifdef MULTI_INSTANCE_SUPPORT |
8687 | if (pbi->m_ins_flag) | |
8688 | start_process_time(pbi); | |
8689 | #endif | |
8690 | ||
b9164398 NQ |
8691 | return IRQ_HANDLED; |
8692 | } | |
8693 | ||
8694 | static irqreturn_t vvp9_isr(int irq, void *data) | |
8695 | { | |
8696 | int i; | |
8697 | unsigned int dec_status; | |
8698 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data; | |
8699 | unsigned int adapt_prob_status; | |
8700 | struct VP9_Common_s *const cm = &pbi->common; | |
fe96802b NQ |
8701 | uint debug_tag; |
8702 | ||
a6c89e96 | 8703 | WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1); |
fe96802b | 8704 | |
b9164398 NQ |
8705 | dec_status = READ_VREG(HEVC_DEC_STATUS_REG); |
8706 | adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG); | |
b34d6d3e ZZ |
8707 | if (!pbi) |
8708 | return IRQ_HANDLED; | |
b9164398 NQ |
8709 | if (pbi->init_flag == 0) |
8710 | return IRQ_HANDLED; | |
8711 | if (pbi->process_busy)/*on process.*/ | |
8712 | return IRQ_HANDLED; | |
8713 | pbi->dec_status = dec_status; | |
8714 | pbi->process_busy = 1; | |
8715 | if (debug & VP9_DEBUG_BUFMGR) | |
a6c89e96 NQ |
8716 | pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n", |
8717 | irq, | |
fe96802b NQ |
8718 | dec_status, READ_VREG(HEVC_PARSER_LCU_START), |
8719 | READ_VREG(HEVC_SHIFT_BYTE_COUNT), | |
8720 | READ_VREG(HEVC_STREAM_START_ADDR), | |
8721 | READ_VREG(HEVC_STREAM_END_ADDR), | |
8722 | READ_VREG(HEVC_STREAM_LEVEL), | |
8723 | READ_VREG(HEVC_STREAM_WR_PTR), | |
8724 | READ_VREG(HEVC_STREAM_RD_PTR) | |
8725 | ); | |
a6c89e96 NQ |
8726 | #ifdef SUPPORT_FB_DECODING |
8727 | /*if (irq != VDEC_IRQ_0) | |
8728 | return IRQ_WAKE_THREAD;*/ | |
8729 | #endif | |
b9164398 | 8730 | |
fe96802b NQ |
8731 | debug_tag = READ_HREG(DEBUG_REG1); |
8732 | if (debug_tag & 0x10000) { | |
fe96802b NQ |
8733 | pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1)); |
8734 | for (i = 0; i < 0x400; i += 4) { | |
8735 | int ii; | |
8736 | if ((i & 0xf) == 0) | |
8737 | pr_info("%03x: ", i); | |
8738 | for (ii = 0; ii < 4; ii++) { | |
8739 | pr_info("%04x ", | |
8740 | pbi->lmem_ptr[i + 3 - ii]); | |
b9164398 | 8741 | } |
fe96802b NQ |
8742 | if (((i + ii) & 0xf) == 0) |
8743 | pr_info("\n"); | |
b9164398 NQ |
8744 | } |
8745 | ||
fe96802b NQ |
8746 | if ((udebug_pause_pos == (debug_tag & 0xffff)) && |
8747 | (udebug_pause_decode_idx == 0 || | |
8748 | udebug_pause_decode_idx == pbi->slice_idx) && | |
8749 | (udebug_pause_val == 0 || | |
8750 | udebug_pause_val == READ_HREG(DEBUG_REG2))) | |
8751 | pbi->ucode_pause_pos = udebug_pause_pos; | |
8752 | else if (debug_tag & 0x20000) | |
8753 | pbi->ucode_pause_pos = 0xffffffff; | |
8754 | if (pbi->ucode_pause_pos) | |
8755 | reset_process_time(pbi); | |
8756 | else | |
8757 | WRITE_HREG(DEBUG_REG1, 0); | |
8758 | } else if (debug_tag != 0) { | |
8759 | pr_info( | |
8760 | "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1), | |
8761 | READ_HREG(DEBUG_REG2), | |
8762 | READ_VREG(HEVC_PARSER_LCU_START)); | |
8763 | if ((udebug_pause_pos == (debug_tag & 0xffff)) && | |
8764 | (udebug_pause_decode_idx == 0 || | |
8765 | udebug_pause_decode_idx == pbi->slice_idx) && | |
8766 | (udebug_pause_val == 0 || | |
8767 | udebug_pause_val == READ_HREG(DEBUG_REG2))) | |
8768 | pbi->ucode_pause_pos = udebug_pause_pos; | |
8769 | if (pbi->ucode_pause_pos) | |
8770 | reset_process_time(pbi); | |
8771 | else | |
8772 | WRITE_HREG(DEBUG_REG1, 0); | |
b9164398 NQ |
8773 | pbi->process_busy = 0; |
8774 | return IRQ_HANDLED; | |
8775 | } | |
8776 | ||
fe96802b NQ |
8777 | #ifdef MULTI_INSTANCE_SUPPORT |
8778 | if (!pbi->m_ins_flag) { | |
8779 | #endif | |
8780 | if (pbi->error_flag == 1) { | |
8781 | pbi->error_flag = 2; | |
8782 | pbi->process_busy = 0; | |
8783 | return IRQ_HANDLED; | |
8784 | } else if (pbi->error_flag == 3) { | |
8785 | pbi->process_busy = 0; | |
8786 | return IRQ_HANDLED; | |
8787 | } | |
8788 | ||
8789 | if (get_free_buf_count(pbi) <= 0) { | |
8790 | /* | |
8791 | if (pbi->wait_buf == 0) | |
8792 | pr_info("set wait_buf to 1\r\n"); | |
8793 | */ | |
8794 | pbi->wait_buf = 1; | |
8795 | pbi->process_busy = 0; | |
8796 | return IRQ_HANDLED; | |
8797 | } | |
8798 | #ifdef MULTI_INSTANCE_SUPPORT | |
b9164398 | 8799 | } |
fe96802b | 8800 | #endif |
b9164398 NQ |
8801 | if ((adapt_prob_status & 0xff) == 0xfd) { |
8802 | /*VP9_REQ_ADAPT_PROB*/ | |
8803 | int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0; | |
8804 | uint8_t *prev_prob_b = | |
8805 | ((uint8_t *)pbi->prob_buffer_addr) + | |
8806 | ((adapt_prob_status >> 8) * 0x1000); | |
8807 | uint8_t *cur_prob_b = | |
8808 | ((uint8_t *)pbi->prob_buffer_addr) + 0x4000; | |
8809 | uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr; | |
fe96802b NQ |
8810 | #ifdef MULTI_INSTANCE_SUPPORT |
8811 | if (pbi->m_ins_flag) | |
8812 | reset_process_time(pbi); | |
8813 | #endif | |
b9164398 NQ |
8814 | adapt_coef_probs(pbi->pic_count, |
8815 | (cm->last_frame_type == KEY_FRAME), | |
8816 | pre_fc, (adapt_prob_status >> 8), | |
8817 | (unsigned int *)prev_prob_b, | |
8818 | (unsigned int *)cur_prob_b, (unsigned int *)count_b); | |
8819 | ||
8820 | memcpy(prev_prob_b, cur_prob_b, PROB_SIZE); | |
8821 | WRITE_VREG(VP9_ADAPT_PROB_REG, 0); | |
8822 | pbi->pic_count += 1; | |
b9164398 | 8823 | #ifdef MULTI_INSTANCE_SUPPORT |
fe96802b NQ |
8824 | if (pbi->m_ins_flag) |
8825 | start_process_time(pbi); | |
b9164398 | 8826 | #endif |
b9164398 | 8827 | |
fe96802b | 8828 | /*return IRQ_HANDLED;*/ |
b9164398 | 8829 | } |
b9164398 NQ |
8830 | return IRQ_WAKE_THREAD; |
8831 | } | |
8832 | ||
a994f6d6 | 8833 | static void vp9_set_clk(struct work_struct *work) |
8834 | { | |
8835 | struct VP9Decoder_s *pbi = container_of(work, | |
8deb3449 NQ |
8836 | struct VP9Decoder_s, set_clk_work); |
8837 | int fps = 96000 / pbi->frame_dur; | |
a994f6d6 | 8838 | |
8deb3449 NQ |
8839 | if (hevc_source_changed(VFORMAT_VP9, |
8840 | frame_width, frame_height, fps) > 0) | |
8841 | pbi->saved_resolution = frame_width * | |
8842 | frame_height * fps; | |
a994f6d6 | 8843 | } |
8844 | ||
b9164398 NQ |
8845 | static void vvp9_put_timer_func(unsigned long arg) |
8846 | { | |
8847 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg; | |
8848 | struct timer_list *timer = &pbi->timer; | |
8849 | uint8_t empty_flag; | |
8850 | unsigned int buf_level; | |
8851 | ||
8852 | enum receviver_start_e state = RECEIVER_INACTIVE; | |
e0614bf7 | 8853 | |
b9164398 NQ |
8854 | if (pbi->m_ins_flag) { |
8855 | if (hw_to_vdec(pbi)->next_status | |
d9a28922 YP |
8856 | == VDEC_STATUS_DISCONNECTED && |
8857 | !pbi->is_used_v4l) { | |
a6c89e96 NQ |
8858 | #ifdef SUPPORT_FB_DECODING |
8859 | if (pbi->run2_busy) | |
8860 | return; | |
8861 | ||
8862 | pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT; | |
8863 | vdec_schedule_work(&pbi->s1_work); | |
8864 | #endif | |
fe96802b NQ |
8865 | pbi->dec_result = DEC_RESULT_FORCE_EXIT; |
8866 | vdec_schedule_work(&pbi->work); | |
5b851ff9 | 8867 | pr_debug( |
b9164398 NQ |
8868 | "vdec requested to be disconnected\n"); |
8869 | return; | |
8870 | } | |
8871 | } | |
8872 | if (pbi->init_flag == 0) { | |
8873 | if (pbi->stat & STAT_TIMER_ARM) { | |
8874 | timer->expires = jiffies + PUT_INTERVAL; | |
8875 | add_timer(&pbi->timer); | |
8876 | } | |
8877 | return; | |
8878 | } | |
8879 | if (pbi->m_ins_flag == 0) { | |
8880 | if (vf_get_receiver(pbi->provider_name)) { | |
8881 | state = | |
8882 | vf_notify_receiver(pbi->provider_name, | |
8883 | VFRAME_EVENT_PROVIDER_QUREY_STATE, | |
8884 | NULL); | |
8885 | if ((state == RECEIVER_STATE_NULL) | |
8886 | || (state == RECEIVER_STATE_NONE)) | |
8887 | state = RECEIVER_INACTIVE; | |
8888 | } else | |
8889 | state = RECEIVER_INACTIVE; | |
8890 | ||
8891 | empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1; | |
8892 | /* error watchdog */ | |
8893 | if (empty_flag == 0) { | |
8894 | /* decoder has input */ | |
8895 | if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) { | |
8896 | ||
8897 | buf_level = READ_VREG(HEVC_STREAM_LEVEL); | |
8898 | /* receiver has no buffer to recycle */ | |
8899 | if ((state == RECEIVER_INACTIVE) && | |
8900 | (kfifo_is_empty(&pbi->display_q) && | |
8901 | buf_level > 0x200) | |
8902 | ) { | |
8903 | WRITE_VREG | |
a6c89e96 | 8904 | (HEVC_ASSIST_MBOX0_IRQ_REG, |
b9164398 NQ |
8905 | 0x1); |
8906 | } | |
8907 | } | |
8908 | ||
8909 | if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) { | |
8910 | /* receiver has no buffer to recycle */ | |
8911 | /*if ((state == RECEIVER_INACTIVE) && | |
e0614bf7 ZZ |
8912 | * (kfifo_is_empty(&pbi->display_q))) { |
8913 | *pr_info("vp9 something error,need reset\n"); | |
8914 | *} | |
8915 | */ | |
b9164398 NQ |
8916 | } |
8917 | } | |
8918 | } | |
fe96802b NQ |
8919 | #ifdef MULTI_INSTANCE_SUPPORT |
8920 | else { | |
8921 | if ( | |
8922 | (decode_timeout_val > 0) && | |
8923 | (pbi->start_process_time > 0) && | |
8924 | ((1000 * (jiffies - pbi->start_process_time) / HZ) | |
8925 | > decode_timeout_val) | |
8926 | ) { | |
8927 | int current_lcu_idx = | |
8928 | READ_VREG(HEVC_PARSER_LCU_START) | |
8929 | & 0xffffff; | |
8930 | if (pbi->last_lcu_idx == current_lcu_idx) { | |
8931 | if (pbi->decode_timeout_count > 0) | |
8932 | pbi->decode_timeout_count--; | |
8933 | if (pbi->decode_timeout_count == 0) { | |
8934 | if (input_frame_based( | |
8935 | hw_to_vdec(pbi)) || | |
8936 | (READ_VREG(HEVC_STREAM_LEVEL) > 0x200)) | |
8937 | timeout_process(pbi); | |
8938 | else { | |
8939 | vp9_print(pbi, 0, | |
8940 | "timeout & empty, again\n"); | |
8941 | dec_again_process(pbi); | |
8942 | } | |
8943 | } | |
8944 | } else { | |
8945 | start_process_time(pbi); | |
8946 | pbi->last_lcu_idx = current_lcu_idx; | |
8947 | } | |
8948 | } | |
8949 | } | |
8950 | #endif | |
8951 | ||
8952 | if ((pbi->ucode_pause_pos != 0) && | |
8953 | (pbi->ucode_pause_pos != 0xffffffff) && | |
8954 | udebug_pause_pos != pbi->ucode_pause_pos) { | |
8955 | pbi->ucode_pause_pos = 0; | |
8956 | WRITE_HREG(DEBUG_REG1, 0); | |
8957 | } | |
8958 | #ifdef MULTI_INSTANCE_SUPPORT | |
8959 | if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) { | |
8960 | pr_info( | |
8961 | "Force Send Again\r\n"); | |
8962 | debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN; | |
8963 | reset_process_time(pbi); | |
8964 | pbi->dec_result = DEC_RESULT_AGAIN; | |
8965 | if (pbi->process_state == | |
8966 | PROC_STATE_DECODESLICE) { | |
b7706e1e | 8967 | if (pbi->mmu_enable) |
8968 | vp9_recycle_mmu_buf(pbi); | |
fe96802b NQ |
8969 | pbi->process_state = |
8970 | PROC_STATE_SENDAGAIN; | |
8971 | } | |
8972 | amhevc_stop(); | |
b9164398 | 8973 | |
fe96802b | 8974 | vdec_schedule_work(&pbi->work); |
b9164398 NQ |
8975 | } |
8976 | ||
fe96802b NQ |
8977 | if (debug & VP9_DEBUG_DUMP_DATA) { |
8978 | debug &= ~VP9_DEBUG_DUMP_DATA; | |
8979 | vp9_print(pbi, 0, | |
8980 | "%s: chunk size 0x%x off 0x%x sum 0x%x\n", | |
8981 | __func__, | |
8982 | pbi->chunk->size, | |
8983 | pbi->chunk->offset, | |
8984 | get_data_check_sum(pbi, pbi->chunk->size) | |
8985 | ); | |
8986 | dump_data(pbi, pbi->chunk->size); | |
8987 | } | |
8988 | #endif | |
b9164398 NQ |
8989 | if (debug & VP9_DEBUG_DUMP_PIC_LIST) { |
8990 | dump_pic_list(pbi); | |
8991 | debug &= ~VP9_DEBUG_DUMP_PIC_LIST; | |
8992 | } | |
8993 | if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) { | |
a6c89e96 | 8994 | WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1); |
b9164398 NQ |
8995 | debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC; |
8996 | } | |
8997 | /*if (debug & VP9_DEBUG_HW_RESET) { | |
8998 | }*/ | |
b9164398 NQ |
8999 | |
9000 | if (radr != 0) { | |
9001 | if (rval != 0) { | |
9002 | WRITE_VREG(radr, rval); | |
9003 | pr_info("WRITE_VREG(%x,%x)\n", radr, rval); | |
9004 | } else | |
9005 | pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr)); | |
9006 | rval = 0; | |
9007 | radr = 0; | |
9008 | } | |
9009 | if (pop_shorts != 0) { | |
9010 | int i; | |
9011 | u32 sum = 0; | |
e0614bf7 | 9012 | |
b9164398 NQ |
9013 | pr_info("pop stream 0x%x shorts\r\n", pop_shorts); |
9014 | for (i = 0; i < pop_shorts; i++) { | |
9015 | u32 data = | |
9016 | (READ_HREG(HEVC_SHIFTED_DATA) >> 16); | |
9017 | WRITE_HREG(HEVC_SHIFT_COMMAND, | |
9018 | (1<<7)|16); | |
9019 | if ((i & 0xf) == 0) | |
9020 | pr_info("%04x:", i); | |
9021 | pr_info("%04x ", data); | |
9022 | if (((i + 1) & 0xf) == 0) | |
9023 | pr_info("\r\n"); | |
9024 | sum += data; | |
9025 | } | |
9026 | pr_info("\r\nsum = %x\r\n", sum); | |
9027 | pop_shorts = 0; | |
9028 | } | |
9029 | if (dbg_cmd != 0) { | |
9030 | if (dbg_cmd == 1) { | |
9031 | u32 disp_laddr; | |
e0614bf7 | 9032 | |
63e810c0 | 9033 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB && |
fe96802b | 9034 | get_double_write_mode(pbi) == 0) { |
b9164398 NQ |
9035 | disp_laddr = |
9036 | READ_VCBUS_REG(AFBC_BODY_BADDR) << 4; | |
9037 | } else { | |
9038 | struct canvas_s cur_canvas; | |
e0614bf7 | 9039 | |
b9164398 NQ |
9040 | canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0) |
9041 | & 0xff), &cur_canvas); | |
9042 | disp_laddr = cur_canvas.addr; | |
9043 | } | |
9044 | pr_info("current displayed buffer address %x\r\n", | |
9045 | disp_laddr); | |
9046 | } | |
9047 | dbg_cmd = 0; | |
9048 | } | |
9049 | /*don't changed at start.*/ | |
95375c25 CG |
9050 | if (pbi->get_frame_dur && pbi->show_frame_num > 60 && |
9051 | pbi->frame_dur > 0 && pbi->saved_resolution != | |
9052 | frame_width * frame_height * | |
9053 | (96000 / pbi->frame_dur)) | |
c8ed76ed | 9054 | vdec_schedule_work(&pbi->set_clk_work); |
b9164398 NQ |
9055 | |
9056 | timer->expires = jiffies + PUT_INTERVAL; | |
9057 | add_timer(timer); | |
9058 | } | |
9059 | ||
9060 | ||
fe96802b | 9061 | int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) |
b9164398 | 9062 | { |
c23e8aee HZ |
9063 | struct VP9Decoder_s *vp9 = |
9064 | (struct VP9Decoder_s *)vdec->private; | |
70809fec | 9065 | |
9b670a2d | 9066 | if (!vp9) |
70809fec NQ |
9067 | return -1; |
9068 | ||
fe96802b NQ |
9069 | vstatus->frame_width = frame_width; |
9070 | vstatus->frame_height = frame_height; | |
9071 | if (vp9->frame_dur != 0) | |
4cd99df0 | 9072 | vstatus->frame_rate = ((96000 * 10 / vp9->frame_dur) % 10) < 5 ? |
9073 | 96000 / vp9->frame_dur : (96000 / vp9->frame_dur +1); | |
b9164398 | 9074 | else |
fe96802b | 9075 | vstatus->frame_rate = -1; |
b9164398 | 9076 | vstatus->error_count = 0; |
fe96802b NQ |
9077 | vstatus->status = vp9->stat | vp9->fatal_error; |
9078 | vstatus->frame_dur = vp9->frame_dur; | |
cc41710a | 9079 | vstatus->bit_rate = vp9->gvs->bit_rate; |
9080 | vstatus->frame_data = vp9->gvs->frame_data; | |
9081 | vstatus->total_data = vp9->gvs->total_data; | |
9082 | vstatus->frame_count = vp9->gvs->frame_count; | |
9083 | vstatus->error_frame_count = vp9->gvs->error_frame_count; | |
9084 | vstatus->drop_frame_count = vp9->gvs->drop_frame_count; | |
4cd99df0 | 9085 | vstatus->i_decoded_frames = vp9->gvs->i_decoded_frames; |
9086 | vstatus->i_lost_frames = vp9->gvs->i_lost_frames; | |
9087 | vstatus->i_concealed_frames = vp9->gvs->i_concealed_frames; | |
9088 | vstatus->p_decoded_frames = vp9->gvs->p_decoded_frames; | |
9089 | vstatus->p_lost_frames = vp9->gvs->p_lost_frames; | |
9090 | vstatus->p_concealed_frames = vp9->gvs->p_concealed_frames; | |
9091 | vstatus->b_decoded_frames = vp9->gvs->b_decoded_frames; | |
9092 | vstatus->b_lost_frames = vp9->gvs->b_lost_frames; | |
9093 | vstatus->b_concealed_frames = vp9->gvs->b_concealed_frames; | |
cc41710a | 9094 | vstatus->total_data = vp9->gvs->total_data; |
9095 | vstatus->samp_cnt = vp9->gvs->samp_cnt; | |
9096 | vstatus->offset = vp9->gvs->offset; | |
fe96802b NQ |
9097 | snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), |
9098 | "%s", DRIVER_NAME); | |
b9164398 NQ |
9099 | return 0; |
9100 | } | |
9101 | ||
d481db31 NQ |
9102 | int vvp9_set_isreset(struct vdec_s *vdec, int isreset) |
9103 | { | |
9104 | is_reset = isreset; | |
9105 | return 0; | |
9106 | } | |
9107 | ||
b9164398 NQ |
9108 | #if 0 |
9109 | static void VP9_DECODE_INIT(void) | |
9110 | { | |
9111 | /* enable vp9 clocks */ | |
9112 | WRITE_VREG(DOS_GCLK_EN3, 0xffffffff); | |
9113 | /* *************************************************************** */ | |
9114 | /* Power ON HEVC */ | |
9115 | /* *************************************************************** */ | |
9116 | /* Powerup HEVC */ | |
9117 | WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0, | |
9118 | READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6))); | |
9119 | WRITE_VREG(DOS_MEM_PD_HEVC, 0x0); | |
9120 | WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2)); | |
9121 | WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2))); | |
9122 | /* remove isolations */ | |
9123 | WRITE_VREG(AO_RTI_GEN_PWR_ISO0, | |
9124 | READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10))); | |
9125 | ||
9126 | } | |
9127 | #endif | |
9128 | ||
a6c89e96 | 9129 | static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask) |
b9164398 NQ |
9130 | { |
9131 | unsigned int data32; | |
9132 | /* VP9_DECODE_INIT(); */ | |
a6c89e96 NQ |
9133 | vp9_config_work_space_hw(pbi, mask); |
9134 | if (mask & HW_MASK_BACK) | |
9135 | init_pic_list_hw(pbi); | |
b9164398 | 9136 | |
a6c89e96 | 9137 | vp9_init_decoder_hw(pbi, mask); |
b9164398 NQ |
9138 | |
9139 | #ifdef VP9_LPF_LVL_UPDATE | |
a6c89e96 NQ |
9140 | if (mask & HW_MASK_BACK) |
9141 | vp9_loop_filter_init(pbi); | |
b9164398 NQ |
9142 | #endif |
9143 | ||
a6c89e96 NQ |
9144 | if ((mask & HW_MASK_FRONT) == 0) |
9145 | return; | |
b9164398 | 9146 | #if 1 |
fe96802b NQ |
9147 | if (debug & VP9_DEBUG_BUFMGR_MORE) |
9148 | pr_info("%s\n", __func__); | |
b9164398 NQ |
9149 | data32 = READ_VREG(HEVC_STREAM_CONTROL); |
9150 | data32 = data32 | | |
9151 | (1 << 0)/*stream_fetch_enable*/ | |
9152 | ; | |
9153 | WRITE_VREG(HEVC_STREAM_CONTROL, data32); | |
a6c89e96 | 9154 | |
63e810c0 | 9155 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { |
a6c89e96 NQ |
9156 | if (debug & VP9_DEBUG_BUFMGR) |
9157 | pr_info("[test.c] Config STREAM_FIFO_CTL\n"); | |
9158 | data32 = READ_VREG(HEVC_STREAM_FIFO_CTL); | |
9159 | data32 = data32 | | |
9160 | (1 << 29) // stream_fifo_hole | |
9161 | ; | |
9162 | WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32); | |
9163 | } | |
b9164398 NQ |
9164 | #if 0 |
9165 | data32 = READ_VREG(HEVC_SHIFT_STARTCODE); | |
9166 | if (data32 != 0x00000100) { | |
9167 | pr_info("vp9 prot init error %d\n", __LINE__); | |
9168 | return; | |
9169 | } | |
9170 | data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); | |
9171 | if (data32 != 0x00000300) { | |
9172 | pr_info("vp9 prot init error %d\n", __LINE__); | |
9173 | return; | |
9174 | } | |
9175 | WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678); | |
9176 | WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0); | |
9177 | data32 = READ_VREG(HEVC_SHIFT_STARTCODE); | |
9178 | if (data32 != 0x12345678) { | |
9179 | pr_info("vp9 prot init error %d\n", __LINE__); | |
9180 | return; | |
9181 | } | |
9182 | data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); | |
9183 | if (data32 != 0x9abcdef0) { | |
9184 | pr_info("vp9 prot init error %d\n", __LINE__); | |
9185 | return; | |
9186 | } | |
9187 | #endif | |
9188 | WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001); | |
9189 | WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300); | |
9190 | #endif | |
9191 | ||
9192 | ||
9193 | ||
9194 | WRITE_VREG(HEVC_WAIT_FLAG, 1); | |
9195 | ||
9196 | /* WRITE_VREG(HEVC_MPSR, 1); */ | |
9197 | ||
9198 | /* clear mailbox interrupt */ | |
a6c89e96 | 9199 | WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1); |
b9164398 NQ |
9200 | |
9201 | /* enable mailbox interrupt */ | |
a6c89e96 | 9202 | WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1); |
b9164398 NQ |
9203 | |
9204 | /* disable PSCALE for hardware sharing */ | |
9205 | WRITE_VREG(HEVC_PSCALE_CTRL, 0); | |
9206 | ||
fe96802b | 9207 | WRITE_VREG(DEBUG_REG1, 0x0); |
b9164398 NQ |
9208 | /*check vps/sps/pps/i-slice in ucode*/ |
9209 | WRITE_VREG(NAL_SEARCH_CTL, 0x8); | |
9210 | ||
fe96802b | 9211 | WRITE_VREG(DECODE_STOP_POS, udebug_flag); |
a6c89e96 NQ |
9212 | #ifdef SUPPORT_FB_DECODING |
9213 | #ifndef FB_DECODING_TEST_SCHEDULE | |
9214 | if (pbi->used_stage_buf_num > 0) { | |
9215 | if (mask & HW_MASK_FRONT) { | |
9216 | data32 = READ_VREG( | |
9217 | HEVC_ASSIST_HED_FB_W_CTL); | |
9218 | data32 = data32 | | |
9219 | (1 << 0) /*hed_fb_wr_en*/ | |
9220 | ; | |
9221 | WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL, | |
9222 | data32); | |
9223 | } | |
9224 | if (mask & HW_MASK_BACK) { | |
9225 | data32 = READ_VREG( | |
9226 | HEVC_ASSIST_HED_FB_R_CTL); | |
9227 | while (data32 & (1 << 7)) { | |
9228 | /*wait finish*/ | |
9229 | data32 = READ_VREG( | |
9230 | HEVC_ASSIST_HED_FB_R_CTL); | |
9231 | } | |
9232 | data32 &= (~(0x1 << 0)); | |
9233 | /*hed_fb_rd_addr_auto_rd*/ | |
9234 | data32 &= (~(0x1 << 1)); | |
9235 | /*rd_id = 0, hed_rd_map_auto_halt_num, | |
9236 | after wr 2 ready, then start reading*/ | |
9237 | data32 |= (0x2 << 16); | |
9238 | WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL, | |
9239 | data32); | |
9240 | ||
9241 | data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/ | |
9242 | data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/ | |
9243 | data32 |= (0x1 << 0); /*hed_fb_rd_en*/ | |
9244 | WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL, | |
9245 | data32); | |
9246 | } | |
b9164398 | 9247 | |
a6c89e96 NQ |
9248 | } |
9249 | #endif | |
9250 | #endif | |
b9164398 NQ |
9251 | } |
9252 | ||
9253 | static int vvp9_local_init(struct VP9Decoder_s *pbi) | |
9254 | { | |
9255 | int i; | |
9256 | int ret; | |
9257 | int width, height; | |
fe96802b NQ |
9258 | if (alloc_lf_buf(pbi) < 0) |
9259 | return -1; | |
9260 | ||
9261 | pbi->gvs = vzalloc(sizeof(struct vdec_info)); | |
9262 | if (NULL == pbi->gvs) { | |
9263 | pr_info("the struct of vdec status malloc failed.\n"); | |
9264 | return -1; | |
9265 | } | |
cc41710a | 9266 | vdec_set_vframe_comm(hw_to_vdec(pbi), DRIVER_NAME); |
b9164398 NQ |
9267 | #ifdef DEBUG_PTS |
9268 | pbi->pts_missed = 0; | |
9269 | pbi->pts_hit = 0; | |
9270 | #endif | |
9271 | pbi->new_frame_displayed = 0; | |
9272 | pbi->last_put_idx = -1; | |
9273 | pbi->saved_resolution = 0; | |
9274 | pbi->get_frame_dur = false; | |
9275 | on_no_keyframe_skiped = 0; | |
c20e6c85 | 9276 | pbi->duration_from_pts_done = 0; |
9277 | pbi->vp9_first_pts_ready = 0; | |
9278 | pbi->frame_cnt_window = 0; | |
b9164398 NQ |
9279 | width = pbi->vvp9_amstream_dec_info.width; |
9280 | height = pbi->vvp9_amstream_dec_info.height; | |
9281 | pbi->frame_dur = | |
9282 | (pbi->vvp9_amstream_dec_info.rate == | |
c20e6c85 | 9283 | 0) ? 3200 : pbi->vvp9_amstream_dec_info.rate; |
b9164398 NQ |
9284 | if (width && height) |
9285 | pbi->frame_ar = height * 0x100 / width; | |
9286 | /* | |
e0614bf7 ZZ |
9287 | *TODO:FOR VERSION |
9288 | */ | |
b9164398 NQ |
9289 | pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version, |
9290 | 0, width, height, pbi->frame_dur); | |
9291 | ||
9292 | if (pbi->frame_dur == 0) | |
9293 | pbi->frame_dur = 96000 / 24; | |
9294 | ||
9295 | INIT_KFIFO(pbi->display_q); | |
9296 | INIT_KFIFO(pbi->newframe_q); | |
9297 | ||
9298 | ||
9299 | for (i = 0; i < VF_POOL_SIZE; i++) { | |
9300 | const struct vframe_s *vf = &pbi->vfpool[i]; | |
e0614bf7 | 9301 | |
b9164398 NQ |
9302 | pbi->vfpool[i].index = -1; |
9303 | kfifo_put(&pbi->newframe_q, vf); | |
9304 | } | |
9305 | ||
9306 | ||
9307 | ret = vp9_local_init(pbi); | |
5f2400c0 | 9308 | |
c20e6c85 | 9309 | if (!pbi->pts_unstable) { |
9310 | pbi->pts_unstable = | |
9311 | (pbi->vvp9_amstream_dec_info.rate == 0)?1:0; | |
9312 | pr_info("set pts unstable\n"); | |
9313 | } | |
5f2400c0 | 9314 | |
b9164398 NQ |
9315 | return ret; |
9316 | } | |
9317 | ||
c23e8aee HZ |
9318 | |
9319 | #ifdef MULTI_INSTANCE_SUPPORT | |
9320 | static s32 vvp9_init(struct vdec_s *vdec) | |
9321 | { | |
9322 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private; | |
9323 | #else | |
b9164398 NQ |
9324 | static s32 vvp9_init(struct VP9Decoder_s *pbi) |
9325 | { | |
c23e8aee | 9326 | #endif |
668e656d | 9327 | int ret; |
6fff1c64 NQ |
9328 | int fw_size = 0x1000 * 16; |
9329 | struct firmware_s *fw = NULL; | |
b9164398 | 9330 | |
b9164398 | 9331 | pbi->stat |= STAT_TIMER_INIT; |
668e656d | 9332 | |
6fff1c64 | 9333 | if (vvp9_local_init(pbi) < 0) |
b9164398 | 9334 | return -EBUSY; |
6fff1c64 NQ |
9335 | |
9336 | fw = vmalloc(sizeof(struct firmware_s) + fw_size); | |
9337 | if (IS_ERR_OR_NULL(fw)) | |
9338 | return -ENOMEM; | |
72a7ad35 | 9339 | |
668e656d | 9340 | if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) { |
6fff1c64 NQ |
9341 | pr_err("get firmware fail.\n"); |
9342 | vfree(fw); | |
9343 | return -1; | |
b9164398 NQ |
9344 | } |
9345 | ||
6fff1c64 NQ |
9346 | fw->len = fw_size; |
9347 | ||
668e656d NQ |
9348 | INIT_WORK(&pbi->set_clk_work, vp9_set_clk); |
9349 | init_timer(&pbi->timer); | |
9350 | ||
b9164398 NQ |
9351 | #ifdef MULTI_INSTANCE_SUPPORT |
9352 | if (pbi->m_ins_flag) { | |
9353 | pbi->timer.data = (ulong) pbi; | |
9354 | pbi->timer.function = vvp9_put_timer_func; | |
9355 | pbi->timer.expires = jiffies + PUT_INTERVAL; | |
9356 | ||
c23e8aee | 9357 | /*add_timer(&pbi->timer); |
b9164398 NQ |
9358 | |
9359 | pbi->stat |= STAT_TIMER_ARM; | |
c23e8aee | 9360 | pbi->stat |= STAT_ISR_REG;*/ |
b9164398 NQ |
9361 | |
9362 | INIT_WORK(&pbi->work, vp9_work); | |
dc4a2edc | 9363 | INIT_WORK(&pbi->recycle_mmu_work, vp9_recycle_mmu_work); |
a6c89e96 NQ |
9364 | #ifdef SUPPORT_FB_DECODING |
9365 | if (pbi->used_stage_buf_num > 0) | |
9366 | INIT_WORK(&pbi->s1_work, vp9_s1_work); | |
9367 | #endif | |
6fff1c64 NQ |
9368 | pbi->fw = fw; |
9369 | ||
2cd6815e NQ |
9370 | /* picture list init.*/ |
9371 | pbi->dec_result = DEC_INIT_PICLIST; | |
9372 | vdec_schedule_work(&pbi->work); | |
9373 | ||
b9164398 NQ |
9374 | return 0; |
9375 | } | |
9376 | #endif | |
b9164398 | 9377 | amhevc_enable(); |
e0614bf7 | 9378 | |
ed867a7b NQ |
9379 | init_pic_list(pbi); |
9380 | ||
668e656d | 9381 | ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data); |
f47294da | 9382 | if (ret < 0) { |
b9164398 | 9383 | amhevc_disable(); |
6fff1c64 | 9384 | vfree(fw); |
668e656d NQ |
9385 | pr_err("VP9: the %s fw loading failed, err: %x\n", |
9386 | tee_enabled() ? "TEE" : "local", ret); | |
b9164398 NQ |
9387 | return -EBUSY; |
9388 | } | |
9389 | ||
6fff1c64 | 9390 | vfree(fw); |
b9164398 NQ |
9391 | |
9392 | pbi->stat |= STAT_MC_LOAD; | |
9393 | ||
9394 | /* enable AMRISC side protocol */ | |
a6c89e96 | 9395 | vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); |
b9164398 | 9396 | |
a6c89e96 | 9397 | if (vdec_request_threaded_irq(VDEC_IRQ_0, |
b9164398 NQ |
9398 | vvp9_isr, |
9399 | vvp9_isr_thread_fn, | |
9400 | IRQF_ONESHOT,/*run thread on this irq disabled*/ | |
9401 | "vvp9-irq", (void *)pbi)) { | |
9402 | pr_info("vvp9 irq register error.\n"); | |
9403 | amhevc_disable(); | |
9404 | return -ENOENT; | |
9405 | } | |
9406 | ||
9407 | pbi->stat |= STAT_ISR_REG; | |
9408 | ||
9409 | pbi->provider_name = PROVIDER_NAME; | |
c23e8aee HZ |
9410 | #ifdef MULTI_INSTANCE_SUPPORT |
9411 | vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, | |
9412 | &vvp9_vf_provider, pbi); | |
9413 | vf_reg_provider(&vvp9_vf_prov); | |
9414 | vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); | |
9415 | if (pbi->frame_dur != 0) { | |
9416 | if (!is_reset) | |
9417 | vf_notify_receiver(pbi->provider_name, | |
9418 | VFRAME_EVENT_PROVIDER_FR_HINT, | |
9419 | (void *) | |
9420 | ((unsigned long)pbi->frame_dur)); | |
9421 | } | |
9422 | #else | |
b9164398 NQ |
9423 | vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider, |
9424 | pbi); | |
9425 | vf_reg_provider(&vvp9_vf_prov); | |
9426 | vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); | |
d481db31 NQ |
9427 | if (!is_reset) |
9428 | vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT, | |
9429 | (void *)((unsigned long)pbi->frame_dur)); | |
c23e8aee | 9430 | #endif |
b9164398 NQ |
9431 | pbi->stat |= STAT_VF_HOOK; |
9432 | ||
9433 | pbi->timer.data = (ulong)pbi; | |
9434 | pbi->timer.function = vvp9_put_timer_func; | |
9435 | pbi->timer.expires = jiffies + PUT_INTERVAL; | |
9436 | ||
ca482a9c | 9437 | pbi->stat |= STAT_VDEC_RUN; |
b9164398 NQ |
9438 | |
9439 | add_timer(&pbi->timer); | |
9440 | ||
9441 | pbi->stat |= STAT_TIMER_ARM; | |
9442 | ||
b9164398 NQ |
9443 | amhevc_start(); |
9444 | ||
b9164398 NQ |
9445 | pbi->init_flag = 1; |
9446 | pbi->process_busy = 0; | |
9447 | pr_info("%d, vvp9_init, RP=0x%x\n", | |
9448 | __LINE__, READ_VREG(HEVC_STREAM_RD_PTR)); | |
9449 | return 0; | |
9450 | } | |
9451 | ||
c23e8aee HZ |
9452 | static int vmvp9_stop(struct VP9Decoder_s *pbi) |
9453 | { | |
9454 | pbi->init_flag = 0; | |
9455 | ||
976f3376 HZ |
9456 | if (pbi->stat & STAT_VDEC_RUN) { |
9457 | amhevc_stop(); | |
9458 | pbi->stat &= ~STAT_VDEC_RUN; | |
9459 | } | |
9460 | if (pbi->stat & STAT_ISR_REG) { | |
9461 | vdec_free_irq(VDEC_IRQ_0, (void *)pbi); | |
9462 | pbi->stat &= ~STAT_ISR_REG; | |
9463 | } | |
c23e8aee HZ |
9464 | if (pbi->stat & STAT_TIMER_ARM) { |
9465 | del_timer_sync(&pbi->timer); | |
9466 | pbi->stat &= ~STAT_TIMER_ARM; | |
9467 | } | |
9468 | ||
9469 | if (pbi->stat & STAT_VF_HOOK) { | |
9470 | if (!is_reset) | |
9471 | vf_notify_receiver(pbi->provider_name, | |
9472 | VFRAME_EVENT_PROVIDER_FR_END_HINT, | |
9473 | NULL); | |
9474 | ||
9475 | vf_unreg_provider(&vvp9_vf_prov); | |
9476 | pbi->stat &= ~STAT_VF_HOOK; | |
9477 | } | |
9478 | vp9_local_uninit(pbi); | |
9479 | reset_process_time(pbi); | |
9480 | cancel_work_sync(&pbi->work); | |
dc4a2edc | 9481 | cancel_work_sync(&pbi->recycle_mmu_work); |
a6c89e96 NQ |
9482 | #ifdef SUPPORT_FB_DECODING |
9483 | if (pbi->used_stage_buf_num > 0) | |
9484 | cancel_work_sync(&pbi->s1_work); | |
9485 | #endif | |
a994f6d6 | 9486 | cancel_work_sync(&pbi->set_clk_work); |
c23e8aee | 9487 | uninit_mmu_buffers(pbi); |
df9574f9 HZ |
9488 | if (pbi->fw) |
9489 | vfree(pbi->fw); | |
9490 | pbi->fw = NULL; | |
c23e8aee HZ |
9491 | return 0; |
9492 | } | |
9493 | ||
b9164398 NQ |
9494 | static int vvp9_stop(struct VP9Decoder_s *pbi) |
9495 | { | |
9496 | ||
9497 | pbi->init_flag = 0; | |
ca482a9c | 9498 | pbi->first_sc_checked = 0; |
b9164398 NQ |
9499 | if (pbi->stat & STAT_VDEC_RUN) { |
9500 | amhevc_stop(); | |
9501 | pbi->stat &= ~STAT_VDEC_RUN; | |
9502 | } | |
9503 | ||
9504 | if (pbi->stat & STAT_ISR_REG) { | |
fe96802b NQ |
9505 | #ifdef MULTI_INSTANCE_SUPPORT |
9506 | if (!pbi->m_ins_flag) | |
9507 | #endif | |
a6c89e96 NQ |
9508 | WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0); |
9509 | vdec_free_irq(VDEC_IRQ_0, (void *)pbi); | |
b9164398 NQ |
9510 | pbi->stat &= ~STAT_ISR_REG; |
9511 | } | |
9512 | ||
9513 | if (pbi->stat & STAT_TIMER_ARM) { | |
9514 | del_timer_sync(&pbi->timer); | |
9515 | pbi->stat &= ~STAT_TIMER_ARM; | |
9516 | } | |
9517 | ||
9518 | if (pbi->stat & STAT_VF_HOOK) { | |
d481db31 NQ |
9519 | if (!is_reset) |
9520 | vf_notify_receiver(pbi->provider_name, | |
9521 | VFRAME_EVENT_PROVIDER_FR_END_HINT, | |
9522 | NULL); | |
b9164398 NQ |
9523 | |
9524 | vf_unreg_provider(&vvp9_vf_prov); | |
9525 | pbi->stat &= ~STAT_VF_HOOK; | |
9526 | } | |
9527 | vp9_local_uninit(pbi); | |
9528 | ||
c8ed76ed | 9529 | cancel_work_sync(&pbi->set_clk_work); |
b9164398 | 9530 | #ifdef MULTI_INSTANCE_SUPPORT |
a6c89e96 | 9531 | if (pbi->m_ins_flag) { |
a6c89e96 NQ |
9532 | #ifdef SUPPORT_FB_DECODING |
9533 | if (pbi->used_stage_buf_num > 0) | |
9534 | cancel_work_sync(&pbi->s1_work); | |
9535 | #endif | |
c8ed76ed | 9536 | cancel_work_sync(&pbi->work); |
dc4a2edc | 9537 | cancel_work_sync(&pbi->recycle_mmu_work); |
a6c89e96 | 9538 | } else |
b9164398 | 9539 | amhevc_disable(); |
b9164398 NQ |
9540 | #else |
9541 | amhevc_disable(); | |
9542 | #endif | |
9543 | uninit_mmu_buffers(pbi); | |
9544 | ||
6fff1c64 NQ |
9545 | vfree(pbi->fw); |
9546 | pbi->fw = NULL; | |
b9164398 NQ |
9547 | return 0; |
9548 | } | |
b9164398 NQ |
9549 | static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi) |
9550 | { | |
fe96802b NQ |
9551 | int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ? |
9552 | CODEC_MM_FLAGS_TVP : 0; | |
0be1523d | 9553 | int buf_size = 48; |
ca482a9c | 9554 | |
976f3376 HZ |
9555 | if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) && |
9556 | (pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) { | |
0be1523d | 9557 | buf_size = 12; |
976f3376 HZ |
9558 | } else if ((pbi->max_pic_w * pbi->max_pic_h > 0) && |
9559 | (pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) { | |
9560 | buf_size = 4; | |
b9164398 | 9561 | } |
ca482a9c HZ |
9562 | pbi->need_cache_size = buf_size * SZ_1M; |
9563 | pbi->sc_start_time = get_jiffies_64(); | |
6276f4ff | 9564 | if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) { |
b7706e1e | 9565 | pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME, |
9566 | pbi->index, FRAME_BUFFERS, | |
ca482a9c | 9567 | pbi->need_cache_size, |
b7706e1e | 9568 | tvp_flag |
9569 | ); | |
9570 | if (!pbi->mmu_box) { | |
9571 | pr_err("vp9 alloc mmu box failed!!\n"); | |
9572 | return -1; | |
9573 | } | |
a6c89e96 | 9574 | } |
b9164398 NQ |
9575 | pbi->bmmu_box = decoder_bmmu_box_alloc_box( |
9576 | DRIVER_NAME, | |
9577 | pbi->index, | |
9578 | MAX_BMMU_BUFFER_NUM, | |
9579 | 4 + PAGE_SHIFT, | |
9580 | CODEC_MM_FLAGS_CMA_CLEAR | | |
fe96802b NQ |
9581 | CODEC_MM_FLAGS_FOR_VDECODER | |
9582 | tvp_flag); | |
b9164398 NQ |
9583 | if (!pbi->bmmu_box) { |
9584 | pr_err("vp9 alloc bmmu box failed!!\n"); | |
9585 | return -1; | |
9586 | } | |
9587 | return 0; | |
9588 | } | |
a674e3cd | 9589 | |
9590 | static struct VP9Decoder_s *gHevc; | |
9591 | ||
b9164398 NQ |
9592 | static int amvdec_vp9_probe(struct platform_device *pdev) |
9593 | { | |
9594 | struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; | |
9595 | struct BUF_s BUF[MAX_BUF_NUM]; | |
a674e3cd | 9596 | struct VP9Decoder_s *pbi; |
fe96802b NQ |
9597 | int ret; |
9598 | #ifndef MULTI_INSTANCE_SUPPORT | |
9599 | int i; | |
9600 | #endif | |
5b851ff9 | 9601 | pr_debug("%s\n", __func__); |
a6c89e96 | 9602 | |
b9164398 | 9603 | mutex_lock(&vvp9_mutex); |
a674e3cd | 9604 | pbi = vmalloc(sizeof(struct VP9Decoder_s)); |
9605 | if (pbi == NULL) { | |
9606 | pr_info("\namvdec_vp9 device data allocation failed\n"); | |
9607 | mutex_unlock(&vvp9_mutex); | |
9608 | return -ENOMEM; | |
9609 | } | |
b9164398 | 9610 | |
a674e3cd | 9611 | gHevc = pbi; |
b9164398 | 9612 | memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); |
a674e3cd | 9613 | memset(pbi, 0, sizeof(struct VP9Decoder_s)); |
b9164398 NQ |
9614 | memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); |
9615 | ||
9616 | pbi->init_flag = 0; | |
ca482a9c | 9617 | pbi->first_sc_checked= 0; |
6f5ee885 | 9618 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
df841122 | 9619 | vp9_max_pic_w = 8192; |
9620 | vp9_max_pic_h = 4608; | |
df841122 | 9621 | } |
a6c89e96 NQ |
9622 | pbi->max_pic_w = vp9_max_pic_w; |
9623 | pbi->max_pic_h = vp9_max_pic_h; | |
fe96802b NQ |
9624 | |
9625 | #ifdef MULTI_INSTANCE_SUPPORT | |
9626 | pbi->eos = 0; | |
9627 | pbi->start_process_time = 0; | |
9628 | pbi->timeout_num = 0; | |
9629 | #endif | |
b9164398 NQ |
9630 | pbi->fatal_error = 0; |
9631 | pbi->show_frame_num = 0; | |
9632 | if (pdata == NULL) { | |
9633 | pr_info("\namvdec_vp9 memory resource undefined.\n"); | |
a674e3cd | 9634 | vfree(pbi); |
b9164398 NQ |
9635 | mutex_unlock(&vvp9_mutex); |
9636 | return -EFAULT; | |
9637 | } | |
9638 | pbi->m_ins_flag = 0; | |
9639 | #ifdef MULTI_INSTANCE_SUPPORT | |
fe96802b NQ |
9640 | pbi->platform_dev = pdev; |
9641 | platform_set_drvdata(pdev, pdata); | |
b9164398 | 9642 | #endif |
b7706e1e | 9643 | pbi->double_write_mode = double_write_mode; |
6276f4ff | 9644 | pbi->mmu_enable = 1; |
b9164398 | 9645 | if (amvdec_vp9_mmu_init(pbi) < 0) { |
a674e3cd | 9646 | vfree(pbi); |
fe96802b | 9647 | mutex_unlock(&vvp9_mutex); |
b9164398 NQ |
9648 | pr_err("vp9 alloc bmmu box failed!!\n"); |
9649 | return -1; | |
9650 | } | |
fe96802b NQ |
9651 | |
9652 | ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID, | |
9653 | work_buf_size, DRIVER_NAME, &pdata->mem_start); | |
9654 | if (ret < 0) { | |
9655 | uninit_mmu_buffers(pbi); | |
a674e3cd | 9656 | vfree(pbi); |
fe96802b NQ |
9657 | mutex_unlock(&vvp9_mutex); |
9658 | return ret; | |
9659 | } | |
9660 | pbi->buf_size = work_buf_size; | |
9661 | ||
9662 | #ifdef MULTI_INSTANCE_SUPPORT | |
9663 | pbi->buf_start = pdata->mem_start; | |
9664 | #else | |
b7706e1e | 9665 | if (!pbi->mmu_enable) |
9666 | pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size; | |
9667 | ||
fe96802b NQ |
9668 | for (i = 0; i < WORK_BUF_SPEC_NUM; i++) |
9669 | amvvp9_workbuff_spec[i].start_adr = pdata->mem_start; | |
9670 | #endif | |
9671 | ||
9672 | ||
b9164398 | 9673 | if (debug) { |
fe96802b NQ |
9674 | pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n", |
9675 | pdata->mem_start, pbi->buf_size); | |
b9164398 NQ |
9676 | } |
9677 | ||
9678 | if (pdata->sys_info) | |
9679 | pbi->vvp9_amstream_dec_info = *pdata->sys_info; | |
9680 | else { | |
9681 | pbi->vvp9_amstream_dec_info.width = 0; | |
9682 | pbi->vvp9_amstream_dec_info.height = 0; | |
9683 | pbi->vvp9_amstream_dec_info.rate = 30; | |
9684 | } | |
0eb79ad7 | 9685 | pbi->no_head = no_head; |
b9164398 NQ |
9686 | #ifdef MULTI_INSTANCE_SUPPORT |
9687 | pbi->cma_dev = pdata->cma_dev; | |
9688 | #else | |
9689 | cma_dev = pdata->cma_dev; | |
9690 | #endif | |
c23e8aee HZ |
9691 | |
9692 | #ifdef MULTI_INSTANCE_SUPPORT | |
9693 | pdata->private = pbi; | |
b9164398 | 9694 | pdata->dec_status = vvp9_dec_status; |
d481db31 NQ |
9695 | pdata->set_isreset = vvp9_set_isreset; |
9696 | is_reset = 0; | |
c23e8aee HZ |
9697 | if (vvp9_init(pdata) < 0) { |
9698 | #else | |
b9164398 | 9699 | if (vvp9_init(pbi) < 0) { |
c23e8aee | 9700 | #endif |
b9164398 NQ |
9701 | pr_info("\namvdec_vp9 init failed.\n"); |
9702 | vp9_local_uninit(pbi); | |
fe96802b | 9703 | uninit_mmu_buffers(pbi); |
a674e3cd | 9704 | vfree(pbi); |
9b670a2d | 9705 | pdata->dec_status = NULL; |
b9164398 NQ |
9706 | mutex_unlock(&vvp9_mutex); |
9707 | return -ENODEV; | |
9708 | } | |
9709 | /*set the max clk for smooth playing...*/ | |
9710 | hevc_source_changed(VFORMAT_VP9, | |
9711 | 4096, 2048, 60); | |
9712 | mutex_unlock(&vvp9_mutex); | |
9713 | ||
9714 | return 0; | |
9715 | } | |
9716 | ||
677ab50d NQ |
9717 | static void vdec_fence_release(struct VP9Decoder_s *pbi, |
9718 | struct vdec_sync *sync) | |
9719 | { | |
9720 | ulong expires; | |
9721 | int i; | |
9722 | ||
9723 | /* notify signal to wake up all fences. */ | |
9724 | vdec_timeline_increase(sync, VF_POOL_SIZE); | |
9725 | ||
9726 | expires = jiffies + msecs_to_jiffies(2000); | |
9727 | while (!check_objs_all_signaled(sync)) { | |
9728 | if (time_after(jiffies, expires)) { | |
9729 | pr_err("wait fence signaled timeout.\n"); | |
9730 | break; | |
9731 | } | |
9732 | } | |
9733 | ||
9734 | for (i = 0; i < VF_POOL_SIZE; i++) { | |
9735 | struct vframe_s *vf = &pbi->vfpool[i]; | |
9736 | ||
9737 | if (vf->fence) { | |
9738 | vdec_fence_put(vf->fence); | |
9739 | vf->fence = NULL; | |
9740 | } | |
9741 | } | |
9742 | ||
9743 | /* decreases refcnt of timeline. */ | |
9744 | vdec_timeline_put(sync); | |
9745 | } | |
9746 | ||
b9164398 NQ |
9747 | static int amvdec_vp9_remove(struct platform_device *pdev) |
9748 | { | |
a674e3cd | 9749 | struct VP9Decoder_s *pbi = gHevc; |
ed867a7b NQ |
9750 | struct vdec_s *vdec = hw_to_vdec(pbi); |
9751 | int i; | |
e0614bf7 | 9752 | |
b9164398 NQ |
9753 | if (debug) |
9754 | pr_info("amvdec_vp9_remove\n"); | |
9755 | ||
9756 | mutex_lock(&vvp9_mutex); | |
9757 | ||
9758 | vvp9_stop(pbi); | |
9759 | ||
b9164398 NQ |
9760 | hevc_source_changed(VFORMAT_VP9, 0, 0, 0); |
9761 | ||
ed867a7b NQ |
9762 | if (vdec->parallel_dec == 1) { |
9763 | for (i = 0; i < FRAME_BUFFERS; i++) { | |
9764 | vdec->free_canvas_ex(pbi->common.buffer_pool-> | |
9765 | frame_bufs[i].buf.y_canvas_index, vdec->id); | |
9766 | vdec->free_canvas_ex(pbi->common.buffer_pool-> | |
9767 | frame_bufs[i].buf.uv_canvas_index, vdec->id); | |
9768 | } | |
9769 | } | |
9770 | ||
b9164398 NQ |
9771 | #ifdef DEBUG_PTS |
9772 | pr_info("pts missed %ld, pts hit %ld, duration %d\n", | |
9773 | pbi->pts_missed, pbi->pts_hit, pbi->frame_dur); | |
9774 | #endif | |
0fb7e163 NQ |
9775 | mem_map_mode = 0; |
9776 | ||
677ab50d NQ |
9777 | if (pbi->enable_fence) |
9778 | vdec_fence_release(pbi, &vdec->sync); | |
9779 | ||
a674e3cd | 9780 | vfree(pbi); |
b9164398 NQ |
9781 | mutex_unlock(&vvp9_mutex); |
9782 | ||
9783 | return 0; | |
9784 | } | |
9785 | ||
9786 | /****************************************/ | |
1cb8d0da NQ |
9787 | #ifdef CONFIG_PM |
9788 | static int vp9_suspend(struct device *dev) | |
9789 | { | |
9790 | amhevc_suspend(to_platform_device(dev), dev->power.power_state); | |
9791 | return 0; | |
9792 | } | |
9793 | ||
9794 | static int vp9_resume(struct device *dev) | |
9795 | { | |
9796 | amhevc_resume(to_platform_device(dev)); | |
9797 | return 0; | |
9798 | } | |
9799 | ||
9800 | static const struct dev_pm_ops vp9_pm_ops = { | |
9801 | SET_SYSTEM_SLEEP_PM_OPS(vp9_suspend, vp9_resume) | |
9802 | }; | |
9803 | #endif | |
b9164398 NQ |
9804 | |
9805 | static struct platform_driver amvdec_vp9_driver = { | |
9806 | .probe = amvdec_vp9_probe, | |
9807 | .remove = amvdec_vp9_remove, | |
b9164398 NQ |
9808 | .driver = { |
9809 | .name = DRIVER_NAME, | |
1cb8d0da NQ |
9810 | #ifdef CONFIG_PM |
9811 | .pm = &vp9_pm_ops, | |
9812 | #endif | |
b9164398 NQ |
9813 | } |
9814 | }; | |
9815 | ||
9816 | static struct codec_profile_t amvdec_vp9_profile = { | |
9817 | .name = "vp9", | |
9818 | .profile = "" | |
9819 | }; | |
9820 | ||
9457f9af NQ |
9821 | static struct codec_profile_t amvdec_vp9_profile_mult; |
9822 | ||
b9164398 NQ |
9823 | static unsigned char get_data_check_sum |
9824 | (struct VP9Decoder_s *pbi, int size) | |
9825 | { | |
9826 | int jj; | |
9827 | int sum = 0; | |
7d2e7e17 NQ |
9828 | u8 *data = NULL; |
9829 | ||
9830 | if (!pbi->chunk->block->is_mapped) | |
9831 | data = codec_mm_vmap(pbi->chunk->block->start + | |
9832 | pbi->chunk->offset, size); | |
9833 | else | |
9834 | data = ((u8 *)pbi->chunk->block->start_virt) + | |
9835 | pbi->chunk->offset; | |
9836 | ||
b9164398 NQ |
9837 | for (jj = 0; jj < size; jj++) |
9838 | sum += data[jj]; | |
7d2e7e17 NQ |
9839 | |
9840 | if (!pbi->chunk->block->is_mapped) | |
9841 | codec_mm_unmap_phyaddr(data); | |
b9164398 NQ |
9842 | return sum; |
9843 | } | |
9844 | ||
9845 | static void dump_data(struct VP9Decoder_s *pbi, int size) | |
9846 | { | |
9847 | int jj; | |
7d2e7e17 | 9848 | u8 *data = NULL; |
fe96802b NQ |
9849 | int padding_size = pbi->chunk->offset & |
9850 | (VDEC_FIFO_ALIGN - 1); | |
7d2e7e17 NQ |
9851 | |
9852 | if (!pbi->chunk->block->is_mapped) | |
9853 | data = codec_mm_vmap(pbi->chunk->block->start + | |
9854 | pbi->chunk->offset, size); | |
9855 | else | |
9856 | data = ((u8 *)pbi->chunk->block->start_virt) + | |
9857 | pbi->chunk->offset; | |
9858 | ||
fe96802b NQ |
9859 | vp9_print(pbi, 0, "padding: "); |
9860 | for (jj = padding_size; jj > 0; jj--) | |
9861 | vp9_print_cont(pbi, | |
9862 | 0, | |
9863 | "%02x ", *(data - jj)); | |
9864 | vp9_print_cont(pbi, 0, "data adr %p\n", | |
9865 | data); | |
9866 | ||
b9164398 NQ |
9867 | for (jj = 0; jj < size; jj++) { |
9868 | if ((jj & 0xf) == 0) | |
9869 | vp9_print(pbi, | |
9870 | 0, | |
9871 | "%06x:", jj); | |
9872 | vp9_print_cont(pbi, | |
9873 | 0, | |
9874 | "%02x ", data[jj]); | |
9875 | if (((jj + 1) & 0xf) == 0) | |
9876 | vp9_print(pbi, | |
9877 | 0, | |
9878 | "\n"); | |
9879 | } | |
9880 | vp9_print(pbi, | |
9881 | 0, | |
9882 | "\n"); | |
7d2e7e17 NQ |
9883 | |
9884 | if (!pbi->chunk->block->is_mapped) | |
9885 | codec_mm_unmap_phyaddr(data); | |
b9164398 NQ |
9886 | } |
9887 | ||
9888 | static void vp9_work(struct work_struct *work) | |
9889 | { | |
9890 | struct VP9Decoder_s *pbi = container_of(work, | |
9891 | struct VP9Decoder_s, work); | |
b9164398 NQ |
9892 | struct vdec_s *vdec = hw_to_vdec(pbi); |
9893 | /* finished decoding one frame or error, | |
9894 | * notify vdec core to switch context | |
9895 | */ | |
fe96802b NQ |
9896 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, |
9897 | "%s dec_result %d %x %x %x\n", | |
9898 | __func__, | |
9899 | pbi->dec_result, | |
9900 | READ_VREG(HEVC_STREAM_LEVEL), | |
9901 | READ_VREG(HEVC_STREAM_WR_PTR), | |
9902 | READ_VREG(HEVC_STREAM_RD_PTR)); | |
9903 | ||
2cd6815e NQ |
9904 | if (pbi->dec_result == DEC_INIT_PICLIST) { |
9905 | init_pic_list(pbi); | |
9906 | pbi->pic_list_init_done = true; | |
9907 | return; | |
9908 | } | |
9909 | ||
65ad8202 GZ |
9910 | if (pbi->dec_result == DEC_RESULT_NEED_MORE_BUFFER) { |
9911 | reset_process_time(pbi); | |
9912 | if (!get_free_buf_count(pbi)) { | |
9913 | pbi->dec_result = DEC_RESULT_NEED_MORE_BUFFER; | |
9914 | vdec_schedule_work(&pbi->work); | |
9915 | } else { | |
9916 | int i; | |
9917 | ||
9918 | if (pbi->mmu_enable) | |
9919 | vp9_recycle_mmu_buf_tail(pbi); | |
9920 | ||
9921 | if (pbi->frame_count > 0) | |
9922 | vp9_bufmgr_postproc(pbi); | |
9923 | ||
9924 | for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { | |
9925 | int ii; | |
9926 | for (ii = 0; ii < 4; ii++) | |
9927 | pbi->vp9_param.l.data[i + ii] = | |
9928 | pbi->rpm_ptr[i + 3 - ii]; | |
9929 | } | |
9930 | continue_decoding(pbi); | |
9931 | pbi->postproc_done = 0; | |
9932 | pbi->process_busy = 0; | |
9933 | ||
9934 | start_process_time(pbi); | |
9935 | } | |
9936 | return; | |
9937 | } | |
9938 | ||
fe96802b NQ |
9939 | if (((pbi->dec_result == DEC_RESULT_GET_DATA) || |
9940 | (pbi->dec_result == DEC_RESULT_GET_DATA_RETRY)) | |
9941 | && (hw_to_vdec(pbi)->next_status != | |
9942 | VDEC_STATUS_DISCONNECTED)) { | |
9943 | if (!vdec_has_more_input(vdec)) { | |
9944 | pbi->dec_result = DEC_RESULT_EOS; | |
9945 | vdec_schedule_work(&pbi->work); | |
9946 | return; | |
9947 | } | |
b9164398 | 9948 | |
b9164398 NQ |
9949 | if (pbi->dec_result == DEC_RESULT_GET_DATA) { |
9950 | vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, | |
9951 | "%s DEC_RESULT_GET_DATA %x %x %x\n", | |
9952 | __func__, | |
9953 | READ_VREG(HEVC_STREAM_LEVEL), | |
9954 | READ_VREG(HEVC_STREAM_WR_PTR), | |
9955 | READ_VREG(HEVC_STREAM_RD_PTR)); | |
9956 | vdec_vframe_dirty(vdec, pbi->chunk); | |
9957 | vdec_clean_input(vdec); | |
9958 | } | |
9959 | ||
fe96802b | 9960 | if (get_free_buf_count(pbi) >= |
65ad8202 | 9961 | pbi->run_ready_min_buf_num) { |
b9164398 | 9962 | int r; |
fe96802b | 9963 | int decode_size; |
b9164398 NQ |
9964 | r = vdec_prepare_input(vdec, &pbi->chunk); |
9965 | if (r < 0) { | |
9966 | pbi->dec_result = DEC_RESULT_GET_DATA_RETRY; | |
9967 | ||
9968 | vp9_print(pbi, | |
9969 | PRINT_FLAG_VDEC_DETAIL, | |
9970 | "amvdec_vh265: Insufficient data\n"); | |
9971 | ||
fe96802b | 9972 | vdec_schedule_work(&pbi->work); |
b9164398 NQ |
9973 | return; |
9974 | } | |
9975 | pbi->dec_result = DEC_RESULT_NONE; | |
9976 | vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, | |
9977 | "%s: chunk size 0x%x sum 0x%x\n", | |
9978 | __func__, r, | |
9979 | (debug & PRINT_FLAG_VDEC_STATUS) ? | |
9980 | get_data_check_sum(pbi, r) : 0 | |
9981 | ); | |
9982 | ||
9983 | if (debug & PRINT_FLAG_VDEC_DATA) | |
9984 | dump_data(pbi, pbi->chunk->size); | |
fe96802b NQ |
9985 | |
9986 | decode_size = pbi->chunk->size + | |
9987 | (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1)); | |
9988 | ||
9989 | WRITE_VREG(HEVC_DECODE_SIZE, | |
9990 | READ_VREG(HEVC_DECODE_SIZE) + decode_size); | |
b9164398 NQ |
9991 | |
9992 | vdec_enable_input(vdec); | |
9993 | ||
9994 | WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); | |
fe96802b NQ |
9995 | |
9996 | start_process_time(pbi); | |
9997 | ||
b9164398 NQ |
9998 | } else{ |
9999 | pbi->dec_result = DEC_RESULT_GET_DATA_RETRY; | |
10000 | ||
10001 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, | |
10002 | "amvdec_vh265: Insufficient data\n"); | |
10003 | ||
fe96802b | 10004 | vdec_schedule_work(&pbi->work); |
b9164398 NQ |
10005 | } |
10006 | return; | |
10007 | } else if (pbi->dec_result == DEC_RESULT_DONE) { | |
a6c89e96 NQ |
10008 | #ifdef SUPPORT_FB_DECODING |
10009 | if (pbi->used_stage_buf_num > 0) { | |
10010 | #ifndef FB_DECODING_TEST_SCHEDULE | |
10011 | if (!is_s2_decoding_finished(pbi)) { | |
10012 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, | |
10013 | "s2 decoding not done, check again later\n"); | |
10014 | vdec_schedule_work(&pbi->work); | |
10015 | } | |
10016 | #endif | |
10017 | inc_s2_pos(pbi); | |
10018 | if (mcrcc_cache_alg_flag) | |
10019 | dump_hit_rate(pbi); | |
10020 | } | |
10021 | #endif | |
b9164398 NQ |
10022 | /* if (!pbi->ctx_valid) |
10023 | pbi->ctx_valid = 1; */ | |
fe96802b NQ |
10024 | pbi->slice_idx++; |
10025 | pbi->frame_count++; | |
10026 | pbi->process_state = PROC_STATE_INIT; | |
10027 | decode_frame_count[pbi->index] = pbi->frame_count; | |
10028 | ||
b7706e1e | 10029 | if (pbi->mmu_enable) |
10030 | pbi->used_4k_num = | |
10031 | (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); | |
b9164398 | 10032 | vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, |
fe96802b | 10033 | "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n", |
b9164398 | 10034 | __func__, |
fe96802b | 10035 | pbi->frame_count, |
b9164398 NQ |
10036 | pbi->dec_result, |
10037 | READ_VREG(HEVC_STREAM_LEVEL), | |
10038 | READ_VREG(HEVC_STREAM_WR_PTR), | |
fe96802b NQ |
10039 | READ_VREG(HEVC_STREAM_RD_PTR), |
10040 | READ_VREG(HEVC_SHIFT_BYTE_COUNT), | |
10041 | READ_VREG(HEVC_SHIFT_BYTE_COUNT) - | |
10042 | pbi->start_shift_bytes | |
10043 | ); | |
b9164398 | 10044 | vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk); |
fe96802b NQ |
10045 | } else if (pbi->dec_result == DEC_RESULT_AGAIN) { |
10046 | /* | |
10047 | stream base: stream buf empty or timeout | |
10048 | frame base: vdec_prepare_input fail | |
10049 | */ | |
10050 | if (!vdec_has_more_input(vdec)) { | |
10051 | pbi->dec_result = DEC_RESULT_EOS; | |
10052 | vdec_schedule_work(&pbi->work); | |
10053 | return; | |
10054 | } | |
10055 | } else if (pbi->dec_result == DEC_RESULT_EOS) { | |
10056 | vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, | |
10057 | "%s: end of stream\n", | |
10058 | __func__); | |
10059 | pbi->eos = 1; | |
10060 | vp9_bufmgr_postproc(pbi); | |
2cd6815e | 10061 | |
b4a59a5a | 10062 | notify_v4l_eos(hw_to_vdec(pbi)); |
2cd6815e | 10063 | |
fe96802b NQ |
10064 | vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk); |
10065 | } else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) { | |
10066 | vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, | |
10067 | "%s: force exit\n", | |
10068 | __func__); | |
10069 | if (pbi->stat & STAT_VDEC_RUN) { | |
10070 | amhevc_stop(); | |
10071 | pbi->stat &= ~STAT_VDEC_RUN; | |
10072 | } | |
10073 | ||
10074 | if (pbi->stat & STAT_ISR_REG) { | |
10075 | #ifdef MULTI_INSTANCE_SUPPORT | |
10076 | if (!pbi->m_ins_flag) | |
10077 | #endif | |
a6c89e96 NQ |
10078 | WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0); |
10079 | vdec_free_irq(VDEC_IRQ_0, (void *)pbi); | |
fe96802b NQ |
10080 | pbi->stat &= ~STAT_ISR_REG; |
10081 | } | |
b9164398 | 10082 | } |
976f3376 HZ |
10083 | if (pbi->stat & STAT_VDEC_RUN) { |
10084 | amhevc_stop(); | |
10085 | pbi->stat &= ~STAT_VDEC_RUN; | |
10086 | } | |
b9164398 | 10087 | |
c23e8aee HZ |
10088 | if (pbi->stat & STAT_TIMER_ARM) { |
10089 | del_timer_sync(&pbi->timer); | |
10090 | pbi->stat &= ~STAT_TIMER_ARM; | |
10091 | } | |
b9164398 | 10092 | /* mark itself has all HW resource released and input released */ |
a6c89e96 NQ |
10093 | #ifdef SUPPORT_FB_DECODING |
10094 | if (pbi->used_stage_buf_num > 0) | |
10095 | vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK); | |
10096 | else | |
10097 | vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | |
10098 | | CORE_MASK_HEVC | |
10099 | | CORE_MASK_HEVC_FRONT | |
10100 | | CORE_MASK_HEVC_BACK | |
10101 | ); | |
10102 | #else | |
05afa03d PY |
10103 | if (vdec->parallel_dec == 1) |
10104 | vdec_core_finish_run(vdec, CORE_MASK_HEVC); | |
10105 | else | |
10106 | vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | |
10107 | | CORE_MASK_HEVC); | |
a6c89e96 NQ |
10108 | #endif |
10109 | trigger_schedule(pbi); | |
b9164398 NQ |
10110 | } |
10111 | ||
10112 | static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi) | |
10113 | { | |
10114 | /* new to do ... */ | |
a6c89e96 NQ |
10115 | #if (!defined SUPPORT_FB_DECODING) |
10116 | vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); | |
10117 | #elif (defined FB_DECODING_TEST_SCHEDULE) | |
10118 | vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); | |
10119 | #else | |
10120 | if (pbi->used_stage_buf_num > 0) | |
10121 | vvp9_prot_init(pbi, HW_MASK_FRONT); | |
10122 | else | |
10123 | vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); | |
10124 | #endif | |
b9164398 NQ |
10125 | return 0; |
10126 | } | |
a6c89e96 | 10127 | static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask) |
b9164398 NQ |
10128 | { |
10129 | struct VP9Decoder_s *pbi = | |
10130 | (struct VP9Decoder_s *)vdec->private; | |
ca482a9c HZ |
10131 | int tvp = vdec_secure(hw_to_vdec(pbi)) ? |
10132 | CODEC_MM_FLAGS_TVP : 0; | |
a6c89e96 NQ |
10133 | unsigned long ret = 0; |
10134 | ||
2cd6815e | 10135 | if (!(pbi->pic_list_init_done && pbi->pic_list_init_done2) || pbi->eos) |
fe96802b | 10136 | return ret; |
ca482a9c HZ |
10137 | if (!pbi->first_sc_checked && pbi->mmu_enable) { |
10138 | int size = decoder_mmu_box_sc_check(pbi->mmu_box, tvp); | |
10139 | pbi->first_sc_checked = 1; | |
10140 | vp9_print(pbi, 0, "vp9 cached=%d need_size=%d speed= %d ms\n", | |
10141 | size, (pbi->need_cache_size >> PAGE_SHIFT), | |
10142 | (int)(get_jiffies_64() - pbi->sc_start_time) * 1000/HZ); | |
10143 | } | |
0fb7e163 | 10144 | |
a6c89e96 NQ |
10145 | #ifdef SUPPORT_FB_DECODING |
10146 | if (pbi->used_stage_buf_num > 0) { | |
10147 | if (mask & CORE_MASK_HEVC_FRONT) { | |
10148 | if (get_free_stage_buf_num(pbi) > 0 | |
10149 | && mv_buf_available(pbi)) | |
10150 | ret |= CORE_MASK_HEVC_FRONT; | |
10151 | } | |
10152 | if (mask & CORE_MASK_HEVC_BACK) { | |
10153 | if (s2_buf_available(pbi) && | |
10154 | (get_free_buf_count(pbi) >= | |
65ad8202 | 10155 | pbi->run_ready_min_buf_num)) { |
a6c89e96 NQ |
10156 | ret |= CORE_MASK_HEVC_BACK; |
10157 | pbi->back_not_run_ready = 0; | |
10158 | } else | |
10159 | pbi->back_not_run_ready = 1; | |
10160 | #if 0 | |
10161 | if (get_free_buf_count(pbi) < | |
10162 | run_ready_min_buf_num) | |
10163 | dump_pic_list(pbi); | |
10164 | #endif | |
10165 | } | |
10166 | } else if (get_free_buf_count(pbi) >= | |
65ad8202 | 10167 | pbi->run_ready_min_buf_num) |
a6c89e96 NQ |
10168 | ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
10169 | | CORE_MASK_HEVC_FRONT | |
10170 | | CORE_MASK_HEVC_BACK; | |
10171 | ||
10172 | if (ret & CORE_MASK_HEVC_FRONT) | |
10173 | not_run_ready[pbi->index] = 0; | |
10174 | else | |
10175 | not_run_ready[pbi->index]++; | |
10176 | ||
10177 | if (ret & CORE_MASK_HEVC_BACK) | |
10178 | not_run2_ready[pbi->index] = 0; | |
10179 | else | |
10180 | not_run2_ready[pbi->index]++; | |
10181 | ||
10182 | vp9_print(pbi, | |
10183 | PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n", | |
10184 | __func__, mask, ret, | |
10185 | get_free_stage_buf_num(pbi), | |
10186 | mv_buf_available(pbi), | |
10187 | s2_buf_available(pbi), | |
10188 | get_free_buf_count(pbi) | |
10189 | ); | |
b9164398 | 10190 | |
a6c89e96 NQ |
10191 | return ret; |
10192 | ||
10193 | #else | |
fe96802b | 10194 | if (get_free_buf_count(pbi) >= |
65ad8202 | 10195 | pbi->run_ready_min_buf_num) { |
05afa03d PY |
10196 | if (vdec->parallel_dec == 1) |
10197 | ret = CORE_MASK_HEVC; | |
10198 | else | |
10199 | ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC; | |
0fb7e163 NQ |
10200 | } |
10201 | ||
10202 | if (pbi->is_used_v4l) { | |
10203 | struct aml_vcodec_ctx *ctx = | |
10204 | (struct aml_vcodec_ctx *)(pbi->v4l2_ctx); | |
10205 | ||
d9a28922 YP |
10206 | if (ctx->param_sets_from_ucode) { |
10207 | if (pbi->v4l_params_parsed) { | |
6d5f1936 | 10208 | if ((ctx->cap_pool.in < pbi->used_buf_num) && |
d9a28922 | 10209 | v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) < |
65ad8202 | 10210 | pbi->run_ready_min_buf_num) |
d9a28922 YP |
10211 | ret = 0; |
10212 | } else { | |
0baa899d | 10213 | if (ctx->v4l_resolution_change) |
d9a28922 YP |
10214 | ret = 0; |
10215 | } | |
0fbadf02 | 10216 | } else if (ctx->cap_pool.in < ctx->dpb_size) { |
71979acf | 10217 | if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) < |
65ad8202 | 10218 | pbi->run_ready_min_buf_num) |
71979acf NQ |
10219 | ret = 0; |
10220 | } | |
0fb7e163 NQ |
10221 | } |
10222 | ||
fe96802b NQ |
10223 | if (ret) |
10224 | not_run_ready[pbi->index] = 0; | |
10225 | else | |
10226 | not_run_ready[pbi->index]++; | |
a6c89e96 NQ |
10227 | |
10228 | vp9_print(pbi, | |
10229 | PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n", | |
10230 | __func__, mask, ret); | |
fe96802b | 10231 | return ret; |
a6c89e96 | 10232 | #endif |
b9164398 NQ |
10233 | } |
10234 | ||
65ad8202 GZ |
10235 | static void vp9_frame_mode_pts_save(struct VP9Decoder_s *pbi) |
10236 | { | |
10237 | int i = 0; | |
10238 | ||
10239 | if (pbi->chunk == NULL) | |
10240 | return; | |
10241 | vp9_print(pbi, VP9_DEBUG_OUT_PTS, | |
10242 | "run front: pts %d, pts64 %lld\n", pbi->chunk->pts, pbi->chunk->pts64); | |
10243 | for (i = (FRAME_BUFFERS - 1); i > 0; i--) { | |
10244 | pbi->frame_mode_pts_save[i] = pbi->frame_mode_pts_save[i - 1]; | |
10245 | pbi->frame_mode_pts64_save[i] = pbi->frame_mode_pts64_save[i - 1]; | |
10246 | } | |
10247 | pbi->frame_mode_pts_save[0] = pbi->chunk->pts; | |
10248 | pbi->frame_mode_pts64_save[0] = pbi->chunk->pts64; | |
10249 | } | |
10250 | ||
a6c89e96 | 10251 | static void run_front(struct vdec_s *vdec) |
b9164398 NQ |
10252 | { |
10253 | struct VP9Decoder_s *pbi = | |
10254 | (struct VP9Decoder_s *)vdec->private; | |
a6c89e96 | 10255 | int ret, size; |
b9164398 | 10256 | |
fe96802b | 10257 | run_count[pbi->index]++; |
b9164398 | 10258 | /* pbi->chunk = vdec_prepare_input(vdec); */ |
a6c89e96 NQ |
10259 | #if (!defined SUPPORT_FB_DECODING) |
10260 | hevc_reset_core(vdec); | |
10261 | #elif (defined FB_DECODING_TEST_SCHEDULE) | |
fe96802b | 10262 | hevc_reset_core(vdec); |
a6c89e96 NQ |
10263 | #else |
10264 | if (pbi->used_stage_buf_num > 0) | |
10265 | fb_reset_core(vdec, HW_MASK_FRONT); | |
10266 | else | |
10267 | hevc_reset_core(vdec); | |
10268 | #endif | |
b9164398 | 10269 | |
a6c89e96 NQ |
10270 | size = vdec_prepare_input(vdec, &pbi->chunk); |
10271 | if (size < 0) { | |
fe96802b NQ |
10272 | input_empty[pbi->index]++; |
10273 | ||
b9164398 NQ |
10274 | pbi->dec_result = DEC_RESULT_AGAIN; |
10275 | ||
10276 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, | |
10277 | "ammvdec_vh265: Insufficient data\n"); | |
10278 | ||
fe96802b | 10279 | vdec_schedule_work(&pbi->work); |
b9164398 NQ |
10280 | return; |
10281 | } | |
75803959 | 10282 | |
fe96802b | 10283 | input_empty[pbi->index] = 0; |
b9164398 | 10284 | pbi->dec_result = DEC_RESULT_NONE; |
fe96802b | 10285 | pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT); |
b9164398 | 10286 | |
65ad8202 GZ |
10287 | vp9_frame_mode_pts_save(pbi); |
10288 | ||
fe96802b NQ |
10289 | if (debug & PRINT_FLAG_VDEC_STATUS) { |
10290 | int ii; | |
10291 | vp9_print(pbi, 0, | |
10292 | "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x", | |
10293 | __func__, | |
a6c89e96 | 10294 | pbi->frame_count, size, |
fe96802b NQ |
10295 | pbi->chunk ? pbi->chunk->size : 0, |
10296 | pbi->chunk ? pbi->chunk->offset : 0, | |
a35da9f0 | 10297 | pbi->chunk ? ((vdec_frame_based(vdec) && |
fe96802b | 10298 | (debug & PRINT_FLAG_VDEC_STATUS)) ? |
a35da9f0 | 10299 | get_data_check_sum(pbi, size) : 0) : 0, |
fe96802b NQ |
10300 | READ_VREG(HEVC_STREAM_START_ADDR), |
10301 | READ_VREG(HEVC_STREAM_END_ADDR), | |
10302 | READ_VREG(HEVC_STREAM_LEVEL), | |
10303 | READ_VREG(HEVC_STREAM_WR_PTR), | |
10304 | READ_VREG(HEVC_STREAM_RD_PTR), | |
10305 | pbi->start_shift_bytes); | |
a35da9f0 | 10306 | if (vdec_frame_based(vdec) && pbi->chunk) { |
7d2e7e17 NQ |
10307 | u8 *data = NULL; |
10308 | ||
10309 | if (!pbi->chunk->block->is_mapped) | |
10310 | data = codec_mm_vmap(pbi->chunk->block->start + | |
10311 | pbi->chunk->offset, 8); | |
10312 | else | |
10313 | data = ((u8 *)pbi->chunk->block->start_virt) + | |
10314 | pbi->chunk->offset; | |
10315 | ||
fe96802b NQ |
10316 | vp9_print_cont(pbi, 0, "data adr %p:", |
10317 | data); | |
10318 | for (ii = 0; ii < 8; ii++) | |
10319 | vp9_print_cont(pbi, 0, "%02x ", | |
10320 | data[ii]); | |
7d2e7e17 NQ |
10321 | |
10322 | if (!pbi->chunk->block->is_mapped) | |
10323 | codec_mm_unmap_phyaddr(data); | |
fe96802b NQ |
10324 | } |
10325 | vp9_print_cont(pbi, 0, "\r\n"); | |
10326 | } | |
158de7c4 HZ |
10327 | if (vdec->mc_loaded) { |
10328 | /*firmware have load before, | |
10329 | and not changes to another. | |
10330 | ignore reload. | |
10331 | */ | |
10332 | } else { | |
10333 | ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data); | |
10334 | if (ret < 0) { | |
10335 | amhevc_disable(); | |
10336 | vp9_print(pbi, PRINT_FLAG_ERROR, | |
10337 | "VP9: the %s fw loading failed, err: %x\n", | |
10338 | tee_enabled() ? "TEE" : "local", ret); | |
10339 | pbi->dec_result = DEC_RESULT_FORCE_EXIT; | |
10340 | vdec_schedule_work(&pbi->work); | |
10341 | return; | |
10342 | } | |
10343 | vdec->mc_loaded = 1; | |
10344 | vdec->mc_type = VFORMAT_VP9; | |
b9164398 | 10345 | } |
a6c89e96 | 10346 | |
b9164398 | 10347 | if (vp9_hw_ctx_restore(pbi) < 0) { |
fe96802b | 10348 | vdec_schedule_work(&pbi->work); |
b9164398 NQ |
10349 | return; |
10350 | } | |
10351 | ||
10352 | vdec_enable_input(vdec); | |
10353 | ||
10354 | WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); | |
10355 | ||
10356 | if (vdec_frame_based(vdec)) { | |
10357 | if (debug & PRINT_FLAG_VDEC_DATA) | |
10358 | dump_data(pbi, pbi->chunk->size); | |
10359 | ||
10360 | WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0); | |
a6c89e96 | 10361 | size = pbi->chunk->size + |
fe96802b | 10362 | (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1)); |
cc41710a | 10363 | if (vdec->mvfrm) |
10364 | vdec->mvfrm->frame_size = pbi->chunk->size; | |
b9164398 | 10365 | } |
a6c89e96 | 10366 | WRITE_VREG(HEVC_DECODE_SIZE, size); |
b9164398 NQ |
10367 | WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx); |
10368 | pbi->init_flag = 1; | |
10369 | ||
fe96802b | 10370 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, |
b9164398 NQ |
10371 | "%s: start hevc (%x %x %x)\n", |
10372 | __func__, | |
10373 | READ_VREG(HEVC_DEC_STATUS_REG), | |
10374 | READ_VREG(HEVC_MPC_E), | |
10375 | READ_VREG(HEVC_MPSR)); | |
10376 | ||
c23e8aee HZ |
10377 | start_process_time(pbi); |
10378 | mod_timer(&pbi->timer, jiffies); | |
10379 | pbi->stat |= STAT_TIMER_ARM; | |
10380 | pbi->stat |= STAT_ISR_REG; | |
b9164398 | 10381 | amhevc_start(); |
fe96802b | 10382 | pbi->stat |= STAT_VDEC_RUN; |
b9164398 NQ |
10383 | } |
10384 | ||
a6c89e96 NQ |
10385 | #ifdef SUPPORT_FB_DECODING |
10386 | static void mpred_process(struct VP9Decoder_s *pbi) | |
10387 | { | |
10388 | union param_u *params = &pbi->s1_param; | |
10389 | unsigned char use_prev_frame_mvs = | |
10390 | !params->p.error_resilient_mode && | |
10391 | params->p.width == pbi->s1_width && | |
10392 | params->p.height == pbi->s1_height && | |
10393 | !pbi->s1_intra_only && | |
10394 | pbi->s1_last_show_frame && | |
10395 | (pbi->s1_frame_type != KEY_FRAME); | |
10396 | pbi->s1_width = params->p.width; | |
10397 | pbi->s1_height = params->p.height; | |
10398 | pbi->s1_frame_type = params->p.frame_type; | |
10399 | pbi->s1_intra_only = | |
10400 | (params->p.show_frame || | |
10401 | params->p.show_existing_frame) | |
10402 | ? 0 : params->p.intra_only; | |
10403 | if ((pbi->s1_frame_type != KEY_FRAME) | |
10404 | && (!pbi->s1_intra_only)) { | |
10405 | unsigned int data32; | |
10406 | int mpred_mv_rd_end_addr; | |
10407 | ||
10408 | mpred_mv_rd_end_addr = | |
10409 | pbi->s1_mpred_mv_wr_start_addr_pre | |
10410 | + (pbi->lcu_total * MV_MEM_UNIT); | |
10411 | ||
10412 | WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412); | |
10413 | WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, | |
10414 | pbi->work_space_buf-> | |
10415 | mpred_above.buf_start); | |
10416 | ||
10417 | data32 = READ_VREG(HEVC_MPRED_CTRL4); | |
10418 | ||
10419 | data32 &= (~(1 << 6)); | |
10420 | data32 |= (use_prev_frame_mvs << 6); | |
10421 | WRITE_VREG(HEVC_MPRED_CTRL4, data32); | |
10422 | ||
10423 | WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR, | |
10424 | pbi->s1_mpred_mv_wr_start_addr); | |
10425 | WRITE_VREG(HEVC_MPRED_MV_WPTR, | |
10426 | pbi->s1_mpred_mv_wr_start_addr); | |
10427 | ||
10428 | WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR, | |
10429 | pbi->s1_mpred_mv_wr_start_addr_pre); | |
10430 | WRITE_VREG(HEVC_MPRED_MV_RPTR, | |
10431 | pbi->s1_mpred_mv_wr_start_addr_pre); | |
10432 | ||
10433 | WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, | |
10434 | mpred_mv_rd_end_addr); | |
10435 | ||
10436 | } else | |
10437 | clear_mpred_hw(pbi); | |
10438 | ||
10439 | if (!params->p.show_existing_frame) { | |
10440 | pbi->s1_mpred_mv_wr_start_addr_pre = | |
10441 | pbi->s1_mpred_mv_wr_start_addr; | |
10442 | pbi->s1_last_show_frame = | |
10443 | params->p.show_frame; | |
10444 | if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM) | |
10445 | put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre); | |
10446 | pbi->s1_mv_buf_index_pre_pre = | |
10447 | pbi->s1_mv_buf_index_pre; | |
10448 | pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index; | |
10449 | } else | |
10450 | put_mv_buf(pbi, &pbi->s1_mv_buf_index); | |
10451 | } | |
10452 | ||
10453 | static void vp9_s1_work(struct work_struct *s1_work) | |
10454 | { | |
10455 | struct VP9Decoder_s *pbi = container_of(s1_work, | |
10456 | struct VP9Decoder_s, s1_work); | |
10457 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, | |
10458 | "%s dec_s1_result %d\n", | |
10459 | __func__, | |
10460 | pbi->dec_s1_result); | |
10461 | ||
10462 | #ifdef FB_DECODING_TEST_SCHEDULE | |
10463 | if (pbi->dec_s1_result == | |
10464 | DEC_S1_RESULT_TEST_TRIGGER_DONE) { | |
10465 | pbi->s1_test_cmd = TEST_SET_PIC_DONE; | |
10466 | WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1); | |
10467 | } | |
10468 | #endif | |
10469 | if (pbi->dec_s1_result == DEC_S1_RESULT_DONE || | |
10470 | pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) { | |
10471 | ||
10472 | vdec_core_finish_run(hw_to_vdec(pbi), | |
10473 | CORE_MASK_HEVC_FRONT); | |
10474 | ||
10475 | trigger_schedule(pbi); | |
10476 | /*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/ | |
10477 | } | |
10478 | ||
10479 | } | |
10480 | ||
10481 | static void run_back(struct vdec_s *vdec) | |
10482 | { | |
10483 | struct VP9Decoder_s *pbi = | |
10484 | (struct VP9Decoder_s *)vdec->private; | |
10485 | int i; | |
10486 | run2_count[pbi->index]++; | |
10487 | if (debug & PRINT_FLAG_VDEC_STATUS) { | |
10488 | vp9_print(pbi, 0, | |
10489 | "%s", __func__); | |
10490 | } | |
10491 | pbi->run2_busy = 1; | |
10492 | #ifndef FB_DECODING_TEST_SCHEDULE | |
10493 | fb_reset_core(vdec, HW_MASK_BACK); | |
10494 | ||
10495 | vvp9_prot_init(pbi, HW_MASK_BACK); | |
10496 | #endif | |
10497 | vp9_recycle_mmu_buf_tail(pbi); | |
10498 | ||
10499 | if (pbi->frame_count > 0) | |
10500 | vp9_bufmgr_postproc(pbi); | |
10501 | ||
10502 | if (get_s2_buf(pbi) >= 0) { | |
10503 | for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { | |
10504 | int ii; | |
10505 | for (ii = 0; ii < 4; ii++) | |
3be38e55 | 10506 | pbi->vp9_param.l.data[i + ii] = |
a6c89e96 NQ |
10507 | pbi->s2_buf->rpm[i + 3 - ii]; |
10508 | } | |
10509 | #ifndef FB_DECODING_TEST_SCHEDULE | |
10510 | WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR, | |
10511 | pbi->stage_mmu_map_phy_addr + | |
10512 | pbi->s2_buf->index * STAGE_MMU_MAP_SIZE); | |
10513 | #endif | |
10514 | continue_decoding(pbi); | |
10515 | } | |
10516 | pbi->run2_busy = 0; | |
10517 | } | |
10518 | #endif | |
10519 | ||
10520 | static void run(struct vdec_s *vdec, unsigned long mask, | |
10521 | void (*callback)(struct vdec_s *, void *), void *arg) | |
10522 | { | |
10523 | struct VP9Decoder_s *pbi = | |
10524 | (struct VP9Decoder_s *)vdec->private; | |
10525 | ||
10526 | vp9_print(pbi, | |
10527 | PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n", | |
10528 | __func__, mask); | |
10529 | ||
cc41710a | 10530 | if (vdec->mvfrm) |
10531 | vdec->mvfrm->hw_decode_start = local_clock(); | |
a6c89e96 NQ |
10532 | run_count[pbi->index]++; |
10533 | pbi->vdec_cb_arg = arg; | |
10534 | pbi->vdec_cb = callback; | |
65ad8202 | 10535 | pbi->one_package_frame_cnt = 0; |
a6c89e96 NQ |
10536 | #ifdef SUPPORT_FB_DECODING |
10537 | if ((mask & CORE_MASK_HEVC) || | |
10538 | (mask & CORE_MASK_HEVC_FRONT)) | |
10539 | run_front(vdec); | |
10540 | ||
10541 | if ((pbi->used_stage_buf_num > 0) | |
10542 | && (mask & CORE_MASK_HEVC_BACK)) | |
10543 | run_back(vdec); | |
10544 | #else | |
10545 | run_front(vdec); | |
10546 | #endif | |
d9a28922 | 10547 | |
a6c89e96 NQ |
10548 | } |
10549 | ||
0fb7e163 NQ |
10550 | static void init_frame_bufs(struct VP9Decoder_s *pbi) |
10551 | { | |
10552 | struct vdec_s *vdec = hw_to_vdec(pbi); | |
10553 | struct VP9_Common_s *const cm = &pbi->common; | |
10554 | struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; | |
10555 | int i; | |
10556 | ||
10557 | for (i = 0; i < pbi->used_buf_num; ++i) { | |
10558 | frame_bufs[i].ref_count = 0; | |
10559 | frame_bufs[i].buf.vf_ref = 0; | |
10560 | frame_bufs[i].buf.decode_idx = 0; | |
75803959 NQ |
10561 | frame_bufs[i].buf.cma_alloc_addr = 0; |
10562 | frame_bufs[i].buf.index = i; | |
0fbadf02 | 10563 | frame_bufs[i].buf.vframe_bound = 0; |
0fb7e163 NQ |
10564 | } |
10565 | ||
10566 | if (vdec->parallel_dec == 1) { | |
10567 | for (i = 0; i < FRAME_BUFFERS; i++) { | |
10568 | vdec->free_canvas_ex | |
10569 | (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index, | |
10570 | vdec->id); | |
10571 | vdec->free_canvas_ex | |
10572 | (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index, | |
10573 | vdec->id); | |
10574 | } | |
10575 | } | |
10576 | } | |
10577 | ||
b9164398 NQ |
10578 | static void reset(struct vdec_s *vdec) |
10579 | { | |
b9164398 NQ |
10580 | struct VP9Decoder_s *pbi = |
10581 | (struct VP9Decoder_s *)vdec->private; | |
10582 | ||
0fb7e163 NQ |
10583 | cancel_work_sync(&pbi->work); |
10584 | if (pbi->stat & STAT_VDEC_RUN) { | |
10585 | amhevc_stop(); | |
10586 | pbi->stat &= ~STAT_VDEC_RUN; | |
10587 | } | |
10588 | ||
10589 | if (pbi->stat & STAT_TIMER_ARM) { | |
10590 | del_timer_sync(&pbi->timer); | |
10591 | pbi->stat &= ~STAT_TIMER_ARM; | |
10592 | } | |
10593 | pbi->dec_result = DEC_RESULT_NONE; | |
10594 | reset_process_time(pbi); | |
0fb7e163 NQ |
10595 | vp9_local_uninit(pbi); |
10596 | if (vvp9_local_init(pbi) < 0) | |
10597 | vp9_print(pbi, 0, "%s local_init failed \r\n", __func__); | |
10598 | init_frame_bufs(pbi); | |
10599 | ||
10600 | pbi->eos = 0; | |
b9164398 | 10601 | |
0fb7e163 | 10602 | vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__); |
b9164398 NQ |
10603 | } |
10604 | ||
a6c89e96 | 10605 | static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq) |
b9164398 NQ |
10606 | { |
10607 | struct VP9Decoder_s *pbi = | |
10608 | (struct VP9Decoder_s *)vdec->private; | |
10609 | return vvp9_isr(0, pbi); | |
10610 | } | |
10611 | ||
a6c89e96 | 10612 | static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq) |
b9164398 NQ |
10613 | { |
10614 | struct VP9Decoder_s *pbi = | |
10615 | (struct VP9Decoder_s *)vdec->private; | |
10616 | return vvp9_isr_thread_fn(0, pbi); | |
10617 | } | |
10618 | ||
fe96802b NQ |
10619 | static void vp9_dump_state(struct vdec_s *vdec) |
10620 | { | |
10621 | struct VP9Decoder_s *pbi = | |
10622 | (struct VP9Decoder_s *)vdec->private; | |
10623 | struct VP9_Common_s *const cm = &pbi->common; | |
10624 | int i; | |
10625 | vp9_print(pbi, 0, "====== %s\n", __func__); | |
10626 | ||
10627 | vp9_print(pbi, 0, | |
10628 | "width/height (%d/%d), used_buf_num %d\n", | |
10629 | cm->width, | |
10630 | cm->height, | |
10631 | pbi->used_buf_num | |
10632 | ); | |
10633 | ||
10634 | vp9_print(pbi, 0, | |
0eb79ad7 | 10635 | "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n", |
fe96802b NQ |
10636 | input_frame_based(vdec), |
10637 | pbi->eos, | |
10638 | pbi->dec_result, | |
10639 | decode_frame_count[pbi->index], | |
10640 | display_frame_count[pbi->index], | |
10641 | run_count[pbi->index], | |
10642 | not_run_ready[pbi->index], | |
187af067 | 10643 | input_empty[pbi->index], |
0eb79ad7 RZ |
10644 | pbi->low_latency_flag, |
10645 | pbi->no_head | |
fe96802b NQ |
10646 | ); |
10647 | ||
10648 | if (vf_get_receiver(vdec->vf_provider_name)) { | |
10649 | enum receviver_start_e state = | |
10650 | vf_notify_receiver(vdec->vf_provider_name, | |
10651 | VFRAME_EVENT_PROVIDER_QUREY_STATE, | |
10652 | NULL); | |
10653 | vp9_print(pbi, 0, | |
10654 | "\nreceiver(%s) state %d\n", | |
10655 | vdec->vf_provider_name, | |
10656 | state); | |
10657 | } | |
10658 | ||
10659 | vp9_print(pbi, 0, | |
10660 | "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n", | |
10661 | __func__, | |
10662 | kfifo_len(&pbi->newframe_q), | |
10663 | VF_POOL_SIZE, | |
10664 | kfifo_len(&pbi->display_q), | |
10665 | VF_POOL_SIZE, | |
10666 | pbi->vf_pre_count, | |
10667 | pbi->vf_get_count, | |
10668 | pbi->vf_put_count, | |
10669 | get_free_buf_count(pbi), | |
65ad8202 | 10670 | pbi->run_ready_min_buf_num |
fe96802b NQ |
10671 | ); |
10672 | ||
10673 | dump_pic_list(pbi); | |
10674 | ||
10675 | for (i = 0; i < MAX_BUF_NUM; i++) { | |
10676 | vp9_print(pbi, 0, | |
10677 | "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n", | |
10678 | i, | |
10679 | pbi->m_mv_BUF[i].start_adr, | |
10680 | pbi->m_mv_BUF[i].size, | |
10681 | pbi->m_mv_BUF[i].used_flag); | |
10682 | } | |
10683 | ||
10684 | vp9_print(pbi, 0, | |
10685 | "HEVC_DEC_STATUS_REG=0x%x\n", | |
10686 | READ_VREG(HEVC_DEC_STATUS_REG)); | |
10687 | vp9_print(pbi, 0, | |
10688 | "HEVC_MPC_E=0x%x\n", | |
10689 | READ_VREG(HEVC_MPC_E)); | |
10690 | vp9_print(pbi, 0, | |
10691 | "DECODE_MODE=0x%x\n", | |
10692 | READ_VREG(DECODE_MODE)); | |
10693 | vp9_print(pbi, 0, | |
10694 | "NAL_SEARCH_CTL=0x%x\n", | |
10695 | READ_VREG(NAL_SEARCH_CTL)); | |
10696 | vp9_print(pbi, 0, | |
10697 | "HEVC_PARSER_LCU_START=0x%x\n", | |
10698 | READ_VREG(HEVC_PARSER_LCU_START)); | |
10699 | vp9_print(pbi, 0, | |
10700 | "HEVC_DECODE_SIZE=0x%x\n", | |
10701 | READ_VREG(HEVC_DECODE_SIZE)); | |
10702 | vp9_print(pbi, 0, | |
10703 | "HEVC_SHIFT_BYTE_COUNT=0x%x\n", | |
10704 | READ_VREG(HEVC_SHIFT_BYTE_COUNT)); | |
10705 | vp9_print(pbi, 0, | |
10706 | "HEVC_STREAM_START_ADDR=0x%x\n", | |
10707 | READ_VREG(HEVC_STREAM_START_ADDR)); | |
10708 | vp9_print(pbi, 0, | |
10709 | "HEVC_STREAM_END_ADDR=0x%x\n", | |
10710 | READ_VREG(HEVC_STREAM_END_ADDR)); | |
10711 | vp9_print(pbi, 0, | |
10712 | "HEVC_STREAM_LEVEL=0x%x\n", | |
10713 | READ_VREG(HEVC_STREAM_LEVEL)); | |
10714 | vp9_print(pbi, 0, | |
10715 | "HEVC_STREAM_WR_PTR=0x%x\n", | |
10716 | READ_VREG(HEVC_STREAM_WR_PTR)); | |
10717 | vp9_print(pbi, 0, | |
10718 | "HEVC_STREAM_RD_PTR=0x%x\n", | |
10719 | READ_VREG(HEVC_STREAM_RD_PTR)); | |
10720 | vp9_print(pbi, 0, | |
10721 | "PARSER_VIDEO_RP=0x%x\n", | |
d631e9c2 | 10722 | STBUF_READ(&vdec->vbuf, get_rp)); |
fe96802b NQ |
10723 | vp9_print(pbi, 0, |
10724 | "PARSER_VIDEO_WP=0x%x\n", | |
d631e9c2 | 10725 | STBUF_READ(&vdec->vbuf, get_wp)); |
fe96802b NQ |
10726 | |
10727 | if (input_frame_based(vdec) && | |
10728 | (debug & PRINT_FLAG_VDEC_DATA) | |
10729 | ) { | |
10730 | int jj; | |
10731 | if (pbi->chunk && pbi->chunk->block && | |
10732 | pbi->chunk->size > 0) { | |
7d2e7e17 NQ |
10733 | u8 *data = NULL; |
10734 | ||
10735 | if (!pbi->chunk->block->is_mapped) | |
10736 | data = codec_mm_vmap( | |
10737 | pbi->chunk->block->start + | |
10738 | pbi->chunk->offset, | |
10739 | pbi->chunk->size); | |
10740 | else | |
10741 | data = ((u8 *)pbi->chunk->block->start_virt) | |
10742 | + pbi->chunk->offset; | |
fe96802b NQ |
10743 | vp9_print(pbi, 0, |
10744 | "frame data size 0x%x\n", | |
10745 | pbi->chunk->size); | |
10746 | for (jj = 0; jj < pbi->chunk->size; jj++) { | |
10747 | if ((jj & 0xf) == 0) | |
10748 | vp9_print(pbi, 0, | |
10749 | "%06x:", jj); | |
10750 | vp9_print_cont(pbi, 0, | |
10751 | "%02x ", data[jj]); | |
10752 | if (((jj + 1) & 0xf) == 0) | |
10753 | vp9_print_cont(pbi, 0, | |
10754 | "\n"); | |
10755 | } | |
7d2e7e17 NQ |
10756 | |
10757 | if (!pbi->chunk->block->is_mapped) | |
10758 | codec_mm_unmap_phyaddr(data); | |
fe96802b NQ |
10759 | } |
10760 | } | |
10761 | ||
10762 | } | |
b9164398 NQ |
10763 | |
10764 | static int ammvdec_vp9_probe(struct platform_device *pdev) | |
10765 | { | |
10766 | struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; | |
fe96802b NQ |
10767 | int ret; |
10768 | int config_val; | |
d481db31 NQ |
10769 | struct vframe_content_light_level_s content_light_level; |
10770 | struct vframe_master_display_colour_s vf_dp; | |
b9164398 NQ |
10771 | |
10772 | struct BUF_s BUF[MAX_BUF_NUM]; | |
10773 | struct VP9Decoder_s *pbi = NULL; | |
5666aa9d | 10774 | pr_debug("%s\n", __func__); |
a6c89e96 | 10775 | |
b9164398 NQ |
10776 | if (pdata == NULL) { |
10777 | pr_info("\nammvdec_vp9 memory resource undefined.\n"); | |
10778 | return -EFAULT; | |
10779 | } | |
fe96802b NQ |
10780 | /*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev, |
10781 | sizeof(struct VP9Decoder_s), GFP_KERNEL);*/ | |
d481db31 | 10782 | memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s)); |
fe96802b | 10783 | pbi = vmalloc(sizeof(struct VP9Decoder_s)); |
b9164398 NQ |
10784 | if (pbi == NULL) { |
10785 | pr_info("\nammvdec_vp9 device data allocation failed\n"); | |
10786 | return -ENOMEM; | |
10787 | } | |
a674e3cd | 10788 | memset(pbi, 0, sizeof(struct VP9Decoder_s)); |
2cd6815e NQ |
10789 | |
10790 | /* the ctx from v4l2 driver. */ | |
10791 | pbi->v4l2_ctx = pdata->private; | |
10792 | ||
b9164398 NQ |
10793 | pdata->private = pbi; |
10794 | pdata->dec_status = vvp9_dec_status; | |
10795 | /* pdata->set_trickmode = set_trickmode; */ | |
10796 | pdata->run_ready = run_ready; | |
10797 | pdata->run = run; | |
10798 | pdata->reset = reset; | |
10799 | pdata->irq_handler = vp9_irq_cb; | |
10800 | pdata->threaded_irq_handler = vp9_threaded_irq_cb; | |
fe96802b | 10801 | pdata->dump_state = vp9_dump_state; |
b9164398 | 10802 | |
b9164398 | 10803 | memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); |
b9164398 NQ |
10804 | memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); |
10805 | ||
fe96802b | 10806 | pbi->index = pdev->id; |
b9164398 NQ |
10807 | |
10808 | if (pdata->use_vfm_path) | |
10809 | snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, | |
10810 | VFM_DEC_PROVIDER_NAME); | |
10811 | else | |
10812 | snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, | |
10813 | MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff); | |
10814 | ||
10815 | vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name, | |
10816 | &vvp9_vf_provider, pbi); | |
10817 | ||
10818 | pbi->provider_name = pdata->vf_provider_name; | |
10819 | platform_set_drvdata(pdev, pdata); | |
10820 | ||
10821 | pbi->platform_dev = pdev; | |
d481db31 | 10822 | pbi->video_signal_type = 0; |
b7706e1e | 10823 | pbi->m_ins_flag = 1; |
63e810c0 | 10824 | if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) |
c23e8aee | 10825 | pbi->stat |= VP9_TRIGGER_FRAME_ENABLE; |
c4ea7ef3 | 10826 | |
6f5ee885 | 10827 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
e0e39311 | 10828 | pbi->max_pic_w = 8192; |
10829 | pbi->max_pic_h = 4608; | |
b295c149 NQ |
10830 | } else { |
10831 | pbi->max_pic_w = 4096; | |
10832 | pbi->max_pic_h = 2304; | |
e0e39311 | 10833 | } |
fe96802b NQ |
10834 | #if 1 |
10835 | if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 && | |
a35da9f0 | 10836 | pdata->config_len) { |
fe96802b | 10837 | #ifdef MULTI_INSTANCE_SUPPORT |
96b88a8a HZ |
10838 | int vp9_buf_width = 0; |
10839 | int vp9_buf_height = 0; | |
fe96802b NQ |
10840 | /*use ptr config for doubel_write_mode, etc*/ |
10841 | vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config); | |
10842 | if (get_config_int(pdata->config, "vp9_double_write_mode", | |
10843 | &config_val) == 0) | |
10844 | pbi->double_write_mode = config_val; | |
10845 | else | |
10846 | pbi->double_write_mode = double_write_mode; | |
0be1523d | 10847 | |
a5c5bec0 YL |
10848 | if (get_config_int(pdata->config, "save_buffer_mode", |
10849 | &config_val) == 0) | |
10850 | pbi->save_buffer_mode = config_val; | |
10851 | else | |
10852 | pbi->save_buffer_mode = 0; | |
96b88a8a HZ |
10853 | if (get_config_int(pdata->config, "vp9_buf_width", |
10854 | &config_val) == 0) { | |
10855 | vp9_buf_width = config_val; | |
10856 | } | |
10857 | if (get_config_int(pdata->config, "vp9_buf_height", | |
10858 | &config_val) == 0) { | |
10859 | vp9_buf_height = config_val; | |
10860 | } | |
a5c5bec0 | 10861 | |
0eb79ad7 RZ |
10862 | if (get_config_int(pdata->config, "no_head", |
10863 | &config_val) == 0) | |
10864 | pbi->no_head = config_val; | |
10865 | else | |
10866 | pbi->no_head = no_head; | |
10867 | ||
0be1523d YL |
10868 | /*use ptr config for max_pic_w, etc*/ |
10869 | if (get_config_int(pdata->config, "vp9_max_pic_w", | |
10870 | &config_val) == 0) { | |
10871 | pbi->max_pic_w = config_val; | |
10872 | } | |
10873 | if (get_config_int(pdata->config, "vp9_max_pic_h", | |
10874 | &config_val) == 0) { | |
10875 | pbi->max_pic_h = config_val; | |
10876 | } | |
96b88a8a HZ |
10877 | if ((pbi->max_pic_w * pbi->max_pic_h) |
10878 | < (vp9_buf_width * vp9_buf_height)) { | |
10879 | pbi->max_pic_w = vp9_buf_width; | |
10880 | pbi->max_pic_h = vp9_buf_height; | |
10881 | vp9_print(pbi, 0, "use buf resolution\n"); | |
10882 | } | |
75803959 | 10883 | |
ae727791 | 10884 | if (get_config_int(pdata->config, "sidebind_type", |
10885 | &config_val) == 0) | |
10886 | pbi->sidebind_type = config_val; | |
10887 | ||
10888 | if (get_config_int(pdata->config, "sidebind_channel_id", | |
10889 | &config_val) == 0) | |
10890 | pbi->sidebind_channel_id = config_val; | |
10891 | ||
75803959 NQ |
10892 | if (get_config_int(pdata->config, |
10893 | "parm_v4l_codec_enable", | |
10894 | &config_val) == 0) | |
10895 | pbi->is_used_v4l = config_val; | |
10896 | ||
10897 | if (get_config_int(pdata->config, | |
10898 | "parm_v4l_buffer_margin", | |
10899 | &config_val) == 0) | |
10900 | pbi->dynamic_buf_num_margin = config_val; | |
9e4bad42 NQ |
10901 | |
10902 | if (get_config_int(pdata->config, | |
10903 | "parm_v4l_canvas_mem_mode", | |
10904 | &config_val) == 0) | |
10905 | pbi->mem_map_mode = config_val; | |
677ab50d NQ |
10906 | |
10907 | if (get_config_int(pdata->config, | |
10908 | "parm_enable_fence", | |
10909 | &config_val) == 0) | |
10910 | pbi->enable_fence = config_val; | |
10911 | ||
10912 | if (get_config_int(pdata->config, | |
10913 | "parm_fence_usage", | |
10914 | &config_val) == 0) | |
10915 | pbi->fence_usage = config_val; | |
fe96802b | 10916 | #endif |
d481db31 NQ |
10917 | if (get_config_int(pdata->config, "HDRStaticInfo", |
10918 | &vf_dp.present_flag) == 0 | |
10919 | && vf_dp.present_flag == 1) { | |
10920 | get_config_int(pdata->config, "mG.x", | |
10921 | &vf_dp.primaries[0][0]); | |
10922 | get_config_int(pdata->config, "mG.y", | |
10923 | &vf_dp.primaries[0][1]); | |
10924 | get_config_int(pdata->config, "mB.x", | |
10925 | &vf_dp.primaries[1][0]); | |
10926 | get_config_int(pdata->config, "mB.y", | |
10927 | &vf_dp.primaries[1][1]); | |
10928 | get_config_int(pdata->config, "mR.x", | |
10929 | &vf_dp.primaries[2][0]); | |
10930 | get_config_int(pdata->config, "mR.y", | |
10931 | &vf_dp.primaries[2][1]); | |
10932 | get_config_int(pdata->config, "mW.x", | |
10933 | &vf_dp.white_point[0]); | |
10934 | get_config_int(pdata->config, "mW.y", | |
10935 | &vf_dp.white_point[1]); | |
10936 | get_config_int(pdata->config, "mMaxDL", | |
10937 | &vf_dp.luminance[0]); | |
10938 | get_config_int(pdata->config, "mMinDL", | |
10939 | &vf_dp.luminance[1]); | |
10940 | vf_dp.content_light_level.present_flag = 1; | |
10941 | get_config_int(pdata->config, "mMaxCLL", | |
10942 | &content_light_level.max_content); | |
10943 | get_config_int(pdata->config, "mMaxFALL", | |
10944 | &content_light_level.max_pic_average); | |
10945 | vf_dp.content_light_level = content_light_level; | |
10946 | pbi->video_signal_type = (1 << 29) | |
10947 | | (5 << 26) /* unspecified */ | |
10948 | | (0 << 25) /* limit */ | |
10949 | | (1 << 24) /* color available */ | |
10950 | | (9 << 16) /* 2020 */ | |
10951 | | (16 << 8) /* 2084 */ | |
10952 | | (9 << 0); /* 2020 */ | |
10953 | } | |
10954 | pbi->vf_dp = vf_dp; | |
fe96802b NQ |
10955 | } else |
10956 | #endif | |
10957 | { | |
5c968d0b | 10958 | if (pdata->sys_info) { |
10959 | pbi->vvp9_amstream_dec_info = *pdata->sys_info; | |
10960 | if ((pbi->vvp9_amstream_dec_info.width != 0) && | |
10961 | (pbi->vvp9_amstream_dec_info.height != 0)) { | |
10962 | pbi->max_pic_w = pbi->vvp9_amstream_dec_info.width; | |
10963 | pbi->max_pic_h = pbi->vvp9_amstream_dec_info.height; | |
10964 | } | |
10965 | } | |
fe96802b NQ |
10966 | /*pbi->vvp9_amstream_dec_info.width = 0; |
10967 | pbi->vvp9_amstream_dec_info.height = 0; | |
10968 | pbi->vvp9_amstream_dec_info.rate = 30;*/ | |
10969 | pbi->double_write_mode = double_write_mode; | |
10970 | } | |
9e4bad42 | 10971 | |
677ab50d NQ |
10972 | if (no_head & 0x10) { |
10973 | pbi->no_head = (no_head & 0xf); | |
10974 | } | |
10975 | ||
9e4bad42 NQ |
10976 | if (!pbi->is_used_v4l) { |
10977 | pbi->mem_map_mode = mem_map_mode; | |
10978 | } | |
65ad8202 | 10979 | pbi->run_ready_min_buf_num = run_ready_min_buf_num; |
e0e39311 | 10980 | if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) { |
10981 | pr_err("over size: %dx%d, probe failed\n", | |
10982 | pbi->max_pic_w, pbi->max_pic_h); | |
10983 | return -1; | |
10984 | } | |
677ab50d NQ |
10985 | |
10986 | if (force_config_fence) { | |
10987 | pbi->enable_fence = true; | |
10988 | pbi->fence_usage = | |
10989 | (force_config_fence >> 4) & 0xf; | |
10990 | if (force_config_fence & 0x2) | |
10991 | pbi->enable_fence = false; | |
10992 | vp9_print(pbi, 0, "enable fence: %d, fence usage: %d\n", | |
10993 | pbi->enable_fence, pbi->fence_usage); | |
10994 | } | |
10995 | ||
10996 | if (pbi->enable_fence) | |
10997 | pdata->sync.usage = pbi->fence_usage; | |
10998 | ||
6276f4ff | 10999 | pbi->mmu_enable = 1; |
d481db31 | 11000 | video_signal_type = pbi->video_signal_type; |
2cd6815e | 11001 | |
0eb79ad7 | 11002 | if (pdata->sys_info) { |
2cd6815e | 11003 | pbi->vvp9_amstream_dec_info = *pdata->sys_info; |
0eb79ad7 | 11004 | } else { |
2cd6815e NQ |
11005 | pbi->vvp9_amstream_dec_info.width = 0; |
11006 | pbi->vvp9_amstream_dec_info.height = 0; | |
11007 | pbi->vvp9_amstream_dec_info.rate = 30; | |
11008 | } | |
dc4915e0 | 11009 | pbi->low_latency_flag = 1; |
2cd6815e | 11010 | |
0eb79ad7 RZ |
11011 | vp9_print(pbi, 0, |
11012 | "no_head %d low_latency %d\n", | |
11013 | pbi->no_head, pbi->low_latency_flag); | |
b9164398 NQ |
11014 | #if 0 |
11015 | pbi->buf_start = pdata->mem_start; | |
11016 | pbi->buf_size = pdata->mem_end - pdata->mem_start + 1; | |
11017 | #else | |
11018 | if (amvdec_vp9_mmu_init(pbi) < 0) { | |
11019 | pr_err("vp9 alloc bmmu box failed!!\n"); | |
fe96802b NQ |
11020 | /* devm_kfree(&pdev->dev, (void *)pbi); */ |
11021 | vfree((void *)pbi); | |
9b670a2d | 11022 | pdata->dec_status = NULL; |
b9164398 NQ |
11023 | return -1; |
11024 | } | |
11025 | ||
11026 | pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE; | |
fe96802b NQ |
11027 | ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID, |
11028 | pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME, | |
11029 | &pbi->cma_alloc_addr); | |
11030 | if (ret < 0) { | |
b9164398 | 11031 | uninit_mmu_buffers(pbi); |
fe96802b NQ |
11032 | /* devm_kfree(&pdev->dev, (void *)pbi); */ |
11033 | vfree((void *)pbi); | |
9b670a2d | 11034 | pdata->dec_status = NULL; |
fe96802b | 11035 | return ret; |
b9164398 NQ |
11036 | } |
11037 | pbi->buf_start = pbi->cma_alloc_addr; | |
11038 | pbi->buf_size = work_buf_size; | |
11039 | #endif | |
b9164398 NQ |
11040 | |
11041 | pbi->init_flag = 0; | |
ca482a9c | 11042 | pbi->first_sc_checked = 0; |
b9164398 NQ |
11043 | pbi->fatal_error = 0; |
11044 | pbi->show_frame_num = 0; | |
b9164398 NQ |
11045 | |
11046 | if (debug) { | |
fe96802b | 11047 | pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n", |
b9164398 | 11048 | pbi->buf_start, |
fe96802b | 11049 | pbi->buf_size); |
b9164398 NQ |
11050 | } |
11051 | ||
b9164398 | 11052 | pbi->cma_dev = pdata->cma_dev; |
c23e8aee | 11053 | if (vvp9_init(pdata) < 0) { |
b9164398 NQ |
11054 | pr_info("\namvdec_vp9 init failed.\n"); |
11055 | vp9_local_uninit(pbi); | |
11056 | uninit_mmu_buffers(pbi); | |
fe96802b NQ |
11057 | /* devm_kfree(&pdev->dev, (void *)pbi); */ |
11058 | vfree((void *)pbi); | |
9b670a2d | 11059 | pdata->dec_status = NULL; |
b9164398 NQ |
11060 | return -ENODEV; |
11061 | } | |
c23e8aee | 11062 | vdec_set_prepare_level(pdata, start_decode_buf_level); |
fe96802b NQ |
11063 | hevc_source_changed(VFORMAT_VP9, |
11064 | 4096, 2048, 60); | |
a6c89e96 NQ |
11065 | #ifdef SUPPORT_FB_DECODING |
11066 | if (pbi->used_stage_buf_num > 0) | |
11067 | vdec_core_request(pdata, | |
11068 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK); | |
11069 | else | |
11070 | vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC | |
11071 | | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK | |
11072 | | CORE_MASK_COMBINE); | |
11073 | #else | |
05afa03d PY |
11074 | if (pdata->parallel_dec == 1) |
11075 | vdec_core_request(pdata, CORE_MASK_HEVC); | |
11076 | else | |
a6c89e96 NQ |
11077 | vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
11078 | | CORE_MASK_COMBINE); | |
11079 | #endif | |
2cd6815e | 11080 | pbi->pic_list_init_done2 = true; |
677ab50d NQ |
11081 | |
11082 | if (pbi->enable_fence) { | |
11083 | /* creat timeline. */ | |
11084 | vdec_timeline_create(&pdata->sync, DRIVER_NAME); | |
11085 | } | |
11086 | ||
b9164398 NQ |
11087 | return 0; |
11088 | } | |
11089 | ||
11090 | static int ammvdec_vp9_remove(struct platform_device *pdev) | |
11091 | { | |
11092 | struct VP9Decoder_s *pbi = (struct VP9Decoder_s *) | |
11093 | (((struct vdec_s *)(platform_get_drvdata(pdev)))->private); | |
05afa03d PY |
11094 | struct vdec_s *vdec = hw_to_vdec(pbi); |
11095 | int i; | |
b9164398 NQ |
11096 | if (debug) |
11097 | pr_info("amvdec_vp9_remove\n"); | |
11098 | ||
c23e8aee | 11099 | vmvp9_stop(pbi); |
b9164398 | 11100 | |
a6c89e96 NQ |
11101 | #ifdef SUPPORT_FB_DECODING |
11102 | vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC | |
11103 | | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK | |
11104 | ); | |
11105 | #else | |
05afa03d PY |
11106 | if (vdec->parallel_dec == 1) |
11107 | vdec_core_release(hw_to_vdec(pbi), CORE_MASK_HEVC); | |
11108 | else | |
11109 | vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC); | |
a6c89e96 | 11110 | #endif |
b9164398 NQ |
11111 | vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED); |
11112 | ||
05afa03d PY |
11113 | if (vdec->parallel_dec == 1) { |
11114 | for (i = 0; i < FRAME_BUFFERS; i++) { | |
11115 | vdec->free_canvas_ex | |
11116 | (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index, | |
11117 | vdec->id); | |
11118 | vdec->free_canvas_ex | |
11119 | (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index, | |
11120 | vdec->id); | |
11121 | } | |
11122 | } | |
11123 | ||
677ab50d NQ |
11124 | if (pbi->enable_fence) |
11125 | vdec_fence_release(pbi, &vdec->sync); | |
b9164398 NQ |
11126 | |
11127 | #ifdef DEBUG_PTS | |
11128 | pr_info("pts missed %ld, pts hit %ld, duration %d\n", | |
11129 | pbi->pts_missed, pbi->pts_hit, pbi->frame_dur); | |
11130 | #endif | |
0fb7e163 NQ |
11131 | mem_map_mode = 0; |
11132 | ||
fe96802b NQ |
11133 | /* devm_kfree(&pdev->dev, (void *)pbi); */ |
11134 | vfree((void *)pbi); | |
b9164398 NQ |
11135 | return 0; |
11136 | } | |
11137 | ||
11138 | static struct platform_driver ammvdec_vp9_driver = { | |
11139 | .probe = ammvdec_vp9_probe, | |
11140 | .remove = ammvdec_vp9_remove, | |
b9164398 NQ |
11141 | .driver = { |
11142 | .name = MULTI_DRIVER_NAME, | |
1cb8d0da NQ |
11143 | #ifdef CONFIG_PM |
11144 | .pm = &vp9_pm_ops, | |
11145 | #endif | |
b9164398 NQ |
11146 | } |
11147 | }; | |
11148 | #endif | |
fe96802b NQ |
11149 | static struct mconfig vp9_configs[] = { |
11150 | MC_PU32("bit_depth_luma", &bit_depth_luma), | |
11151 | MC_PU32("bit_depth_chroma", &bit_depth_chroma), | |
11152 | MC_PU32("frame_width", &frame_width), | |
11153 | MC_PU32("frame_height", &frame_height), | |
11154 | MC_PU32("debug", &debug), | |
11155 | MC_PU32("radr", &radr), | |
11156 | MC_PU32("rval", &rval), | |
11157 | MC_PU32("pop_shorts", &pop_shorts), | |
11158 | MC_PU32("dbg_cmd", &dbg_cmd), | |
11159 | MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index), | |
11160 | MC_PU32("endian", &endian), | |
11161 | MC_PU32("step", &step), | |
11162 | MC_PU32("udebug_flag", &udebug_flag), | |
11163 | MC_PU32("decode_pic_begin", &decode_pic_begin), | |
11164 | MC_PU32("slice_parse_begin", &slice_parse_begin), | |
11165 | MC_PU32("i_only_flag", &i_only_flag), | |
11166 | MC_PU32("error_handle_policy", &error_handle_policy), | |
11167 | MC_PU32("buf_alloc_width", &buf_alloc_width), | |
11168 | MC_PU32("buf_alloc_height", &buf_alloc_height), | |
11169 | MC_PU32("buf_alloc_depth", &buf_alloc_depth), | |
11170 | MC_PU32("buf_alloc_size", &buf_alloc_size), | |
11171 | MC_PU32("buffer_mode", &buffer_mode), | |
11172 | MC_PU32("buffer_mode_dbg", &buffer_mode_dbg), | |
dfe41deb | 11173 | MC_PU32("max_buf_num", &max_buf_num), |
fe96802b NQ |
11174 | MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin), |
11175 | MC_PU32("mem_map_mode", &mem_map_mode), | |
11176 | MC_PU32("double_write_mode", &double_write_mode), | |
11177 | MC_PU32("enable_mem_saving", &enable_mem_saving), | |
11178 | MC_PU32("force_w_h", &force_w_h), | |
11179 | MC_PU32("force_fps", &force_fps), | |
11180 | MC_PU32("max_decoding_time", &max_decoding_time), | |
11181 | MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped), | |
11182 | MC_PU32("start_decode_buf_level", &start_decode_buf_level), | |
11183 | MC_PU32("decode_timeout_val", &decode_timeout_val), | |
a6c89e96 NQ |
11184 | MC_PU32("vp9_max_pic_w", &vp9_max_pic_w), |
11185 | MC_PU32("vp9_max_pic_h", &vp9_max_pic_h), | |
fe96802b NQ |
11186 | }; |
11187 | static struct mconfig_node vp9_node; | |
b9164398 NQ |
11188 | |
11189 | static int __init amvdec_vp9_driver_init_module(void) | |
11190 | { | |
fe96802b | 11191 | |
fe96802b | 11192 | struct BuffInfo_s *p_buf_info; |
df841122 | 11193 | |
11194 | if (vdec_is_support_4k()) { | |
6f5ee885 | 11195 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) |
df841122 | 11196 | p_buf_info = &amvvp9_workbuff_spec[2]; |
11197 | else | |
11198 | p_buf_info = &amvvp9_workbuff_spec[1]; | |
11199 | } else | |
c23e8aee | 11200 | p_buf_info = &amvvp9_workbuff_spec[0]; |
df841122 | 11201 | |
fe96802b NQ |
11202 | init_buff_spec(NULL, p_buf_info); |
11203 | work_buf_size = | |
11204 | (p_buf_info->end_adr - p_buf_info->start_adr | |
11205 | + 0xffff) & (~0xffff); | |
11206 | ||
b9164398 | 11207 | pr_debug("amvdec_vp9 module init\n"); |
b7706e1e | 11208 | |
b9164398 NQ |
11209 | error_handle_policy = 0; |
11210 | ||
11211 | #ifdef ERROR_HANDLE_DEBUG | |
11212 | dbg_nal_skip_flag = 0; | |
11213 | dbg_nal_skip_count = 0; | |
11214 | #endif | |
fe96802b | 11215 | udebug_flag = 0; |
b9164398 NQ |
11216 | decode_pic_begin = 0; |
11217 | slice_parse_begin = 0; | |
11218 | step = 0; | |
11219 | buf_alloc_size = 0; | |
11220 | #ifdef MULTI_INSTANCE_SUPPORT | |
11221 | if (platform_driver_register(&ammvdec_vp9_driver)) | |
11222 | pr_err("failed to register ammvdec_vp9 driver\n"); | |
11223 | ||
11224 | #endif | |
11225 | if (platform_driver_register(&amvdec_vp9_driver)) { | |
11226 | pr_err("failed to register amvdec_vp9 driver\n"); | |
11227 | return -ENODEV; | |
11228 | } | |
11229 | ||
6f5ee885 | 11230 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) { |
e0e39311 | 11231 | amvdec_vp9_profile.profile = |
51c859b2 | 11232 | "8k, 10bit, dwrite, compressed, fence"; |
e0e39311 | 11233 | } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL |
678a5126 JW |
11234 | /*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/ |
11235 | && get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TXL) { | |
0eb79ad7 RZ |
11236 | if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) { |
11237 | if (vdec_is_support_4k()) | |
11238 | amvdec_vp9_profile.profile = | |
51c859b2 | 11239 | "4k, 10bit, dwrite, compressed, fence"; |
0eb79ad7 RZ |
11240 | else |
11241 | amvdec_vp9_profile.profile = | |
51c859b2 | 11242 | "10bit, dwrite, compressed, fence"; |
0eb79ad7 RZ |
11243 | } else { |
11244 | if (vdec_is_support_4k()) | |
11245 | amvdec_vp9_profile.profile = | |
51c859b2 | 11246 | "4k, 10bit, dwrite, compressed, fence"; |
0eb79ad7 RZ |
11247 | else |
11248 | amvdec_vp9_profile.profile = | |
51c859b2 | 11249 | "10bit, dwrite, compressed, fence"; |
0eb79ad7 RZ |
11250 | } |
11251 | ||
b9164398 NQ |
11252 | } else { |
11253 | amvdec_vp9_profile.name = "vp9_unsupport"; | |
11254 | } | |
11255 | ||
c4ea7ef3 | 11256 | if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) |
dfe41deb | 11257 | max_buf_num = MAX_BUF_NUM_LESS; |
c4ea7ef3 | 11258 | |
b9164398 | 11259 | vcodec_profile_register(&amvdec_vp9_profile); |
9457f9af NQ |
11260 | amvdec_vp9_profile_mult = amvdec_vp9_profile; |
11261 | amvdec_vp9_profile_mult.name = "mvp9"; | |
11262 | vcodec_profile_register(&amvdec_vp9_profile_mult); | |
fe96802b NQ |
11263 | INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node, |
11264 | "vp9", vp9_configs, CONFIG_FOR_RW); | |
b9164398 NQ |
11265 | |
11266 | return 0; | |
11267 | } | |
11268 | ||
11269 | static void __exit amvdec_vp9_driver_remove_module(void) | |
11270 | { | |
11271 | pr_debug("amvdec_vp9 module remove.\n"); | |
11272 | #ifdef MULTI_INSTANCE_SUPPORT | |
11273 | platform_driver_unregister(&ammvdec_vp9_driver); | |
11274 | #endif | |
11275 | platform_driver_unregister(&amvdec_vp9_driver); | |
11276 | } | |
11277 | ||
11278 | /****************************************/ | |
b9164398 NQ |
11279 | |
11280 | module_param(bit_depth_luma, uint, 0664); | |
11281 | MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n"); | |
11282 | ||
11283 | module_param(bit_depth_chroma, uint, 0664); | |
11284 | MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n"); | |
11285 | ||
11286 | module_param(frame_width, uint, 0664); | |
11287 | MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n"); | |
11288 | ||
11289 | module_param(frame_height, uint, 0664); | |
11290 | MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n"); | |
11291 | ||
11292 | module_param(debug, uint, 0664); | |
11293 | MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n"); | |
11294 | ||
11295 | module_param(radr, uint, 0664); | |
fe96802b | 11296 | MODULE_PARM_DESC(radr, "\n radr\n"); |
b9164398 NQ |
11297 | |
11298 | module_param(rval, uint, 0664); | |
fe96802b | 11299 | MODULE_PARM_DESC(rval, "\n rval\n"); |
b9164398 NQ |
11300 | |
11301 | module_param(pop_shorts, uint, 0664); | |
fe96802b | 11302 | MODULE_PARM_DESC(pop_shorts, "\n rval\n"); |
b9164398 NQ |
11303 | |
11304 | module_param(dbg_cmd, uint, 0664); | |
fe96802b | 11305 | MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n"); |
b9164398 NQ |
11306 | |
11307 | module_param(dbg_skip_decode_index, uint, 0664); | |
fe96802b | 11308 | MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n"); |
b9164398 NQ |
11309 | |
11310 | module_param(endian, uint, 0664); | |
fe96802b | 11311 | MODULE_PARM_DESC(endian, "\n rval\n"); |
b9164398 NQ |
11312 | |
11313 | module_param(step, uint, 0664); | |
11314 | MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n"); | |
11315 | ||
b9164398 NQ |
11316 | module_param(decode_pic_begin, uint, 0664); |
11317 | MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n"); | |
11318 | ||
11319 | module_param(slice_parse_begin, uint, 0664); | |
11320 | MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n"); | |
11321 | ||
11322 | module_param(i_only_flag, uint, 0664); | |
11323 | MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n"); | |
11324 | ||
187af067 | 11325 | module_param(low_latency_flag, uint, 0664); |
11326 | MODULE_PARM_DESC(low_latency_flag, "\n amvdec_vp9 low_latency_flag\n"); | |
11327 | ||
0eb79ad7 RZ |
11328 | module_param(no_head, uint, 0664); |
11329 | MODULE_PARM_DESC(no_head, "\n amvdec_vp9 no_head\n"); | |
11330 | ||
b9164398 NQ |
11331 | module_param(error_handle_policy, uint, 0664); |
11332 | MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n"); | |
11333 | ||
11334 | module_param(buf_alloc_width, uint, 0664); | |
11335 | MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n"); | |
11336 | ||
11337 | module_param(buf_alloc_height, uint, 0664); | |
11338 | MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n"); | |
11339 | ||
11340 | module_param(buf_alloc_depth, uint, 0664); | |
11341 | MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n"); | |
11342 | ||
11343 | module_param(buf_alloc_size, uint, 0664); | |
11344 | MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n"); | |
11345 | ||
11346 | module_param(buffer_mode, uint, 0664); | |
11347 | MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n"); | |
11348 | ||
11349 | module_param(buffer_mode_dbg, uint, 0664); | |
11350 | MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n"); | |
11351 | /*USE_BUF_BLOCK*/ | |
dfe41deb RZ |
11352 | module_param(max_buf_num, uint, 0664); |
11353 | MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n"); | |
11354 | ||
b9164398 NQ |
11355 | module_param(dynamic_buf_num_margin, uint, 0664); |
11356 | MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n"); | |
fe96802b NQ |
11357 | |
11358 | module_param(mv_buf_margin, uint, 0664); | |
11359 | MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n"); | |
11360 | ||
11361 | module_param(run_ready_min_buf_num, uint, 0664); | |
11362 | MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n"); | |
11363 | ||
b9164398 NQ |
11364 | /**/ |
11365 | ||
11366 | module_param(mem_map_mode, uint, 0664); | |
11367 | MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n"); | |
11368 | ||
11369 | #ifdef SUPPORT_10BIT | |
11370 | module_param(double_write_mode, uint, 0664); | |
11371 | MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n"); | |
11372 | ||
11373 | module_param(enable_mem_saving, uint, 0664); | |
11374 | MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n"); | |
11375 | ||
11376 | module_param(force_w_h, uint, 0664); | |
11377 | MODULE_PARM_DESC(force_w_h, "\n force_w_h\n"); | |
11378 | #endif | |
11379 | ||
11380 | module_param(force_fps, uint, 0664); | |
11381 | MODULE_PARM_DESC(force_fps, "\n force_fps\n"); | |
11382 | ||
11383 | module_param(max_decoding_time, uint, 0664); | |
11384 | MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n"); | |
11385 | ||
11386 | module_param(on_no_keyframe_skiped, uint, 0664); | |
11387 | MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n"); | |
11388 | ||
c23e8aee HZ |
11389 | module_param(mcrcc_cache_alg_flag, uint, 0664); |
11390 | MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n"); | |
11391 | ||
b9164398 | 11392 | #ifdef MULTI_INSTANCE_SUPPORT |
fe96802b | 11393 | module_param(start_decode_buf_level, int, 0664); |
b9164398 | 11394 | MODULE_PARM_DESC(start_decode_buf_level, |
fe96802b NQ |
11395 | "\n vp9 start_decode_buf_level\n"); |
11396 | ||
11397 | module_param(decode_timeout_val, uint, 0664); | |
11398 | MODULE_PARM_DESC(decode_timeout_val, | |
11399 | "\n vp9 decode_timeout_val\n"); | |
11400 | ||
a6c89e96 NQ |
11401 | module_param(vp9_max_pic_w, uint, 0664); |
11402 | MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n"); | |
11403 | ||
11404 | module_param(vp9_max_pic_h, uint, 0664); | |
11405 | MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n"); | |
11406 | ||
fe96802b NQ |
11407 | module_param_array(decode_frame_count, uint, |
11408 | &max_decode_instance_num, 0664); | |
11409 | ||
11410 | module_param_array(display_frame_count, uint, | |
11411 | &max_decode_instance_num, 0664); | |
11412 | ||
11413 | module_param_array(max_process_time, uint, | |
11414 | &max_decode_instance_num, 0664); | |
11415 | ||
11416 | module_param_array(run_count, uint, | |
11417 | &max_decode_instance_num, 0664); | |
11418 | ||
11419 | module_param_array(input_empty, uint, | |
11420 | &max_decode_instance_num, 0664); | |
11421 | ||
11422 | module_param_array(not_run_ready, uint, | |
11423 | &max_decode_instance_num, 0664); | |
b9164398 NQ |
11424 | #endif |
11425 | ||
a6c89e96 NQ |
11426 | #ifdef SUPPORT_FB_DECODING |
11427 | module_param_array(not_run2_ready, uint, | |
11428 | &max_decode_instance_num, 0664); | |
11429 | ||
11430 | module_param_array(run2_count, uint, | |
11431 | &max_decode_instance_num, 0664); | |
11432 | ||
11433 | module_param(stage_buf_num, uint, 0664); | |
11434 | MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n"); | |
11435 | #endif | |
11436 | ||
fe96802b NQ |
11437 | module_param(udebug_flag, uint, 0664); |
11438 | MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n"); | |
11439 | ||
11440 | module_param(udebug_pause_pos, uint, 0664); | |
11441 | MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n"); | |
11442 | ||
11443 | module_param(udebug_pause_val, uint, 0664); | |
11444 | MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n"); | |
11445 | ||
11446 | module_param(udebug_pause_decode_idx, uint, 0664); | |
11447 | MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n"); | |
11448 | ||
7c2956be PY |
11449 | module_param(without_display_mode, uint, 0664); |
11450 | MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n"); | |
11451 | ||
677ab50d NQ |
11452 | module_param(force_config_fence, uint, 0664); |
11453 | MODULE_PARM_DESC(force_config_fence, "\n force enable fence\n"); | |
11454 | ||
65ad8202 GZ |
11455 | module_param(force_pts_unstable, uint, 0664); |
11456 | MODULE_PARM_DESC(force_pts_unstable, "\n force_pts_unstable\n"); | |
11457 | ||
b9164398 NQ |
11458 | module_init(amvdec_vp9_driver_init_module); |
11459 | module_exit(amvdec_vp9_driver_remove_module); | |
11460 | ||
11461 | MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver"); | |
11462 | MODULE_LICENSE("GPL"); | |
a6c89e96 | 11463 |