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media_module: mh264/h265/avs2 [2/2]
[GitHub/LineageOS/G12/android_hardware_amlogic_kernel-modules_media.git] / drivers / frame_provider / decoder / h264 / vh264.c
CommitLineData
b9164398
NQ		 1/*
2 * drivers/amlogic/media/frame_provider/decoder/h264/vh264.c
3 *
4 * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
e0614bf7 16 */
b9164398 17
5b851ff9 18#define DEBUG
b9164398
NQ		 19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/timer.h>
24#include <linux/kfifo.h>
25#include <linux/platform_device.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include <linux/amlogic/media/vfm/vframe_provider.h>
31#include <linux/amlogic/media/vfm/vframe_receiver.h>
32#include <linux/amlogic/media/utils/vformat.h>
33#include <linux/amlogic/media/frame_sync/tsync.h>
34#include <linux/workqueue.h>
35#include <linux/dma-mapping.h>
36#include <linux/atomic.h>
37#include <linux/module.h>
38#include <linux/slab.h>
39#include "../../../stream_input/amports/amports_priv.h"
40#include <linux/amlogic/media/canvas/canvas.h>
b9164398
NQ		 41
42#include "../utils/vdec.h"
43#include <linux/amlogic/media/utils/vdec_reg.h>
44#include "../utils/amvdec.h"
b9164398
NQ		 45#include "vh264.h"
46#include "../../../stream_input/parser/streambuf.h"
47#include <linux/delay.h>
48#include <linux/amlogic/media/video_sink/video.h>
8247f369 49#include <linux/amlogic/tee.h>
b9164398 50#include <linux/amlogic/media/ge2d/ge2d.h>
fe96802b
NQ		 51#include "../utils/decoder_mmu_box.h"
52#include "../utils/decoder_bmmu_box.h"
53#include <linux/amlogic/media/codec_mm/codec_mm.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
6fff1c64 55#include "../utils/firmware.h"
d481db31 56#include <linux/amlogic/tee.h>
63e810c0 57#include "../../../common/chips/decoder_cpu_ver_info.h"
9cc3c918
RZ		 58#include <linux/uaccess.h>
59
b9164398 60
a093654a
TG		 61#include <trace/events/meson_atrace.h>
62
63
b9164398
NQ		 64#define DRIVER_NAME "amvdec_h264"
65#define MODULE_NAME "amvdec_h264"
66#define MEM_NAME "codec_264"
67#define HANDLE_H264_IRQ
d481db31
NQ		 68
69#if 0
70/* currently, only iptv supports this function*/
71#define SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY
72#endif
73
b9164398
NQ		 74/* #define DEBUG_PTS */
75#if 0 /* MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6TV */
76#define DROP_B_FRAME_FOR_1080P_50_60FPS
77#endif
78#define RATE_MEASURE_NUM 8
79#define RATE_CORRECTION_THRESHOLD 5
80#define RATE_24_FPS 4004 /* 23.97 */
81#define RATE_25_FPS 3840 /* 25 */
82#define DUR2PTS(x) ((x)*90/96)
83#define PTS2DUR(x) ((x)*96/90)
84#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
85#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
f8537a67 86#define VDEC_CLOCK_ADJUST_FRAME 30
b9164398
NQ		 87
88static inline bool close_to(int a, int b, int m)
89{
90 return (abs(a - b) < m) ? true : false;
91}
92
93static DEFINE_MUTEX(vh264_mutex);
b9164398
NQ		 94#define DEF_BUF_START_ADDR 0x1000000
95#define V_BUF_ADDR_OFFSET_NEW (0x1ee000)
96#define V_BUF_ADDR_OFFSET (0x13e000)
97
98#define PIC_SINGLE_FRAME 0
99#define PIC_TOP_BOT_TOP 1
100#define PIC_BOT_TOP_BOT 2
101#define PIC_DOUBLE_FRAME 3
102#define PIC_TRIPLE_FRAME 4
103#define PIC_TOP_BOT 5
104#define PIC_BOT_TOP 6
105#define PIC_INVALID 7
106
107#define EXTEND_SAR 0xff
108
109#define VF_POOL_SIZE 64
110#define VF_BUF_NUM 24
fe96802b 111#define WORKSPACE_BUF_NUM 2
b9164398
NQ		 112#define PUT_INTERVAL (HZ/100)
113#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
114
115#define SWITCHING_STATE_OFF 0
116#define SWITCHING_STATE_ON_CMD3 1
117#define SWITCHING_STATE_ON_CMD1 2
118#define SWITCHING_STATE_ON_CMD1_PENDING 3
119
120
121#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
122#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
123#define DEC_CONTROL_FLAG_DISABLE_FAST_POC 0x0004
124
125#define INCPTR(p) ptr_atomic_wrap_inc(&p)
126
127#define SLICE_TYPE_I 2
128#define SLICE_TYPE_P 5
129#define SLICE_TYPE_B 6
130
131struct buffer_spec_s {
132 unsigned int y_addr;
133 unsigned int u_addr;
134 unsigned int v_addr;
135
136 int y_canvas_index;
137 int u_canvas_index;
138 int v_canvas_index;
139
140 unsigned int y_canvas_width;
141 unsigned int u_canvas_width;
142 unsigned int v_canvas_width;
143
144 unsigned int y_canvas_height;
145 unsigned int u_canvas_height;
146 unsigned int v_canvas_height;
147
148 unsigned long phy_addr;
149 int alloc_count;
150};
151
152#define spec2canvas(x) \
153 (((x)->v_canvas_index << 16) | \
154 ((x)->u_canvas_index << 8) | \
155 ((x)->y_canvas_index << 0))
156
157static struct vframe_s *vh264_vf_peek(void *);
158static struct vframe_s *vh264_vf_get(void *);
159static void vh264_vf_put(struct vframe_s *, void *);
160static int vh264_vf_states(struct vframe_states *states, void *);
161static int vh264_event_cb(int type, void *data, void *private_data);
162
163static void vh264_prot_init(void);
fe96802b 164static int vh264_local_init(void);
b9164398
NQ		 165static void vh264_put_timer_func(unsigned long arg);
166static void stream_switching_done(void);
167
168static const char vh264_dec_id[] = "vh264-dev";
169
170#define PROVIDER_NAME "decoder.h264"
171
172static const struct vframe_operations_s vh264_vf_provider_ops = {
173 .peek = vh264_vf_peek,
174 .get = vh264_vf_get,
175 .put = vh264_vf_put,
176 .event_cb = vh264_event_cb,
177 .vf_states = vh264_vf_states,
178};
179
180static struct vframe_provider_s vh264_vf_prov;
181/*TODO irq*/
182#if 1
b9164398
NQ		 183static u32 frame_width, frame_height, frame_dur, frame_prog, frame_packing_type,
184 last_duration;
185static u32 saved_resolution;
186static u32 last_mb_width, last_mb_height;
187#else
188static u32 frame_buffer_size;
189static u32 frame_width, frame_height, frame_dur, frame_prog, last_duration;
190static u32 last_mb_width, last_mb_height;
191static u32 frame_packing_type;
192#endif
193static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
194static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
195static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE);
196static DECLARE_KFIFO(delay_display_q, struct vframe_s *, VF_POOL_SIZE);
197
198static struct vframe_s vfpool[VF_POOL_SIZE];
199static s32 vfbuf_use[VF_BUF_NUM];
200static struct buffer_spec_s buffer_spec[VF_BUF_NUM];
201static struct buffer_spec_s fense_buffer_spec[2];
fe96802b
NQ		 202/* disp buf + keep buf+ fense buf + workspace */
203
204#define MAX_BLK_BUFFERS (VF_BUF_NUM + 2 + WORKSPACE_BUF_NUM)
205#define VF_BUFFER_IDX(n) (WORKSPACE_BUF_NUM + n)
206#define FENSE_BUFFER_IDX(n) (WORKSPACE_BUF_NUM + VF_BUF_NUM + n)
207
208#define USER_DATA_RUND_SIZE (USER_DATA_SIZE + 4096)
b9164398
NQ		 209static struct vframe_s fense_vf[2];
210
211static struct timer_list recycle_timer;
212static u32 stat;
b9164398 213static s32 buf_offset;
b9164398
NQ		 214static u32 pts_outside;
215static u32 sync_outside;
216static u32 dec_control;
217static u32 vh264_ratio;
218static u32 vh264_rotation;
219static u32 use_idr_framerate;
e0614bf7 220static u32 high_bandwidth;
b9164398
NQ		 221
222static u32 seq_info;
223static u32 timing_info_present_flag;
224static u32 fixed_frame_rate_flag;
225static u32 fixed_frame_rate_check_count;
226static u32 aspect_ratio_info;
227static u32 num_units_in_tick;
228static u32 time_scale;
229static u32 h264_ar;
230static u32 decoder_debug_flag;
231static u32 dpb_size_adj = 6;
fe96802b 232static u32 fr_hint_status;
b9164398
NQ		 233
234#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS
235static u32 last_interlaced;
236#endif
237static bool is_4k;
238static unsigned char h264_first_pts_ready;
239static bool h264_first_valid_pts_ready;
240static u32 h264pts1, h264pts2;
241static u32 h264_pts_count, duration_from_pts_done, duration_on_correcting;
242static u32 vh264_error_count;
243static u32 vh264_no_disp_count;
244static u32 fatal_error_flag;
245static u32 fatal_error_reset;
246static u32 max_refer_buf = 1;
247static u32 decoder_force_reset;
248static unsigned int no_idr_error_count;
249static unsigned int no_idr_error_max = 60;
8458676f 250static unsigned int canvas_mode;
251
d481db31
NQ		 252#ifdef SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY
253/* 0~128*/
254static u32 bad_block_scale;
255#endif
9cc3c918 256static u32 enable_userdata_debug;
d481db31 257
b9164398
NQ		 258static unsigned int enable_switch_fense = 1;
259#define EN_SWITCH_FENCE() (enable_switch_fense && !is_4k)
a8f62ee0
RZ		 260static struct vframe_qos_s s_vframe_qos;
261static int frame_count;
262
b9164398
NQ		 263#if 0
264static u32 vh264_no_disp_wd_count;
265#endif
266static u32 vh264_running;
267static s32 vh264_stream_switching_state;
268static s32 vh264_eos;
269static struct vframe_s *p_last_vf;
270static s32 iponly_early_mode;
271static void *mm_blk_handle;
fe96802b 272static int tvp_flag;
d481db31 273static bool is_reset;
b9164398
NQ		 274
275/*TODO irq*/
276#if 1
277static u32 last_pts, last_pts_remainder;
278#else
279static u32 last_pts;
280#endif
281static bool check_pts_discontinue;
282static u32 wait_buffer_counter;
283static u32 video_signal_from_vui;
284
285static uint error_recovery_mode;
286static uint error_recovery_mode_in = 3;
287static uint error_recovery_mode_use = 3;
288
289static uint mb_total = 0, mb_width = 0, mb_height;
290static uint saved_idc_level;
291#define UCODE_IP_ONLY 2
292#define UCODE_IP_ONLY_PARAM 1
293static uint ucode_type;
294
295#ifdef DEBUG_PTS
296static unsigned long pts_missed, pts_hit;
297#endif
298static uint debugfirmware;
299
300static atomic_t vh264_active = ATOMIC_INIT(0);
301static int vh264_reset;
302static struct work_struct error_wd_work;
303static struct work_struct stream_switching_work;
304static struct work_struct set_parameter_work;
fe96802b 305static struct work_struct notify_work;
a994f6d6 306static struct work_struct set_clk_work;
fe96802b
NQ		 307static struct work_struct userdata_push_work;
308
a8f62ee0
RZ		 309struct h264_qos_data_node_t {
310 struct list_head list;
311
312 uint32_t b_offset;
313 int poc;
314 /* picture qos infomation*/
315 int max_qp;
316 int avg_qp;
317 int min_qp;
318 int max_skip;
319 int avg_skip;
320 int min_skip;
321 int max_mv;
322 int min_mv;
323 int avg_mv;
324};
fe96802b 325
a8f62ee0
RZ		 326/*qos data records list waiting for match with picture that be display*/
327static struct list_head picture_qos_list;
328/*free qos data records list*/
329static struct list_head free_qos_nodes_list;
330#define MAX_FREE_QOS_NODES 64
331static struct h264_qos_data_node_t free_nodes[MAX_FREE_QOS_NODES];
332static struct work_struct qos_work;
b9164398
NQ		 333static struct dec_sysinfo vh264_amstream_dec_info;
334static dma_addr_t mc_dma_handle;
335static void *mc_cpu_addr;
336static u32 first_offset;
337static u32 first_pts;
a8f62ee0 338static u32 first_frame_size;
b9164398
NQ		 339static u64 first_pts64;
340static bool first_pts_cached;
341static void *sei_data_buffer;
342static dma_addr_t sei_data_buffer_phys;
343static int clk_adj_frame_count;
344
345#define MC_OFFSET_HEADER 0x0000
346#define MC_OFFSET_DATA 0x1000
347#define MC_OFFSET_MMCO 0x2000
348#define MC_OFFSET_LIST 0x3000
349#define MC_OFFSET_SLICE 0x4000
350
351#define MC_TOTAL_SIZE (20*SZ_1K)
352#define MC_SWAP_SIZE (4*SZ_1K)
353
354#define MODE_ERROR 0
355#define MODE_FULL 1
356
357static DEFINE_SPINLOCK(lock);
358static DEFINE_SPINLOCK(prepare_lock);
359static DEFINE_SPINLOCK(recycle_lock);
360
361static bool block_display_q;
362static int vh264_stop(int mode);
363static s32 vh264_init(void);
364
8458676f 365
b9164398
NQ		 366#define DFS_HIGH_THEASHOLD 3
367
368static bool pts_discontinue;
369
370static struct ge2d_context_s *ge2d_videoh264_context;
371
fe96802b
NQ		 372static struct vdec_info *gvs;
373
9cc3c918
RZ		 374static struct vdec_s *vdec_h264;
375
b9164398
NQ		 376static int ge2d_videoh264task_init(void)
377{
378 if (ge2d_videoh264_context == NULL)
379 ge2d_videoh264_context = create_ge2d_work_queue();
380
381 if (ge2d_videoh264_context == NULL) {
382 pr_info("create_ge2d_work_queue video task failed\n");
383 return -1;
384 }
385 return 0;
386}
387
388static int ge2d_videoh264task_release(void)
389{
390 if (ge2d_videoh264_context) {
391 destroy_ge2d_work_queue(ge2d_videoh264_context);
392 ge2d_videoh264_context = NULL;
393 }
394 return 0;
395}
396
397static int ge2d_canvas_dup(struct canvas_s *srcy, struct canvas_s *srcu,
398 struct canvas_s *des, int format, u32 srcindex,
399 u32 desindex)
400{
401
402 struct config_para_ex_s ge2d_config;
403 /* pr_info("[%s]h264 ADDR srcy[0x%lx] srcu[0x%lx] des[0x%lx]\n",
e0614bf7
ZZ		 404 * __func__, srcy->addr, srcu->addr, des->addr);
405 */
b9164398
NQ		 406 memset(&ge2d_config, 0, sizeof(struct config_para_ex_s));
407
408 ge2d_config.alu_const_color = 0;
409 ge2d_config.bitmask_en = 0;
410 ge2d_config.src1_gb_alpha = 0;
411
412 ge2d_config.src_planes[0].addr = srcy->addr;
413 ge2d_config.src_planes[0].w = srcy->width;
414 ge2d_config.src_planes[0].h = srcy->height;
415
416 ge2d_config.src_planes[1].addr = srcu->addr;
417 ge2d_config.src_planes[1].w = srcu->width;
418 ge2d_config.src_planes[1].h = srcu->height;
419
420 ge2d_config.dst_planes[0].addr = des->addr;
421 ge2d_config.dst_planes[0].w = des->width;
422 ge2d_config.dst_planes[0].h = des->height;
423
424 ge2d_config.src_para.canvas_index = srcindex;
425 ge2d_config.src_para.mem_type = CANVAS_TYPE_INVALID;
426 ge2d_config.src_para.format = format;
427 ge2d_config.src_para.fill_color_en = 0;
428 ge2d_config.src_para.fill_mode = 0;
429 ge2d_config.src_para.color = 0;
430 ge2d_config.src_para.top = 0;
431 ge2d_config.src_para.left = 0;
432 ge2d_config.src_para.width = srcy->width;
433 ge2d_config.src_para.height = srcy->height;
434
435 ge2d_config.dst_para.canvas_index = desindex;
436 ge2d_config.dst_para.mem_type = CANVAS_TYPE_INVALID;
437 ge2d_config.dst_para.format = format;
438 ge2d_config.dst_para.fill_color_en = 0;
439 ge2d_config.dst_para.fill_mode = 0;
440 ge2d_config.dst_para.color = 0;
441 ge2d_config.dst_para.top = 0;
442 ge2d_config.dst_para.left = 0;
443 ge2d_config.dst_para.width = srcy->width;
444 ge2d_config.dst_para.height = srcy->height;
445
446 if (ge2d_context_config_ex(ge2d_videoh264_context, &ge2d_config) < 0) {
447 pr_info("ge2d_context_config_ex failed\n");
448 return -1;
449 }
450
451 stretchblt_noalpha(ge2d_videoh264_context, 0, 0, srcy->width,
452 srcy->height, 0, 0, srcy->width, srcy->height);
453
454 return 0;
455}
456
457static inline int fifo_level(void)
458{
459 return VF_POOL_SIZE - kfifo_len(&newframe_q);
460}
461
462
463void spec_set_canvas(struct buffer_spec_s *spec,
e0614bf7 464 unsigned int width, unsigned int height)
b9164398 465{
8458676f 466 int endian;
467
468 endian = (canvas_mode == CANVAS_BLKMODE_LINEAR)?7:0;
469 canvas_config_ex(spec->y_canvas_index,
b9164398
NQ		 470 spec->y_addr,
471 width, height,
8458676f 472 CANVAS_ADDR_NOWRAP, canvas_mode, endian);
473
474 canvas_config_ex(spec->u_canvas_index,
475 spec->u_addr,
476 width, height / 2,
477 CANVAS_ADDR_NOWRAP, canvas_mode, endian);
b9164398 478
fe96802b
NQ		 479}
480
481static void vh264_notify_work(struct work_struct *work)
482{
483 pr_info("frame duration changed %d\n", frame_dur);
484 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
485 (void *)((unsigned long)frame_dur));
486
487 return;
b9164398
NQ		 488}
489
490static void prepare_display_q(void)
491{
492 unsigned long flags;
493 int count;
494
495 spin_lock_irqsave(&prepare_lock, flags);
496
497 if (block_display_q) {
498 spin_unlock_irqrestore(&prepare_lock, flags);
499 return;
500 }
501
502 spin_unlock_irqrestore(&prepare_lock, flags);
503
504 count = (int)VF_POOL_SIZE -
505 kfifo_len(&delay_display_q) -
506 kfifo_len(&display_q) -
507 kfifo_len(&recycle_q) -
508 kfifo_len(&newframe_q);
509
510 if ((vh264_stream_switching_state != SWITCHING_STATE_OFF)
511 || !EN_SWITCH_FENCE())
512 count = 0;
513 else
514 count = (count < 2) ? 0 : 2;
515
516 while (kfifo_len(&delay_display_q) > count) {
517 struct vframe_s *vf;
518
519 if (kfifo_get(&delay_display_q, &vf)) {
520 kfifo_put(&display_q,
521 (const struct vframe_s *)vf);
a093654a 522 ATRACE_COUNTER(MODULE_NAME, vf->pts);
b9164398
NQ		 523 vf_notify_receiver(PROVIDER_NAME,
524 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
525 }
526 }
527}
528
529static struct vframe_s *vh264_vf_peek(void *op_arg)
530{
531 struct vframe_s *vf;
532
533 if (kfifo_peek(&display_q, &vf))
534 return vf;
535
536 return NULL;
537}
538
539static struct vframe_s *vh264_vf_get(void *op_arg)
540{
541 struct vframe_s *vf;
542
543 if (kfifo_get(&display_q, &vf))
544 return vf;
545
546 return NULL;
547}
548
549static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
550{
551 unsigned long flags;
552
553 spin_lock_irqsave(&recycle_lock, flags);
554
e0614bf7 555 if ((vf != &fense_vf[0]) && (vf != &fense_vf[1]))
b9164398
NQ		 556 kfifo_put(&recycle_q, (const struct vframe_s *)vf);
557
558 spin_unlock_irqrestore(&recycle_lock, flags);
559}
560
561static int vh264_event_cb(int type, void *data, void *private_data)
562{
563 if (type & VFRAME_EVENT_RECEIVER_RESET) {
564 unsigned long flags;
565
566 amvdec_stop();
567#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
568 vf_light_unreg_provider(&vh264_vf_prov);
569#endif
570 spin_lock_irqsave(&lock, flags);
571 vh264_local_init();
572 vh264_prot_init();
573 spin_unlock_irqrestore(&lock, flags);
574#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
575 vf_reg_provider(&vh264_vf_prov);
576#endif
577 amvdec_start();
578 }
579 return 0;
580}
581
582static int vh264_vf_states(struct vframe_states *states, void *op_arg)
583{
584 unsigned long flags;
585
586 spin_lock_irqsave(&lock, flags);
587
588 states->vf_pool_size = VF_POOL_SIZE;
589 states->buf_free_num = kfifo_len(&newframe_q);
590 states->buf_avail_num = kfifo_len(&display_q) +
591 kfifo_len(&delay_display_q);
592 states->buf_recycle_num = kfifo_len(&recycle_q);
593
594 spin_unlock_irqrestore(&lock, flags);
595
596 return 0;
597}
598
599#if 0
600static tvin_trans_fmt_t convert_3d_format(u32 type)
601{
602 const tvin_trans_fmt_t conv_tab[] = {
603 0, /* checkerboard */
604 0, /* column alternation */
605 TVIN_TFMT_3D_LA, /* row alternation */
606 TVIN_TFMT_3D_LRH_OLER, /* side by side */
607 TVIN_TFMT_3D_FA /* top bottom */
608 };
609
610 return (type <= 4) ? conv_tab[type] : 0;
611}
612#endif
613
fe96802b 614
9cc3c918
RZ		 615
616#define DUMP_CC_AS_ASCII
617
618#ifdef DUMP_CC_AS_ASCII
fe96802b
NQ		 619static int vbi_to_ascii(int c)
620{
621 if (c < 0)
622 return '?';
623
624 c &= 0x7F;
625
626 if (c < 0x20 || c >= 0x7F)
627 return '.';
628
629 return c;
630}
631
9cc3c918 632static void dump_cc_ascii(const uint8_t *buf, unsigned int vpts, int poc)
fe96802b
NQ		 633{
634 int cc_flag;
635 int cc_count;
636 int i;
637 int szAscii[32];
638 int index = 0;
639
640 cc_flag = buf[1] & 0x40;
641 if (!cc_flag) {
642 pr_info("### cc_flag is invalid\n");
643 return;
644 }
645 cc_count = buf[1] & 0x1f;
646
647 for (i = 0; i < cc_count; ++i) {
648 unsigned int b0;
649 unsigned int cc_valid;
650 unsigned int cc_type;
651 unsigned char cc_data1;
652 unsigned char cc_data2;
653
654 b0 = buf[3 + i * 3];
655 cc_valid = b0 & 4;
656 cc_type = b0 & 3;
657 cc_data1 = buf[4 + i * 3];
658 cc_data2 = buf[5 + i * 3];
659
660
661 if (cc_type == 0) {
662 /* NTSC pair, Line 21 */
663 szAscii[index++] = vbi_to_ascii(cc_data1);
664 szAscii[index++] = vbi_to_ascii(cc_data2);
665 if ((!cc_valid) || (i >= 3))
666 break;
667 }
668 }
9cc3c918
RZ		 669
670 if (index > 0 && index <= 8) {
671 char pr_buf[128];
672 int len;
673
674 sprintf(pr_buf, "push vpts:0x%x, poc:%d :", vpts, poc);
675 len = strlen(pr_buf);
676 for (i=0;i<index;i++)
677 sprintf(pr_buf + len + i*2, "%c ", szAscii[i]);
678 pr_info("%s\n", pr_buf);
fe96802b 679 }
9cc3c918 680
fe96802b 681}
9cc3c918 682#endif
fe96802b
NQ		 683
684/*
685#define DUMP_USER_DATA_HEX
686*/
fe96802b
NQ		 687#ifdef DUMP_USER_DATA_HEX
688static void print_data(unsigned char *pdata, int len)
689{
690 int nLeft;
9cc3c918 691 char buf[128];
fe96802b
NQ		 692
693 nLeft = len;
9cc3c918
RZ		 694 while (nLeft >= 16) {
695 int i;
696
697 for (i=0;i<16;i++)
698 sprintf(buf+i*3, "%02x ", pdata[i]);
699
700 pr_info("%s\n", buf);
701 nLeft -= 16;
702 pdata += 16;
703 }
fe96802b
NQ		 704
705 while (nLeft >= 8) {
9cc3c918
RZ		 706 int i;
707 for (i=0;i<nLeft;i++)
708 sprintf(buf+i*3, "%02x ", pdata[i]);
709
710 pr_info("%s\n", buf);
fe96802b
NQ		 711 nLeft -= 8;
712 pdata += 8;
713 }
714}
715#endif
716
9cc3c918
RZ		 717
718
fe96802b
NQ		 719static void aml_swap_data(uint8_t *user_data, int ud_size)
720{
721 int swap_blocks, i, j, k, m;
722 unsigned char c_temp;
723
724 /* swap byte order */
725 swap_blocks = ud_size / 8;
726 for (i = 0; i < swap_blocks; i++) {
727 j = i * 8;
728 k = j + 7;
729 for (m = 0; m < 4; m++) {
730 c_temp = user_data[j];
731 user_data[j++] = user_data[k];
732 user_data[k--] = c_temp;
733 }
734 }
735}
736
9cc3c918
RZ		 737
738static void udr_dump_data(unsigned int user_data_wp,
fe96802b 739 unsigned int user_data_length,
9cc3c918 740 unsigned int pts,
fe96802b
NQ		 741 int poc)
742{
743 unsigned char *pdata;
744 int user_data_len;
745 int wp_start;
746 int nLeft;
747 unsigned char szBuf[256];
748 int nOffset;
749
750 dma_sync_single_for_cpu(amports_get_dma_device(),
751 sei_data_buffer_phys, USER_DATA_SIZE,
752 DMA_FROM_DEVICE);
753
754 if (user_data_length & 0x07)
755 user_data_len = (user_data_length + 8) & 0xFFFFFFF8;
756 else
757 user_data_len = user_data_length;
758
759 if (user_data_wp >= user_data_len) {
760 wp_start = user_data_wp - user_data_len;
761
762 pdata = (unsigned char *)sei_data_buffer;
763 pdata += wp_start;
764 nLeft = user_data_len;
765
766 memset(szBuf, 0, 256);
767 memcpy(szBuf, pdata, user_data_len);
768 } else {
769 wp_start = user_data_wp +
770 USER_DATA_SIZE - user_data_len;
771
772 pdata = (unsigned char *)sei_data_buffer;
773 pdata += wp_start;
774 nLeft = USER_DATA_SIZE - wp_start;
775
776 memset(szBuf, 0, 256);
777 memcpy(szBuf, pdata, nLeft);
778 nOffset = nLeft;
779
780 pdata = (unsigned char *)sei_data_buffer;
781 nLeft = user_data_wp;
782 memcpy(szBuf+nOffset, pdata, nLeft);
783 }
784
785 aml_swap_data(szBuf, user_data_len);
9cc3c918 786
fe96802b
NQ		 787#ifdef DUMP_USER_DATA_HEX
788 print_data(szBuf, user_data_len);
789#endif
9cc3c918
RZ		 790
791#ifdef DUMP_CC_AS_ASCII
792 dump_cc_ascii(szBuf+7, pts, poc);
793#endif
794}
795
796
797struct vh264_userdata_recored_t {
798 struct userdata_meta_info_t meta_info;
799 u32 rec_start;
800 u32 rec_len;
801};
802
803#define USERDATA_FIFO_NUM 256
804
805struct vh264_userdata_info_t {
806 struct vh264_userdata_recored_t records[USERDATA_FIFO_NUM];
807 u8 *data_buf;
808 u8 *data_buf_end;
809 u32 buf_len;
810 u32 read_index;
811 u32 write_index;
812 u32 last_wp;
813};
814
815static struct vh264_userdata_info_t *p_userdata_mgr;
816
817static DEFINE_MUTEX(userdata_mutex);
818
819
820void vh264_crate_userdata_manager(u8 *userdata_buf, int buf_len)
821{
822 p_userdata_mgr = (struct vh264_userdata_info_t *)
823 vmalloc(sizeof(struct vh264_userdata_info_t));
824 if (p_userdata_mgr) {
825 memset(p_userdata_mgr, 0,
826 sizeof(struct vh264_userdata_info_t));
827 p_userdata_mgr->data_buf = userdata_buf;
828 p_userdata_mgr->buf_len = buf_len;
829 p_userdata_mgr->data_buf_end = userdata_buf + buf_len;
830 }
831}
832
833void vh264_destroy_userdata_manager(void)
834{
835 if (p_userdata_mgr) {
836 vfree(p_userdata_mgr);
837 p_userdata_mgr = NULL;
838 }
839}
840
841/*
842#define DUMP_USER_DATA
843*/
844#ifdef DUMP_USER_DATA
845
846#define MAX_USER_DATA_SIZE 3145728
847static void *user_data_buf;
848static unsigned char *pbuf_start;
849static int total_len;
850static int bskip;
851static int n_userdata_id;
852
853
854static void print_mem_data(unsigned char *pdata,
855 int len,
856 unsigned int flag,
857 unsigned int duration,
858 unsigned int vpts,
859 unsigned int vpts_valid,
860 int rec_id)
861{
862 int nLeft;
863
864 nLeft = len;
865#if 0
866 pr_info("%d len = %d, flag = %d, duration = %d, vpts = 0x%x, vpts_valid = %d\n",
867 rec_id, len, flag,
868 duration, vpts, vpts_valid);
869#endif
870 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
871 rec_id, len, flag, vpts);
872
873
874 while (nLeft >= 16) {
875 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
876 pdata[0], pdata[1], pdata[2], pdata[3],
877 pdata[4], pdata[5], pdata[6], pdata[7],
878 pdata[8], pdata[9], pdata[10], pdata[11],
879 pdata[12], pdata[13], pdata[14], pdata[15]);
880 nLeft -= 16;
881 pdata += 16;
882 }
883
884
885 while (nLeft > 0) {
886 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
887 pdata[0], pdata[1], pdata[2], pdata[3],
888 pdata[4], pdata[5], pdata[6], pdata[7]);
889 nLeft -= 8;
890 pdata += 8;
891 }
892}
893
894
895static void dump_data(u8 *pdata,
896 unsigned int user_data_length,
897 unsigned int flag,
898 unsigned int duration,
899 unsigned int vpts,
900 unsigned int vpts_valid,
901 int rec_id)
902{
903 unsigned char szBuf[256];
904
905
906 memset(szBuf, 0, 256);
907 memcpy(szBuf, pdata, user_data_length);
908/*
909 aml_swap_data(szBuf, user_data_length);
910*/
911
912 print_mem_data(szBuf, user_data_length,
913 flag, duration, vpts,
914 vpts_valid, rec_id);
915
916#ifdef DEBUG_CC_DUMP_ASCII
917 dump_cc_ascii(szBuf+7);
918#endif
919}
920
921static void push_to_buf(u8 *pdata, int len, struct userdata_meta_info_t *pmeta)
922{
923 u32 *pLen;
924 int info_cnt;
925 u8 *pbuf_end;
926
927 if (!user_data_buf)
928 return;
929
930 if (bskip) {
931 pr_info("over size, skip\n");
932 return;
933 }
934 info_cnt = 0;
935 pLen = (u32 *)pbuf_start;
936
937 *pLen = len;
938 pbuf_start += sizeof(u32);
939 info_cnt++;
940 pLen++;
941
942 *pLen = pmeta->duration;
943 pbuf_start += sizeof(u32);
944 info_cnt++;
945 pLen++;
946
947 *pLen = pmeta->flags;
948 pbuf_start += sizeof(u32);
949 info_cnt++;
950 pLen++;
951
952 *pLen = pmeta->vpts;
953 pbuf_start += sizeof(u32);
954 info_cnt++;
955 pLen++;
956
957 *pLen = pmeta->vpts_valid;
958 pbuf_start += sizeof(u32);
959 info_cnt++;
960 pLen++;
961
962
963 *pLen = n_userdata_id;
964 pbuf_start += sizeof(u32);
965 info_cnt++;
966 pLen++;
967
968
969
970 pbuf_end = (u8 *)sei_data_buffer + USER_DATA_SIZE;
971 if (pdata + len > pbuf_end) {
972 int first_section_len;
973
974 first_section_len = pbuf_end - pdata;
975 memcpy(pbuf_start, pdata, first_section_len);
976 pdata = (u8 *)sei_data_buffer;
977 pbuf_start += first_section_len;
978 memcpy(pbuf_start, pdata, len - first_section_len);
979 pbuf_start += len - first_section_len;
980 } else {
981 memcpy(pbuf_start, pdata, len);
982 pbuf_start += len;
983 }
984
985 total_len += len + info_cnt * sizeof(u32);
986 if (total_len >= MAX_USER_DATA_SIZE-4096)
987 bskip = 1;
988}
989
990
991static void dump_userdata_info(
992 void *puser_data,
993 int len,
994 struct userdata_meta_info_t *pmeta)
995{
996 u8 *pstart;
997
998 pstart = (u8 *)puser_data;
999
1000
1001 push_to_buf(pstart, len, pmeta);
1002}
1003
1004static void show_user_data_buf(void)
1005{
1006 u8 *pbuf;
1007 int len;
1008 unsigned int flag;
1009 unsigned int duration;
1010 unsigned int vpts;
1011 unsigned int vpts_valid;
1012 int rec_id;
1013
1014 pr_info("show user data buf\n");
1015 pbuf = user_data_buf;
1016
1017 while (pbuf < pbuf_start) {
1018 u32 *pLen;
1019
1020 pLen = (u32 *)pbuf;
1021
1022 len = *pLen;
1023 pLen++;
1024 pbuf += sizeof(u32);
1025
1026 duration = *pLen;
1027 pLen++;
1028 pbuf += sizeof(u32);
1029
1030 flag = *pLen;
1031 pLen++;
1032 pbuf += sizeof(u32);
1033
1034 vpts = *pLen;
1035 pLen++;
1036 pbuf += sizeof(u32);
1037
1038 vpts_valid = *pLen;
1039 pLen++;
1040 pbuf += sizeof(u32);
1041
1042 rec_id = *pLen;
1043 pLen++;
1044 pbuf += sizeof(u32);
1045
1046 dump_data(pbuf, len, flag, duration, vpts, vpts_valid, rec_id);
1047 pbuf += len;
1048 msleep(30);
1049 }
1050}
1051
1052static int vh264_init_userdata_dump(void)
1053{
1054 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
1055 if (user_data_buf)
1056 return 1;
1057 else
1058 return 0;
1059}
1060
1061static void vh264_dump_userdata(void)
1062{
1063 if (user_data_buf) {
1064 show_user_data_buf();
1065 kfree(user_data_buf);
1066 user_data_buf = NULL;
1067 }
1068}
1069
1070static void vh264_reset_user_data_buf(void)
1071{
1072 total_len = 0;
1073 pbuf_start = user_data_buf;
1074 bskip = 0;
1075 n_userdata_id = 0;
fe96802b
NQ		 1076}
1077#endif
1078
9cc3c918
RZ		 1079static void vh264_add_userdata(struct userdata_meta_info_t meta_info, int wp)
1080{
1081 struct vh264_userdata_recored_t *p_userdata_rec;
1082 int data_length;
1083
1084 mutex_lock(&userdata_mutex);
1085
1086 if (p_userdata_mgr) {
1087 if (wp > p_userdata_mgr->last_wp)
1088 data_length = wp - p_userdata_mgr->last_wp;
1089 else
1090 data_length = wp + p_userdata_mgr->buf_len -
1091 p_userdata_mgr->last_wp;
1092
1093 if (data_length & 0x7)
1094 data_length = (((data_length + 8) >> 3) << 3);
1095#if 0
1096 pr_info("wakeup_push: ri:%d, wi:%d, data_len:%d, last_wp:%d, wp:%d, id = %d\n",
1097 p_userdata_mgr->read_index,
1098 p_userdata_mgr->write_index,
1099 data_length,
1100 p_userdata_mgr->last_wp,
1101 wp,
1102 n_userdata_id);
1103#endif
1104 p_userdata_rec = p_userdata_mgr->records +
1105 p_userdata_mgr->write_index;
1106 p_userdata_rec->meta_info = meta_info;
1107 p_userdata_rec->rec_start = p_userdata_mgr->last_wp;
1108 p_userdata_rec->rec_len = data_length;
1109 p_userdata_mgr->last_wp = wp;
1110
1111#ifdef DUMP_USER_DATA
1112 dump_userdata_info(p_userdata_mgr->data_buf +
1113 p_userdata_rec->rec_start,
1114 data_length,
1115 &meta_info);
1116 n_userdata_id++;
1117#endif
1118
1119 p_userdata_mgr->write_index++;
1120 if (p_userdata_mgr->write_index >= USERDATA_FIFO_NUM)
1121 p_userdata_mgr->write_index = 0;
1122 }
1123 mutex_unlock(&userdata_mutex);
1124
1125 vdec_wakeup_userdata_poll(vdec_h264);
1126}
1127
1128static int vh264_user_data_read(struct vdec_s *vdec,
1129 struct userdata_param_t *puserdata_para)
1130{
1131 int rec_ri, rec_wi;
1132 int rec_len;
1133 u8 *rec_data_start;
1134 u8 *pdest_buf;
1135 struct vh264_userdata_recored_t *p_userdata_rec;
1136 u32 data_size;
1137 u32 res;
1138 int copy_ok = 1;
1139
1140
1141 pdest_buf = puserdata_para->pbuf_addr;
1142
1143
1144 mutex_lock(&userdata_mutex);
1145
1146 if (!p_userdata_mgr) {
1147 mutex_unlock(&userdata_mutex);
1148 return 0;
1149 }
1150/*
1151 pr_info("ri = %d, wi = %d\n",
1152 p_userdata_mgr->read_index,
1153 p_userdata_mgr->write_index);
1154*/
1155 rec_ri = p_userdata_mgr->read_index;
1156 rec_wi = p_userdata_mgr->write_index;
1157
1158 if (rec_ri == rec_wi) {
1159 mutex_unlock(&userdata_mutex);
1160 return 0;
1161 }
1162
1163 p_userdata_rec = p_userdata_mgr->records + rec_ri;
1164
1165 rec_len = p_userdata_rec->rec_len;
1166 rec_data_start = p_userdata_rec->rec_start + p_userdata_mgr->data_buf;
1167/*
1168 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
1169 p_userdata_rec->rec_len,
1170 p_userdata_rec->rec_start,
1171 puserdata_para->buf_len);
1172*/
1173 if (rec_len <= puserdata_para->buf_len) {
1174 /* dvb user data buffer is enought to copy the whole recored. */
1175 data_size = rec_len;
1176 if (rec_data_start + data_size
1177 > p_userdata_mgr->data_buf_end) {
1178 int first_section_len;
1179
1180 first_section_len = p_userdata_mgr->buf_len -
1181 p_userdata_rec->rec_start;
1182 res = (u32)copy_to_user((void *)pdest_buf,
1183 (void *)rec_data_start,
1184 first_section_len);
1185 if (res) {
1186 pr_info("p1 read not end res=%d, request=%d\n",
1187 res, first_section_len);
1188 copy_ok = 0;
1189
1190 p_userdata_rec->rec_len -=
1191 first_section_len - res;
1192 p_userdata_rec->rec_start +=
1193 first_section_len - res;
1194 puserdata_para->data_size =
1195 first_section_len - res;
1196 } else {
1197 res = (u32)copy_to_user(
1198 (void *)(pdest_buf+first_section_len),
1199 (void *)p_userdata_mgr->data_buf,
1200 data_size - first_section_len);
1201 if (res) {
1202 pr_info("p2 read not end res=%d, request=%d\n",
1203 res, data_size);
1204 copy_ok = 0;
1205 }
1206 p_userdata_rec->rec_len -=
1207 data_size - res;
1208 p_userdata_rec->rec_start =
1209 data_size - first_section_len - res;
1210 puserdata_para->data_size =
1211 data_size - res;
1212 }
1213 } else {
1214 res = (u32)copy_to_user((void *)pdest_buf,
1215 (void *)rec_data_start,
1216 data_size);
1217 if (res) {
1218 pr_info("p3 read not end res=%d, request=%d\n",
1219 res, data_size);
1220 copy_ok = 0;
1221 }
1222 p_userdata_rec->rec_len -= data_size - res;
1223 p_userdata_rec->rec_start += data_size - res;
1224 puserdata_para->data_size = data_size - res;
1225 }
1226
1227 if (copy_ok) {
1228 p_userdata_mgr->read_index++;
1229 if (p_userdata_mgr->read_index >= USERDATA_FIFO_NUM)
1230 p_userdata_mgr->read_index = 0;
1231 }
1232 } else {
1233 /* dvb user data buffer is not enought
1234 to copy the whole recored. */
1235 data_size = puserdata_para->buf_len;
1236 if (rec_data_start + data_size
1237 > p_userdata_mgr->data_buf_end) {
1238 int first_section_len;
1239
1240 first_section_len = p_userdata_mgr->buf_len
1241 - p_userdata_rec->rec_start;
1242 res = (u32)copy_to_user((void *)pdest_buf,
1243 (void *)rec_data_start,
1244 first_section_len);
1245 if (res) {
1246 pr_info("p4 read not end res=%d, request=%d\n",
1247 res, first_section_len);
1248 copy_ok = 0;
1249 p_userdata_rec->rec_len -=
1250 first_section_len - res;
1251 p_userdata_rec->rec_start +=
1252 first_section_len - res;
1253 puserdata_para->data_size =
1254 first_section_len - res;
1255 } else {
1256 /* first secton copy is ok*/
1257 res = (u32)copy_to_user(
1258 (void *)(pdest_buf+first_section_len),
1259 (void *)p_userdata_mgr->data_buf,
1260 data_size - first_section_len);
1261 if (res) {
1262 pr_info("p5 read not end res=%d, request=%d\n",
1263 res,
1264 data_size - first_section_len);
1265 copy_ok = 0;
1266 }
1267
1268 p_userdata_rec->rec_len -= data_size - res;
1269 p_userdata_rec->rec_start =
1270 data_size - first_section_len - res;
1271 puserdata_para->data_size = data_size - res;
1272 }
1273 } else {
1274 res = (u32)copy_to_user((void *)pdest_buf,
1275 (void *)rec_data_start,
1276 data_size);
1277 if (res) {
1278 pr_info("p6 read not end res=%d, request=%d\n",
1279 res, data_size);
1280 copy_ok = 0;
1281 }
1282
1283 p_userdata_rec->rec_len -= data_size - res;
1284 p_userdata_rec->rec_start += data_size - res;
1285 puserdata_para->data_size = data_size - res;
1286 }
1287
1288 if (copy_ok) {
1289 p_userdata_mgr->read_index++;
1290 if (p_userdata_mgr->read_index
1291 >= USERDATA_FIFO_NUM)
1292 p_userdata_mgr->read_index = 0;
1293 }
1294
1295 }
1296 puserdata_para->meta_info = p_userdata_rec->meta_info;
1297
1298 if (p_userdata_mgr->read_index <= p_userdata_mgr->write_index)
1299 puserdata_para->meta_info.records_in_que =
1300 p_userdata_mgr->write_index -
1301 p_userdata_mgr->read_index;
1302 else
1303 puserdata_para->meta_info.records_in_que =
1304 p_userdata_mgr->write_index +
1305 USERDATA_FIFO_NUM -
1306 p_userdata_mgr->read_index;
1307
1308 puserdata_para->version = (0<<24|0<<16|0<<8|1);
1309
1310 mutex_unlock(&userdata_mutex);
1311
1312 return 1;
1313}
1314
1315static void vh264_wakeup_userdata_poll(struct vdec_s *vdec)
1316{
1317 amstream_wakeup_userdata_poll(vdec);
1318}
1319
1320static void vh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
1321{
1322 mutex_lock(&userdata_mutex);
1323
1324 if (p_userdata_mgr) {
1325 pr_info("h264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
1326 bInit, p_userdata_mgr->read_index,
1327 p_userdata_mgr->write_index);
1328 p_userdata_mgr->read_index = 0;
1329 p_userdata_mgr->write_index = 0;
1330
1331 if (bInit)
1332 p_userdata_mgr->last_wp = 0;
1333 }
1334
1335 mutex_unlock(&userdata_mutex);
1336}
1337
a8f62ee0
RZ		 1338static void h264_reset_qos_mgr(void)
1339{
1340 int i;
1341
1342 pr_info("h264_reset_qos_mgr\n");
1343
1344 INIT_LIST_HEAD(&free_qos_nodes_list);
1345 INIT_LIST_HEAD(&picture_qos_list);
1346
1347 for (i = 0; i < MAX_FREE_QOS_NODES; i++) {
1348 free_nodes[i].b_offset = 0xFFFFFFFF;
1349
1350 list_add_tail(&free_nodes[i].list,
1351 &free_qos_nodes_list);
1352 }
1353}
1354
1355
1356static void load_qos_data(int pic_number, uint32_t b_offset)
1357{
1358 uint32_t blk88_y_count;
1359 uint32_t blk88_c_count;
1360 uint32_t blk22_mv_count;
1361 uint32_t rdata32;
1362 int32_t mv_hi;
1363 int32_t mv_lo;
1364 uint32_t rdata32_l;
1365 uint32_t mvx_L0_hi;
1366 uint32_t mvy_L0_hi;
1367 uint32_t mvx_L1_hi;
1368 uint32_t mvy_L1_hi;
1369 int64_t value;
1370 uint64_t temp_value;
1371/*
1372#define DEBUG_QOS
1373*/
1374#define SUPPORT_NODE
1375
1376#ifdef SUPPORT_NODE
1377 struct h264_qos_data_node_t *node;
1378 struct h264_qos_data_node_t *tmp;
1379 int bFoundNode = 0;
1380
1381 node = NULL;
1382 if (!list_empty(&picture_qos_list)) {
1383 list_for_each_entry_safe(node, tmp, &picture_qos_list, list) {
1384 if (node->b_offset == b_offset) {
1385 bFoundNode = 1;
1386 break;
1387 }
1388 }
1389 }
1390 /*
1391 pr_info("bFoundNode = %d, node:0x%p\n", bFoundNode, node);
1392 */
1393 if (!bFoundNode) {
1394 if (!list_empty(&free_qos_nodes_list)) {
1395 node = list_entry(
1396 free_qos_nodes_list.next,
1397 struct h264_qos_data_node_t,
1398 list);
1399 /*
1400 pr_info("get a node:0x%p\n", node);
1401 */
1402 } else {
1403 pr_info("there is no qos data node avaible\n");
1404
1405 return;
1406 }
1407 }
1408
1409 node->b_offset = b_offset;
1410 node->poc = pic_number;
1411
1412 node->max_mv = 0;
1413 node->avg_mv = 0;
1414 node->min_mv = 0;
1415
1416 node->max_skip = 0;
1417 node->avg_skip = 0;
1418 node->min_skip = 0;
1419
1420 node->max_qp = 0;
1421 node->avg_qp = 0;
1422 node->min_qp = 0;
1423#endif
1424
1425
1426
1427
1428
1429
1430 /* set rd_idx to 0 */
1431 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
1432 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
1433 if (blk88_y_count == 0) {
1434#ifdef DEBUG_QOS
1435 pr_info(" [Picture %d Quality] NO Data yet.\n",
1436 pic_number);
1437#endif
1438 /* reset all counts */
1439 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
1440
1441#ifdef SUPPORT_NODE
1442 list_move(&node->list, &picture_qos_list);
1443#endif
1444 return;
1445 }
1446 /* qp_y_sum */
1447 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1448#ifdef DEBUG_QOS
1449 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
1450 pic_number, rdata32/blk88_y_count,
1451 rdata32, blk88_y_count);
1452#endif
1453#ifdef SUPPORT_NODE
1454 node->avg_qp = rdata32/blk88_y_count;
1455#endif
1456
1457 /* intra_y_count */
1458 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1459#ifdef DEBUG_QOS
1460 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
1461 pic_number, rdata32*100/blk88_y_count,
1462 '%', rdata32);
1463#endif
1464 /* skipped_y_count */
1465 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1466#ifdef DEBUG_QOS
1467 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
1468 pic_number, rdata32*100/blk88_y_count,
1469 '%', rdata32);
1470#endif
1471#ifdef SUPPORT_NODE
1472 node->avg_skip = rdata32*100/blk88_y_count;
1473#endif
1474 /* coeff_non_zero_y_count */
1475 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1476#ifdef DEBUG_QOS
1477 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
1478 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
1479 '%', rdata32);
1480#endif
1481 /* blk66_c_count */
1482 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
1483 if (blk88_c_count == 0) {
1484#ifdef DEBUG_QOS
1485 pr_info(" [Picture %d Quality] NO Data yet.\n",
1486 pic_number);
1487#endif
1488 /* reset all counts */
1489 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
1490
1491#ifdef SUPPORT_NODE
1492 list_move(&node->list, &picture_qos_list);
1493#endif
1494 return;
1495 }
1496 /* qp_c_sum */
1497 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1498#ifdef DEBUG_QOS
1499 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
1500 pic_number, rdata32/blk88_c_count,
1501 rdata32, blk88_c_count);
1502#endif
1503 /* intra_c_count */
1504 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1505#ifdef DEBUG_QOS
1506 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
1507 pic_number, rdata32*100/blk88_c_count,
1508 '%', rdata32);
1509#endif
1510 /* skipped_cu_c_count */
1511 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1512#ifdef DEBUG_QOS
1513 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
1514 pic_number, rdata32*100/blk88_c_count,
1515 '%', rdata32);
1516#endif
1517 /* coeff_non_zero_c_count */
1518 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1519#ifdef DEBUG_QOS
1520 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
1521 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
1522 '%', rdata32);
1523#endif
1524
1525 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
1526 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
1527 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1528#ifdef DEBUG_QOS
1529 pr_info(" [Picture %d Quality] Y QP min : %d\n",
1530 pic_number, (rdata32>>0)&0xff);
1531#endif
1532#ifdef SUPPORT_NODE
1533 node->min_qp = (rdata32>>0)&0xff;
1534#endif
1535
1536#ifdef DEBUG_QOS
1537 pr_info(" [Picture %d Quality] Y QP max : %d\n",
1538 pic_number, (rdata32>>8)&0xff);
1539#endif
1540#ifdef SUPPORT_NODE
1541 node->max_qp = (rdata32>>8)&0xff;
1542#endif
1543
1544#ifdef DEBUG_QOS
1545 pr_info(" [Picture %d Quality] C QP min : %d\n",
1546 pic_number, (rdata32>>16)&0xff);
1547 pr_info(" [Picture %d Quality] C QP max : %d\n",
1548 pic_number, (rdata32>>24)&0xff);
1549#endif
1550
1551 /* blk22_mv_count */
1552 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
1553 if (blk22_mv_count == 0) {
1554#ifdef DEBUG_QOS
1555 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
1556 pic_number);
1557#endif
1558 /* reset all counts */
1559 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
1560#ifdef SUPPORT_NODE
1561 list_move(&node->list, &picture_qos_list);
1562#endif
1563 return;
1564 }
1565 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
1566 mvy_L0_count[39:32], mvx_L0_count[39:32] */
1567 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1568 /* should all be 0x00 or 0xff */
1569#ifdef DEBUG_QOS
1570 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
1571 pic_number, rdata32);
1572#endif
1573 mvx_L0_hi = ((rdata32>>0)&0xff);
1574 mvy_L0_hi = ((rdata32>>8)&0xff);
1575 mvx_L1_hi = ((rdata32>>16)&0xff);
1576 mvy_L1_hi = ((rdata32>>24)&0xff);
1577
1578 /* mvx_L0_count[31:0] */
1579 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
1580 temp_value = mvx_L0_hi;
1581 temp_value = (temp_value << 32) | rdata32_l;
1582
1583 if (mvx_L0_hi & 0x80)
1584 value = 0xFFFFFFF000000000 | temp_value;
1585 else
1586 value = temp_value;
1587 value = div_s64(value, blk22_mv_count);
1588#ifdef DEBUG_QOS
1589 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
1590 pic_number, (int)(value),
1591 value, blk22_mv_count);
1592#endif
1593#ifdef SUPPORT_NODE
1594 node->avg_mv = value;
1595#endif
1596
1597 /* mvy_L0_count[31:0] */
1598 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
1599 temp_value = mvy_L0_hi;
1600 temp_value = (temp_value << 32) | rdata32_l;
1601
1602 if (mvy_L0_hi & 0x80)
1603 value = 0xFFFFFFF000000000 | temp_value;
1604 else
1605 value = temp_value;
1606#ifdef DEBUG_QOS
1607 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
1608 pic_number, rdata32_l/blk22_mv_count,
1609 value, blk22_mv_count);
1610#endif
1611
1612 /* mvx_L1_count[31:0] */
1613 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
1614 temp_value = mvx_L1_hi;
1615 temp_value = (temp_value << 32) | rdata32_l;
1616 if (mvx_L1_hi & 0x80)
1617 value = 0xFFFFFFF000000000 | temp_value;
1618 else
1619 value = temp_value;
1620#ifdef DEBUG_QOS
1621 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
1622 pic_number, rdata32_l/blk22_mv_count,
1623 value, blk22_mv_count);
1624#endif
1625
1626 /* mvy_L1_count[31:0] */
1627 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
1628 temp_value = mvy_L1_hi;
1629 temp_value = (temp_value << 32) | rdata32_l;
1630 if (mvy_L1_hi & 0x80)
1631 value = 0xFFFFFFF000000000 | temp_value;
1632 else
1633 value = temp_value;
1634#ifdef DEBUG_QOS
1635 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
1636 pic_number, rdata32_l/blk22_mv_count,
1637 value, blk22_mv_count);
1638#endif
1639
1640 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
1641 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1642 mv_hi = (rdata32>>16)&0xffff;
1643 if (mv_hi & 0x8000)
1644 mv_hi = 0x8000 - mv_hi;
1645#ifdef DEBUG_QOS
1646 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
1647 pic_number, mv_hi);
1648#endif
1649#ifdef SUPPORT_NODE
1650 node->max_mv = mv_hi;
1651#endif
1652
1653 mv_lo = (rdata32>>0)&0xffff;
1654 if (mv_lo & 0x8000)
1655 mv_lo = 0x8000 - mv_lo;
1656#ifdef DEBUG_QOS
1657 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
1658 pic_number, mv_lo);
1659#endif
1660#ifdef SUPPORT_NODE
1661 node->min_mv = mv_lo;
1662#endif
1663
1664 /* {mvy_L0_max, mvy_L0_min} */
1665 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1666 mv_hi = (rdata32>>16)&0xffff;
1667 if (mv_hi & 0x8000)
1668 mv_hi = 0x8000 - mv_hi;
1669#ifdef DEBUG_QOS
1670 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
1671 pic_number, mv_hi);
1672#endif
1673
1674 mv_lo = (rdata32>>0)&0xffff;
1675 if (mv_lo & 0x8000)
1676 mv_lo = 0x8000 - mv_lo;
1677#ifdef DEBUG_QOS
1678 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
1679 pic_number, mv_lo);
1680#endif
1681
1682 /* {mvx_L1_max, mvx_L1_min} */
1683 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1684 mv_hi = (rdata32>>16)&0xffff;
1685 if (mv_hi & 0x8000)
1686 mv_hi = 0x8000 - mv_hi;
1687#ifdef DEBUG_QOS
1688 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
1689 pic_number, mv_hi);
1690#endif
1691
1692 mv_lo = (rdata32>>0)&0xffff;
1693 if (mv_lo & 0x8000)
1694 mv_lo = 0x8000 - mv_lo;
1695#ifdef DEBUG_QOS
1696 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
1697 pic_number, mv_lo);
1698#endif
1699
1700 /* {mvy_L1_max, mvy_L1_min} */
1701 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
1702 mv_hi = (rdata32>>16)&0xffff;
1703 if (mv_hi & 0x8000)
1704 mv_hi = 0x8000 - mv_hi;
1705#ifdef DEBUG_QOS
1706 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
1707 pic_number, mv_hi);
1708#endif
1709 mv_lo = (rdata32>>0)&0xffff;
1710 if (mv_lo & 0x8000)
1711 mv_lo = 0x8000 - mv_lo;
1712#ifdef DEBUG_QOS
1713 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
1714 pic_number, mv_lo);
1715#endif
1716
1717 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
1718#ifdef DEBUG_QOS
1719 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
1720 pic_number, rdata32);
1721#endif
1722 /* reset all counts */
1723 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
1724#ifdef SUPPORT_NODE
1725 list_move(&node->list, &picture_qos_list);
1726#endif
1727}
1728
1729void search_qos_node(struct vframe_qos_s *picture_qos, uint32_t b_offset)
1730{
1731 struct h264_qos_data_node_t *node;
1732 struct h264_qos_data_node_t *tmp;
1733
1734 if (!list_empty(&picture_qos_list)) {
1735 list_for_each_entry_safe(node, tmp, &picture_qos_list, list) {
1736 if (node->b_offset == b_offset) {
1737
1738 picture_qos->avg_mv = node->avg_mv;
1739 picture_qos->min_mv = node->min_mv;
1740 picture_qos->max_mv = node->max_mv;
1741
1742 picture_qos->avg_skip = node->avg_skip;
1743 picture_qos->min_skip = node->min_skip;
1744 picture_qos->max_skip = node->max_skip;
1745
1746 picture_qos->avg_qp = node->avg_qp;
1747 picture_qos->min_qp = node->min_qp;
1748 picture_qos->max_qp = node->max_qp;
1749
1750#if 0
1751 pr_info("POC:%d, mv: max:%d, avg:%d, min:%d\n"
1752 "qp: max:%d, avg:%d, min:%d\n"
1753 "skip: max:%d, avg:%d, min:%d\n",
1754 node->poc,
1755 picture_qos->max_mv,
1756 picture_qos->avg_mv,
1757 picture_qos->min_mv,
1758 picture_qos->max_qp,
1759 picture_qos->avg_qp,
1760 picture_qos->min_qp,
1761 picture_qos->max_skip,
1762 picture_qos->avg_skip,
1763 picture_qos->min_skip);
1764#endif
1765 node->b_offset = 0xFFFFFFFF;
1766 list_move(&node->list, &free_qos_nodes_list);
1767
1768 break;
1769 }
1770 }
1771 }
1772}
1773
1774static void qos_do_work(struct work_struct *work)
1775{
1776 uint32_t poc;
1777 uint32_t bOffset;
1778
1779
1780 poc = READ_VREG(AV_SCRATCH_M);
1781 bOffset = READ_VREG(AV_SCRATCH_L);
1782/*
1783 pr_info("poc:%d, bOffset:0x%x\n", poc, bOffset);
1784*/
1785 load_qos_data(poc, bOffset);
1786
1787
1788 WRITE_VREG(AV_SCRATCH_0, 0);
1789}
fe96802b
NQ		 1790
1791static void userdata_push_do_work(struct work_struct *work)
1792{
1793 unsigned int sei_itu35_flags;
1794 unsigned int sei_itu35_wp;
1795 unsigned int sei_itu35_data_length;
fe96802b 1796
9cc3c918
RZ		 1797 struct userdata_meta_info_t meta_info;
1798 u32 offset, pts;
1799 u64 pts_us64 = 0;
1800 u32 slice_type;
1801 u32 reg;
1802 u32 poc_number;
1803 u32 picture_struct;
1804
1805 memset(&meta_info, 0, sizeof(meta_info));
1806
1807 meta_info.duration = frame_dur;
1808
1809 reg = READ_VREG(AV_SCRATCH_M);
1810 poc_number = reg & 0x7FFFFFF;
1811 if ((poc_number >> 16) == 0x7FF)
1812 poc_number = (reg & 0x7FFFFFF) - 0x8000000;
1813
1814 slice_type = (reg >> 29) & 0x7;
1815 switch (slice_type) {
1816 case SLICE_TYPE_I:
1817 meta_info.flags |= 1<<7;
1818 break;
1819 case SLICE_TYPE_P:
1820 meta_info.flags |= 3<<7;
1821 break;
1822 case SLICE_TYPE_B:
1823 meta_info.flags |= 2<<7;
1824 break;
1825 }
1826 meta_info.poc_number = poc_number;
1827 picture_struct = (reg >> 27) & 0x3;
1828
1829 meta_info.flags |= (VFORMAT_H264 << 3) | (picture_struct << 12);
1830
1831
1832 offset = READ_VREG(AV_SCRATCH_L);
1833
1834 if (pts_pickout_offset_us64
1835 (PTS_TYPE_VIDEO, offset, &pts, 0, &pts_us64) != 0) {
1836 pr_info("pts pick outfailed, offset:0x%x\n", offset);
1837 pts = -1;
1838 meta_info.vpts_valid = 0;
1839 } else
1840 meta_info.vpts_valid = 1;
1841 meta_info.vpts = pts;
1842/*
1843 pr_info("offset:0x%x, vpts:0x%x, slice:%d, poc:%d\n",
1844 offset, pts, slice_type,
1845 poc_number);
1846*/
fe96802b
NQ		 1847 sei_itu35_flags = READ_VREG(AV_SCRATCH_J);
1848 sei_itu35_wp = (sei_itu35_flags >> 16) & 0xffff;
1849 sei_itu35_data_length = sei_itu35_flags & 0x7fff;
1850
9cc3c918
RZ		 1851 if (enable_userdata_debug)
1852 udr_dump_data(sei_itu35_wp,
1853 sei_itu35_data_length,
1854 pts, poc_number);
1855
1856
1857 vh264_add_userdata(meta_info, sei_itu35_wp);
1858
fe96802b 1859 WRITE_VREG(AV_SCRATCH_J, 0);
fe96802b
NQ		 1860}
1861
1862
b9164398
NQ		 1863static void set_frame_info(struct vframe_s *vf)
1864{
1865 vf->width = frame_width;
1866 vf->height = frame_height;
1867 vf->duration = frame_dur;
1868 vf->ratio_control =
1869 (min(h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
1870 DISP_RATIO_ASPECT_RATIO_BIT;
1871 vf->orientation = vh264_rotation;
1872 vf->flag = 0;
1873
1874#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER_3D_PROCESS
1875 vf->trans_fmt = 0;
1876 if ((vf->trans_fmt == TVIN_TFMT_3D_LRF) ||
1877 (vf->trans_fmt == TVIN_TFMT_3D_LA)) {
1878 vf->left_eye.start_x = 0;
1879 vf->left_eye.start_y = 0;
1880 vf->left_eye.width = frame_width / 2;
1881 vf->left_eye.height = frame_height;
1882
1883 vf->right_eye.start_x = 0;
1884 vf->right_eye.start_y = 0;
1885 vf->right_eye.width = frame_width / 2;
1886 vf->right_eye.height = frame_height;
1887 } else if ((vf->trans_fmt == TVIN_TFMT_3D_LRH_OLER) ||
1888 (vf->trans_fmt == TVIN_TFMT_3D_TB)) {
1889 vf->left_eye.start_x = 0;
1890 vf->left_eye.start_y = 0;
1891 vf->left_eye.width = frame_width / 2;
1892 vf->left_eye.height = frame_height;
1893
1894 vf->right_eye.start_x = 0;
1895 vf->right_eye.start_y = 0;
1896 vf->right_eye.width = frame_width / 2;
1897 vf->right_eye.height = frame_height;
1898 }
1899#endif
1900
1901}
1902
1903#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
1904static void vh264_ppmgr_reset(void)
1905{
1906 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL);
1907
1908 vh264_local_init();
1909
1910 pr_info("vh264dec: vf_ppmgr_reset\n");
1911}
1912#endif
1913
1914static int get_max_dpb_size(int level_idc, int mb_width, int mb_height)
1915{
1916 int size, r;
1917
1918 switch (level_idc) {
1919 case 10:
1920 r = 1485;
1921 break;
1922 case 11:
1923 r = 3375;
1924 break;
1925 case 12:
1926 case 13:
1927 case 20:
1928 r = 8910;
1929 break;
1930 case 21:
1931 r = 17820;
1932 break;
1933 case 22:
1934 case 30:
1935 r = 30375;
1936 break;
1937 case 31:
1938 r = 67500;
1939 break;
1940 case 32:
1941 r = 76800;
1942 break;
1943 case 40:
1944 case 41:
1945 case 42:
1946 r = 122880;
1947 break;
1948 case 50:
1949 r = 414000;
1950 break;
1951 case 51:
1952 case 52:
1953 r = 691200;
1954 break;
1955 default:
1956 return 0;
1957 }
1958 size = (mb_width * mb_height +
1959 (mb_width * mb_height / 2)) * 256 * 10;
1960 r = (r * 1024 + size-1) / size;
1961 r = min(r, 16);
1962 /*pr_info("max_dpb %d size:%d\n", r, size);*/
1963 return r;
1964}
1965static void vh264_set_params(struct work_struct *work)
1966{
1967 int aspect_ratio_info_present_flag, aspect_ratio_idc;
1968 int max_dpb_size, actual_dpb_size, max_reference_size;
fe96802b 1969 int i, mb_mv_byte, ret;
b9164398 1970 unsigned long addr;
8458676f 1971 unsigned int post_canvas, buf_size, endian;
b9164398
NQ		 1972 unsigned int frame_mbs_only_flag;
1973 unsigned int chroma_format_idc, chroma444, video_signal;
1974 unsigned int crop_infor, crop_bottom, crop_right, level_idc;
b9164398
NQ		 1975 if (!atomic_read(&vh264_active))
1976 return;
1977 mutex_lock(&vh264_mutex);
1978 if (vh264_stream_switching_state == SWITCHING_STATE_ON_CMD1)
1979 vh264_stream_switching_state = SWITCHING_STATE_ON_CMD1_PENDING;
1980 post_canvas = get_post_canvas();
1981 clk_adj_frame_count = 0;
1982 /* set to max decoder clock rate at the beginning */
f8537a67 1983
1984 if (vdec_is_support_4k())
1985 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
1986 else
1987 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
1988
b9164398
NQ		 1989 timing_info_present_flag = 0;
1990 mb_width = READ_VREG(AV_SCRATCH_1);
1991 seq_info = READ_VREG(AV_SCRATCH_2);
1992 aspect_ratio_info = READ_VREG(AV_SCRATCH_3);
1993 num_units_in_tick = READ_VREG(AV_SCRATCH_4);
1994 time_scale = READ_VREG(AV_SCRATCH_5);
1995 level_idc = READ_VREG(AV_SCRATCH_A);
1996 if (level_idc > 0)
1997 saved_idc_level = level_idc;
1998 else if (saved_idc_level > 0)
1999 level_idc = saved_idc_level;
2000 video_signal = READ_VREG(AV_SCRATCH_H);
2001 video_signal_from_vui =
2002 ((video_signal & 0xffff) << 8) |
2003 ((video_signal & 0xff0000) >> 16) |
2004 ((video_signal & 0x3f000000));
2005/*
e0614bf7
ZZ		 2006 * pr_info("video_signal_type_present_flag 0x%x\n",
2007 * (video_signal_from_vui >> 29) & 1);
2008 * pr_info("video_format 0x%x\n",
2009 * (video_signal_from_vui >> 26) & 7);
2010 * pr_info("video_full_range_flag 0x%x\n",
2011 * (video_signal_from_vui >> 25) & 1);
2012 * pr_info("color_description_present_flag 0x%x\n",
2013 * (video_signal_from_vui >> 24) & 1);
2014 * pr_info("color_primaries 0x%x\n",
2015 * (video_signal_from_vui >> 16) & 0xff);
2016 * pr_info("transfer_characteristic 0x%x\n",
2017 * (video_signal_from_vui >> 8) & 0xff);
2018 * pr_info("matrix_coefficient 0x%x\n",
2019 * video_signal_from_vui & 0xff);
2020 */
b9164398
NQ		 2021
2022 mb_total = (mb_width >> 8) & 0xffff;
2023 max_reference_size = (mb_width >> 24) & 0x7f;
2024 mb_mv_byte = (mb_width & 0x80000000) ? 24 : 96;
2025 if (ucode_type == UCODE_IP_ONLY_PARAM)
2026 mb_mv_byte = 96;
2027 mb_width = mb_width & 0xff;
63e810c0 2028 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
b9164398
NQ		 2029 if (!mb_width && mb_total)
2030 mb_width = 256;
2031 }
a35da9f0
PY		 2032 if (mb_width)
2033 mb_height = mb_total / mb_width;
b9164398
NQ		 2034 last_duration = 0;
2035 /* AV_SCRATCH_2
2036 * bit 15: frame_mbs_only_flag
e0614bf7
ZZ		 2037 * bit 13-14: chroma_format_idc
2038 */
b9164398
NQ		 2039 frame_mbs_only_flag = (seq_info >> 15) & 0x01;
2040 chroma_format_idc = (seq_info >> 13) & 0x03;
2041 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
2042
2043 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
e0614bf7
ZZ		 2044 * @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
2045 * (2 - frame_mbs_only_flag)
2046 */
b9164398
NQ		 2047 crop_infor = READ_VREG(AV_SCRATCH_6);
2048 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
2049 crop_right = ((crop_infor >> 16) & 0xff) >> (2 - frame_mbs_only_flag);
2050
2051 /* if width or height from outside is not equal to mb, then use mb */
2052 /* add: for seeking stream with other resolution */
2053 if ((last_mb_width && (last_mb_width != mb_width))
2054 || (mb_width != ((frame_width + 15) >> 4)))
2055 frame_width = 0;
2056 if ((last_mb_height && (last_mb_height != mb_height))
2057 || (mb_height != ((frame_height + 15) >> 4)))
2058 frame_height = 0;
2059 last_mb_width = mb_width;
2060 last_mb_height = mb_height;
2061
2062 if ((frame_width == 0) || (frame_height == 0) || crop_infor) {
2063 frame_width = mb_width << 4;
2064 frame_height = mb_height << 4;
2065 if (frame_mbs_only_flag) {
2066 frame_height =
2067 frame_height - (2 >> chroma444) *
2068 min(crop_bottom,
2069 (unsigned int)((8 << chroma444) - 1));
2070 frame_width =
2071 frame_width - (2 >> chroma444) * min(crop_right,
2072 (unsigned
2073 int)((8 << chroma444) - 1));
2074 } else {
2075 frame_height =
2076 frame_height - (4 >> chroma444) *
2077 min(crop_bottom,
2078 (unsigned int)((8 << chroma444)
2079 - 1));
2080 frame_width =
2081 frame_width - (4 >> chroma444) * min(crop_right,
2082 (unsigned
2083 int)((8 <<
2084 chroma444)
2085 - 1));
2086 }
2087#if 0
2088 pr_info
2089 ("frame_mbs_only_flag %d, crop_bottom %d, frame_height %d, ",
2090 frame_mbs_only_flag, crop_bottom, frame_height);
2091 pr_info
2092 ("mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
2093 mb_height, crop_right, frame_width, mb_width);
2094#endif
2095 if (frame_height == 1088)
2096 frame_height = 1080;
2097 }
2098
2099 mb_width = (mb_width + 3) & 0xfffffffc;
2100 mb_height = (mb_height + 3) & 0xfffffffc;
2101 mb_total = mb_width * mb_height;
2102
2103 /*max_reference_size <= max_dpb_size <= actual_dpb_size*/
2104 is_4k = (mb_total > 8160) ? true:false;
2105
fe96802b
NQ		 2106
2107 max_dpb_size = get_max_dpb_size(level_idc, mb_width, mb_height);
2108 if (max_dpb_size < max_reference_size)
2109 max_dpb_size = max_reference_size;
2110 if (max_dpb_size > 15
63e810c0 2111 && get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB
fe96802b 2112 && (codec_mm_get_total_size() < 80 * SZ_1M)) {
b9164398
NQ		 2113 actual_dpb_size
2114 = max_reference_size + dpb_size_adj;
2115 if (actual_dpb_size > VF_BUF_NUM)
2116 actual_dpb_size = VF_BUF_NUM;
b9164398 2117 } else {
fe96802b 2118 actual_dpb_size = max_dpb_size + dpb_size_adj;
b9164398 2119 actual_dpb_size = min(actual_dpb_size, VF_BUF_NUM);
b9164398 2120 }
b9164398 2121 max_reference_size++;
fe96802b
NQ		 2122 pr_info("actual_dpb_size %d max_dpb_size %d max_ref %d\n",
2123 actual_dpb_size, max_dpb_size,
2124 max_reference_size);
2125 buf_size = mb_total * mb_mv_byte * max_reference_size;
b9164398 2126
fe96802b
NQ		 2127 ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, 1,
2128 buf_size, DRIVER_NAME, &addr);
2129
2130 if (ret < 0) {
b9164398
NQ		 2131 fatal_error_flag =
2132 DECODER_FATAL_ERROR_NO_MEM;
2133 vh264_running = 0;
2134 mutex_unlock(&vh264_mutex);
b9164398
NQ		 2135 return;
2136 }
b9164398 2137
fe96802b
NQ		 2138 WRITE_VREG(AV_SCRATCH_1, addr);
2139 WRITE_VREG(AV_SCRATCH_3, post_canvas);
2140 WRITE_VREG(AV_SCRATCH_4, addr + buf_size);
2141
2142 if (!(READ_VREG(AV_SCRATCH_F) & 0x1)) {
b9164398 2143 for (i = 0; i < actual_dpb_size; i++) {
b9164398
NQ		 2144#ifdef DOUBLE_WRITE
2145 int page_count =
2146 PAGE_ALIGN((mb_total << 8) + (mb_total
2147 << 7) + (mb_total << 6) +
2148 (mb_total << 5)) / PAGE_SIZE;
2149#else
2150 int page_count =
2151 PAGE_ALIGN((mb_total << 8) +
2152 (mb_total << 7)) / PAGE_SIZE;
2153#endif
fe96802b
NQ		 2154
2155 ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle,
2156 VF_BUFFER_IDX(i),
2157 page_count << PAGE_SHIFT,
2158 DRIVER_NAME, &buffer_spec[i].phy_addr);
2159
2160 if (ret < 0) {
2161 buffer_spec[i].alloc_count = 0;
2162 fatal_error_flag =
2163 DECODER_FATAL_ERROR_NO_MEM;
2164 vh264_running = 0;
2165 mutex_unlock(&vh264_mutex);
2166 return;
b9164398 2167 }
fe96802b
NQ		 2168
2169 addr = buffer_spec[i].phy_addr;
2170 buffer_spec[i].alloc_count = page_count;
2171
b9164398
NQ		 2172 if (i <= 21) {
2173 buffer_spec[i].y_addr = addr;
2174 addr += mb_total << 8;
2175 buffer_spec[i].u_addr = addr;
2176 buffer_spec[i].v_addr = addr;
2177 addr += mb_total << 7;
2178 vfbuf_use[i] = 0;
2179
2180 buffer_spec[i].y_canvas_index = 128 + i * 2;
2181 buffer_spec[i].u_canvas_index = 128 + i * 2 + 1;
2182 buffer_spec[i].v_canvas_index = 128 + i * 2 + 1;
2183
2184 buffer_spec[i].y_canvas_width = mb_width << 4;
2185 buffer_spec[i].y_canvas_height = mb_height << 4;
2186 buffer_spec[i].u_canvas_width = mb_width << 4;
2187 buffer_spec[i].u_canvas_height = mb_height << 4;
2188 buffer_spec[i].v_canvas_width = mb_width << 4;
2189 buffer_spec[i].v_canvas_height = mb_height << 4;
2190
8458676f 2191 endian = (canvas_mode == CANVAS_BLKMODE_LINEAR)?7:0;
2192 canvas_config_ex(128 + i * 2,
b9164398
NQ		 2193 buffer_spec[i].y_addr,
2194 mb_width << 4, mb_height << 4,
2195 CANVAS_ADDR_NOWRAP,
8458676f 2196 canvas_mode, endian);
2197 canvas_config_ex(128 + i * 2 + 1,
b9164398
NQ		 2198 buffer_spec[i].u_addr,
2199 mb_width << 4, mb_height << 3,
2200 CANVAS_ADDR_NOWRAP,
8458676f 2201 canvas_mode, endian);
b9164398
NQ		 2202 WRITE_VREG(ANC0_CANVAS_ADDR + i,
2203 spec2canvas(&buffer_spec[i]));
2204 } else {
2205 buffer_spec[i].y_canvas_index =
2206 2 * (i - 21) + 4;
2207 buffer_spec[i].y_addr = addr;
2208 addr += mb_total << 8;
2209 buffer_spec[i].u_canvas_index =
2210 2 * (i - 21) + 5;
2211 buffer_spec[i].v_canvas_index =
2212 2 * (i - 21) + 5;
2213 buffer_spec[i].u_addr = addr;
2214 addr += mb_total << 7;
2215 vfbuf_use[i] = 0;
2216
2217 buffer_spec[i].y_canvas_width = mb_width << 4;
2218 buffer_spec[i].y_canvas_height = mb_height << 4;
2219 buffer_spec[i].u_canvas_width = mb_width << 4;
2220 buffer_spec[i].u_canvas_height = mb_height << 4;
2221 buffer_spec[i].v_canvas_width = mb_width << 4;
2222 buffer_spec[i].v_canvas_height = mb_height << 4;
2223
2224 spec_set_canvas(&buffer_spec[i]
2225 , mb_width << 4, mb_height << 4);
2226 WRITE_VREG(ANC0_CANVAS_ADDR + i
2227 , spec2canvas(&buffer_spec[i]));
2228 }
2229 }
fe96802b
NQ		 2230 } else {
2231 fatal_error_flag =
2232 DECODER_FATAL_ERROR_NO_MEM;
2233 vh264_running = 0;
2234 mutex_unlock(&vh264_mutex);
2235 pr_err("never be here!!\n");
2236 return;
2237 }
b9164398
NQ		 2238
2239 timing_info_present_flag = seq_info & 0x2;
2240 fixed_frame_rate_flag = 0;
2241 aspect_ratio_info_present_flag = seq_info & 0x1;
2242 aspect_ratio_idc = (seq_info >> 16) & 0xff;
2243
2244 if (timing_info_present_flag) {
2245 fixed_frame_rate_flag = seq_info & 0x40;
2246
2247 if (((num_units_in_tick * 120) >= time_scale
2248 && ((!sync_outside) || (!frame_dur))) &&
2249 num_units_in_tick
2250 && time_scale) {
2251 if (use_idr_framerate || !frame_dur
2252 || !duration_from_pts_done || vh264_running) {
2253 u32 frame_dur_es =
2254 div_u64(96000ULL * 2 *
2255 num_units_in_tick,
2256 time_scale);
2257
2258 /* hack to avoid use ES frame duration
e0614bf7 2259 * when it's half of the rate from
b9164398
NQ		 2260 * system info
2261 */
2262 /* sometimes the encoder is given a wrong
e0614bf7
ZZ		 2263 * frame rate but the system side information
2264 *is more reliable
2265 */
fe96802b 2266 if ((frame_dur * 2) != frame_dur_es) {
b9164398 2267 frame_dur = frame_dur_es;
fe96802b
NQ		 2268 if (fr_hint_status == VDEC_NEED_HINT) {
2269 schedule_work(&notify_work);
2270 fr_hint_status = VDEC_HINTED;
2271 }
2272 }
b9164398
NQ		 2273 }
2274 }
2275 } else
2276 pr_info("H.264: timing_info not present\n");
2277
2278 if (aspect_ratio_info_present_flag) {
2279 if (aspect_ratio_idc == EXTEND_SAR) {
2280 h264_ar =
2281 div_u64(256ULL * (aspect_ratio_info >> 16) *
2282 frame_height,
2283 (aspect_ratio_info & 0xffff) *
2284 frame_width);
2285 } else {
2286 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
2287 * aspect_ratio_idc);
2288 */
2289
2290 switch (aspect_ratio_idc) {
2291 case 1:
2292 h264_ar = 0x100 * frame_height / frame_width;
2293 break;
2294 case 2:
2295 h264_ar = 0x100 * frame_height * 11 /
2296 (frame_width * 12);
2297 break;
2298 case 3:
2299 h264_ar = 0x100 * frame_height * 11 /
2300 (frame_width * 10);
2301 break;
2302 case 4:
2303 h264_ar = 0x100 * frame_height * 11 /
2304 (frame_width * 16);
2305 break;
2306 case 5:
2307 h264_ar = 0x100 * frame_height * 33 /
2308 (frame_width * 40);
2309 break;
2310 case 6:
2311 h264_ar = 0x100 * frame_height * 11 /
2312 (frame_width * 24);
2313 break;
2314 case 7:
2315 h264_ar = 0x100 * frame_height * 11 /
2316 (frame_width * 20);
2317 break;
2318 case 8:
2319 h264_ar = 0x100 * frame_height * 11 /
2320 (frame_width * 32);
2321 break;
2322 case 9:
2323 h264_ar = 0x100 * frame_height * 33 /
2324 (frame_width * 80);
2325 break;
2326 case 10:
2327 h264_ar = 0x100 * frame_height * 11 /
2328 (frame_width * 18);
2329 break;
2330 case 11:
2331 h264_ar = 0x100 * frame_height * 11 /
2332 (frame_width * 15);
2333 break;
2334 case 12:
2335 h264_ar = 0x100 * frame_height * 33 /
2336 (frame_width * 64);
2337 break;
2338 case 13:
2339 h264_ar = 0x100 * frame_height * 99 /
2340 (frame_width * 160);
2341 break;
2342 case 14:
2343 h264_ar = 0x100 * frame_height * 3 /
2344 (frame_width * 4);
2345 break;
2346 case 15:
2347 h264_ar = 0x100 * frame_height * 2 /
2348 (frame_width * 3);
2349 break;
2350 case 16:
2351 h264_ar = 0x100 * frame_height * 1 /
2352 (frame_width * 2);
2353 break;
2354 default:
2355 if (vh264_ratio >> 16) {
2356 h264_ar = (frame_height *
2357 (vh264_ratio & 0xffff) *
2358 0x100 +
2359 ((vh264_ratio >> 16) *
2360 frame_width / 2)) /
2361 ((vh264_ratio >> 16) *
2362 frame_width);
2363 } else {
2364 h264_ar = frame_height * 0x100 /
2365 frame_width;
2366 }
2367 break;
2368 }
2369 }
2370 } else {
2371 pr_info("v264dec: aspect_ratio not available from source\n");
2372 if (vh264_ratio >> 16) {
2373 /* high 16 bit is width, low 16 bit is height */
2374 h264_ar =
2375 ((vh264_ratio & 0xffff) * frame_height * 0x100 +
2376 (vh264_ratio >> 16) * frame_width / 2) /
2377 ((vh264_ratio >> 16) * frame_width);
2378 } else
2379 h264_ar = frame_height * 0x100 / frame_width;
2380 }
2381
2382 WRITE_VREG(AV_SCRATCH_0,
2383 (max_reference_size << 24) | (actual_dpb_size << 16) |
2384 (max_dpb_size << 8));
2385 if (vh264_stream_switching_state != SWITCHING_STATE_OFF) {
2386 vh264_stream_switching_state = SWITCHING_STATE_OFF;
2387 pr_info("Leaving switching mode.\n");
2388 }
2389 mutex_unlock(&vh264_mutex);
2390}
2391
e0614bf7
ZZ		 2392static unsigned int pts_inc_by_duration(
2393 unsigned int *new_pts, unsigned int *new_pts_rem)
b9164398 2394{
e0614bf7 2395 unsigned int r, rem;
b9164398
NQ		 2396
2397 r = last_pts + DUR2PTS(frame_dur);
2398 rem = last_pts_remainder + DUR2PTS_REM(frame_dur);
2399
2400 if (rem >= 96) {
2401 r++;
2402 rem -= 96;
2403 }
2404
2405 if (new_pts)
2406 *new_pts = r;
2407 if (new_pts_rem)
2408 *new_pts_rem = rem;
2409
2410 return r;
2411}
2412static inline bool vh264_isr_parser(struct vframe_s *vf,
2413 unsigned int pts_valid, unsigned int buffer_index,
2414 unsigned int pts)
2415{
2416 unsigned int pts_duration = 0;
2417
2418 if (h264_first_pts_ready == 0) {
2419 if (pts_valid == 0) {
2420 vfbuf_use[buffer_index]++;
2421 vf->index = buffer_index;
2422 kfifo_put(&recycle_q,
2423 (const struct vframe_s *)vf);
2424 return false;
2425 }
2426
2427 h264pts1 = pts;
2428 h264_pts_count = 0;
2429 h264_first_pts_ready = 1;
2430 } else {
2431 if (pts < h264pts1) {
2432 if (h264_pts_count > 24) {
2433 pr_info("invalid h264pts1, reset\n");
2434 h264pts1 = pts;
2435 h264_pts_count = 0;
2436 }
2437 }
2438 if (pts_valid && (pts > h264pts1) && (h264_pts_count > 24)
2439 && (duration_from_pts_done == 0)) {
2440 unsigned int
2441 old_duration = frame_dur;
2442 h264pts2 = pts;
2443
2444 pts_duration = (h264pts2 - h264pts1) * 16 /
2445 (h264_pts_count * 15);
2446
2447 if ((pts_duration != frame_dur)
2448 && (!pts_outside)) {
2449 if (use_idr_framerate) {
2450 bool pts_c_24 = close_to(pts_duration,
2451 RATE_24_FPS,
2452 RATE_CORRECTION_THRESHOLD);
2453 bool frm_c_25 = close_to(frame_dur,
2454 RATE_25_FPS,
2455 RATE_CORRECTION_THRESHOLD);
2456 bool pts_c_25 = close_to(pts_duration,
2457 RATE_25_FPS,
2458 RATE_CORRECTION_THRESHOLD);
2459 bool frm_c_24 = close_to(frame_dur,
2460 RATE_24_FPS,
2461 RATE_CORRECTION_THRESHOLD);
2462 if ((pts_c_24 && frm_c_25)
2463 || (pts_c_25 && frm_c_24)) {
2464 pr_info
2465 ("H.264:Correct frame dur ");
2466 pr_info
2467 (" from %d to duration based ",
2468 frame_dur);
2469 pr_info
2470 ("on PTS %d ---\n",
2471 pts_duration);
2472 frame_dur = pts_duration;
2473 duration_from_pts_done = 1;
2474 } else if (((frame_dur < 96000 / 240)
2475 && (pts_duration > 96000 / 240))
2476 || (!duration_on_correcting &&
2477 !frm_c_25 && !frm_c_24)) {
2478 /* fft: if the frame rate is
2479 * not regular, use the
e0614bf7
ZZ		 2480 * calculate rate insteadof.
2481 */
b9164398
NQ		 2482 pr_info
2483 ("H.264:Correct frame dur ");
2484 pr_info
2485 (" from %d to duration based ",
2486 frame_dur);
2487 pr_info
2488 ("on PTS %d ---\n",
2489 pts_duration);
2490 frame_dur = pts_duration;
2491 duration_on_correcting = 1;
2492 }
2493 } else {
2494 if (close_to(pts_duration,
2495 frame_dur, 2000)) {
2496 frame_dur = pts_duration;
2497 pr_info
2498 ("used calculate frame rate,");
2499 pr_info("on duration =%d\n",
2500 frame_dur);
2501 } else {
2502 pr_info
2503 ("don't use calculate frame ");
2504 pr_info
2505 ("rate pts_duration =%d\n",
2506 pts_duration);
2507 }
2508 }
2509 }
2510
2511 if (duration_from_pts_done == 0) {
2512 if (close_to
2513 (pts_duration,
2514 old_duration,
2515 RATE_CORRECTION_THRESHOLD)) {
2516 pr_info
2517 ("finished correct frame dur");
2518 pr_info
2519 (" new=%d,old_duration=%d,cnt=%d\n",
2520 pts_duration,
2521 old_duration,
2522 h264_pts_count);
2523 duration_from_pts_done = 1;
2524 } else { /*not the same,redo it. */
2525 if (!close_to(pts_duration,
2526 old_duration, 1000) &&
2527 !close_to(pts_duration,
2528 frame_dur, 1000) &&
2529 close_to(pts_duration,
2530 last_duration, 200)) {
2531 /* yangle: frame_dur must
2532 * wrong,recover it.
2533 */
2534 frame_dur = pts_duration;
2535 }
2536
2537 pr_info
2538 ("restart correct frame duration ");
2539 pr_info
2540 ("new=%d,old_duration=%d,cnt=%d\n",
2541 pts_duration,
2542 old_duration,
2543 h264_pts_count);
2544 h264pts1 = h264pts2;
2545 h264_pts_count = 0;
2546 duration_from_pts_done = 0;
e0614bf7
ZZ		 2547 }
2548 }
b9164398
NQ		 2549 last_duration = pts_duration;
2550 }
2551 }
2552 return true;
2553}
2554#ifdef HANDLE_H264_IRQ
2555static irqreturn_t vh264_isr(int irq, void *dev_id)
2556#else
2557static void vh264_isr(void)
2558#endif
2559{
2560 unsigned int buffer_index;
2561 struct vframe_s *vf;
2562 unsigned int cpu_cmd;
2563 unsigned int pts, pts_lookup_save, pts_valid_save, pts_valid = 0;
2564 unsigned int pts_us64_valid = 0;
a8f62ee0 2565 unsigned int framesize;
b9164398
NQ		 2566 u64 pts_us64;
2567 bool force_interlaced_frame = false;
a8f62ee0 2568#ifdef ENABLE_SEI_ITU_T35
b9164398 2569 unsigned int sei_itu35_flags;
a8f62ee0 2570#endif
b9164398
NQ		 2571 static const unsigned int idr_num =
2572 FIX_FRAME_RATE_CHECK_IDRFRAME_NUM;
2573 static const unsigned int flg_1080_itl =
2574 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE;
2575 static const unsigned int flg_576_itl =
2576 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
2577
2578 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
2579
2580 if (0 == (stat & STAT_VDEC_RUN)) {
2581 pr_info("decoder is not running\n");
2582#ifdef HANDLE_H264_IRQ
2583 return IRQ_HANDLED;
2584#else
2585 return;
2586#endif
2587 }
2588
2589 cpu_cmd = READ_VREG(AV_SCRATCH_0);
2590
2591#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS
2592 if ((frame_dur < 2004) &&
2593 (frame_width >= 1400) &&
2594 (frame_height >= 1000) && (last_interlaced == 0))
2595 SET_VREG_MASK(AV_SCRATCH_F, 0x8);
2596#endif
2597 if ((decoder_force_reset == 1)
2598 || ((error_recovery_mode != 1)
2599 && (no_idr_error_count >= no_idr_error_max)
2600 && (ucode_type != UCODE_IP_ONLY_PARAM))) {
2601 vh264_running = 0;
2602 pr_info("force reset decoder %d!!!\n", no_idr_error_count);
2603 schedule_work(&error_wd_work);
2604 decoder_force_reset = 0;
2605 no_idr_error_count = 0;
2606 } else if ((cpu_cmd & 0xff) == 1) {
2607 if (unlikely
2608 (vh264_running
2609 && (kfifo_len(&newframe_q) != VF_POOL_SIZE))) {
2610 /* a cmd 1 sent during decoding w/o getting a cmd 3. */
2611 /* should not happen but the original code has such
2612 * case, do the same process
2613 */
2614 if ((READ_VREG(AV_SCRATCH_1) & 0xff)
2615 == 1) {/*invalid mb_width*/
2616 vh264_running = 0;
2617 fatal_error_flag = DECODER_FATAL_ERROR_UNKNOWN;
2618 /* this is fatal error, need restart */
2619 pr_info("cmd 1 fatal error happened\n");
2620 schedule_work(&error_wd_work);
2621 } else {
2622 vh264_stream_switching_state = SWITCHING_STATE_ON_CMD1;
2623 pr_info("Enter switching mode cmd1.\n");
2624 schedule_work(&stream_switching_work);
2625 }
2626 return IRQ_HANDLED;
2627 }
2628 pr_info("Enter set parameter cmd1.\n");
2629 schedule_work(&set_parameter_work);
2630 return IRQ_HANDLED;
2631 } else if ((cpu_cmd & 0xff) == 2) {
2632 int frame_mb_only, pic_struct_present, pic_struct, prog_frame,
2633 poc_sel, idr_flag, eos, error;
2634 int i, status, num_frame, b_offset;
2635 int current_error_count, slice_type;
2636
2637 vh264_running = 1;
2638 vh264_no_disp_count = 0;
2639 num_frame = (cpu_cmd >> 8) & 0xff;
2640 frame_mb_only = seq_info & 0x8000;
2641 pic_struct_present = seq_info & 0x10;
2642
2643 current_error_count = READ_VREG(AV_SCRATCH_D);
2644 if (vh264_error_count != current_error_count) {
2645 /* pr_info("decoder error happened, count %d\n",
e0614bf7
ZZ		 2646 * current_error_count);
2647 */
b9164398
NQ		 2648 vh264_error_count = current_error_count;
2649 }
2650
2651 for (i = 0; (i < num_frame) && (!vh264_eos); i++) {
2652 status = READ_VREG(AV_SCRATCH_1 + i);
2653 buffer_index = status & 0x1f;
2654 error = status & 0x200;
2655 slice_type = (READ_VREG(AV_SCRATCH_H) >> (i * 4)) & 0xf;
2656
2657 if ((error_recovery_mode_use & 2) && error)
2658 check_pts_discontinue = true;
2659 if (ucode_type == UCODE_IP_ONLY_PARAM
2660 && iponly_early_mode)
2661 continue;
2662 if ((p_last_vf != NULL)
2663 && (p_last_vf->index == buffer_index))
2664 continue;
2665
2666 if (buffer_index >= VF_BUF_NUM)
2667 continue;
2668
2669 pic_struct = (status >> 5) & 0x7;
2670 prog_frame = status & 0x100;
2671 poc_sel = status & 0x200;
2672 idr_flag = status & 0x400;
2673 frame_packing_type = (status >> 12) & 0x7;
2674 eos = (status >> 15) & 1;
2675
2676 if (eos)
2677 vh264_eos = 1;
2678
2679 b_offset = (status >> 16) & 0xffff;
2680
2681 if (error)
2682 no_idr_error_count++;
2683 if (idr_flag ||
2684 (!error && (slice_type != SLICE_TYPE_I)))
2685 no_idr_error_count = 0;
2686
2687 if (decoder_debug_flag) {
2688 pr_info
2689 ("slice_type %x idr %x error %x count %d",
2690 slice_type, idr_flag, error,
2691 no_idr_error_count);
2692 pr_info(" prog %x pic_struct %x offset %x\n",
2693 prog_frame, pic_struct, b_offset);
2694 }
2695#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS
2696 last_interlaced = prog_frame ? 0 : 1;
2697#endif
2698 if (kfifo_get(&newframe_q, &vf) == 0) {
2699 pr_info
2700 ("fatal error, no available buffer slot.");
2701 return IRQ_HANDLED;
2702 }
2703
f8537a67 2704 if (clk_adj_frame_count < (VDEC_CLOCK_ADJUST_FRAME + 1))
b9164398
NQ		 2705 clk_adj_frame_count++;
2706
2707 set_frame_info(vf);
2708
2709 switch (i) {
2710 case 0:
2711 b_offset |=
2712 (READ_VREG(AV_SCRATCH_A) & 0xffff)
2713 << 16;
2714 break;
2715 case 1:
2716 b_offset |=
2717 READ_VREG(AV_SCRATCH_A) & 0xffff0000;
2718 break;
2719 case 2:
2720 b_offset |=
2721 (READ_VREG(AV_SCRATCH_B) & 0xffff)
2722 << 16;
2723 break;
2724 case 3:
2725 b_offset |=
2726 READ_VREG(AV_SCRATCH_B) & 0xffff0000;
2727 break;
2728 case 4:
2729 b_offset |=
2730 (READ_VREG(AV_SCRATCH_C) & 0xffff)
2731 << 16;
2732 break;
2733 case 5:
2734 b_offset |=
2735 READ_VREG(AV_SCRATCH_C) & 0xffff0000;
2736 break;
2737 default:
2738 break;
2739 }
2740
fe96802b
NQ		 2741 if (error)
2742 gvs->drop_frame_count++;
2743
b9164398
NQ		 2744 /* add 64bit pts us ; */
2745 if (unlikely
2746 ((b_offset == first_offset)
2747 && (first_pts_cached))) {
2748 pts = first_pts;
2749 pts_us64 = first_pts64;
a8f62ee0 2750 framesize = first_frame_size;
b9164398
NQ		 2751 first_pts_cached = false;
2752 pts_valid = 1;
2753 pts_us64_valid = 1;
2754#ifdef DEBUG_PTS
2755 pts_hit++;
2756#endif
2757 } else if (pts_lookup_offset_us64
a8f62ee0
RZ		 2758 (PTS_TYPE_VIDEO, b_offset, &pts,
2759 &framesize, 0, &pts_us64) == 0) {
b9164398
NQ		 2760 pts_valid = 1;
2761 pts_us64_valid = 1;
2762#ifdef DEBUG_PTS
2763 pts_hit++;
2764#endif
2765 } else {
2766 pts_valid = 0;
2767 pts_us64_valid = 0;
a8f62ee0 2768 framesize = 0;
b9164398
NQ		 2769#ifdef DEBUG_PTS
2770 pts_missed++;
2771#endif
2772 }
2773
a8f62ee0
RZ		 2774 if (idr_flag)
2775 s_vframe_qos.type = 4;
2776 else if (slice_type == SLICE_TYPE_I)
2777 s_vframe_qos.type = 1;
2778 else if (slice_type == SLICE_TYPE_P)
2779 s_vframe_qos.type = 2;
2780 else if (slice_type == SLICE_TYPE_B || slice_type == 8)
2781 s_vframe_qos.type = 3;
2782
2783 s_vframe_qos.size = framesize;
2784
2785 if (pts_valid)
2786 s_vframe_qos.pts = pts;
2787 else
2788 s_vframe_qos.pts = last_pts + DUR2PTS(frame_dur);
2789#ifndef ENABLE_SEI_ITU_T35
2790 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
2791 u32 reg_data;
2792 if (i) {
2793 reg_data = READ_VREG(AV_SCRATCH_N);
2794 s_vframe_qos.max_mv
2795 = (reg_data >> 16) & 0xffff;
2796 s_vframe_qos.avg_mv
2797 = (reg_data >> 8) & 0xff;
2798 s_vframe_qos.min_mv
2799 = reg_data & 0xff;
2800 reg_data = READ_VREG(AV_SCRATCH_L);
2801 s_vframe_qos.max_qp
2802 = (reg_data >> 16) & 0xff;
2803 s_vframe_qos.avg_qp
2804 = (reg_data >> 8) & 0xff;
2805 s_vframe_qos.min_qp
2806 = reg_data & 0xff;
2807 reg_data = READ_VREG(AV_SCRATCH_M);
2808 s_vframe_qos.max_skip
2809 = (reg_data >> 16) & 0xff;
2810 s_vframe_qos.avg_skip
2811 = (reg_data >> 8) & 0xff;
2812 s_vframe_qos.min_skip
2813 = reg_data & 0xff;
2814 } else {
2815 reg_data = READ_VREG(AV_SCRATCH_J);
2816 s_vframe_qos.max_mv
2817 = (reg_data >> 16) & 0xffff;
2818 s_vframe_qos.avg_mv
2819 = (reg_data >> 8) & 0xff;
2820 s_vframe_qos.min_mv
2821 = reg_data & 0xff;
2822 reg_data = READ_VREG(AV_SCRATCH_I);
2823 s_vframe_qos.max_qp
2824 = (reg_data >> 16) & 0xff;
2825 s_vframe_qos.avg_qp
2826 = (reg_data >> 8) & 0xff;
2827 s_vframe_qos.min_qp
2828 = reg_data & 0xff;
2829 reg_data = READ_VREG(AV_SCRATCH_K);
2830 s_vframe_qos.max_skip
2831 = (reg_data >> 16) & 0xff;
2832 s_vframe_qos.avg_skip
2833 = (reg_data >> 8) & 0xff;
2834 s_vframe_qos.min_skip
2835 = reg_data & 0xff;
2836 }
2837 if (decoder_debug_flag&0x2) {
2838 pr_info("max_mv %d avg_mv %d min_mv %d slice_type %d offset %x i = %d\n",
2839 s_vframe_qos.max_mv,
2840 s_vframe_qos.avg_mv,
2841 s_vframe_qos.min_mv,
2842 slice_type,
2843 b_offset,
2844 i);
2845 pr_info("max_qp %d avg_qp %d min_qp %d\n",
2846 s_vframe_qos.max_qp,
2847 s_vframe_qos.avg_qp,
2848 s_vframe_qos.min_qp);
2849 pr_info("max_skip %d avg_skip %d min_skip %d\n",
2850 s_vframe_qos.max_skip,
2851 s_vframe_qos.avg_skip,
2852 s_vframe_qos.min_skip);
2853 }
2854 } else
2855 search_qos_node(&s_vframe_qos, b_offset);
2856#endif
2857 frame_count++;
2858
2859 s_vframe_qos.num = frame_count;
2860 vdec_fill_frame_info(&s_vframe_qos, 1);
2861
b9164398
NQ		 2862 /* on second IDR frame,check the diff between pts
2863 * compute from duration and pts from lookup ,
2864 * if large than frame_dur,we think it is uncorrect.
2865 */
2866 pts_lookup_save = pts;
2867 pts_valid_save = pts_valid;
2868 if (fixed_frame_rate_flag
2869 && (fixed_frame_rate_check_count <=
2870 idr_num)) {
2871 if (idr_flag && pts_valid) {
2872 fixed_frame_rate_check_count++;
2873 /* pr_info("diff:%d\n",
e0614bf7
ZZ		 2874 * last_pts - pts_lookup_save);
2875 */
b9164398
NQ		 2876 if ((fixed_frame_rate_check_count ==
2877 idr_num) &&
2878 (abs(pts - (last_pts +
2879 DUR2PTS(frame_dur))) >
2880 DUR2PTS(frame_dur))) {
2881 fixed_frame_rate_flag = 0;
2882 pr_info("pts sync mode play\n");
2883 }
2884
2885 if (fixed_frame_rate_flag
2886 && (fixed_frame_rate_check_count
2887 > idr_num)) {
2888 pr_info
2889 ("fix_frame_rate mode play\n");
2890 }
2891 }
2892 }
2893
2894 if (READ_VREG(AV_SCRATCH_F) & 2) {
2895 /* for I only mode, ignore the PTS information
e0614bf7 2896 * and only uses frame duration for each I
b9164398
NQ		 2897 * frame decoded
2898 */
2899 if (p_last_vf)
2900 pts_valid = 0;
2901 /* also skip frame duration calculation
2902 * based on PTS
2903 */
2904 duration_from_pts_done = 1;
2905 /* and add a default duration for 1/30 second
2906 * if there is no valid frame
e0614bf7
ZZ		 2907 * duration available
2908 */
b9164398
NQ		 2909 if (frame_dur == 0)
2910 frame_dur = 96000 / 30;
2911 }
2912
2913 if (sync_outside == 0) {
2914 if (!vh264_isr_parser(vf,
2915 pts_valid, buffer_index, pts))
2916 continue;
2917
2918 h264_pts_count++;
2919 } else {
2920 if (!idr_flag)
2921 pts_valid = 0;
2922 }
2923
2924 if (pts_valid && !pts_discontinue) {
2925 pts_discontinue =
2926 (abs(last_pts - pts) >=
2927 tsync_vpts_discontinuity_margin());
2928 }
2929 /* if use_idr_framerate or fixed frame rate, only
2930 * use PTS for IDR frames except for pts discontinue
2931 */
2932 if (timing_info_present_flag &&
2933 frame_dur &&
2934 (use_idr_framerate ||
2935 (fixed_frame_rate_flag != 0))
2936 && pts_valid && h264_first_valid_pts_ready
2937 && (!pts_discontinue)) {
2938 pts_valid =
2939 (slice_type == SLICE_TYPE_I) ? 1 : 0;
2940 }
2941
2942 if (!h264_first_valid_pts_ready && pts_valid) {
2943 h264_first_valid_pts_ready = true;
2944 last_pts = pts - DUR2PTS(frame_dur);
2945 last_pts_remainder = 0;
2946 }
2947 /* calculate PTS of next frame and smooth
2948 * PTS for fixed rate source
2949 */
2950 if (pts_valid) {
2951 if ((fixed_frame_rate_flag) &&
2952 (!pts_discontinue) &&
2953 (abs(pts_inc_by_duration(NULL, NULL)
2954 - pts)
2955 < DUR2PTS(frame_dur))) {
2956 pts = pts_inc_by_duration(&pts,
2957 &last_pts_remainder);
2958 } else
2959 last_pts_remainder = 0;
2960
2961 } else {
2962 if (fixed_frame_rate_flag && !pts_discontinue &&
2963 (fixed_frame_rate_check_count > idr_num) &&
2964 pts_valid_save && (sync_outside == 0) &&
2965 (abs(pts_inc_by_duration(NULL, NULL) - pts)
2966 > DUR2PTS(frame_dur))) {
2967 duration_from_pts_done = 0;
2968 pr_info("recalc frame_dur\n");
2969 } else
2970 pts = pts_inc_by_duration(&pts,
2971 &last_pts_remainder);
2972 pts_valid = 1;
2973 }
2974
2975 if ((dec_control &
2976 flg_1080_itl)
2977 && (frame_width == 1920)
2978 && (frame_height >= 1080)
2979 && (vf->duration == 3203))
2980 force_interlaced_frame = true;
2981 else if ((dec_control &
2982 flg_576_itl)
2983 && (frame_width == 720)
2984 && (frame_height == 576)
2985 && (vf->duration == 3840))
2986 force_interlaced_frame = true;
2987
2988 /* for frames with PTS, check if there is PTS
2989 * discontinue based on previous frames
e0614bf7 2990 * (including error frames),
b9164398
NQ		 2991 * force no VPTS discontinue reporting if we saw
2992 *errors earlier but only once.
2993 */
fe96802b
NQ		 2994
2995 /*count info*/
2996 gvs->frame_dur = frame_dur;
2997 vdec_count_info(gvs, error, b_offset);
2998
b9164398
NQ		 2999 if ((pts_valid) && (check_pts_discontinue)
3000 && (!error)) {
3001 if (pts_discontinue) {
3002 vf->flag = 0;
3003 check_pts_discontinue = false;
3004 } else if ((pts - last_pts) < 90000) {
3005 vf->flag = VFRAME_FLAG_NO_DISCONTINUE;
3006 check_pts_discontinue = false;
3007 }
3008 }
3009
3010 last_pts = pts;
3011
3012 if (fixed_frame_rate_flag
3013 && (fixed_frame_rate_check_count <=
3014 idr_num)
3015 && (sync_outside == 0)
3016 && pts_valid_save)
3017 pts = pts_lookup_save;
3018
3019 if (pic_struct_present) {
3020 if ((pic_struct == PIC_TOP_BOT)
3021 || (pic_struct == PIC_BOT_TOP))
3022 prog_frame = 0;
3023 }
3024
3025 if ((!force_interlaced_frame)
3026 && (prog_frame
3027 || (pic_struct_present
3028 && pic_struct
3029 <= PIC_TRIPLE_FRAME))) {
3030 if (pic_struct_present) {
3031 if (pic_struct == PIC_TOP_BOT_TOP
3032 || pic_struct
3033 == PIC_BOT_TOP_BOT) {
3034 vf->duration +=
3035 vf->duration >> 1;
3036 } else if (pic_struct ==
3037 PIC_DOUBLE_FRAME)
3038 vf->duration += vf->duration;
3039 else if (pic_struct ==
3040 PIC_TRIPLE_FRAME) {
3041 vf->duration +=
3042 vf->duration << 1;
3043 }
3044 }
3045
3046 last_pts =
3047 last_pts + DUR2PTS(vf->duration -
3048 frame_dur);
3049
3050 vf->index = buffer_index;
3051 vf->type =
3052 VIDTYPE_PROGRESSIVE |
3053 VIDTYPE_VIU_FIELD |
3054 VIDTYPE_VIU_NV21;
3055 vf->duration_pulldown = 0;
3056 vf->signal_type = video_signal_from_vui;
3057 vf->index = buffer_index;
3058 vf->pts = (pts_valid) ? pts : 0;
3059 if (pts_us64_valid == 1)
3060 vf->pts_us64 = pts_us64;
3061 else
3062 vf->pts_us64 = div64_u64(((u64)vf->pts)*100, 9);
3063 vf->canvas0Addr = vf->canvas1Addr =
3064 spec2canvas(&buffer_spec[buffer_index]);
3065 vf->type_original = vf->type;
3066 vfbuf_use[buffer_index]++;
3067 vf->mem_handle =
3068 decoder_bmmu_box_get_mem_handle(
3069 mm_blk_handle,
fe96802b 3070 VF_BUFFER_IDX(buffer_index));
5050c738 3071 decoder_do_frame_check(NULL, vf);
b9164398
NQ		 3072 if ((error_recovery_mode_use & 2) && error) {
3073 kfifo_put(&recycle_q,
3074 (const struct vframe_s *)vf);
3075 } else {
3076 p_last_vf = vf;
3077 pts_discontinue = false;
3078 kfifo_put(&delay_display_q,
3079 (const struct vframe_s *)vf);
3080 }
3081 } else {
3082 if (pic_struct_present
3083 && pic_struct == PIC_TOP_BOT)
3084 vf->type = VIDTYPE_INTERLACE_TOP;
3085 else if (pic_struct_present
3086 && pic_struct == PIC_BOT_TOP)
3087 vf->type = VIDTYPE_INTERLACE_BOTTOM;
3088 else {
3089 vf->type =
3090 poc_sel ?
3091 VIDTYPE_INTERLACE_BOTTOM :
3092 VIDTYPE_INTERLACE_TOP;
3093 }
3094 vf->type |= VIDTYPE_VIU_NV21;
3095 vf->type |= VIDTYPE_INTERLACE_FIRST;
3096
e0614bf7 3097 high_bandwidth |=
b9164398
NQ		 3098 ((codec_mm_get_total_size() < 80 * SZ_1M)
3099 & ((READ_VREG(AV_SCRATCH_N) & 0xf) == 3)
3100 & ((frame_width * frame_height) >= 1920*1080));
e0614bf7 3101 if (high_bandwidth)
b9164398
NQ		 3102 vf->flag |= VFRAME_FLAG_HIGH_BANDWIDTH;
3103
3104 vf->duration >>= 1;
3105 vf->duration_pulldown = 0;
3106 vf->signal_type = video_signal_from_vui;
3107 vf->index = buffer_index;
3108 vf->pts = (pts_valid) ? pts : 0;
3109 if (pts_us64_valid == 1)
3110 vf->pts_us64 = pts_us64;
3111 else
3112 vf->pts_us64 = div64_u64(((u64)vf->pts)*100, 9);
3113 vf->canvas0Addr = vf->canvas1Addr =
3114 spec2canvas(&buffer_spec[buffer_index]);
3115 vf->type_original = vf->type;
3116 vfbuf_use[buffer_index]++;
3117 vf->ready_jiffies64 = jiffies_64;
3118 vf->mem_handle =
3119 decoder_bmmu_box_get_mem_handle(
3120 mm_blk_handle,
fe96802b 3121 VF_BUFFER_IDX(buffer_index));
5050c738 3122 decoder_do_frame_check(NULL, vf);
b9164398
NQ		 3123 if ((error_recovery_mode_use & 2) && error) {
3124 kfifo_put(&recycle_q,
3125 (const struct vframe_s *)vf);
3126 continue;
3127 } else {
3128 pts_discontinue = false;
3129 kfifo_put(&delay_display_q,
3130 (const struct vframe_s *)vf);
3131 }
3132
3133 if (READ_VREG(AV_SCRATCH_F) & 2)
3134 continue;
3135
3136 if (kfifo_get(&newframe_q, &vf) == 0) {
3137 pr_info
3138 ("fatal error, no avail buffer slot.");
3139 return IRQ_HANDLED;
3140 }
3141
3142 set_frame_info(vf);
3143
3144 if (pic_struct_present
3145 && pic_struct == PIC_TOP_BOT)
3146 vf->type = VIDTYPE_INTERLACE_BOTTOM;
3147 else if (pic_struct_present
3148 && pic_struct == PIC_BOT_TOP)
3149 vf->type = VIDTYPE_INTERLACE_TOP;
3150 else {
3151 vf->type =
3152 poc_sel ?
3153 VIDTYPE_INTERLACE_TOP :
3154 VIDTYPE_INTERLACE_BOTTOM;
3155 }
3156
3157 vf->type |= VIDTYPE_VIU_NV21;
3158 vf->duration >>= 1;
3159 vf->duration_pulldown = 0;
3160 vf->signal_type = video_signal_from_vui;
3161 vf->index = buffer_index;
3162 vf->pts = 0;
3163 vf->pts_us64 = 0;
3164 vf->canvas0Addr = vf->canvas1Addr =
3165 spec2canvas(&buffer_spec[buffer_index]);
3166 vf->type_original = vf->type;
3167 vfbuf_use[buffer_index]++;
e0614bf7 3168 if (high_bandwidth)
b9164398
NQ		 3169 vf->flag |= VFRAME_FLAG_HIGH_BANDWIDTH;
3170
3171 p_last_vf = vf;
3172 vf->ready_jiffies64 = jiffies_64;
3173 vf->mem_handle =
3174 decoder_bmmu_box_get_mem_handle(
3175 mm_blk_handle,
fe96802b 3176 VF_BUFFER_IDX(buffer_index));
b9164398
NQ		 3177 kfifo_put(&delay_display_q,
3178 (const struct vframe_s *)vf);
3179 }
3180 }
3181
3182 WRITE_VREG(AV_SCRATCH_0, 0);
3183 } else if ((cpu_cmd & 0xff) == 3) {
3184 vh264_running = 1;
3185 vh264_stream_switching_state = SWITCHING_STATE_ON_CMD3;
3186
3187 pr_info("Enter switching mode cmd3.\n");
3188 schedule_work(&stream_switching_work);
3189
3190 } else if ((cpu_cmd & 0xff) == 4) {
3191 vh264_running = 1;
3192 /* reserved for slice group */
3193 WRITE_VREG(AV_SCRATCH_0, 0);
3194 } else if ((cpu_cmd & 0xff) == 5) {
3195 vh264_running = 1;
3196 /* reserved for slice group */
3197 WRITE_VREG(AV_SCRATCH_0, 0);
3198 } else if ((cpu_cmd & 0xff) == 6) {
3199 vh264_running = 0;
3200 fatal_error_flag = DECODER_FATAL_ERROR_UNKNOWN;
3201 /* this is fatal error, need restart */
fe96802b 3202 pr_info("fatal error happend\n");
fe96802b 3203 amvdec_stop();
b9164398
NQ		 3204 if (!fatal_error_reset)
3205 schedule_work(&error_wd_work);
3206 } else if ((cpu_cmd & 0xff) == 7) {
3207 vh264_running = 0;
3208 frame_width = (READ_VREG(AV_SCRATCH_1) + 1) * 16;
3209 pr_info("Over decoder supported size, width = %d\n",
3210 frame_width);
3211 fatal_error_flag = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
3212 } else if ((cpu_cmd & 0xff) == 8) {
3213 vh264_running = 0;
3214 frame_height = (READ_VREG(AV_SCRATCH_1) + 1) * 16;
3215 pr_info("Over decoder supported size, height = %d\n",
3216 frame_height);
3217 fatal_error_flag = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
3218 } else if ((cpu_cmd & 0xff) == 9) {
3219 first_offset = READ_VREG(AV_SCRATCH_1);
3220 if (pts_lookup_offset_us64
a8f62ee0
RZ		 3221 (PTS_TYPE_VIDEO, first_offset, &first_pts,
3222 &first_frame_size, 0,
b9164398
NQ		 3223 &first_pts64) == 0)
3224 first_pts_cached = true;
3225 WRITE_VREG(AV_SCRATCH_0, 0);
b9164398 3226 } else if ((cpu_cmd & 0xff) == 0xa) {
e0614bf7 3227 int b_offset;
a8f62ee0 3228 unsigned int frame_size;
e0614bf7
ZZ		 3229
3230 b_offset = READ_VREG(AV_SCRATCH_2);
3231 buffer_index = READ_VREG(AV_SCRATCH_1);
3232 /*pr_info("iponly output %d b_offset %x\n",
3233 * buffer_index,b_offset);
3234 */
3235 if (kfifo_get(&newframe_q, &vf) == 0) {
b9164398 3236 WRITE_VREG(AV_SCRATCH_0, 0);
e0614bf7
ZZ		 3237 pr_info
3238 ("fatal error, no available buffer slot.");
3239 return IRQ_HANDLED;
3240 }
3241 if (pts_lookup_offset_us64 (PTS_TYPE_VIDEO, b_offset,
a8f62ee0
RZ		 3242 &pts, &frame_size,
3243 0, &pts_us64) != 0)
e0614bf7
ZZ		 3244 vf->pts_us64 = vf->pts = 0;
3245 else {
3246 vf->pts_us64 = pts_us64;
3247 vf->pts = pts;
b9164398 3248 }
e0614bf7
ZZ		 3249 set_frame_info(vf);
3250 vf->type = VIDTYPE_PROGRESSIVE |
3251 VIDTYPE_VIU_FIELD |
3252 VIDTYPE_VIU_NV21;
3253 vf->duration_pulldown = 0;
3254 vf->signal_type = video_signal_from_vui;
3255 vf->index = buffer_index;
3256 vf->canvas0Addr = vf->canvas1Addr =
3257 spec2canvas(&buffer_spec[buffer_index]);
3258 vf->type_original = vf->type;
3259 vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3260 mm_blk_handle,
3261 VF_BUFFER_IDX(buffer_index));
3262 vfbuf_use[buffer_index]++;
3263 p_last_vf = vf;
3264 pts_discontinue = false;
3265 iponly_early_mode = 1;
5050c738 3266 decoder_do_frame_check(NULL, vf);
e0614bf7
ZZ		 3267 kfifo_put(&delay_display_q,
3268 (const struct vframe_s *)vf);
3269 WRITE_VREG(AV_SCRATCH_0, 0);
a8f62ee0
RZ		 3270 } else if ((cpu_cmd & 0xff) == 0xB) {
3271 schedule_work(&qos_work);
e0614bf7 3272 }
a8f62ee0 3273#ifdef ENABLE_SEI_ITU_T35
b9164398
NQ		 3274 sei_itu35_flags = READ_VREG(AV_SCRATCH_J);
3275 if (sei_itu35_flags & (1 << 15)) { /* data ready */
fe96802b 3276 schedule_work(&userdata_push_work);
b9164398 3277 }
a8f62ee0 3278#endif
b9164398
NQ		 3279#ifdef HANDLE_H264_IRQ
3280 return IRQ_HANDLED;
3281#else
3282 return;
3283#endif
3284}
3285
a994f6d6 3286static void vh264_set_clk(struct work_struct *work)
3287{
3288 if (ucode_type != UCODE_IP_ONLY_PARAM &&
3289 (clk_adj_frame_count > VDEC_CLOCK_ADJUST_FRAME) &&
3290 frame_dur > 0 && saved_resolution !=
3291 frame_width * frame_height * (96000 / frame_dur)) {
3292 int fps = 96000 / frame_dur;
3293
3294 if (frame_dur < 10) /*dur is too small ,think it errors fps*/
3295 fps = 60;
3296 saved_resolution = frame_width * frame_height * fps;
3297 vdec_source_changed(VFORMAT_H264,
3298 frame_width, frame_height, fps);
3299 }
3300}
3301
b9164398
NQ		 3302static void vh264_put_timer_func(unsigned long arg)
3303{
3304 struct timer_list *timer = (struct timer_list *)arg;
3305 unsigned int wait_buffer_status;
3306 unsigned int wait_i_pass_frames;
3307 unsigned int reg_val;
3308
3309 enum receviver_start_e state = RECEIVER_INACTIVE;
3310
3311 if (vh264_reset) {
3312 pr_info("operation forbidden in timer !\n");
3313 goto exit;
3314 }
3315
3316 prepare_display_q();
3317
3318 if (vf_get_receiver(PROVIDER_NAME)) {
3319 state =
3320 vf_notify_receiver(PROVIDER_NAME,
3321 VFRAME_EVENT_PROVIDER_QUREY_STATE,
3322 NULL);
3323 if ((state == RECEIVER_STATE_NULL)
3324 || (state == RECEIVER_STATE_NONE)) {
3325 /* receiver has no event_cb or receiver's
3326 * event_cb does not process this event
3327 */
3328 state = RECEIVER_INACTIVE;
3329 }
3330 } else
3331 state = RECEIVER_INACTIVE;
3332#ifndef HANDLE_H264_IRQ
3333 vh264_isr();
3334#endif
3335
3336 if (vh264_stream_switching_state != SWITCHING_STATE_OFF)
3337 wait_buffer_counter = 0;
3338 else {
3339 reg_val = READ_VREG(AV_SCRATCH_9);
3340 wait_buffer_status = reg_val & (1 << 31);
3341 wait_i_pass_frames = reg_val & 0xff;
3342 if (wait_buffer_status) {
3343 if (kfifo_is_empty(&display_q) &&
3344 kfifo_is_empty(&delay_display_q) &&
3345 kfifo_is_empty(&recycle_q) &&
3346 (state == RECEIVER_INACTIVE)) {
3347 pr_info("$$$$decoder is waiting for buffer\n");
3348 if (++wait_buffer_counter > 4) {
3349 amvdec_stop();
fe96802b 3350 schedule_work(&error_wd_work);
b9164398
NQ		 3351 }
3352 } else
3353 wait_buffer_counter = 0;
3354 } else if (wait_i_pass_frames > 1000) {
3355 pr_info("i passed frames > 1000\n");
3356 amvdec_stop();
fe96802b 3357 schedule_work(&error_wd_work);
b9164398
NQ		 3358 }
3359 }
3360
3361#if 0
3362 if (!wait_buffer_status) {
3363 if (vh264_no_disp_count++ > NO_DISP_WD_COUNT) {
3364 pr_info("$$$decoder did not send frame out\n");
3365 amvdec_stop();
3366#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
3367 vh264_ppmgr_reset();
3368#else
3369 vf_light_unreg_provider(PROVIDER_NAME);
3370 vh264_local_init();
3371 vf_reg_provider(vh264_vf_prov);
3372#endif
3373 vh264_prot_init();
3374 amvdec_start();
3375
3376 vh264_no_disp_count = 0;
3377 vh264_no_disp_wd_count++;
3378 }
3379 }
3380#endif
3381
3382 while (!kfifo_is_empty(&recycle_q) &&
3383 ((READ_VREG(AV_SCRATCH_7) == 0)
3384 || (READ_VREG(AV_SCRATCH_8) == 0))
3385 && (vh264_stream_switching_state == SWITCHING_STATE_OFF)) {
3386 struct vframe_s *vf;
3387
3388 if (kfifo_get(&recycle_q, &vf)) {
a35da9f0 3389 if (vf->index < VF_BUF_NUM) {
b9164398
NQ		 3390 if (--vfbuf_use[vf->index] == 0) {
3391 if (READ_VREG(AV_SCRATCH_7) == 0) {
3392 WRITE_VREG(AV_SCRATCH_7,
3393 vf->index + 1);
3394 } else {
3395 WRITE_VREG(AV_SCRATCH_8,
3396 vf->index + 1);
3397 }
3398 }
3399
3400 vf->index = VF_BUF_NUM;
3401 kfifo_put(&newframe_q,
3402 (const struct vframe_s *)vf);
3403 }
3404 }
3405 }
3406
3407 if (vh264_stream_switching_state != SWITCHING_STATE_OFF) {
3408 while (!kfifo_is_empty(&recycle_q)) {
3409 struct vframe_s *vf;
3410
3411 if (kfifo_get(&recycle_q, &vf)) {
a35da9f0 3412 if (vf->index < VF_BUF_NUM) {
b9164398
NQ		 3413 vf->index = VF_BUF_NUM;
3414 kfifo_put(&newframe_q,
3415 (const struct vframe_s *)vf);
3416 }
3417 }
3418 }
3419
3420 WRITE_VREG(AV_SCRATCH_7, 0);
3421 WRITE_VREG(AV_SCRATCH_8, 0);
3422
3423 if (kfifo_len(&newframe_q) == VF_POOL_SIZE)
3424 stream_switching_done();
3425 }
3426
a994f6d6 3427 schedule_work(&set_clk_work);
b9164398 3428
b9164398
NQ		 3429exit:
3430 timer->expires = jiffies + PUT_INTERVAL;
3431
3432 add_timer(timer);
3433}
3434
fe96802b 3435int vh264_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
b9164398 3436{
70809fec
NQ		 3437 if (!(stat & STAT_VDEC_RUN))
3438 return -1;
3439
fe96802b
NQ		 3440 vstatus->frame_width = frame_width;
3441 vstatus->frame_height = frame_height;
b9164398 3442 if (frame_dur != 0)
fe96802b 3443 vstatus->frame_rate = 96000 / frame_dur;
b9164398 3444 else
fe96802b 3445 vstatus->frame_rate = -1;
b9164398
NQ		 3446 vstatus->error_count = READ_VREG(AV_SCRATCH_D);
3447 vstatus->status = stat;
3448 if (fatal_error_reset)
3449 vstatus->status |= fatal_error_flag;
fe96802b
NQ		 3450 vstatus->bit_rate = gvs->bit_rate;
3451 vstatus->frame_dur = frame_dur;
3452 vstatus->frame_data = gvs->frame_data;
3453 vstatus->total_data = gvs->total_data;
3454 vstatus->frame_count = gvs->frame_count;
3455 vstatus->error_frame_count = gvs->error_frame_count;
3456 vstatus->drop_frame_count = gvs->drop_frame_count;
3457 vstatus->total_data = gvs->total_data;
3458 vstatus->samp_cnt = gvs->samp_cnt;
3459 vstatus->offset = gvs->offset;
3460 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
3461 "%s", DRIVER_NAME);
3462
3463 return 0;
3464}
3465
3466static int vh264_vdec_info_init(void)
3467{
3468 gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL);
3469 if (NULL == gvs) {
3470 pr_info("the struct of vdec status malloc failed.\n");
3471 return -ENOMEM;
3472 }
b9164398
NQ		 3473 return 0;
3474}
3475
3476int vh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
3477{
3478 if (trickmode == TRICKMODE_I) {
3479 WRITE_VREG(AV_SCRATCH_F,
3480 (READ_VREG(AV_SCRATCH_F) & 0xfffffffc) | 2);
3481 trickmode_i = 1;
3482 } else if (trickmode == TRICKMODE_NONE) {
3483 WRITE_VREG(AV_SCRATCH_F, READ_VREG(AV_SCRATCH_F) & 0xfffffffc);
3484 trickmode_i = 0;
3485 }
3486
3487 return 0;
3488}
3489
d481db31
NQ		 3490int vh264_set_isreset(struct vdec_s *vdec, int isreset)
3491{
3492 is_reset = isreset;
3493 return 0;
3494}
3495
b9164398
NQ		 3496static void vh264_prot_init(void)
3497{
3498
3499 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
3500 ;
3501 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
3502 ; /* reg address is 0x350 */
3503
3504#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
3505 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
3506 WRITE_VREG(DOS_SW_RESET0, 0);
3507
3508 READ_VREG(DOS_SW_RESET0);
3509 READ_VREG(DOS_SW_RESET0);
3510 READ_VREG(DOS_SW_RESET0);
3511
3512 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
3513 WRITE_VREG(DOS_SW_RESET0, 0);
3514
3515 WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8));
3516 WRITE_VREG(DOS_SW_RESET0, 0);
3517
3518 READ_VREG(DOS_SW_RESET0);
3519 READ_VREG(DOS_SW_RESET0);
3520 READ_VREG(DOS_SW_RESET0);
3521
3522#else
fe96802b 3523 WRITE_RESET_REG(RESET0_REGISTER,
b9164398 3524 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
fe96802b
NQ		 3525 READ_RESET_REG(RESET0_REGISTER);
3526 WRITE_RESET_REG(RESET0_REGISTER,
b9164398
NQ		 3527 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
3528
fe96802b 3529 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
b9164398
NQ		 3530#endif
3531
3532 WRITE_VREG(POWER_CTL_VLD,
3533 READ_VREG(POWER_CTL_VLD) |
3534 (0 << 10) | (1 << 9) | (1 << 6));
3535
3536 /* disable PSCALE for hardware sharing */
3537 WRITE_VREG(PSCALE_CTRL, 0);
3538
3539 WRITE_VREG(AV_SCRATCH_0, 0);
3540 WRITE_VREG(AV_SCRATCH_1, buf_offset);
8247f369 3541 if (!tee_enabled())
d481db31 3542 WRITE_VREG(AV_SCRATCH_G, mc_dma_handle);
b9164398
NQ		 3543 WRITE_VREG(AV_SCRATCH_7, 0);
3544 WRITE_VREG(AV_SCRATCH_8, 0);
3545 WRITE_VREG(AV_SCRATCH_9, 0);
3546 WRITE_VREG(AV_SCRATCH_N, 0);
3547
d481db31
NQ		 3548#ifdef SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY
3549 if (bad_block_scale > 128)
3550 bad_block_scale = 128;
3551 WRITE_VREG(AV_SCRATCH_A, bad_block_scale);
3552#endif
3553
b9164398
NQ		 3554 error_recovery_mode_use =
3555 (error_recovery_mode !=
3556 0) ? error_recovery_mode : error_recovery_mode_in;
3557 WRITE_VREG(AV_SCRATCH_F,
3558 (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
3559 (READ_VREG(AV_SCRATCH_F) & 0xffffff43) |
3560 ((error_recovery_mode_use & 0x1) << 4));
3561 if (dec_control & DEC_CONTROL_FLAG_DISABLE_FAST_POC)
3562 SET_VREG_MASK(AV_SCRATCH_F, 1 << 7);
3563 /* clear mailbox interrupt */
3564 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
3565
3566 /* enable mailbox interrupt */
3567 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
3568
3569 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
3570 if (ucode_type == UCODE_IP_ONLY_PARAM)
3571 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
3572 else
3573 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
3574
3575 WRITE_VREG(AV_SCRATCH_I, (u32)(sei_data_buffer_phys - buf_offset));
3576 WRITE_VREG(AV_SCRATCH_J, 0);
3577 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
63e810c0 3578 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_M8) && !is_meson_mtvd_cpu()) {
b9164398
NQ		 3579 /* pr_info("vh264 meson8 prot init\n"); */
3580 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
3581 }
3582 /* #endif */
3583}
3584
fe96802b 3585static int vh264_local_init(void)
b9164398 3586{
fe96802b
NQ		 3587 int i, ret;
3588 u32 size;
3589 unsigned long buf_start;
b9164398
NQ		 3590 vh264_ratio = vh264_amstream_dec_info.ratio;
3591 /* vh264_ratio = 0x100; */
3592
3593 vh264_rotation = (((unsigned long) vh264_amstream_dec_info.param)
3594 >> 16) & 0xffff;
3595
b9164398
NQ		 3596 frame_prog = 0;
3597 frame_width = vh264_amstream_dec_info.width;
3598 frame_height = vh264_amstream_dec_info.height;
3599 frame_dur = vh264_amstream_dec_info.rate;
3600 pts_outside = ((unsigned long) vh264_amstream_dec_info.param) & 0x01;
3601 sync_outside = ((unsigned long) vh264_amstream_dec_info.param & 0x02)
3602 >> 1;
3603 use_idr_framerate = ((unsigned long) vh264_amstream_dec_info.param
3604 & 0x04) >> 2;
3605 max_refer_buf = !(((unsigned long) vh264_amstream_dec_info.param
3606 & 0x10) >> 4);
fe96802b
NQ		 3607 if (!vh264_reset) {
3608 if (mm_blk_handle) {
3609 decoder_bmmu_box_free(mm_blk_handle);
3610 mm_blk_handle = NULL;
3611 }
3612
b9164398
NQ		 3613 mm_blk_handle = decoder_bmmu_box_alloc_box(
3614 DRIVER_NAME,
3615 0,
3616 MAX_BLK_BUFFERS,
3617 4 + PAGE_SHIFT,
3618 CODEC_MM_FLAGS_CMA_CLEAR |
fe96802b
NQ		 3619 CODEC_MM_FLAGS_FOR_VDECODER |
3620 tvp_flag);
3621 }
b9164398 3622 pr_info
5b851ff9 3623 ("H264 sysinfo: %dx%d duration=%d, pts_outside=%d \n",
b9164398
NQ		 3624 frame_width, frame_height, frame_dur, pts_outside);
3625 pr_debug("sync_outside=%d, use_idr_framerate=%d\n",
3626 sync_outside, use_idr_framerate);
3627
63e810c0 3628 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB)
fe96802b
NQ		 3629 size = V_BUF_ADDR_OFFSET_NEW;
3630 else
3631 size = V_BUF_ADDR_OFFSET;
3632
3633 ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, 0,
3634 size, DRIVER_NAME, &buf_start);
3635 if (ret < 0)
3636 return ret;
3637
3638 buf_offset = buf_start - DEF_BUF_START_ADDR;
3639
b9164398
NQ		 3640 if ((unsigned long) vh264_amstream_dec_info.param & 0x08)
3641 ucode_type = UCODE_IP_ONLY_PARAM;
3642 else
3643 ucode_type = 0;
3644
3645 if ((unsigned long) vh264_amstream_dec_info.param & 0x20)
3646 error_recovery_mode_in = 1;
3647 else
3648 error_recovery_mode_in = 3;
3649
3650 if (!vh264_running) {
3651 last_mb_width = 0;
3652 last_mb_height = 0;
3653 }
3654
3655 for (i = 0; i < VF_BUF_NUM; i++)
3656 vfbuf_use[i] = 0;
3657
3658 INIT_KFIFO(display_q);
3659 INIT_KFIFO(delay_display_q);
3660 INIT_KFIFO(recycle_q);
3661 INIT_KFIFO(newframe_q);
3662
3663 for (i = 0; i < VF_POOL_SIZE; i++) {
3664 const struct vframe_s *vf = &vfpool[i];
3665
3666 vfpool[i].index = VF_BUF_NUM;
3667 vfpool[i].bufWidth = 1920;
3668 kfifo_put(&newframe_q, vf);
3669 }
3670
3671#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS
3672 last_interlaced = 1;
3673#endif
3674 h264_first_pts_ready = 0;
3675 h264_first_valid_pts_ready = false;
3676 h264pts1 = 0;
3677 h264pts2 = 0;
3678 h264_pts_count = 0;
3679 duration_from_pts_done = 0;
3680 vh264_error_count = READ_VREG(AV_SCRATCH_D);
3681
3682 p_last_vf = NULL;
3683 check_pts_discontinue = false;
3684 last_pts = 0;
3685 wait_buffer_counter = 0;
3686 vh264_no_disp_count = 0;
3687 fatal_error_flag = 0;
e0614bf7 3688 high_bandwidth = 0;
b9164398
NQ		 3689 vh264_stream_switching_state = SWITCHING_STATE_OFF;
3690#ifdef DEBUG_PTS
3691 pts_missed = 0;
3692 pts_hit = 0;
3693#endif
3694 pts_discontinue = false;
3695 no_idr_error_count = 0;
fe96802b 3696
9cc3c918 3697 vh264_reset_userdata_fifo(vdec_h264, 1);
a8f62ee0 3698 h264_reset_qos_mgr();
fe96802b
NQ		 3699
3700 if (enable_switch_fense) {
3701 for (i = 0; i < ARRAY_SIZE(fense_buffer_spec); i++) {
3702 struct buffer_spec_s *s = &fense_buffer_spec[i];
3703 s->alloc_count = 3 * SZ_1M / PAGE_SIZE;
3704 ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle,
3705 FENSE_BUFFER_IDX(i),
3706 3 * SZ_1M, DRIVER_NAME, &s->phy_addr);
3707
3708 if (ret < 0) {
3709 fatal_error_flag =
3710 DECODER_FATAL_ERROR_NO_MEM;
3711 vh264_running = 0;
3712 return ret;
3713 }
3714 s->y_canvas_index = 2 * i;
3715 s->u_canvas_index = 2 * i + 1;
3716 s->v_canvas_index = 2 * i + 1;
3717 }
3718 }
3719 return 0;
b9164398
NQ		 3720}
3721
3722static s32 vh264_init(void)
3723{
fe96802b 3724 int ret = 0;
b9164398
NQ		 3725 int trickmode_fffb = 0;
3726 int firmwareloaded = 0;
b9164398
NQ		 3727
3728 /* pr_info("\nvh264_init\n"); */
3729 init_timer(&recycle_timer);
3730
3731 stat |= STAT_TIMER_INIT;
3732
3733 vh264_running = 0;/* init here to reset last_mb_width&last_mb_height */
3734 vh264_eos = 0;
3735 duration_on_correcting = 0;
3736 first_pts = 0;
3737 first_pts64 = 0;
3738 first_offset = 0;
3739 first_pts_cached = false;
3740 fixed_frame_rate_check_count = 0;
fe96802b 3741 fr_hint_status = VDEC_NO_NEED_HINT;
b9164398
NQ		 3742 saved_resolution = 0;
3743 iponly_early_mode = 0;
3744 saved_idc_level = 0;
b9164398 3745
a8f62ee0
RZ		 3746 frame_count = 0;
3747 memset(&s_vframe_qos, 0, sizeof(s_vframe_qos));
fe96802b
NQ		 3748 /*init vdec status*/
3749 ret = vh264_vdec_info_init();
3750 if (0 != ret)
3751 return -ret;
3752
fe96802b
NQ		 3753 ret = vh264_local_init();
3754 if (ret < 0)
3755 return ret;
3756 query_video_status(0, &trickmode_fffb);
b9164398
NQ		 3757
3758 amvdec_enable();
8247f369 3759 if (!firmwareloaded && tee_enabled()) {
668e656d
NQ		 3760 ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, NULL);
3761 if (ret < 0) {
d481db31 3762 amvdec_disable();
668e656d
NQ		 3763 pr_err("H264: the %s fw loading failed, err: %x\n",
3764 tee_enabled() ? "TEE" : "local", ret);
3765 return ret;
d481db31
NQ		 3766 }
3767 } else {
b9164398
NQ		 3768 /* -- ucode loading (amrisc and swap code) */
3769 mc_cpu_addr =
3770 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
3771 &mc_dma_handle, GFP_KERNEL);
3772 if (!mc_cpu_addr) {
3773 amvdec_disable();
fe96802b 3774 del_timer_sync(&recycle_timer);
b9164398
NQ		 3775 pr_err("vh264_init: Can not allocate mc memory.\n");
3776 return -ENOMEM;
3777 }
3778
3779 pr_debug("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
3780 (void *)mc_dma_handle, mc_cpu_addr);
3781 if (debugfirmware) {
3782 int r0, r1, r2, r3, r4, r5;
3783 char firmwarename[32];
3784
3785 pr_debug("start load debug %d firmware ...\n", debugfirmware);
3786
3787 snprintf(firmwarename, 32, "%s%d", "vh264_mc", debugfirmware);
3788 r0 = amvdec_loadmc_ex(VFORMAT_H264, firmwarename, NULL);
3789
3790#define DEBUGGET_FW(t, name, buf, size, ret)\
3791 do {\
3792 snprintf(firmwarename, 32, "%s%d", name,\
3793 debugfirmware);\
3794 ret = get_decoder_firmware_data(t,\
3795 firmwarename, buf, size);\
3796 } while (0)
3797 /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_HEADER, vh264_header_mc,
e0614bf7
ZZ		 3798 *MC_SWAP_SIZE);
3799 */
b9164398
NQ		 3800 DEBUGGET_FW(VFORMAT_H264, "vh264_header_mc",
3801 (u8 *) mc_cpu_addr + MC_OFFSET_HEADER,
3802 MC_SWAP_SIZE, r1);
3803
3804 /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_DATA, vh264_data_mc,
e0614bf7
ZZ		 3805 *MC_SWAP_SIZE);
3806 */
b9164398
NQ		 3807 DEBUGGET_FW(VFORMAT_H264, "vh264_data_mc",
3808 (u8 *) mc_cpu_addr + MC_OFFSET_DATA, MC_SWAP_SIZE, r2);
3809 /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_MMCO, vh264_mmco_mc,
e0614bf7
ZZ		 3810 *MC_SWAP_SIZE);
3811 */
b9164398
NQ		 3812 DEBUGGET_FW(VFORMAT_H264, "vh264_mmco_mc",
3813 (u8 *) mc_cpu_addr + MC_OFFSET_MMCO, MC_SWAP_SIZE, r3);
3814 /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_LIST, vh264_list_mc,
e0614bf7
ZZ		 3815 *MC_SWAP_SIZE);
3816 */
b9164398
NQ		 3817 DEBUGGET_FW(VFORMAT_H264, "vh264_list_mc",
3818 (u8 *) mc_cpu_addr + MC_OFFSET_LIST, MC_SWAP_SIZE, r4);
3819 /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_SLICE, vh264_slice_mc,
e0614bf7
ZZ		 3820 *MC_SWAP_SIZE);
3821 */
b9164398
NQ		 3822 DEBUGGET_FW(VFORMAT_H264, "vh264_slice_mc",
3823 (u8 *) mc_cpu_addr + MC_OFFSET_SLICE, MC_SWAP_SIZE, r5);
3824
3825 if (r0 < 0 || r1 < 0 || r2 < 0 || r3 < 0 || r4 < 0 || r5 < 0) {
3826 pr_err("264 load debugfirmware err %d,%d,%d,%d,%d,%d\n",
3827 r0, r1, r2, r3, r4, r5);
3828 amvdec_disable();
3829 if (mc_cpu_addr) {
3830 dma_free_coherent(amports_get_dma_device(),
3831 MC_TOTAL_SIZE, mc_cpu_addr,
3832 mc_dma_handle);
3833 mc_cpu_addr = NULL;
3834 }
3835 return -EBUSY;
3836 }
3837 firmwareloaded = 1;
3838 } else {
668e656d 3839 int ret = -1;
b9164398 3840 char *buf = vmalloc(0x1000 * 16);
e0614bf7 3841
b9164398
NQ		 3842 if (IS_ERR_OR_NULL(buf))
3843 return -ENOMEM;
3844
668e656d 3845 if (get_firmware_data(VIDEO_DEC_H264, buf) < 0) {
b9164398
NQ		 3846 pr_err("get firmware fail.");
3847 vfree(buf);
3848 return -1;
3849 }
3850
3851 ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);
3852 memcpy((u8 *) mc_cpu_addr + MC_OFFSET_HEADER,
3853 buf + 0x4000, MC_SWAP_SIZE);
3854 memcpy((u8 *) mc_cpu_addr + MC_OFFSET_DATA,
3855 buf + 0x2000, MC_SWAP_SIZE);
3856 memcpy((u8 *) mc_cpu_addr + MC_OFFSET_MMCO,
3857 buf + 0x6000, MC_SWAP_SIZE);
3858 memcpy((u8 *) mc_cpu_addr + MC_OFFSET_LIST,
3859 buf + 0x3000, MC_SWAP_SIZE);
3860 memcpy((u8 *) mc_cpu_addr + MC_OFFSET_SLICE,
3861 buf + 0x5000, MC_SWAP_SIZE);
3862
3863 vfree(buf);
3864
3865 if (ret < 0) {
b9164398
NQ		 3866 amvdec_disable();
3867 if (mc_cpu_addr) {
3868 dma_free_coherent(amports_get_dma_device(),
3869 MC_TOTAL_SIZE, mc_cpu_addr,
3870 mc_dma_handle);
3871 mc_cpu_addr = NULL;
3872 }
668e656d
NQ		 3873 pr_err("H264: the %s fw loading failed, err: %x\n",
3874 tee_enabled() ? "TEE" : "local", ret);
b9164398
NQ		 3875 return -EBUSY;
3876 }
3877 }
d481db31 3878 }
b9164398
NQ		 3879
3880 stat |= STAT_MC_LOAD;
fe96802b 3881
b9164398
NQ		 3882 /* enable AMRISC side protocol */
3883 vh264_prot_init();
3884
3885#ifdef HANDLE_H264_IRQ
3886 /*TODO irq */
3887
3888 if (vdec_request_irq(VDEC_IRQ_1, vh264_isr,
3889 "vh264-irq", (void *)vh264_dec_id)) {
3890 pr_err("vh264 irq register error.\n");
3891 amvdec_disable();
3892 return -ENOENT;
3893 }
3894#endif
3895
3896 stat |= STAT_ISR_REG;
3897
3898#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
3899 vf_provider_init(&vh264_vf_prov, PROVIDER_NAME, &vh264_vf_provider_ops,
3900 NULL);
3901 vf_reg_provider(&vh264_vf_prov);
3902 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
3903#else
3904 vf_provider_init(&vh264_vf_prov, PROVIDER_NAME, &vh264_vf_provider_ops,
3905 NULL);
3906 vf_reg_provider(&vh264_vf_prov);
3907#endif
3908
fe96802b 3909 if (frame_dur != 0) {
6d2907a6 3910 if (!is_reset) {
d481db31
NQ		 3911 vf_notify_receiver(PROVIDER_NAME,
3912 VFRAME_EVENT_PROVIDER_FR_HINT,
3913 (void *)((unsigned long)frame_dur));
6d2907a6
LC		 3914 fr_hint_status = VDEC_HINTED;
3915 }
fe96802b
NQ		 3916 } else
3917 fr_hint_status = VDEC_NEED_HINT;
b9164398
NQ		 3918
3919 stat |= STAT_VF_HOOK;
3920
3921 recycle_timer.data = (ulong) &recycle_timer;
3922 recycle_timer.function = vh264_put_timer_func;
3923 recycle_timer.expires = jiffies + PUT_INTERVAL;
3924
3925 add_timer(&recycle_timer);
3926
3927 stat |= STAT_TIMER_ARM;
3928
3929 vh264_stream_switching_state = SWITCHING_STATE_OFF;
3930
3931 stat |= STAT_VDEC_RUN;
3932 wmb(); /* Ensure fetchbuf contents visible */
3933
3934 /* -- start decoder */
3935 amvdec_start();
3936
3937 init_userdata_fifo();
3938
3939 return 0;
3940}
3941
3942static int vh264_stop(int mode)
3943{
3944
3945
3946 if (stat & STAT_VDEC_RUN) {
3947 amvdec_stop();
3948 stat &= ~STAT_VDEC_RUN;
3949 }
3950
3951 if (stat & STAT_ISR_REG) {
3952 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
3953 /*TODO irq */
3954
3955 vdec_free_irq(VDEC_IRQ_1, (void *)vh264_dec_id);
3956
3957 stat &= ~STAT_ISR_REG;
3958 }
3959
3960 if (stat & STAT_TIMER_ARM) {
3961 del_timer_sync(&recycle_timer);
3962 stat &= ~STAT_TIMER_ARM;
3963 }
3964
3965 if (stat & STAT_VF_HOOK) {
3966 if (mode == MODE_FULL) {
6d2907a6 3967 if (fr_hint_status == VDEC_HINTED)
fe96802b 3968 vf_notify_receiver(PROVIDER_NAME,
b9164398
NQ		 3969 VFRAME_EVENT_PROVIDER_FR_END_HINT,
3970 NULL);
fe96802b 3971 fr_hint_status = VDEC_NO_NEED_HINT;
b9164398
NQ		 3972 }
3973
3974 vf_unreg_provider(&vh264_vf_prov);
3975 stat &= ~STAT_VF_HOOK;
3976 }
3977
3978 if (stat & STAT_MC_LOAD) {
3979 if (mc_cpu_addr != NULL) {
3980 dma_free_coherent(amports_get_dma_device(),
3981 MC_TOTAL_SIZE, mc_cpu_addr,
3982 mc_dma_handle);
3983 mc_cpu_addr = NULL;
3984 }
3985 }
3986 if (sei_data_buffer != NULL) {
3987 dma_free_coherent(
3988 amports_get_dma_device(),
fe96802b 3989 USER_DATA_RUND_SIZE,
b9164398
NQ		 3990 sei_data_buffer,
3991 sei_data_buffer_phys);
3992 sei_data_buffer = NULL;
3993 sei_data_buffer_phys = 0;
3994 }
3995 amvdec_disable();
3996 if (mm_blk_handle) {
3997 decoder_bmmu_box_free(mm_blk_handle);
3998 mm_blk_handle = NULL;
3999 }
4000 memset(&fense_buffer_spec, 0, sizeof(fense_buffer_spec));
4001 memset(&buffer_spec, 0, sizeof(buffer_spec));
4002 return 0;
4003}
4004
48459a8e
HZ		 4005static void wait_vh264_search_done(void)
4006{
4007 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
4008 int count = 0;
4009 do {
4010 usleep_range(100, 500);
4011 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
4012 break;
4013 if (count > 2000) {
4014 pr_info("%s, timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
4015 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
4016 break;
4017 } else
4018 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
4019 count++;
4020 } while (1);
4021}
4022
4023
b9164398
NQ		 4024static void error_do_work(struct work_struct *work)
4025{
b9164398
NQ		 4026
4027 /*
4028 * we need to lock vh264_stop/vh264_init.
4029 * because we will call amvdec_h264_remove on this step;
4030 * then we may call more than once on
4031 * free_irq/deltimer/..and some other.
4032 */
4033 if (atomic_read(&vh264_active)) {
d481db31 4034 amvdec_stop();
fe96802b 4035 do {
48459a8e 4036 msleep(50);
fe96802b 4037 } while (vh264_stream_switching_state != SWITCHING_STATE_OFF);
48459a8e 4038 wait_vh264_search_done();
b9164398
NQ		 4039 vh264_reset = 1;
4040#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
4041 vh264_ppmgr_reset();
4042#else
4043 vf_light_unreg_provider(&vh264_vf_prov);
4044
4045 vh264_local_init();
4046
4047 vf_reg_provider(&vh264_vf_prov);
4048#endif
b9164398 4049 vh264_prot_init();
b9164398
NQ		 4050 amvdec_start();
4051 vh264_reset = 0;
4052 }
b9164398
NQ		 4053}
4054
4055static void stream_switching_done(void)
4056{
4057 int state = vh264_stream_switching_state;
4058
4059 WRITE_VREG(AV_SCRATCH_7, 0);
4060 WRITE_VREG(AV_SCRATCH_8, 0);
4061 WRITE_VREG(AV_SCRATCH_9, 0);
4062
4063 if (state == SWITCHING_STATE_ON_CMD1) {
4064 pr_info("Enter set parameter cmd1 switching_state %x.\n",
4065 vh264_stream_switching_state);
4066 schedule_work(&set_parameter_work);
4067 return;
4068 } else if (state == SWITCHING_STATE_ON_CMD1_PENDING)
4069 return;
4070
4071 vh264_stream_switching_state = SWITCHING_STATE_OFF;
4072
4073 wmb(); /* Ensure fetchbuf contents visible */
4074
4075 if (state == SWITCHING_STATE_ON_CMD3)
4076 WRITE_VREG(AV_SCRATCH_0, 0);
4077
4078 pr_info("Leaving switching mode.\n");
4079}
4080
4081/* construt a new frame as a copy of last frame so frame receiver can
4082 * release all buffer resources to decoder.
4083 */
4084static void stream_switching_do(struct work_struct *work)
4085{
4086 int mb_total_num, mb_width_num, mb_height_num, i = 0;
4087 struct vframe_s *vf = NULL;
4088 u32 y_index, u_index, src_index, des_index, y_desindex, u_desindex;
4089 struct canvas_s csy, csu, cyd;
4090 unsigned long flags;
4091 bool delay = true;
4092
4093 if (!atomic_read(&vh264_active))
4094 return;
4095
4096 if (vh264_stream_switching_state == SWITCHING_STATE_OFF)
4097 return;
4098
4099 spin_lock_irqsave(&prepare_lock, flags);
4100
4101 block_display_q = true;
4102
4103 spin_unlock_irqrestore(&prepare_lock, flags);
4104
4105 mb_total_num = mb_total;
4106 mb_width_num = mb_width;
4107 mb_height_num = mb_height;
4108
4109 while (is_4k || kfifo_len(&delay_display_q) > 2) {
4110 if (kfifo_get(&delay_display_q, &vf)) {
4111 kfifo_put(&display_q,
4112 (const struct vframe_s *)vf);
a093654a 4113 ATRACE_COUNTER(MODULE_NAME, vf->pts);
b9164398
NQ		 4114 vf_notify_receiver(PROVIDER_NAME,
4115 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
4116 } else
4117 break;
4118 }
4119
4120 if (!kfifo_get(&delay_display_q, &vf)) {
4121 vf = p_last_vf;
4122 delay = false;
4123 }
4124
4125 while (vf) {
4126 int buffer_index;
4127
4128 buffer_index = vf->index & 0xff;
4129
4130 /* construct a clone of the frame from last frame */
fe96802b
NQ		 4131
4132#if 0
4133
b9164398
NQ		 4134 pr_info("src yaddr[0x%x] index[%d] width[%d] heigth[%d]\n",
4135 buffer_spec[buffer_index].y_addr,
4136 buffer_spec[buffer_index].y_canvas_index,
4137 buffer_spec[buffer_index].y_canvas_width,
4138 buffer_spec[buffer_index].y_canvas_height);
4139
4140 pr_info("src uaddr[0x%x] index[%d] width[%d] heigth[%d]\n",
4141 buffer_spec[buffer_index].u_addr,
4142 buffer_spec[buffer_index].u_canvas_index,
4143 buffer_spec[buffer_index].u_canvas_width,
4144 buffer_spec[buffer_index].u_canvas_height);
4145#endif
4146 if (EN_SWITCH_FENCE()) {
4147 y_index = buffer_spec[buffer_index].y_canvas_index;
4148 u_index = buffer_spec[buffer_index].u_canvas_index;
4149
4150 canvas_read(y_index, &csy);
4151 canvas_read(u_index, &csu);
4152
4153 canvas_config(fense_buffer_spec[i].y_canvas_index,
4154 fense_buffer_spec[i].phy_addr,
4155 mb_width_num << 4, mb_height_num << 4,
4156 CANVAS_ADDR_NOWRAP,
4157 CANVAS_BLKMODE_LINEAR);
4158 canvas_config(fense_buffer_spec[i].u_canvas_index,
4159 fense_buffer_spec[i].phy_addr +
4160 (mb_total_num << 8),
4161 mb_width_num << 4, mb_height_num << 3,
4162 CANVAS_ADDR_NOWRAP,
4163 CANVAS_BLKMODE_LINEAR);
4164
4165 y_desindex = fense_buffer_spec[i].y_canvas_index;
4166 u_desindex = fense_buffer_spec[i].u_canvas_index;
4167
4168 canvas_read(y_desindex, &cyd);
4169
4170 src_index = ((y_index & 0xff) |
4171 ((u_index << 8) & 0x0000ff00));
4172 des_index = ((y_desindex & 0xff) |
4173 ((u_desindex << 8) & 0x0000ff00));
4174
4175 ge2d_canvas_dup(&csy, &csu, &cyd,
4176 GE2D_FORMAT_M24_NV21,
4177 src_index,
4178 des_index);
4179 }
4180 vf->mem_handle = decoder_bmmu_box_get_mem_handle(
4181 mm_blk_handle,
4182 FENSE_BUFFER_IDX(i));
4183 fense_vf[i] = *vf;
4184 fense_vf[i].index = -1;
4185
4186 if (EN_SWITCH_FENCE())
4187 fense_vf[i].canvas0Addr =
4188 spec2canvas(&fense_buffer_spec[i]);
4189 else
4190 fense_vf[i].flag |= VFRAME_FLAG_SWITCHING_FENSE;
4191
4192 /* send clone to receiver */
4193 kfifo_put(&display_q,
4194 (const struct vframe_s *)&fense_vf[i]);
a093654a 4195 ATRACE_COUNTER(MODULE_NAME, fense_vf[i].pts);
b9164398
NQ		 4196 /* early recycle frames for last session */
4197 if (delay)
4198 vh264_vf_put(vf, NULL);
4199
4200 vf_notify_receiver(PROVIDER_NAME,
4201 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
4202
4203 i++;
4204
4205 if (!kfifo_get(&delay_display_q, &vf))
4206 break;
4207 }
4208
4209 block_display_q = false;
4210
4211 pr_info("Switching fense frame post\n");
4212}
4213
4214static int amvdec_h264_probe(struct platform_device *pdev)
4215{
4216 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
4217
4218 mutex_lock(&vh264_mutex);
4219
4220 if (pdata == NULL) {
4221 pr_info("\namvdec_h264 memory resource undefined.\n");
4222 mutex_unlock(&vh264_mutex);
4223 return -EFAULT;
4224 }
8458676f 4225 canvas_mode = pdata->canvas_mode;
fe96802b 4226 tvp_flag = vdec_secure(pdata) ? CODEC_MM_FLAGS_TVP : 0;
b9164398
NQ		 4227 if (pdata->sys_info)
4228 vh264_amstream_dec_info = *pdata->sys_info;
e0614bf7 4229 if (sei_data_buffer == NULL) {
b9164398
NQ		 4230 sei_data_buffer =
4231 dma_alloc_coherent(amports_get_dma_device(),
fe96802b 4232 USER_DATA_RUND_SIZE,
b9164398
NQ		 4233 &sei_data_buffer_phys, GFP_KERNEL);
4234 if (!sei_data_buffer) {
4235 pr_info("%s: Can not allocate sei_data_buffer\n",
4236 __func__);
4237 mutex_unlock(&vh264_mutex);
4238 return -ENOMEM;
4239 }
4240 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
e0614bf7
ZZ		 4241 * sei_data_buffer, sei_data_buffer_phys,
4242 * (u32)sei_data_buffer_remap);
4243 */
b9164398 4244 }
b9164398
NQ		 4245 pdata->dec_status = vh264_dec_status;
4246 pdata->set_trickmode = vh264_set_trickmode;
d481db31 4247 pdata->set_isreset = vh264_set_isreset;
9cc3c918
RZ		 4248
4249 pdata->user_data_read = vh264_user_data_read;
4250 pdata->reset_userdata_fifo = vh264_reset_userdata_fifo;
4251 pdata->wakeup_userdata_poll = vh264_wakeup_userdata_poll;
4252
d481db31 4253 is_reset = 0;
f8537a67 4254 clk_adj_frame_count = 0;
b9164398
NQ		 4255 if (vh264_init() < 0) {
4256 pr_info("\namvdec_h264 init failed.\n");
fe96802b
NQ		 4257 kfree(gvs);
4258 gvs = NULL;
9b670a2d 4259 pdata->dec_status = NULL;
b9164398
NQ		 4260 mutex_unlock(&vh264_mutex);
4261 return -ENODEV;
4262 }
9cc3c918
RZ		 4263 vdec_h264 = pdata;
4264 vh264_crate_userdata_manager(sei_data_buffer, USER_DATA_SIZE);
4265 vh264_reset_userdata_fifo(vdec_h264, 1);
4266
4267#ifdef DUMP_USER_DATA
4268 vh264_init_userdata_dump();
4269 vh264_reset_user_data_buf();
4270#endif
b9164398
NQ		 4271
4272 INIT_WORK(&error_wd_work, error_do_work);
4273 INIT_WORK(&stream_switching_work, stream_switching_do);
4274 INIT_WORK(&set_parameter_work, vh264_set_params);
fe96802b 4275 INIT_WORK(&notify_work, vh264_notify_work);
a994f6d6 4276 INIT_WORK(&set_clk_work, vh264_set_clk);
fe96802b 4277 INIT_WORK(&userdata_push_work, userdata_push_do_work);
a8f62ee0
RZ		 4278 INIT_WORK(&qos_work, qos_do_work);
4279
4280
fe96802b 4281
b9164398
NQ		 4282 atomic_set(&vh264_active, 1);
4283
4284 mutex_unlock(&vh264_mutex);
4285
4286 return 0;
4287}
4288
4289static int amvdec_h264_remove(struct platform_device *pdev)
4290{
4291 atomic_set(&vh264_active, 0);
4292 cancel_work_sync(&set_parameter_work);
4293 cancel_work_sync(&error_wd_work);
4294 cancel_work_sync(&stream_switching_work);
fe96802b 4295 cancel_work_sync(&notify_work);
a994f6d6 4296 cancel_work_sync(&set_clk_work);
fe96802b 4297 cancel_work_sync(&userdata_push_work);
a8f62ee0
RZ		 4298 cancel_work_sync(&qos_work);
4299
4300 mutex_lock(&vh264_mutex);
b9164398 4301 vh264_stop(MODE_FULL);
27f94fbd
HZ		 4302 wait_vh264_search_done();
4303 mutex_lock(&vh264_mutex);
b9164398 4304 vdec_source_changed(VFORMAT_H264, 0, 0, 0);
9cc3c918
RZ		 4305#ifdef DUMP_USER_DATA
4306 vh264_dump_userdata();
4307#endif
4308 vh264_destroy_userdata_manager();
b9164398
NQ		 4309 atomic_set(&vh264_active, 0);
4310#ifdef DEBUG_PTS
4311 pr_info
4312 ("pts missed %ld, pts hit %ld, pts_outside %d, duration %d, ",
4313 pts_missed, pts_hit, pts_outside, frame_dur);
4314 pr_info("sync_outside %d, use_idr_framerate %d\n",
4315 sync_outside, use_idr_framerate);
4316#endif
fe96802b
NQ		 4317 kfree(gvs);
4318 gvs = NULL;
b9164398
NQ		 4319 mutex_unlock(&vh264_mutex);
4320 return 0;
4321}
4322
4323/****************************************/
4324
4325static struct platform_driver amvdec_h264_driver = {
4326 .probe = amvdec_h264_probe,
4327 .remove = amvdec_h264_remove,
4328#ifdef CONFIG_PM
4329 .suspend = amvdec_suspend,
4330 .resume = amvdec_resume,
4331#endif
4332 .driver = {
4333 .name = DRIVER_NAME,
4334 }
4335};
4336
4337static struct codec_profile_t amvdec_h264_profile = {
4338 .name = "h264",
4339 .profile = ""
4340};
4341
fe96802b
NQ		 4342
4343static struct mconfig h264_configs[] = {
4344 MC_PU32("stat", &stat),
4345 MC_PU32("error_recovery_mode", &error_recovery_mode),
4346 MC_PU32("sync_outside", &sync_outside),
4347 MC_PU32("dec_control", &dec_control),
4348 MC_PU32("fatal_error_reset", &fatal_error_reset),
4349 MC_PU32("max_refer_buf", &max_refer_buf),
4350 MC_PU32("ucode_type", &ucode_type),
4351 MC_PU32("debugfirmware", &debugfirmware),
4352 MC_PU32("fixed_frame_rate_flag", &fixed_frame_rate_flag),
4353 MC_PU32("decoder_debug_flag", &decoder_debug_flag),
4354 MC_PU32("dpb_size_adj", &dpb_size_adj),
4355 MC_PU32("decoder_force_reset", &decoder_force_reset),
4356 MC_PU32("no_idr_error_max", &no_idr_error_max),
4357 MC_PU32("enable_switch_fense", &enable_switch_fense),
4358};
4359static struct mconfig_node h264_node;
4360
4361
b9164398
NQ		 4362static int __init amvdec_h264_driver_init_module(void)
4363{
4364 pr_debug("amvdec_h264 module init\n");
4365
4366 ge2d_videoh264task_init();
4367
4368 if (platform_driver_register(&amvdec_h264_driver)) {
4369 pr_err("failed to register amvdec_h264 driver\n");
4370 return -ENODEV;
4371 }
63e810c0 4372 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB
b9164398
NQ		 4373 && (codec_mm_get_total_size() > 80 * SZ_1M)) {
4374 amvdec_h264_profile.profile = "4k";
b9164398 4375 }
b9164398 4376 vcodec_profile_register(&amvdec_h264_profile);
fe96802b
NQ		 4377 INIT_REG_NODE_CONFIGS("media.decoder", &h264_node,
4378 "h264", h264_configs, CONFIG_FOR_RW);
b9164398
NQ		 4379 return 0;
4380}
4381
4382static void __exit amvdec_h264_driver_remove_module(void)
4383{
4384 pr_debug("amvdec_h264 module remove.\n");
4385
4386 platform_driver_unregister(&amvdec_h264_driver);
4387
4388 ge2d_videoh264task_release();
4389}
4390
4391/****************************************/
4392
4393module_param(stat, uint, 0664);
4394MODULE_PARM_DESC(stat, "\n amvdec_h264 stat\n");
4395module_param(error_recovery_mode, uint, 0664);
4396MODULE_PARM_DESC(error_recovery_mode, "\n amvdec_h264 error_recovery_mode\n");
4397module_param(sync_outside, uint, 0664);
4398MODULE_PARM_DESC(sync_outside, "\n amvdec_h264 sync_outside\n");
4399module_param(dec_control, uint, 0664);
4400MODULE_PARM_DESC(dec_control, "\n amvdec_h264 decoder control\n");
a8f62ee0
RZ		 4401module_param(frame_count, uint, 0664);
4402MODULE_PARM_DESC(frame_count,
4403 "\n amvdec_h264 decoded total count\n");
b9164398
NQ		 4404module_param(fatal_error_reset, uint, 0664);
4405MODULE_PARM_DESC(fatal_error_reset,
4406 "\n amvdec_h264 decoder reset when fatal error happens\n");
4407module_param(max_refer_buf, uint, 0664);
4408MODULE_PARM_DESC(max_refer_buf,
4409 "\n amvdec_h264 dec buffering or not for reference frame\n");
4410module_param(ucode_type, uint, 0664);
4411MODULE_PARM_DESC(ucode_type,
4412 "\n amvdec_h264 dec buffering or not for reference frame\n");
4413module_param(debugfirmware, uint, 0664);
4414MODULE_PARM_DESC(debugfirmware, "\n amvdec_h264 debug load firmware\n");
4415module_param(fixed_frame_rate_flag, uint, 0664);
4416MODULE_PARM_DESC(fixed_frame_rate_flag,
4417 "\n amvdec_h264 fixed_frame_rate_flag\n");
4418module_param(decoder_debug_flag, uint, 0664);
4419MODULE_PARM_DESC(decoder_debug_flag,
4420 "\n amvdec_h264 decoder_debug_flag\n");
4421
4422module_param(dpb_size_adj, uint, 0664);
4423MODULE_PARM_DESC(dpb_size_adj,
4424 "\n amvdec_h264 dpb_size_adj\n");
4425
4426
4427module_param(decoder_force_reset, uint, 0664);
4428MODULE_PARM_DESC(decoder_force_reset,
4429 "\n amvdec_h264 decoder force reset\n");
4430module_param(no_idr_error_max, uint, 0664);
4431MODULE_PARM_DESC(no_idr_error_max,
4432 "\n print no_idr_error_max\n");
4433module_param(enable_switch_fense, uint, 0664);
4434MODULE_PARM_DESC(enable_switch_fense,
4435 "\n enable switch fense\n");
4436
d481db31
NQ		 4437#ifdef SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY
4438module_param(bad_block_scale, uint, 0664);
4439MODULE_PARM_DESC(bad_block_scale,
4440 "\n print bad_block_scale\n");
4441#endif
b9164398 4442
9cc3c918
RZ		 4443module_param(enable_userdata_debug, uint, 0664);
4444MODULE_PARM_DESC(enable_userdata_debug,
4445 "\n enable_userdata_debug\n");
4446
4447
b9164398
NQ		 4448module_init(amvdec_h264_driver_init_module);
4449module_exit(amvdec_h264_driver_remove_module);
4450
4451MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
4452MODULE_LICENSE("GPL");
4453MODULE_AUTHOR("Chen Zhang <chen.zhang@amlogic.com>");