Commit | Line | Data |
---|---|---|
c781c06d KH |
1 | /* |
2 | * Driver for OHCI 1394 controllers | |
ed568912 | 3 | * |
ed568912 KH |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
e524f616 | 21 | #include <linux/compiler.h> |
ed568912 | 22 | #include <linux/delay.h> |
cf3e72fd | 23 | #include <linux/dma-mapping.h> |
c26f0234 | 24 | #include <linux/gfp.h> |
a7fb60db SR |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/kernel.h> | |
faa2fb4e | 28 | #include <linux/mm.h> |
a7fb60db | 29 | #include <linux/module.h> |
ad3c0fe8 | 30 | #include <linux/moduleparam.h> |
a7fb60db | 31 | #include <linux/pci.h> |
c26f0234 | 32 | #include <linux/spinlock.h> |
cf3e72fd | 33 | |
c26f0234 | 34 | #include <asm/page.h> |
ee71c2f9 | 35 | #include <asm/system.h> |
ed568912 | 36 | |
ea8d006b SR |
37 | #ifdef CONFIG_PPC_PMAC |
38 | #include <asm/pmac_feature.h> | |
39 | #endif | |
40 | ||
ed568912 | 41 | #include "fw-ohci.h" |
a7fb60db | 42 | #include "fw-transaction.h" |
ed568912 | 43 | |
a77754a7 KH |
44 | #define DESCRIPTOR_OUTPUT_MORE 0 |
45 | #define DESCRIPTOR_OUTPUT_LAST (1 << 12) | |
46 | #define DESCRIPTOR_INPUT_MORE (2 << 12) | |
47 | #define DESCRIPTOR_INPUT_LAST (3 << 12) | |
48 | #define DESCRIPTOR_STATUS (1 << 11) | |
49 | #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) | |
50 | #define DESCRIPTOR_PING (1 << 7) | |
51 | #define DESCRIPTOR_YY (1 << 6) | |
52 | #define DESCRIPTOR_NO_IRQ (0 << 4) | |
53 | #define DESCRIPTOR_IRQ_ERROR (1 << 4) | |
54 | #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) | |
55 | #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) | |
56 | #define DESCRIPTOR_WAIT (3 << 0) | |
ed568912 KH |
57 | |
58 | struct descriptor { | |
59 | __le16 req_count; | |
60 | __le16 control; | |
61 | __le32 data_address; | |
62 | __le32 branch_address; | |
63 | __le16 res_count; | |
64 | __le16 transfer_status; | |
65 | } __attribute__((aligned(16))); | |
66 | ||
295e3feb KH |
67 | struct db_descriptor { |
68 | __le16 first_size; | |
69 | __le16 control; | |
70 | __le16 second_req_count; | |
71 | __le16 first_req_count; | |
72 | __le32 branch_address; | |
73 | __le16 second_res_count; | |
74 | __le16 first_res_count; | |
75 | __le32 reserved0; | |
76 | __le32 first_buffer; | |
77 | __le32 second_buffer; | |
78 | __le32 reserved1; | |
79 | } __attribute__((aligned(16))); | |
80 | ||
a77754a7 KH |
81 | #define CONTROL_SET(regs) (regs) |
82 | #define CONTROL_CLEAR(regs) ((regs) + 4) | |
83 | #define COMMAND_PTR(regs) ((regs) + 12) | |
84 | #define CONTEXT_MATCH(regs) ((regs) + 16) | |
72e318e0 | 85 | |
32b46093 | 86 | struct ar_buffer { |
ed568912 | 87 | struct descriptor descriptor; |
32b46093 KH |
88 | struct ar_buffer *next; |
89 | __le32 data[0]; | |
90 | }; | |
ed568912 | 91 | |
32b46093 KH |
92 | struct ar_context { |
93 | struct fw_ohci *ohci; | |
94 | struct ar_buffer *current_buffer; | |
95 | struct ar_buffer *last_buffer; | |
96 | void *pointer; | |
72e318e0 | 97 | u32 regs; |
ed568912 KH |
98 | struct tasklet_struct tasklet; |
99 | }; | |
100 | ||
30200739 KH |
101 | struct context; |
102 | ||
103 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
104 | struct descriptor *d, | |
105 | struct descriptor *last); | |
fe5ca634 DM |
106 | |
107 | /* | |
108 | * A buffer that contains a block of DMA-able coherent memory used for | |
109 | * storing a portion of a DMA descriptor program. | |
110 | */ | |
111 | struct descriptor_buffer { | |
112 | struct list_head list; | |
113 | dma_addr_t buffer_bus; | |
114 | size_t buffer_size; | |
115 | size_t used; | |
116 | struct descriptor buffer[0]; | |
117 | }; | |
118 | ||
30200739 | 119 | struct context { |
373b2edd | 120 | struct fw_ohci *ohci; |
30200739 | 121 | u32 regs; |
fe5ca634 | 122 | int total_allocation; |
373b2edd | 123 | |
fe5ca634 DM |
124 | /* |
125 | * List of page-sized buffers for storing DMA descriptors. | |
126 | * Head of list contains buffers in use and tail of list contains | |
127 | * free buffers. | |
128 | */ | |
129 | struct list_head buffer_list; | |
130 | ||
131 | /* | |
132 | * Pointer to a buffer inside buffer_list that contains the tail | |
133 | * end of the current DMA program. | |
134 | */ | |
135 | struct descriptor_buffer *buffer_tail; | |
136 | ||
137 | /* | |
138 | * The descriptor containing the branch address of the first | |
139 | * descriptor that has not yet been filled by the device. | |
140 | */ | |
141 | struct descriptor *last; | |
142 | ||
143 | /* | |
144 | * The last descriptor in the DMA program. It contains the branch | |
145 | * address that must be updated upon appending a new descriptor. | |
146 | */ | |
147 | struct descriptor *prev; | |
30200739 KH |
148 | |
149 | descriptor_callback_t callback; | |
150 | ||
373b2edd | 151 | struct tasklet_struct tasklet; |
30200739 | 152 | }; |
30200739 | 153 | |
a77754a7 KH |
154 | #define IT_HEADER_SY(v) ((v) << 0) |
155 | #define IT_HEADER_TCODE(v) ((v) << 4) | |
156 | #define IT_HEADER_CHANNEL(v) ((v) << 8) | |
157 | #define IT_HEADER_TAG(v) ((v) << 14) | |
158 | #define IT_HEADER_SPEED(v) ((v) << 16) | |
159 | #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) | |
ed568912 KH |
160 | |
161 | struct iso_context { | |
162 | struct fw_iso_context base; | |
30200739 | 163 | struct context context; |
0642b657 | 164 | int excess_bytes; |
9b32d5f3 KH |
165 | void *header; |
166 | size_t header_length; | |
ed568912 KH |
167 | }; |
168 | ||
169 | #define CONFIG_ROM_SIZE 1024 | |
170 | ||
171 | struct fw_ohci { | |
172 | struct fw_card card; | |
173 | ||
e364cf4e | 174 | u32 version; |
ed568912 KH |
175 | __iomem char *registers; |
176 | dma_addr_t self_id_bus; | |
177 | __le32 *self_id_cpu; | |
178 | struct tasklet_struct bus_reset_tasklet; | |
e636fe25 | 179 | int node_id; |
ed568912 KH |
180 | int generation; |
181 | int request_generation; | |
d60d7f1d | 182 | u32 bus_seconds; |
11bf20ad | 183 | bool old_uninorth; |
ed568912 | 184 | |
c781c06d KH |
185 | /* |
186 | * Spinlock for accessing fw_ohci data. Never call out of | |
187 | * this driver with this lock held. | |
188 | */ | |
ed568912 KH |
189 | spinlock_t lock; |
190 | u32 self_id_buffer[512]; | |
191 | ||
192 | /* Config rom buffers */ | |
193 | __be32 *config_rom; | |
194 | dma_addr_t config_rom_bus; | |
195 | __be32 *next_config_rom; | |
196 | dma_addr_t next_config_rom_bus; | |
197 | u32 next_header; | |
198 | ||
199 | struct ar_context ar_request_ctx; | |
200 | struct ar_context ar_response_ctx; | |
f319b6a0 KH |
201 | struct context at_request_ctx; |
202 | struct context at_response_ctx; | |
ed568912 KH |
203 | |
204 | u32 it_context_mask; | |
205 | struct iso_context *it_context_list; | |
206 | u32 ir_context_mask; | |
207 | struct iso_context *ir_context_list; | |
208 | }; | |
209 | ||
95688e97 | 210 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
211 | { |
212 | return container_of(card, struct fw_ohci, card); | |
213 | } | |
214 | ||
295e3feb KH |
215 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
216 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
217 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
218 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
219 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
220 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
221 | |
222 | #define CONTEXT_RUN 0x8000 | |
223 | #define CONTEXT_WAKE 0x1000 | |
224 | #define CONTEXT_DEAD 0x0800 | |
225 | #define CONTEXT_ACTIVE 0x0400 | |
226 | ||
227 | #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 | |
228 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
229 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
230 | ||
231 | #define FW_OHCI_MAJOR 240 | |
232 | #define OHCI1394_REGISTER_SIZE 0x800 | |
233 | #define OHCI_LOOP_COUNT 500 | |
234 | #define OHCI1394_PCI_HCI_Control 0x40 | |
235 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 236 | #define OHCI_TCODE_PHY_PACKET 0x0e |
e364cf4e | 237 | #define OHCI_VERSION_1_1 0x010010 |
0edeefd9 | 238 | |
ed568912 KH |
239 | static char ohci_driver_name[] = KBUILD_MODNAME; |
240 | ||
ad3c0fe8 SR |
241 | #ifdef CONFIG_FIREWIRE_OHCI_DEBUG |
242 | ||
243 | #define OHCI_PARAM_DEBUG_IRQS 1 | |
244 | #define OHCI_PARAM_DEBUG_SELFIDS 2 | |
245 | #define OHCI_PARAM_DEBUG_AT_AR 4 | |
246 | ||
247 | static int param_debug; | |
248 | module_param_named(debug, param_debug, int, 0644); | |
249 | MODULE_PARM_DESC(debug, "Verbose logging (default = 0" | |
250 | ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) | |
251 | ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) | |
252 | ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) | |
253 | ", or a combination, or all = -1)"); | |
254 | ||
255 | static void log_irqs(u32 evt) | |
256 | { | |
257 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_IRQS))) | |
258 | return; | |
259 | ||
75f7832e | 260 | printk(KERN_DEBUG KBUILD_MODNAME ": IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s\n", |
ad3c0fe8 SR |
261 | evt, |
262 | evt & OHCI1394_selfIDComplete ? " selfID" : "", | |
263 | evt & OHCI1394_RQPkt ? " AR_req" : "", | |
264 | evt & OHCI1394_RSPkt ? " AR_resp" : "", | |
265 | evt & OHCI1394_reqTxComplete ? " AT_req" : "", | |
266 | evt & OHCI1394_respTxComplete ? " AT_resp" : "", | |
267 | evt & OHCI1394_isochRx ? " IR" : "", | |
268 | evt & OHCI1394_isochTx ? " IT" : "", | |
269 | evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", | |
270 | evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", | |
271 | evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", | |
75f7832e | 272 | evt & OHCI1394_regAccessFail ? " regAccessFail" : "", |
ad3c0fe8 SR |
273 | evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | |
274 | OHCI1394_RSPkt | OHCI1394_reqTxComplete | | |
275 | OHCI1394_respTxComplete | OHCI1394_isochRx | | |
276 | OHCI1394_isochTx | OHCI1394_postedWriteErr | | |
75f7832e JW |
277 | OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | |
278 | OHCI1394_regAccessFail) | |
ad3c0fe8 SR |
279 | ? " ?" : ""); |
280 | } | |
281 | ||
282 | static const char *speed[] = { | |
283 | [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", | |
284 | }; | |
285 | static const char *power[] = { | |
286 | [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", | |
287 | [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", | |
288 | }; | |
289 | static const char port[] = { '.', '-', 'p', 'c', }; | |
290 | ||
291 | static char _p(u32 *s, int shift) | |
292 | { | |
293 | return port[*s >> shift & 3]; | |
294 | } | |
295 | ||
296 | static void log_selfids(int generation, int self_id_count, u32 *s) | |
297 | { | |
298 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) | |
299 | return; | |
300 | ||
301 | printk(KERN_DEBUG KBUILD_MODNAME ": %d selfIDs, generation %d\n", | |
302 | self_id_count, generation); | |
303 | ||
304 | for (; self_id_count--; ++s) | |
305 | if ((*s & 1 << 23) == 0) | |
306 | printk(KERN_DEBUG "selfID 0: %08x, phy %d [%c%c%c] " | |
307 | "%s gc=%d %s %s%s%s\n", | |
308 | *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), | |
309 | speed[*s >> 14 & 3], *s >> 16 & 63, | |
310 | power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", | |
311 | *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); | |
312 | else | |
313 | printk(KERN_DEBUG "selfID n: %08x, phy %d " | |
314 | "[%c%c%c%c%c%c%c%c]\n", | |
315 | *s, *s >> 24 & 63, | |
316 | _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), | |
317 | _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); | |
318 | } | |
319 | ||
320 | static const char *evts[] = { | |
321 | [0x00] = "evt_no_status", [0x01] = "-reserved-", | |
322 | [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", | |
323 | [0x04] = "evt_underrun", [0x05] = "evt_overrun", | |
324 | [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", | |
325 | [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", | |
326 | [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", | |
327 | [0x0c] = "-reserved-", [0x0d] = "-reserved-", | |
328 | [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", | |
329 | [0x10] = "-reserved-", [0x11] = "ack_complete", | |
330 | [0x12] = "ack_pending ", [0x13] = "-reserved-", | |
331 | [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", | |
332 | [0x16] = "ack_busy_B", [0x17] = "-reserved-", | |
333 | [0x18] = "-reserved-", [0x19] = "-reserved-", | |
334 | [0x1a] = "-reserved-", [0x1b] = "ack_tardy", | |
335 | [0x1c] = "-reserved-", [0x1d] = "ack_data_error", | |
336 | [0x1e] = "ack_type_error", [0x1f] = "-reserved-", | |
337 | [0x20] = "pending/cancelled", | |
338 | }; | |
339 | static const char *tcodes[] = { | |
340 | [0x0] = "QW req", [0x1] = "BW req", | |
341 | [0x2] = "W resp", [0x3] = "-reserved-", | |
342 | [0x4] = "QR req", [0x5] = "BR req", | |
343 | [0x6] = "QR resp", [0x7] = "BR resp", | |
344 | [0x8] = "cycle start", [0x9] = "Lk req", | |
345 | [0xa] = "async stream packet", [0xb] = "Lk resp", | |
346 | [0xc] = "-reserved-", [0xd] = "-reserved-", | |
347 | [0xe] = "link internal", [0xf] = "-reserved-", | |
348 | }; | |
349 | static const char *phys[] = { | |
350 | [0x0] = "phy config packet", [0x1] = "link-on packet", | |
351 | [0x2] = "self-id packet", [0x3] = "-reserved-", | |
352 | }; | |
353 | ||
354 | static void log_ar_at_event(char dir, int speed, u32 *header, int evt) | |
355 | { | |
356 | int tcode = header[0] >> 4 & 0xf; | |
357 | char specific[12]; | |
358 | ||
359 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) | |
360 | return; | |
361 | ||
362 | if (unlikely(evt >= ARRAY_SIZE(evts))) | |
363 | evt = 0x1f; | |
364 | ||
365 | if (header[0] == ~header[1]) { | |
366 | printk(KERN_DEBUG "A%c %s, %s, %08x\n", | |
367 | dir, evts[evt], phys[header[0] >> 30 & 0x3], | |
368 | header[0]); | |
369 | return; | |
370 | } | |
371 | ||
372 | switch (tcode) { | |
373 | case 0x0: case 0x6: case 0x8: | |
374 | snprintf(specific, sizeof(specific), " = %08x", | |
375 | be32_to_cpu((__force __be32)header[3])); | |
376 | break; | |
377 | case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: | |
378 | snprintf(specific, sizeof(specific), " %x,%x", | |
379 | header[3] >> 16, header[3] & 0xffff); | |
380 | break; | |
381 | default: | |
382 | specific[0] = '\0'; | |
383 | } | |
384 | ||
385 | switch (tcode) { | |
386 | case 0xe: case 0xa: | |
387 | printk(KERN_DEBUG "A%c %s, %s\n", | |
388 | dir, evts[evt], tcodes[tcode]); | |
389 | break; | |
390 | case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: | |
391 | printk(KERN_DEBUG "A%c spd %x tl %02x, " | |
392 | "%04x -> %04x, %s, " | |
393 | "%s, %04x%08x%s\n", | |
394 | dir, speed, header[0] >> 10 & 0x3f, | |
395 | header[1] >> 16, header[0] >> 16, evts[evt], | |
396 | tcodes[tcode], header[1] & 0xffff, header[2], specific); | |
397 | break; | |
398 | default: | |
399 | printk(KERN_DEBUG "A%c spd %x tl %02x, " | |
400 | "%04x -> %04x, %s, " | |
401 | "%s%s\n", | |
402 | dir, speed, header[0] >> 10 & 0x3f, | |
403 | header[1] >> 16, header[0] >> 16, evts[evt], | |
404 | tcodes[tcode], specific); | |
405 | } | |
406 | } | |
407 | ||
408 | #else | |
409 | ||
410 | #define log_irqs(evt) | |
411 | #define log_selfids(generation, self_id_count, sid) | |
412 | #define log_ar_at_event(dir, speed, header, evt) | |
413 | ||
414 | #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ | |
415 | ||
95688e97 | 416 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
417 | { |
418 | writel(data, ohci->registers + offset); | |
419 | } | |
420 | ||
95688e97 | 421 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
422 | { |
423 | return readl(ohci->registers + offset); | |
424 | } | |
425 | ||
95688e97 | 426 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
427 | { |
428 | /* Do a dummy read to flush writes. */ | |
429 | reg_read(ohci, OHCI1394_Version); | |
430 | } | |
431 | ||
432 | static int | |
433 | ohci_update_phy_reg(struct fw_card *card, int addr, | |
434 | int clear_bits, int set_bits) | |
435 | { | |
436 | struct fw_ohci *ohci = fw_ohci(card); | |
437 | u32 val, old; | |
438 | ||
439 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
362e901c | 440 | flush_writes(ohci); |
ed568912 KH |
441 | msleep(2); |
442 | val = reg_read(ohci, OHCI1394_PhyControl); | |
443 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
444 | fw_error("failed to set phy reg bits.\n"); | |
445 | return -EBUSY; | |
446 | } | |
447 | ||
448 | old = OHCI1394_PhyControl_ReadData(val); | |
449 | old = (old & ~clear_bits) | set_bits; | |
450 | reg_write(ohci, OHCI1394_PhyControl, | |
451 | OHCI1394_PhyControl_Write(addr, old)); | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
32b46093 | 456 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 457 | { |
32b46093 KH |
458 | struct device *dev = ctx->ohci->card.device; |
459 | struct ar_buffer *ab; | |
f5101d58 | 460 | dma_addr_t uninitialized_var(ab_bus); |
32b46093 KH |
461 | size_t offset; |
462 | ||
bde1709a | 463 | ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC); |
32b46093 KH |
464 | if (ab == NULL) |
465 | return -ENOMEM; | |
466 | ||
2d826cc5 | 467 | memset(&ab->descriptor, 0, sizeof(ab->descriptor)); |
a77754a7 KH |
468 | ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | |
469 | DESCRIPTOR_STATUS | | |
470 | DESCRIPTOR_BRANCH_ALWAYS); | |
32b46093 KH |
471 | offset = offsetof(struct ar_buffer, data); |
472 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
473 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
474 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
475 | ab->descriptor.branch_address = 0; | |
476 | ||
ec839e43 | 477 | ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1); |
32b46093 KH |
478 | ctx->last_buffer->next = ab; |
479 | ctx->last_buffer = ab; | |
480 | ||
a77754a7 | 481 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
ed568912 | 482 | flush_writes(ctx->ohci); |
32b46093 KH |
483 | |
484 | return 0; | |
ed568912 KH |
485 | } |
486 | ||
11bf20ad SR |
487 | #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) |
488 | #define cond_le32_to_cpu(v) \ | |
489 | (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v)) | |
490 | #else | |
491 | #define cond_le32_to_cpu(v) le32_to_cpu(v) | |
492 | #endif | |
493 | ||
32b46093 | 494 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 495 | { |
ed568912 | 496 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
497 | struct fw_packet p; |
498 | u32 status, length, tcode; | |
43286568 | 499 | int evt; |
2639a6fb | 500 | |
11bf20ad SR |
501 | p.header[0] = cond_le32_to_cpu(buffer[0]); |
502 | p.header[1] = cond_le32_to_cpu(buffer[1]); | |
503 | p.header[2] = cond_le32_to_cpu(buffer[2]); | |
2639a6fb KH |
504 | |
505 | tcode = (p.header[0] >> 4) & 0x0f; | |
506 | switch (tcode) { | |
507 | case TCODE_WRITE_QUADLET_REQUEST: | |
508 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 509 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 510 | p.header_length = 16; |
32b46093 | 511 | p.payload_length = 0; |
2639a6fb KH |
512 | break; |
513 | ||
2639a6fb | 514 | case TCODE_READ_BLOCK_REQUEST : |
11bf20ad | 515 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
32b46093 KH |
516 | p.header_length = 16; |
517 | p.payload_length = 0; | |
518 | break; | |
519 | ||
520 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
521 | case TCODE_READ_BLOCK_RESPONSE: |
522 | case TCODE_LOCK_REQUEST: | |
523 | case TCODE_LOCK_RESPONSE: | |
11bf20ad | 524 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
2639a6fb | 525 | p.header_length = 16; |
32b46093 | 526 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
527 | break; |
528 | ||
529 | case TCODE_WRITE_RESPONSE: | |
530 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 531 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 532 | p.header_length = 12; |
32b46093 | 533 | p.payload_length = 0; |
2639a6fb KH |
534 | break; |
535 | } | |
ed568912 | 536 | |
32b46093 KH |
537 | p.payload = (void *) buffer + p.header_length; |
538 | ||
539 | /* FIXME: What to do about evt_* errors? */ | |
540 | length = (p.header_length + p.payload_length + 3) / 4; | |
11bf20ad | 541 | status = cond_le32_to_cpu(buffer[length]); |
43286568 | 542 | evt = (status >> 16) & 0x1f; |
32b46093 | 543 | |
43286568 | 544 | p.ack = evt - 16; |
32b46093 KH |
545 | p.speed = (status >> 21) & 0x7; |
546 | p.timestamp = status & 0xffff; | |
547 | p.generation = ohci->request_generation; | |
ed568912 | 548 | |
43286568 | 549 | log_ar_at_event('R', p.speed, p.header, evt); |
ad3c0fe8 | 550 | |
c781c06d KH |
551 | /* |
552 | * The OHCI bus reset handler synthesizes a phy packet with | |
ed568912 KH |
553 | * the new generation number when a bus reset happens (see |
554 | * section 8.4.2.3). This helps us determine when a request | |
555 | * was received and make sure we send the response in the same | |
556 | * generation. We only need this for requests; for responses | |
557 | * we use the unique tlabel for finding the matching | |
c781c06d KH |
558 | * request. |
559 | */ | |
ed568912 | 560 | |
43286568 | 561 | if (evt == OHCI1394_evt_bus_reset) |
25df287d | 562 | ohci->request_generation = (p.header[2] >> 16) & 0xff; |
ed568912 | 563 | else if (ctx == &ohci->ar_request_ctx) |
2639a6fb | 564 | fw_core_handle_request(&ohci->card, &p); |
ed568912 | 565 | else |
2639a6fb | 566 | fw_core_handle_response(&ohci->card, &p); |
ed568912 | 567 | |
32b46093 KH |
568 | return buffer + length + 1; |
569 | } | |
ed568912 | 570 | |
32b46093 KH |
571 | static void ar_context_tasklet(unsigned long data) |
572 | { | |
573 | struct ar_context *ctx = (struct ar_context *)data; | |
574 | struct fw_ohci *ohci = ctx->ohci; | |
575 | struct ar_buffer *ab; | |
576 | struct descriptor *d; | |
577 | void *buffer, *end; | |
578 | ||
579 | ab = ctx->current_buffer; | |
580 | d = &ab->descriptor; | |
581 | ||
582 | if (d->res_count == 0) { | |
583 | size_t size, rest, offset; | |
6b84236d JW |
584 | dma_addr_t start_bus; |
585 | void *start; | |
32b46093 | 586 | |
c781c06d KH |
587 | /* |
588 | * This descriptor is finished and we may have a | |
32b46093 | 589 | * packet split across this and the next buffer. We |
c781c06d KH |
590 | * reuse the page for reassembling the split packet. |
591 | */ | |
32b46093 KH |
592 | |
593 | offset = offsetof(struct ar_buffer, data); | |
6b84236d JW |
594 | start = buffer = ab; |
595 | start_bus = le32_to_cpu(ab->descriptor.data_address) - offset; | |
32b46093 | 596 | |
32b46093 KH |
597 | ab = ab->next; |
598 | d = &ab->descriptor; | |
599 | size = buffer + PAGE_SIZE - ctx->pointer; | |
600 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
601 | memmove(buffer, ctx->pointer, size); | |
602 | memcpy(buffer + size, ab->data, rest); | |
603 | ctx->current_buffer = ab; | |
604 | ctx->pointer = (void *) ab->data + rest; | |
605 | end = buffer + size + rest; | |
606 | ||
607 | while (buffer < end) | |
608 | buffer = handle_ar_packet(ctx, buffer); | |
609 | ||
bde1709a | 610 | dma_free_coherent(ohci->card.device, PAGE_SIZE, |
6b84236d | 611 | start, start_bus); |
32b46093 KH |
612 | ar_context_add_page(ctx); |
613 | } else { | |
614 | buffer = ctx->pointer; | |
615 | ctx->pointer = end = | |
616 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
617 | ||
618 | while (buffer < end) | |
619 | buffer = handle_ar_packet(ctx, buffer); | |
620 | } | |
ed568912 KH |
621 | } |
622 | ||
623 | static int | |
72e318e0 | 624 | ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs) |
ed568912 | 625 | { |
32b46093 | 626 | struct ar_buffer ab; |
ed568912 | 627 | |
72e318e0 KH |
628 | ctx->regs = regs; |
629 | ctx->ohci = ohci; | |
630 | ctx->last_buffer = &ab; | |
ed568912 KH |
631 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
632 | ||
32b46093 KH |
633 | ar_context_add_page(ctx); |
634 | ar_context_add_page(ctx); | |
635 | ctx->current_buffer = ab.next; | |
636 | ctx->pointer = ctx->current_buffer->data; | |
637 | ||
2aef469a KH |
638 | return 0; |
639 | } | |
640 | ||
641 | static void ar_context_run(struct ar_context *ctx) | |
642 | { | |
643 | struct ar_buffer *ab = ctx->current_buffer; | |
644 | dma_addr_t ab_bus; | |
645 | size_t offset; | |
646 | ||
647 | offset = offsetof(struct ar_buffer, data); | |
0a9972ba | 648 | ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; |
2aef469a KH |
649 | |
650 | reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1); | |
a77754a7 | 651 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); |
32b46093 | 652 | flush_writes(ctx->ohci); |
ed568912 | 653 | } |
373b2edd | 654 | |
a186b4a6 JW |
655 | static struct descriptor * |
656 | find_branch_descriptor(struct descriptor *d, int z) | |
657 | { | |
658 | int b, key; | |
659 | ||
660 | b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; | |
661 | key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; | |
662 | ||
663 | /* figure out which descriptor the branch address goes in */ | |
664 | if (z == 2 && (b == 3 || key == 2)) | |
665 | return d; | |
666 | else | |
667 | return d + z - 1; | |
668 | } | |
669 | ||
30200739 KH |
670 | static void context_tasklet(unsigned long data) |
671 | { | |
672 | struct context *ctx = (struct context *) data; | |
30200739 KH |
673 | struct descriptor *d, *last; |
674 | u32 address; | |
675 | int z; | |
fe5ca634 | 676 | struct descriptor_buffer *desc; |
30200739 | 677 | |
fe5ca634 DM |
678 | desc = list_entry(ctx->buffer_list.next, |
679 | struct descriptor_buffer, list); | |
680 | last = ctx->last; | |
30200739 | 681 | while (last->branch_address != 0) { |
fe5ca634 | 682 | struct descriptor_buffer *old_desc = desc; |
30200739 KH |
683 | address = le32_to_cpu(last->branch_address); |
684 | z = address & 0xf; | |
fe5ca634 DM |
685 | address &= ~0xf; |
686 | ||
687 | /* If the branch address points to a buffer outside of the | |
688 | * current buffer, advance to the next buffer. */ | |
689 | if (address < desc->buffer_bus || | |
690 | address >= desc->buffer_bus + desc->used) | |
691 | desc = list_entry(desc->list.next, | |
692 | struct descriptor_buffer, list); | |
693 | d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); | |
a186b4a6 | 694 | last = find_branch_descriptor(d, z); |
30200739 KH |
695 | |
696 | if (!ctx->callback(ctx, d, last)) | |
697 | break; | |
698 | ||
fe5ca634 DM |
699 | if (old_desc != desc) { |
700 | /* If we've advanced to the next buffer, move the | |
701 | * previous buffer to the free list. */ | |
702 | unsigned long flags; | |
703 | old_desc->used = 0; | |
704 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
705 | list_move_tail(&old_desc->list, &ctx->buffer_list); | |
706 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); | |
707 | } | |
708 | ctx->last = last; | |
30200739 KH |
709 | } |
710 | } | |
711 | ||
fe5ca634 DM |
712 | /* |
713 | * Allocate a new buffer and add it to the list of free buffers for this | |
714 | * context. Must be called with ohci->lock held. | |
715 | */ | |
716 | static int | |
717 | context_add_buffer(struct context *ctx) | |
718 | { | |
719 | struct descriptor_buffer *desc; | |
f5101d58 | 720 | dma_addr_t uninitialized_var(bus_addr); |
fe5ca634 DM |
721 | int offset; |
722 | ||
723 | /* | |
724 | * 16MB of descriptors should be far more than enough for any DMA | |
725 | * program. This will catch run-away userspace or DoS attacks. | |
726 | */ | |
727 | if (ctx->total_allocation >= 16*1024*1024) | |
728 | return -ENOMEM; | |
729 | ||
730 | desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, | |
731 | &bus_addr, GFP_ATOMIC); | |
732 | if (!desc) | |
733 | return -ENOMEM; | |
734 | ||
735 | offset = (void *)&desc->buffer - (void *)desc; | |
736 | desc->buffer_size = PAGE_SIZE - offset; | |
737 | desc->buffer_bus = bus_addr + offset; | |
738 | desc->used = 0; | |
739 | ||
740 | list_add_tail(&desc->list, &ctx->buffer_list); | |
741 | ctx->total_allocation += PAGE_SIZE; | |
742 | ||
743 | return 0; | |
744 | } | |
745 | ||
30200739 KH |
746 | static int |
747 | context_init(struct context *ctx, struct fw_ohci *ohci, | |
fe5ca634 | 748 | u32 regs, descriptor_callback_t callback) |
30200739 KH |
749 | { |
750 | ctx->ohci = ohci; | |
751 | ctx->regs = regs; | |
fe5ca634 DM |
752 | ctx->total_allocation = 0; |
753 | ||
754 | INIT_LIST_HEAD(&ctx->buffer_list); | |
755 | if (context_add_buffer(ctx) < 0) | |
30200739 KH |
756 | return -ENOMEM; |
757 | ||
fe5ca634 DM |
758 | ctx->buffer_tail = list_entry(ctx->buffer_list.next, |
759 | struct descriptor_buffer, list); | |
760 | ||
30200739 KH |
761 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); |
762 | ctx->callback = callback; | |
763 | ||
c781c06d KH |
764 | /* |
765 | * We put a dummy descriptor in the buffer that has a NULL | |
30200739 | 766 | * branch address and looks like it's been sent. That way we |
fe5ca634 | 767 | * have a descriptor to append DMA programs to. |
c781c06d | 768 | */ |
fe5ca634 DM |
769 | memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); |
770 | ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); | |
771 | ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); | |
772 | ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); | |
773 | ctx->last = ctx->buffer_tail->buffer; | |
774 | ctx->prev = ctx->buffer_tail->buffer; | |
30200739 KH |
775 | |
776 | return 0; | |
777 | } | |
778 | ||
9b32d5f3 | 779 | static void |
30200739 KH |
780 | context_release(struct context *ctx) |
781 | { | |
782 | struct fw_card *card = &ctx->ohci->card; | |
fe5ca634 | 783 | struct descriptor_buffer *desc, *tmp; |
30200739 | 784 | |
fe5ca634 DM |
785 | list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) |
786 | dma_free_coherent(card->device, PAGE_SIZE, desc, | |
787 | desc->buffer_bus - | |
788 | ((void *)&desc->buffer - (void *)desc)); | |
30200739 KH |
789 | } |
790 | ||
fe5ca634 | 791 | /* Must be called with ohci->lock held */ |
30200739 KH |
792 | static struct descriptor * |
793 | context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus) | |
794 | { | |
fe5ca634 DM |
795 | struct descriptor *d = NULL; |
796 | struct descriptor_buffer *desc = ctx->buffer_tail; | |
797 | ||
798 | if (z * sizeof(*d) > desc->buffer_size) | |
799 | return NULL; | |
800 | ||
801 | if (z * sizeof(*d) > desc->buffer_size - desc->used) { | |
802 | /* No room for the descriptor in this buffer, so advance to the | |
803 | * next one. */ | |
30200739 | 804 | |
fe5ca634 DM |
805 | if (desc->list.next == &ctx->buffer_list) { |
806 | /* If there is no free buffer next in the list, | |
807 | * allocate one. */ | |
808 | if (context_add_buffer(ctx) < 0) | |
809 | return NULL; | |
810 | } | |
811 | desc = list_entry(desc->list.next, | |
812 | struct descriptor_buffer, list); | |
813 | ctx->buffer_tail = desc; | |
814 | } | |
30200739 | 815 | |
fe5ca634 | 816 | d = desc->buffer + desc->used / sizeof(*d); |
2d826cc5 | 817 | memset(d, 0, z * sizeof(*d)); |
fe5ca634 | 818 | *d_bus = desc->buffer_bus + desc->used; |
30200739 KH |
819 | |
820 | return d; | |
821 | } | |
822 | ||
295e3feb | 823 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
824 | { |
825 | struct fw_ohci *ohci = ctx->ohci; | |
826 | ||
a77754a7 | 827 | reg_write(ohci, COMMAND_PTR(ctx->regs), |
fe5ca634 | 828 | le32_to_cpu(ctx->last->branch_address)); |
a77754a7 KH |
829 | reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); |
830 | reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); | |
30200739 KH |
831 | flush_writes(ohci); |
832 | } | |
833 | ||
834 | static void context_append(struct context *ctx, | |
835 | struct descriptor *d, int z, int extra) | |
836 | { | |
837 | dma_addr_t d_bus; | |
fe5ca634 | 838 | struct descriptor_buffer *desc = ctx->buffer_tail; |
30200739 | 839 | |
fe5ca634 | 840 | d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); |
30200739 | 841 | |
fe5ca634 DM |
842 | desc->used += (z + extra) * sizeof(*d); |
843 | ctx->prev->branch_address = cpu_to_le32(d_bus | z); | |
844 | ctx->prev = find_branch_descriptor(d, z); | |
30200739 | 845 | |
a77754a7 | 846 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
30200739 KH |
847 | flush_writes(ctx->ohci); |
848 | } | |
849 | ||
850 | static void context_stop(struct context *ctx) | |
851 | { | |
852 | u32 reg; | |
b8295668 | 853 | int i; |
30200739 | 854 | |
a77754a7 | 855 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); |
b8295668 | 856 | flush_writes(ctx->ohci); |
30200739 | 857 | |
b8295668 | 858 | for (i = 0; i < 10; i++) { |
a77754a7 | 859 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
b8295668 KH |
860 | if ((reg & CONTEXT_ACTIVE) == 0) |
861 | break; | |
862 | ||
863 | fw_notify("context_stop: still active (0x%08x)\n", reg); | |
b980f5a2 | 864 | mdelay(1); |
b8295668 | 865 | } |
30200739 | 866 | } |
ed568912 | 867 | |
f319b6a0 KH |
868 | struct driver_data { |
869 | struct fw_packet *packet; | |
870 | }; | |
ed568912 | 871 | |
c781c06d KH |
872 | /* |
873 | * This function apppends a packet to the DMA queue for transmission. | |
f319b6a0 | 874 | * Must always be called with the ochi->lock held to ensure proper |
c781c06d KH |
875 | * generation handling and locking around packet queue manipulation. |
876 | */ | |
f319b6a0 KH |
877 | static int |
878 | at_context_queue_packet(struct context *ctx, struct fw_packet *packet) | |
ed568912 | 879 | { |
ed568912 | 880 | struct fw_ohci *ohci = ctx->ohci; |
4b6d51ec | 881 | dma_addr_t d_bus, uninitialized_var(payload_bus); |
f319b6a0 KH |
882 | struct driver_data *driver_data; |
883 | struct descriptor *d, *last; | |
884 | __le32 *header; | |
ed568912 | 885 | int z, tcode; |
f319b6a0 | 886 | u32 reg; |
ed568912 | 887 | |
f319b6a0 KH |
888 | d = context_get_descriptors(ctx, 4, &d_bus); |
889 | if (d == NULL) { | |
890 | packet->ack = RCODE_SEND_ERROR; | |
891 | return -1; | |
ed568912 KH |
892 | } |
893 | ||
a77754a7 | 894 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
f319b6a0 KH |
895 | d[0].res_count = cpu_to_le16(packet->timestamp); |
896 | ||
c781c06d KH |
897 | /* |
898 | * The DMA format for asyncronous link packets is different | |
ed568912 KH |
899 | * from the IEEE1394 layout, so shift the fields around |
900 | * accordingly. If header_length is 8, it's a PHY packet, to | |
c781c06d KH |
901 | * which we need to prepend an extra quadlet. |
902 | */ | |
f319b6a0 KH |
903 | |
904 | header = (__le32 *) &d[1]; | |
ed568912 | 905 | if (packet->header_length > 8) { |
f319b6a0 KH |
906 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | |
907 | (packet->speed << 16)); | |
908 | header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
909 | (packet->header[0] & 0xffff0000)); | |
910 | header[2] = cpu_to_le32(packet->header[2]); | |
ed568912 KH |
911 | |
912 | tcode = (packet->header[0] >> 4) & 0x0f; | |
913 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
f319b6a0 | 914 | header[3] = cpu_to_le32(packet->header[3]); |
ed568912 | 915 | else |
f319b6a0 KH |
916 | header[3] = (__force __le32) packet->header[3]; |
917 | ||
918 | d[0].req_count = cpu_to_le16(packet->header_length); | |
ed568912 | 919 | } else { |
f319b6a0 KH |
920 | header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | |
921 | (packet->speed << 16)); | |
922 | header[1] = cpu_to_le32(packet->header[0]); | |
923 | header[2] = cpu_to_le32(packet->header[1]); | |
924 | d[0].req_count = cpu_to_le16(12); | |
ed568912 KH |
925 | } |
926 | ||
f319b6a0 KH |
927 | driver_data = (struct driver_data *) &d[3]; |
928 | driver_data->packet = packet; | |
20d11673 | 929 | packet->driver_data = driver_data; |
a186b4a6 | 930 | |
f319b6a0 KH |
931 | if (packet->payload_length > 0) { |
932 | payload_bus = | |
933 | dma_map_single(ohci->card.device, packet->payload, | |
934 | packet->payload_length, DMA_TO_DEVICE); | |
935 | if (dma_mapping_error(payload_bus)) { | |
936 | packet->ack = RCODE_SEND_ERROR; | |
937 | return -1; | |
938 | } | |
939 | ||
940 | d[2].req_count = cpu_to_le16(packet->payload_length); | |
941 | d[2].data_address = cpu_to_le32(payload_bus); | |
942 | last = &d[2]; | |
943 | z = 3; | |
ed568912 | 944 | } else { |
f319b6a0 KH |
945 | last = &d[0]; |
946 | z = 2; | |
ed568912 | 947 | } |
ed568912 | 948 | |
a77754a7 KH |
949 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
950 | DESCRIPTOR_IRQ_ALWAYS | | |
951 | DESCRIPTOR_BRANCH_ALWAYS); | |
ed568912 | 952 | |
76f73ca1 JW |
953 | /* |
954 | * If the controller and packet generations don't match, we need to | |
955 | * bail out and try again. If IntEvent.busReset is set, the AT context | |
956 | * is halted, so appending to the context and trying to run it is | |
957 | * futile. Most controllers do the right thing and just flush the AT | |
958 | * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but | |
959 | * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind | |
960 | * up stalling out. So we just bail out in software and try again | |
961 | * later, and everyone is happy. | |
962 | * FIXME: Document how the locking works. | |
963 | */ | |
964 | if (ohci->generation != packet->generation || | |
965 | reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) { | |
ab88ca48 SR |
966 | if (packet->payload_length > 0) |
967 | dma_unmap_single(ohci->card.device, payload_bus, | |
968 | packet->payload_length, DMA_TO_DEVICE); | |
f319b6a0 KH |
969 | packet->ack = RCODE_GENERATION; |
970 | return -1; | |
971 | } | |
972 | ||
973 | context_append(ctx, d, z, 4 - z); | |
ed568912 | 974 | |
f319b6a0 | 975 | /* If the context isn't already running, start it up. */ |
a77754a7 | 976 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
053b3080 | 977 | if ((reg & CONTEXT_RUN) == 0) |
f319b6a0 KH |
978 | context_run(ctx, 0); |
979 | ||
980 | return 0; | |
ed568912 KH |
981 | } |
982 | ||
f319b6a0 KH |
983 | static int handle_at_packet(struct context *context, |
984 | struct descriptor *d, | |
985 | struct descriptor *last) | |
ed568912 | 986 | { |
f319b6a0 | 987 | struct driver_data *driver_data; |
ed568912 | 988 | struct fw_packet *packet; |
f319b6a0 KH |
989 | struct fw_ohci *ohci = context->ohci; |
990 | dma_addr_t payload_bus; | |
ed568912 KH |
991 | int evt; |
992 | ||
f319b6a0 KH |
993 | if (last->transfer_status == 0) |
994 | /* This descriptor isn't done yet, stop iteration. */ | |
995 | return 0; | |
ed568912 | 996 | |
f319b6a0 KH |
997 | driver_data = (struct driver_data *) &d[3]; |
998 | packet = driver_data->packet; | |
999 | if (packet == NULL) | |
1000 | /* This packet was cancelled, just continue. */ | |
1001 | return 1; | |
730c32f5 | 1002 | |
f319b6a0 KH |
1003 | payload_bus = le32_to_cpu(last->data_address); |
1004 | if (payload_bus != 0) | |
1005 | dma_unmap_single(ohci->card.device, payload_bus, | |
ed568912 | 1006 | packet->payload_length, DMA_TO_DEVICE); |
ed568912 | 1007 | |
f319b6a0 KH |
1008 | evt = le16_to_cpu(last->transfer_status) & 0x1f; |
1009 | packet->timestamp = le16_to_cpu(last->res_count); | |
ed568912 | 1010 | |
ad3c0fe8 SR |
1011 | log_ar_at_event('T', packet->speed, packet->header, evt); |
1012 | ||
f319b6a0 KH |
1013 | switch (evt) { |
1014 | case OHCI1394_evt_timeout: | |
1015 | /* Async response transmit timed out. */ | |
1016 | packet->ack = RCODE_CANCELLED; | |
1017 | break; | |
ed568912 | 1018 | |
f319b6a0 | 1019 | case OHCI1394_evt_flushed: |
c781c06d KH |
1020 | /* |
1021 | * The packet was flushed should give same error as | |
1022 | * when we try to use a stale generation count. | |
1023 | */ | |
f319b6a0 KH |
1024 | packet->ack = RCODE_GENERATION; |
1025 | break; | |
ed568912 | 1026 | |
f319b6a0 | 1027 | case OHCI1394_evt_missing_ack: |
c781c06d KH |
1028 | /* |
1029 | * Using a valid (current) generation count, but the | |
1030 | * node is not on the bus or not sending acks. | |
1031 | */ | |
f319b6a0 KH |
1032 | packet->ack = RCODE_NO_ACK; |
1033 | break; | |
ed568912 | 1034 | |
f319b6a0 KH |
1035 | case ACK_COMPLETE + 0x10: |
1036 | case ACK_PENDING + 0x10: | |
1037 | case ACK_BUSY_X + 0x10: | |
1038 | case ACK_BUSY_A + 0x10: | |
1039 | case ACK_BUSY_B + 0x10: | |
1040 | case ACK_DATA_ERROR + 0x10: | |
1041 | case ACK_TYPE_ERROR + 0x10: | |
1042 | packet->ack = evt - 0x10; | |
1043 | break; | |
ed568912 | 1044 | |
f319b6a0 KH |
1045 | default: |
1046 | packet->ack = RCODE_SEND_ERROR; | |
1047 | break; | |
1048 | } | |
ed568912 | 1049 | |
f319b6a0 | 1050 | packet->callback(packet, &ohci->card, packet->ack); |
ed568912 | 1051 | |
f319b6a0 | 1052 | return 1; |
ed568912 KH |
1053 | } |
1054 | ||
a77754a7 KH |
1055 | #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) |
1056 | #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) | |
1057 | #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) | |
1058 | #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) | |
1059 | #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) | |
93c4cceb KH |
1060 | |
1061 | static void | |
1062 | handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
1063 | { | |
1064 | struct fw_packet response; | |
1065 | int tcode, length, i; | |
1066 | ||
a77754a7 | 1067 | tcode = HEADER_GET_TCODE(packet->header[0]); |
93c4cceb | 1068 | if (TCODE_IS_BLOCK_PACKET(tcode)) |
a77754a7 | 1069 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); |
93c4cceb KH |
1070 | else |
1071 | length = 4; | |
1072 | ||
1073 | i = csr - CSR_CONFIG_ROM; | |
1074 | if (i + length > CONFIG_ROM_SIZE) { | |
1075 | fw_fill_response(&response, packet->header, | |
1076 | RCODE_ADDRESS_ERROR, NULL, 0); | |
1077 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
1078 | fw_fill_response(&response, packet->header, | |
1079 | RCODE_TYPE_ERROR, NULL, 0); | |
1080 | } else { | |
1081 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
1082 | (void *) ohci->config_rom + i, length); | |
1083 | } | |
1084 | ||
1085 | fw_core_handle_response(&ohci->card, &response); | |
1086 | } | |
1087 | ||
1088 | static void | |
1089 | handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
1090 | { | |
1091 | struct fw_packet response; | |
1092 | int tcode, length, ext_tcode, sel; | |
1093 | __be32 *payload, lock_old; | |
1094 | u32 lock_arg, lock_data; | |
1095 | ||
a77754a7 KH |
1096 | tcode = HEADER_GET_TCODE(packet->header[0]); |
1097 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); | |
93c4cceb | 1098 | payload = packet->payload; |
a77754a7 | 1099 | ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); |
93c4cceb KH |
1100 | |
1101 | if (tcode == TCODE_LOCK_REQUEST && | |
1102 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
1103 | lock_arg = be32_to_cpu(payload[0]); | |
1104 | lock_data = be32_to_cpu(payload[1]); | |
1105 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
1106 | lock_arg = 0; | |
1107 | lock_data = 0; | |
1108 | } else { | |
1109 | fw_fill_response(&response, packet->header, | |
1110 | RCODE_TYPE_ERROR, NULL, 0); | |
1111 | goto out; | |
1112 | } | |
1113 | ||
1114 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
1115 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
1116 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
1117 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
1118 | ||
1119 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
1120 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
1121 | else | |
1122 | fw_notify("swap not done yet\n"); | |
1123 | ||
1124 | fw_fill_response(&response, packet->header, | |
2d826cc5 | 1125 | RCODE_COMPLETE, &lock_old, sizeof(lock_old)); |
93c4cceb KH |
1126 | out: |
1127 | fw_core_handle_response(&ohci->card, &response); | |
1128 | } | |
1129 | ||
1130 | static void | |
f319b6a0 | 1131 | handle_local_request(struct context *ctx, struct fw_packet *packet) |
93c4cceb KH |
1132 | { |
1133 | u64 offset; | |
1134 | u32 csr; | |
1135 | ||
473d28c7 KH |
1136 | if (ctx == &ctx->ohci->at_request_ctx) { |
1137 | packet->ack = ACK_PENDING; | |
1138 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1139 | } | |
93c4cceb KH |
1140 | |
1141 | offset = | |
1142 | ((unsigned long long) | |
a77754a7 | 1143 | HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | |
93c4cceb KH |
1144 | packet->header[2]; |
1145 | csr = offset - CSR_REGISTER_BASE; | |
1146 | ||
1147 | /* Handle config rom reads. */ | |
1148 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
1149 | handle_local_rom(ctx->ohci, packet, csr); | |
1150 | else switch (csr) { | |
1151 | case CSR_BUS_MANAGER_ID: | |
1152 | case CSR_BANDWIDTH_AVAILABLE: | |
1153 | case CSR_CHANNELS_AVAILABLE_HI: | |
1154 | case CSR_CHANNELS_AVAILABLE_LO: | |
1155 | handle_local_lock(ctx->ohci, packet, csr); | |
1156 | break; | |
1157 | default: | |
1158 | if (ctx == &ctx->ohci->at_request_ctx) | |
1159 | fw_core_handle_request(&ctx->ohci->card, packet); | |
1160 | else | |
1161 | fw_core_handle_response(&ctx->ohci->card, packet); | |
1162 | break; | |
1163 | } | |
473d28c7 KH |
1164 | |
1165 | if (ctx == &ctx->ohci->at_response_ctx) { | |
1166 | packet->ack = ACK_COMPLETE; | |
1167 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1168 | } | |
93c4cceb | 1169 | } |
e636fe25 | 1170 | |
ed568912 | 1171 | static void |
f319b6a0 | 1172 | at_context_transmit(struct context *ctx, struct fw_packet *packet) |
ed568912 | 1173 | { |
ed568912 | 1174 | unsigned long flags; |
f319b6a0 | 1175 | int retval; |
ed568912 KH |
1176 | |
1177 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
1178 | ||
a77754a7 | 1179 | if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && |
e636fe25 | 1180 | ctx->ohci->generation == packet->generation) { |
93c4cceb KH |
1181 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1182 | handle_local_request(ctx, packet); | |
1183 | return; | |
e636fe25 | 1184 | } |
ed568912 | 1185 | |
f319b6a0 | 1186 | retval = at_context_queue_packet(ctx, packet); |
ed568912 KH |
1187 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1188 | ||
f319b6a0 KH |
1189 | if (retval < 0) |
1190 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
a186b4a6 | 1191 | |
ed568912 KH |
1192 | } |
1193 | ||
1194 | static void bus_reset_tasklet(unsigned long data) | |
1195 | { | |
1196 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 1197 | int self_id_count, i, j, reg; |
ed568912 KH |
1198 | int generation, new_generation; |
1199 | unsigned long flags; | |
4eaff7d6 SR |
1200 | void *free_rom = NULL; |
1201 | dma_addr_t free_rom_bus = 0; | |
ed568912 KH |
1202 | |
1203 | reg = reg_read(ohci, OHCI1394_NodeID); | |
1204 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
02ff8f8e | 1205 | fw_notify("node ID not valid, new bus reset in progress\n"); |
ed568912 KH |
1206 | return; |
1207 | } | |
02ff8f8e SR |
1208 | if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { |
1209 | fw_notify("malconfigured bus\n"); | |
1210 | return; | |
1211 | } | |
1212 | ohci->node_id = reg & (OHCI1394_NodeID_busNumber | | |
1213 | OHCI1394_NodeID_nodeNumber); | |
ed568912 | 1214 | |
c8a9a498 SR |
1215 | reg = reg_read(ohci, OHCI1394_SelfIDCount); |
1216 | if (reg & OHCI1394_SelfIDCount_selfIDError) { | |
1217 | fw_notify("inconsistent self IDs\n"); | |
1218 | return; | |
1219 | } | |
c781c06d KH |
1220 | /* |
1221 | * The count in the SelfIDCount register is the number of | |
ed568912 KH |
1222 | * bytes in the self ID receive buffer. Since we also receive |
1223 | * the inverted quadlets and a header quadlet, we shift one | |
c781c06d KH |
1224 | * bit extra to get the actual number of self IDs. |
1225 | */ | |
c8a9a498 | 1226 | self_id_count = (reg >> 3) & 0x3ff; |
016bf3df SR |
1227 | if (self_id_count == 0) { |
1228 | fw_notify("inconsistent self IDs\n"); | |
1229 | return; | |
1230 | } | |
11bf20ad | 1231 | generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; |
ee71c2f9 | 1232 | rmb(); |
ed568912 KH |
1233 | |
1234 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
c8a9a498 SR |
1235 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { |
1236 | fw_notify("inconsistent self IDs\n"); | |
1237 | return; | |
1238 | } | |
11bf20ad SR |
1239 | ohci->self_id_buffer[j] = |
1240 | cond_le32_to_cpu(ohci->self_id_cpu[i]); | |
ed568912 | 1241 | } |
ee71c2f9 | 1242 | rmb(); |
ed568912 | 1243 | |
c781c06d KH |
1244 | /* |
1245 | * Check the consistency of the self IDs we just read. The | |
ed568912 KH |
1246 | * problem we face is that a new bus reset can start while we |
1247 | * read out the self IDs from the DMA buffer. If this happens, | |
1248 | * the DMA buffer will be overwritten with new self IDs and we | |
1249 | * will read out inconsistent data. The OHCI specification | |
1250 | * (section 11.2) recommends a technique similar to | |
1251 | * linux/seqlock.h, where we remember the generation of the | |
1252 | * self IDs in the buffer before reading them out and compare | |
1253 | * it to the current generation after reading them out. If | |
1254 | * the two generations match we know we have a consistent set | |
c781c06d KH |
1255 | * of self IDs. |
1256 | */ | |
ed568912 KH |
1257 | |
1258 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
1259 | if (new_generation != generation) { | |
1260 | fw_notify("recursive bus reset detected, " | |
1261 | "discarding self ids\n"); | |
1262 | return; | |
1263 | } | |
1264 | ||
1265 | /* FIXME: Document how the locking works. */ | |
1266 | spin_lock_irqsave(&ohci->lock, flags); | |
1267 | ||
1268 | ohci->generation = generation; | |
f319b6a0 KH |
1269 | context_stop(&ohci->at_request_ctx); |
1270 | context_stop(&ohci->at_response_ctx); | |
ed568912 KH |
1271 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
1272 | ||
c781c06d KH |
1273 | /* |
1274 | * This next bit is unrelated to the AT context stuff but we | |
ed568912 KH |
1275 | * have to do it under the spinlock also. If a new config rom |
1276 | * was set up before this reset, the old one is now no longer | |
1277 | * in use and we can free it. Update the config rom pointers | |
1278 | * to point to the current config rom and clear the | |
c781c06d KH |
1279 | * next_config_rom pointer so a new udpate can take place. |
1280 | */ | |
ed568912 KH |
1281 | |
1282 | if (ohci->next_config_rom != NULL) { | |
0bd243c4 KH |
1283 | if (ohci->next_config_rom != ohci->config_rom) { |
1284 | free_rom = ohci->config_rom; | |
1285 | free_rom_bus = ohci->config_rom_bus; | |
1286 | } | |
ed568912 KH |
1287 | ohci->config_rom = ohci->next_config_rom; |
1288 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
1289 | ohci->next_config_rom = NULL; | |
1290 | ||
c781c06d KH |
1291 | /* |
1292 | * Restore config_rom image and manually update | |
ed568912 KH |
1293 | * config_rom registers. Writing the header quadlet |
1294 | * will indicate that the config rom is ready, so we | |
c781c06d KH |
1295 | * do that last. |
1296 | */ | |
ed568912 KH |
1297 | reg_write(ohci, OHCI1394_BusOptions, |
1298 | be32_to_cpu(ohci->config_rom[2])); | |
1299 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
1300 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
1301 | } | |
1302 | ||
080de8c2 SR |
1303 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
1304 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); | |
1305 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); | |
1306 | #endif | |
1307 | ||
ed568912 KH |
1308 | spin_unlock_irqrestore(&ohci->lock, flags); |
1309 | ||
4eaff7d6 SR |
1310 | if (free_rom) |
1311 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1312 | free_rom, free_rom_bus); | |
1313 | ||
ad3c0fe8 SR |
1314 | log_selfids(generation, self_id_count, ohci->self_id_buffer); |
1315 | ||
e636fe25 | 1316 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
1317 | self_id_count, ohci->self_id_buffer); |
1318 | } | |
1319 | ||
1320 | static irqreturn_t irq_handler(int irq, void *data) | |
1321 | { | |
1322 | struct fw_ohci *ohci = data; | |
d60d7f1d | 1323 | u32 event, iso_event, cycle_time; |
ed568912 KH |
1324 | int i; |
1325 | ||
1326 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
1327 | ||
a515958d | 1328 | if (!event || !~event) |
ed568912 KH |
1329 | return IRQ_NONE; |
1330 | ||
1331 | reg_write(ohci, OHCI1394_IntEventClear, event); | |
ad3c0fe8 | 1332 | log_irqs(event); |
ed568912 KH |
1333 | |
1334 | if (event & OHCI1394_selfIDComplete) | |
1335 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
1336 | ||
1337 | if (event & OHCI1394_RQPkt) | |
1338 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
1339 | ||
1340 | if (event & OHCI1394_RSPkt) | |
1341 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
1342 | ||
1343 | if (event & OHCI1394_reqTxComplete) | |
1344 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
1345 | ||
1346 | if (event & OHCI1394_respTxComplete) | |
1347 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
1348 | ||
c889475f | 1349 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed568912 KH |
1350 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); |
1351 | ||
1352 | while (iso_event) { | |
1353 | i = ffs(iso_event) - 1; | |
30200739 | 1354 | tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed568912 KH |
1355 | iso_event &= ~(1 << i); |
1356 | } | |
1357 | ||
c889475f | 1358 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed568912 KH |
1359 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); |
1360 | ||
1361 | while (iso_event) { | |
1362 | i = ffs(iso_event) - 1; | |
30200739 | 1363 | tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed568912 KH |
1364 | iso_event &= ~(1 << i); |
1365 | } | |
1366 | ||
75f7832e JW |
1367 | if (unlikely(event & OHCI1394_regAccessFail)) |
1368 | fw_error("Register access failure - " | |
1369 | "please notify linux1394-devel@lists.sf.net\n"); | |
1370 | ||
e524f616 SR |
1371 | if (unlikely(event & OHCI1394_postedWriteErr)) |
1372 | fw_error("PCI posted write error\n"); | |
1373 | ||
bb9f2206 SR |
1374 | if (unlikely(event & OHCI1394_cycleTooLong)) { |
1375 | if (printk_ratelimit()) | |
1376 | fw_notify("isochronous cycle too long\n"); | |
1377 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1378 | OHCI1394_LinkControl_cycleMaster); | |
1379 | } | |
1380 | ||
d60d7f1d KH |
1381 | if (event & OHCI1394_cycle64Seconds) { |
1382 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1383 | if ((cycle_time & 0x80000000) == 0) | |
1384 | ohci->bus_seconds++; | |
1385 | } | |
1386 | ||
ed568912 KH |
1387 | return IRQ_HANDLED; |
1388 | } | |
1389 | ||
2aef469a KH |
1390 | static int software_reset(struct fw_ohci *ohci) |
1391 | { | |
1392 | int i; | |
1393 | ||
1394 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1395 | ||
1396 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1397 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1398 | OHCI1394_HCControl_softReset) == 0) | |
1399 | return 0; | |
1400 | msleep(1); | |
1401 | } | |
1402 | ||
1403 | return -EBUSY; | |
1404 | } | |
1405 | ||
ed568912 KH |
1406 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) |
1407 | { | |
1408 | struct fw_ohci *ohci = fw_ohci(card); | |
1409 | struct pci_dev *dev = to_pci_dev(card->device); | |
02214724 JW |
1410 | u32 lps; |
1411 | int i; | |
ed568912 | 1412 | |
2aef469a KH |
1413 | if (software_reset(ohci)) { |
1414 | fw_error("Failed to reset ohci card.\n"); | |
1415 | return -EBUSY; | |
1416 | } | |
1417 | ||
1418 | /* | |
1419 | * Now enable LPS, which we need in order to start accessing | |
1420 | * most of the registers. In fact, on some cards (ALI M5251), | |
1421 | * accessing registers in the SClk domain without LPS enabled | |
1422 | * will lock up the machine. Wait 50msec to make sure we have | |
02214724 JW |
1423 | * full link enabled. However, with some cards (well, at least |
1424 | * a JMicron PCIe card), we have to try again sometimes. | |
2aef469a KH |
1425 | */ |
1426 | reg_write(ohci, OHCI1394_HCControlSet, | |
1427 | OHCI1394_HCControl_LPS | | |
1428 | OHCI1394_HCControl_postedWriteEnable); | |
1429 | flush_writes(ohci); | |
02214724 JW |
1430 | |
1431 | for (lps = 0, i = 0; !lps && i < 3; i++) { | |
1432 | msleep(50); | |
1433 | lps = reg_read(ohci, OHCI1394_HCControlSet) & | |
1434 | OHCI1394_HCControl_LPS; | |
1435 | } | |
1436 | ||
1437 | if (!lps) { | |
1438 | fw_error("Failed to set Link Power Status\n"); | |
1439 | return -EIO; | |
1440 | } | |
2aef469a KH |
1441 | |
1442 | reg_write(ohci, OHCI1394_HCControlClear, | |
1443 | OHCI1394_HCControl_noByteSwapData); | |
1444 | ||
1445 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1446 | OHCI1394_LinkControl_rcvSelfID | | |
1447 | OHCI1394_LinkControl_cycleTimerEnable | | |
1448 | OHCI1394_LinkControl_cycleMaster); | |
1449 | ||
1450 | reg_write(ohci, OHCI1394_ATRetries, | |
1451 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1452 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1453 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1454 | ||
1455 | ar_context_run(&ohci->ar_request_ctx); | |
1456 | ar_context_run(&ohci->ar_response_ctx); | |
1457 | ||
1458 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | |
1459 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); | |
1460 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1461 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1462 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1463 | OHCI1394_selfIDComplete | | |
1464 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1465 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1466 | OHCI1394_isochRx | OHCI1394_isochTx | | |
bb9f2206 | 1467 | OHCI1394_postedWriteErr | OHCI1394_cycleTooLong | |
75f7832e JW |
1468 | OHCI1394_cycle64Seconds | OHCI1394_regAccessFail | |
1469 | OHCI1394_masterIntEnable); | |
2aef469a KH |
1470 | |
1471 | /* Activate link_on bit and contender bit in our self ID packets.*/ | |
1472 | if (ohci_update_phy_reg(card, 4, 0, | |
1473 | PHY_LINK_ACTIVE | PHY_CONTENDER) < 0) | |
1474 | return -EIO; | |
1475 | ||
c781c06d KH |
1476 | /* |
1477 | * When the link is not yet enabled, the atomic config rom | |
ed568912 KH |
1478 | * update mechanism described below in ohci_set_config_rom() |
1479 | * is not active. We have to update ConfigRomHeader and | |
1480 | * BusOptions manually, and the write to ConfigROMmap takes | |
1481 | * effect immediately. We tie this to the enabling of the | |
1482 | * link, so we have a valid config rom before enabling - the | |
1483 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
1484 | * values before enabling. | |
1485 | * | |
1486 | * However, when the ConfigROMmap is written, some controllers | |
1487 | * always read back quadlets 0 and 2 from the config rom to | |
1488 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
1489 | * They shouldn't do that in this initial case where the link | |
1490 | * isn't enabled. This means we have to use the same | |
1491 | * workaround here, setting the bus header to 0 and then write | |
1492 | * the right values in the bus reset tasklet. | |
1493 | */ | |
1494 | ||
0bd243c4 KH |
1495 | if (config_rom) { |
1496 | ohci->next_config_rom = | |
1497 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1498 | &ohci->next_config_rom_bus, | |
1499 | GFP_KERNEL); | |
1500 | if (ohci->next_config_rom == NULL) | |
1501 | return -ENOMEM; | |
ed568912 | 1502 | |
0bd243c4 KH |
1503 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); |
1504 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
1505 | } else { | |
1506 | /* | |
1507 | * In the suspend case, config_rom is NULL, which | |
1508 | * means that we just reuse the old config rom. | |
1509 | */ | |
1510 | ohci->next_config_rom = ohci->config_rom; | |
1511 | ohci->next_config_rom_bus = ohci->config_rom_bus; | |
1512 | } | |
ed568912 | 1513 | |
0bd243c4 | 1514 | ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]); |
ed568912 KH |
1515 | ohci->next_config_rom[0] = 0; |
1516 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
0bd243c4 KH |
1517 | reg_write(ohci, OHCI1394_BusOptions, |
1518 | be32_to_cpu(ohci->next_config_rom[2])); | |
ed568912 KH |
1519 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); |
1520 | ||
1521 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
1522 | ||
1523 | if (request_irq(dev->irq, irq_handler, | |
65efffa8 | 1524 | IRQF_SHARED, ohci_driver_name, ohci)) { |
ed568912 KH |
1525 | fw_error("Failed to allocate shared interrupt %d.\n", |
1526 | dev->irq); | |
1527 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1528 | ohci->config_rom, ohci->config_rom_bus); | |
1529 | return -EIO; | |
1530 | } | |
1531 | ||
1532 | reg_write(ohci, OHCI1394_HCControlSet, | |
1533 | OHCI1394_HCControl_linkEnable | | |
1534 | OHCI1394_HCControl_BIBimageValid); | |
1535 | flush_writes(ohci); | |
1536 | ||
c781c06d KH |
1537 | /* |
1538 | * We are ready to go, initiate bus reset to finish the | |
1539 | * initialization. | |
1540 | */ | |
ed568912 KH |
1541 | |
1542 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1543 | ||
1544 | return 0; | |
1545 | } | |
1546 | ||
1547 | static int | |
1548 | ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) | |
1549 | { | |
1550 | struct fw_ohci *ohci; | |
1551 | unsigned long flags; | |
4eaff7d6 | 1552 | int retval = -EBUSY; |
ed568912 | 1553 | __be32 *next_config_rom; |
f5101d58 | 1554 | dma_addr_t uninitialized_var(next_config_rom_bus); |
ed568912 KH |
1555 | |
1556 | ohci = fw_ohci(card); | |
1557 | ||
c781c06d KH |
1558 | /* |
1559 | * When the OHCI controller is enabled, the config rom update | |
ed568912 KH |
1560 | * mechanism is a bit tricky, but easy enough to use. See |
1561 | * section 5.5.6 in the OHCI specification. | |
1562 | * | |
1563 | * The OHCI controller caches the new config rom address in a | |
1564 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
1565 | * for the changes to take place. When the bus reset is | |
1566 | * detected, the controller loads the new values for the | |
1567 | * ConfigRomHeader and BusOptions registers from the specified | |
1568 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
1569 | * shadow register. All automatically and atomically. | |
1570 | * | |
1571 | * Now, there's a twist to this story. The automatic load of | |
1572 | * ConfigRomHeader and BusOptions doesn't honor the | |
1573 | * noByteSwapData bit, so with a be32 config rom, the | |
1574 | * controller will load be32 values in to these registers | |
1575 | * during the atomic update, even on litte endian | |
1576 | * architectures. The workaround we use is to put a 0 in the | |
1577 | * header quadlet; 0 is endian agnostic and means that the | |
1578 | * config rom isn't ready yet. In the bus reset tasklet we | |
1579 | * then set up the real values for the two registers. | |
1580 | * | |
1581 | * We use ohci->lock to avoid racing with the code that sets | |
1582 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
1583 | */ | |
1584 | ||
1585 | next_config_rom = | |
1586 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1587 | &next_config_rom_bus, GFP_KERNEL); | |
1588 | if (next_config_rom == NULL) | |
1589 | return -ENOMEM; | |
1590 | ||
1591 | spin_lock_irqsave(&ohci->lock, flags); | |
1592 | ||
1593 | if (ohci->next_config_rom == NULL) { | |
1594 | ohci->next_config_rom = next_config_rom; | |
1595 | ohci->next_config_rom_bus = next_config_rom_bus; | |
1596 | ||
1597 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1598 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
1599 | length * 4); | |
1600 | ||
1601 | ohci->next_header = config_rom[0]; | |
1602 | ohci->next_config_rom[0] = 0; | |
1603 | ||
1604 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
1605 | ohci->next_config_rom_bus); | |
4eaff7d6 | 1606 | retval = 0; |
ed568912 KH |
1607 | } |
1608 | ||
1609 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1610 | ||
c781c06d KH |
1611 | /* |
1612 | * Now initiate a bus reset to have the changes take | |
ed568912 KH |
1613 | * effect. We clean up the old config rom memory and DMA |
1614 | * mappings in the bus reset tasklet, since the OHCI | |
1615 | * controller could need to access it before the bus reset | |
c781c06d KH |
1616 | * takes effect. |
1617 | */ | |
ed568912 KH |
1618 | if (retval == 0) |
1619 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
4eaff7d6 SR |
1620 | else |
1621 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1622 | next_config_rom, next_config_rom_bus); | |
ed568912 KH |
1623 | |
1624 | return retval; | |
1625 | } | |
1626 | ||
1627 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1628 | { | |
1629 | struct fw_ohci *ohci = fw_ohci(card); | |
1630 | ||
1631 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1632 | } | |
1633 | ||
1634 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1635 | { | |
1636 | struct fw_ohci *ohci = fw_ohci(card); | |
1637 | ||
1638 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1639 | } | |
1640 | ||
730c32f5 KH |
1641 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
1642 | { | |
1643 | struct fw_ohci *ohci = fw_ohci(card); | |
f319b6a0 KH |
1644 | struct context *ctx = &ohci->at_request_ctx; |
1645 | struct driver_data *driver_data = packet->driver_data; | |
1646 | int retval = -ENOENT; | |
730c32f5 | 1647 | |
f319b6a0 | 1648 | tasklet_disable(&ctx->tasklet); |
730c32f5 | 1649 | |
f319b6a0 KH |
1650 | if (packet->ack != 0) |
1651 | goto out; | |
730c32f5 | 1652 | |
ad3c0fe8 | 1653 | log_ar_at_event('T', packet->speed, packet->header, 0x20); |
f319b6a0 KH |
1654 | driver_data->packet = NULL; |
1655 | packet->ack = RCODE_CANCELLED; | |
1656 | packet->callback(packet, &ohci->card, packet->ack); | |
1657 | retval = 0; | |
730c32f5 | 1658 | |
f319b6a0 KH |
1659 | out: |
1660 | tasklet_enable(&ctx->tasklet); | |
730c32f5 | 1661 | |
f319b6a0 | 1662 | return retval; |
730c32f5 KH |
1663 | } |
1664 | ||
ed568912 KH |
1665 | static int |
1666 | ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) | |
1667 | { | |
080de8c2 SR |
1668 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
1669 | return 0; | |
1670 | #else | |
ed568912 KH |
1671 | struct fw_ohci *ohci = fw_ohci(card); |
1672 | unsigned long flags; | |
907293d7 | 1673 | int n, retval = 0; |
ed568912 | 1674 | |
c781c06d KH |
1675 | /* |
1676 | * FIXME: Make sure this bitmask is cleared when we clear the busReset | |
1677 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. | |
1678 | */ | |
ed568912 KH |
1679 | |
1680 | spin_lock_irqsave(&ohci->lock, flags); | |
1681 | ||
1682 | if (ohci->generation != generation) { | |
1683 | retval = -ESTALE; | |
1684 | goto out; | |
1685 | } | |
1686 | ||
c781c06d KH |
1687 | /* |
1688 | * Note, if the node ID contains a non-local bus ID, physical DMA is | |
1689 | * enabled for _all_ nodes on remote buses. | |
1690 | */ | |
907293d7 SR |
1691 | |
1692 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
1693 | if (n < 32) | |
1694 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
1695 | else | |
1696 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
1697 | ||
ed568912 | 1698 | flush_writes(ohci); |
ed568912 | 1699 | out: |
6cad95fe | 1700 | spin_unlock_irqrestore(&ohci->lock, flags); |
ed568912 | 1701 | return retval; |
080de8c2 | 1702 | #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ |
ed568912 | 1703 | } |
373b2edd | 1704 | |
d60d7f1d KH |
1705 | static u64 |
1706 | ohci_get_bus_time(struct fw_card *card) | |
1707 | { | |
1708 | struct fw_ohci *ohci = fw_ohci(card); | |
1709 | u32 cycle_time; | |
1710 | u64 bus_time; | |
1711 | ||
1712 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1713 | bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time; | |
1714 | ||
1715 | return bus_time; | |
1716 | } | |
1717 | ||
d2746dc1 KH |
1718 | static int handle_ir_dualbuffer_packet(struct context *context, |
1719 | struct descriptor *d, | |
1720 | struct descriptor *last) | |
ed568912 | 1721 | { |
295e3feb KH |
1722 | struct iso_context *ctx = |
1723 | container_of(context, struct iso_context, context); | |
1724 | struct db_descriptor *db = (struct db_descriptor *) d; | |
c70dc788 | 1725 | __le32 *ir_header; |
9b32d5f3 | 1726 | size_t header_length; |
c70dc788 KH |
1727 | void *p, *end; |
1728 | int i; | |
d2746dc1 | 1729 | |
efbf390a | 1730 | if (db->first_res_count != 0 && db->second_res_count != 0) { |
0642b657 DM |
1731 | if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) { |
1732 | /* This descriptor isn't done yet, stop iteration. */ | |
1733 | return 0; | |
1734 | } | |
1735 | ctx->excess_bytes -= le16_to_cpu(db->second_req_count); | |
1736 | } | |
295e3feb | 1737 | |
c70dc788 KH |
1738 | header_length = le16_to_cpu(db->first_req_count) - |
1739 | le16_to_cpu(db->first_res_count); | |
1740 | ||
1741 | i = ctx->header_length; | |
1742 | p = db + 1; | |
1743 | end = p + header_length; | |
1744 | while (p < end && i + ctx->base.header_size <= PAGE_SIZE) { | |
c781c06d KH |
1745 | /* |
1746 | * The iso header is byteswapped to little endian by | |
15536221 KH |
1747 | * the controller, but the remaining header quadlets |
1748 | * are big endian. We want to present all the headers | |
1749 | * as big endian, so we have to swap the first | |
c781c06d KH |
1750 | * quadlet. |
1751 | */ | |
15536221 KH |
1752 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); |
1753 | memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); | |
c70dc788 | 1754 | i += ctx->base.header_size; |
0642b657 | 1755 | ctx->excess_bytes += |
efbf390a | 1756 | (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff; |
c70dc788 KH |
1757 | p += ctx->base.header_size + 4; |
1758 | } | |
c70dc788 | 1759 | ctx->header_length = i; |
9b32d5f3 | 1760 | |
0642b657 DM |
1761 | ctx->excess_bytes -= le16_to_cpu(db->second_req_count) - |
1762 | le16_to_cpu(db->second_res_count); | |
1763 | ||
a77754a7 | 1764 | if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) { |
c70dc788 KH |
1765 | ir_header = (__le32 *) (db + 1); |
1766 | ctx->base.callback(&ctx->base, | |
1767 | le32_to_cpu(ir_header[0]) & 0xffff, | |
9b32d5f3 | 1768 | ctx->header_length, ctx->header, |
295e3feb | 1769 | ctx->base.callback_data); |
9b32d5f3 KH |
1770 | ctx->header_length = 0; |
1771 | } | |
ed568912 | 1772 | |
295e3feb | 1773 | return 1; |
ed568912 KH |
1774 | } |
1775 | ||
a186b4a6 JW |
1776 | static int handle_ir_packet_per_buffer(struct context *context, |
1777 | struct descriptor *d, | |
1778 | struct descriptor *last) | |
1779 | { | |
1780 | struct iso_context *ctx = | |
1781 | container_of(context, struct iso_context, context); | |
bcee893c | 1782 | struct descriptor *pd; |
a186b4a6 | 1783 | __le32 *ir_header; |
bcee893c DM |
1784 | void *p; |
1785 | int i; | |
a186b4a6 | 1786 | |
bcee893c DM |
1787 | for (pd = d; pd <= last; pd++) { |
1788 | if (pd->transfer_status) | |
1789 | break; | |
1790 | } | |
1791 | if (pd > last) | |
a186b4a6 JW |
1792 | /* Descriptor(s) not done yet, stop iteration */ |
1793 | return 0; | |
1794 | ||
a186b4a6 | 1795 | i = ctx->header_length; |
bcee893c | 1796 | p = last + 1; |
a186b4a6 | 1797 | |
bcee893c DM |
1798 | if (ctx->base.header_size > 0 && |
1799 | i + ctx->base.header_size <= PAGE_SIZE) { | |
a186b4a6 JW |
1800 | /* |
1801 | * The iso header is byteswapped to little endian by | |
1802 | * the controller, but the remaining header quadlets | |
1803 | * are big endian. We want to present all the headers | |
1804 | * as big endian, so we have to swap the first quadlet. | |
1805 | */ | |
1806 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); | |
1807 | memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); | |
bcee893c | 1808 | ctx->header_length += ctx->base.header_size; |
a186b4a6 JW |
1809 | } |
1810 | ||
bcee893c DM |
1811 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { |
1812 | ir_header = (__le32 *) p; | |
a186b4a6 JW |
1813 | ctx->base.callback(&ctx->base, |
1814 | le32_to_cpu(ir_header[0]) & 0xffff, | |
1815 | ctx->header_length, ctx->header, | |
1816 | ctx->base.callback_data); | |
1817 | ctx->header_length = 0; | |
1818 | } | |
1819 | ||
a186b4a6 JW |
1820 | return 1; |
1821 | } | |
1822 | ||
30200739 KH |
1823 | static int handle_it_packet(struct context *context, |
1824 | struct descriptor *d, | |
1825 | struct descriptor *last) | |
ed568912 | 1826 | { |
30200739 KH |
1827 | struct iso_context *ctx = |
1828 | container_of(context, struct iso_context, context); | |
373b2edd | 1829 | |
30200739 KH |
1830 | if (last->transfer_status == 0) |
1831 | /* This descriptor isn't done yet, stop iteration. */ | |
1832 | return 0; | |
1833 | ||
a77754a7 | 1834 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) |
9b32d5f3 KH |
1835 | ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count), |
1836 | 0, NULL, ctx->base.callback_data); | |
30200739 KH |
1837 | |
1838 | return 1; | |
ed568912 KH |
1839 | } |
1840 | ||
30200739 | 1841 | static struct fw_iso_context * |
eb0306ea | 1842 | ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size) |
ed568912 KH |
1843 | { |
1844 | struct fw_ohci *ohci = fw_ohci(card); | |
1845 | struct iso_context *ctx, *list; | |
30200739 | 1846 | descriptor_callback_t callback; |
295e3feb | 1847 | u32 *mask, regs; |
ed568912 | 1848 | unsigned long flags; |
9b32d5f3 | 1849 | int index, retval = -ENOMEM; |
ed568912 KH |
1850 | |
1851 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
1852 | mask = &ohci->it_context_mask; | |
1853 | list = ohci->it_context_list; | |
30200739 | 1854 | callback = handle_it_packet; |
ed568912 | 1855 | } else { |
373b2edd SR |
1856 | mask = &ohci->ir_context_mask; |
1857 | list = ohci->ir_context_list; | |
a186b4a6 JW |
1858 | if (ohci->version >= OHCI_VERSION_1_1) |
1859 | callback = handle_ir_dualbuffer_packet; | |
1860 | else | |
1861 | callback = handle_ir_packet_per_buffer; | |
ed568912 KH |
1862 | } |
1863 | ||
1864 | spin_lock_irqsave(&ohci->lock, flags); | |
1865 | index = ffs(*mask) - 1; | |
1866 | if (index >= 0) | |
1867 | *mask &= ~(1 << index); | |
1868 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1869 | ||
1870 | if (index < 0) | |
1871 | return ERR_PTR(-EBUSY); | |
1872 | ||
373b2edd SR |
1873 | if (type == FW_ISO_CONTEXT_TRANSMIT) |
1874 | regs = OHCI1394_IsoXmitContextBase(index); | |
1875 | else | |
1876 | regs = OHCI1394_IsoRcvContextBase(index); | |
1877 | ||
ed568912 | 1878 | ctx = &list[index]; |
2d826cc5 | 1879 | memset(ctx, 0, sizeof(*ctx)); |
9b32d5f3 KH |
1880 | ctx->header_length = 0; |
1881 | ctx->header = (void *) __get_free_page(GFP_KERNEL); | |
1882 | if (ctx->header == NULL) | |
1883 | goto out; | |
1884 | ||
fe5ca634 | 1885 | retval = context_init(&ctx->context, ohci, regs, callback); |
9b32d5f3 KH |
1886 | if (retval < 0) |
1887 | goto out_with_header; | |
ed568912 KH |
1888 | |
1889 | return &ctx->base; | |
9b32d5f3 KH |
1890 | |
1891 | out_with_header: | |
1892 | free_page((unsigned long)ctx->header); | |
1893 | out: | |
1894 | spin_lock_irqsave(&ohci->lock, flags); | |
1895 | *mask |= 1 << index; | |
1896 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1897 | ||
1898 | return ERR_PTR(retval); | |
ed568912 KH |
1899 | } |
1900 | ||
eb0306ea KH |
1901 | static int ohci_start_iso(struct fw_iso_context *base, |
1902 | s32 cycle, u32 sync, u32 tags) | |
ed568912 | 1903 | { |
373b2edd | 1904 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1905 | struct fw_ohci *ohci = ctx->context.ohci; |
8a2f7d93 | 1906 | u32 control, match; |
ed568912 KH |
1907 | int index; |
1908 | ||
295e3feb KH |
1909 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { |
1910 | index = ctx - ohci->it_context_list; | |
8a2f7d93 KH |
1911 | match = 0; |
1912 | if (cycle >= 0) | |
1913 | match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
295e3feb | 1914 | (cycle & 0x7fff) << 16; |
21efb3cf | 1915 | |
295e3feb KH |
1916 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); |
1917 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
8a2f7d93 | 1918 | context_run(&ctx->context, match); |
295e3feb KH |
1919 | } else { |
1920 | index = ctx - ohci->ir_context_list; | |
a186b4a6 JW |
1921 | control = IR_CONTEXT_ISOCH_HEADER; |
1922 | if (ohci->version >= OHCI_VERSION_1_1) | |
1923 | control |= IR_CONTEXT_DUAL_BUFFER_MODE; | |
8a2f7d93 KH |
1924 | match = (tags << 28) | (sync << 8) | ctx->base.channel; |
1925 | if (cycle >= 0) { | |
1926 | match |= (cycle & 0x07fff) << 12; | |
1927 | control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; | |
1928 | } | |
ed568912 | 1929 | |
295e3feb KH |
1930 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
1931 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
a77754a7 | 1932 | reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); |
8a2f7d93 | 1933 | context_run(&ctx->context, control); |
295e3feb | 1934 | } |
ed568912 KH |
1935 | |
1936 | return 0; | |
1937 | } | |
1938 | ||
b8295668 KH |
1939 | static int ohci_stop_iso(struct fw_iso_context *base) |
1940 | { | |
1941 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1942 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
b8295668 KH |
1943 | int index; |
1944 | ||
1945 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1946 | index = ctx - ohci->it_context_list; | |
1947 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
1948 | } else { | |
1949 | index = ctx - ohci->ir_context_list; | |
1950 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
1951 | } | |
1952 | flush_writes(ohci); | |
1953 | context_stop(&ctx->context); | |
1954 | ||
1955 | return 0; | |
1956 | } | |
1957 | ||
ed568912 KH |
1958 | static void ohci_free_iso_context(struct fw_iso_context *base) |
1959 | { | |
1960 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1961 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
1962 | unsigned long flags; |
1963 | int index; | |
1964 | ||
b8295668 KH |
1965 | ohci_stop_iso(base); |
1966 | context_release(&ctx->context); | |
9b32d5f3 | 1967 | free_page((unsigned long)ctx->header); |
b8295668 | 1968 | |
ed568912 KH |
1969 | spin_lock_irqsave(&ohci->lock, flags); |
1970 | ||
1971 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1972 | index = ctx - ohci->it_context_list; | |
ed568912 KH |
1973 | ohci->it_context_mask |= 1 << index; |
1974 | } else { | |
1975 | index = ctx - ohci->ir_context_list; | |
ed568912 KH |
1976 | ohci->ir_context_mask |= 1 << index; |
1977 | } | |
ed568912 KH |
1978 | |
1979 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1980 | } | |
1981 | ||
1982 | static int | |
295e3feb KH |
1983 | ohci_queue_iso_transmit(struct fw_iso_context *base, |
1984 | struct fw_iso_packet *packet, | |
1985 | struct fw_iso_buffer *buffer, | |
1986 | unsigned long payload) | |
ed568912 | 1987 | { |
373b2edd | 1988 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1989 | struct descriptor *d, *last, *pd; |
ed568912 KH |
1990 | struct fw_iso_packet *p; |
1991 | __le32 *header; | |
9aad8125 | 1992 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
1993 | u32 z, header_z, payload_z, irq; |
1994 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 1995 | int page, end_page, i, length, offset; |
ed568912 | 1996 | |
c781c06d KH |
1997 | /* |
1998 | * FIXME: Cycle lost behavior should be configurable: lose | |
1999 | * packet, retransmit or terminate.. | |
2000 | */ | |
ed568912 KH |
2001 | |
2002 | p = packet; | |
9aad8125 | 2003 | payload_index = payload; |
ed568912 KH |
2004 | |
2005 | if (p->skip) | |
2006 | z = 1; | |
2007 | else | |
2008 | z = 2; | |
2009 | if (p->header_length > 0) | |
2010 | z++; | |
2011 | ||
2012 | /* Determine the first page the payload isn't contained in. */ | |
2013 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
2014 | if (p->payload_length > 0) | |
2015 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
2016 | else | |
2017 | payload_z = 0; | |
2018 | ||
2019 | z += payload_z; | |
2020 | ||
2021 | /* Get header size in number of descriptors. */ | |
2d826cc5 | 2022 | header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); |
ed568912 | 2023 | |
30200739 KH |
2024 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
2025 | if (d == NULL) | |
2026 | return -ENOMEM; | |
ed568912 KH |
2027 | |
2028 | if (!p->skip) { | |
a77754a7 | 2029 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
ed568912 KH |
2030 | d[0].req_count = cpu_to_le16(8); |
2031 | ||
2032 | header = (__le32 *) &d[1]; | |
a77754a7 KH |
2033 | header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | |
2034 | IT_HEADER_TAG(p->tag) | | |
2035 | IT_HEADER_TCODE(TCODE_STREAM_DATA) | | |
2036 | IT_HEADER_CHANNEL(ctx->base.channel) | | |
2037 | IT_HEADER_SPEED(ctx->base.speed)); | |
ed568912 | 2038 | header[1] = |
a77754a7 | 2039 | cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + |
ed568912 KH |
2040 | p->payload_length)); |
2041 | } | |
2042 | ||
2043 | if (p->header_length > 0) { | |
2044 | d[2].req_count = cpu_to_le16(p->header_length); | |
2d826cc5 | 2045 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); |
ed568912 KH |
2046 | memcpy(&d[z], p->header, p->header_length); |
2047 | } | |
2048 | ||
2049 | pd = d + z - payload_z; | |
2050 | payload_end_index = payload_index + p->payload_length; | |
2051 | for (i = 0; i < payload_z; i++) { | |
2052 | page = payload_index >> PAGE_SHIFT; | |
2053 | offset = payload_index & ~PAGE_MASK; | |
2054 | next_page_index = (page + 1) << PAGE_SHIFT; | |
2055 | length = | |
2056 | min(next_page_index, payload_end_index) - payload_index; | |
2057 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
2058 | |
2059 | page_bus = page_private(buffer->pages[page]); | |
2060 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
2061 | |
2062 | payload_index += length; | |
2063 | } | |
2064 | ||
ed568912 | 2065 | if (p->interrupt) |
a77754a7 | 2066 | irq = DESCRIPTOR_IRQ_ALWAYS; |
ed568912 | 2067 | else |
a77754a7 | 2068 | irq = DESCRIPTOR_NO_IRQ; |
ed568912 | 2069 | |
30200739 | 2070 | last = z == 2 ? d : d + z - 1; |
a77754a7 KH |
2071 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
2072 | DESCRIPTOR_STATUS | | |
2073 | DESCRIPTOR_BRANCH_ALWAYS | | |
cbb59da7 | 2074 | irq); |
ed568912 | 2075 | |
30200739 | 2076 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
2077 | |
2078 | return 0; | |
2079 | } | |
373b2edd | 2080 | |
295e3feb | 2081 | static int |
d2746dc1 KH |
2082 | ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base, |
2083 | struct fw_iso_packet *packet, | |
2084 | struct fw_iso_buffer *buffer, | |
2085 | unsigned long payload) | |
295e3feb KH |
2086 | { |
2087 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
2088 | struct db_descriptor *db = NULL; | |
2089 | struct descriptor *d; | |
2090 | struct fw_iso_packet *p; | |
2091 | dma_addr_t d_bus, page_bus; | |
2092 | u32 z, header_z, length, rest; | |
c70dc788 | 2093 | int page, offset, packet_count, header_size; |
373b2edd | 2094 | |
c781c06d KH |
2095 | /* |
2096 | * FIXME: Cycle lost behavior should be configurable: lose | |
2097 | * packet, retransmit or terminate.. | |
2098 | */ | |
295e3feb KH |
2099 | |
2100 | p = packet; | |
2101 | z = 2; | |
2102 | ||
c781c06d KH |
2103 | /* |
2104 | * The OHCI controller puts the status word in the header | |
2105 | * buffer too, so we need 4 extra bytes per packet. | |
2106 | */ | |
c70dc788 KH |
2107 | packet_count = p->header_length / ctx->base.header_size; |
2108 | header_size = packet_count * (ctx->base.header_size + 4); | |
2109 | ||
295e3feb | 2110 | /* Get header size in number of descriptors. */ |
2d826cc5 | 2111 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); |
295e3feb KH |
2112 | page = payload >> PAGE_SHIFT; |
2113 | offset = payload & ~PAGE_MASK; | |
2114 | rest = p->payload_length; | |
2115 | ||
295e3feb KH |
2116 | /* FIXME: make packet-per-buffer/dual-buffer a context option */ |
2117 | while (rest > 0) { | |
2118 | d = context_get_descriptors(&ctx->context, | |
2119 | z + header_z, &d_bus); | |
2120 | if (d == NULL) | |
2121 | return -ENOMEM; | |
2122 | ||
2123 | db = (struct db_descriptor *) d; | |
a77754a7 KH |
2124 | db->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2125 | DESCRIPTOR_BRANCH_ALWAYS); | |
c70dc788 | 2126 | db->first_size = cpu_to_le16(ctx->base.header_size + 4); |
0642b657 DM |
2127 | if (p->skip && rest == p->payload_length) { |
2128 | db->control |= cpu_to_le16(DESCRIPTOR_WAIT); | |
2129 | db->first_req_count = db->first_size; | |
2130 | } else { | |
2131 | db->first_req_count = cpu_to_le16(header_size); | |
2132 | } | |
1e1d196b | 2133 | db->first_res_count = db->first_req_count; |
2d826cc5 | 2134 | db->first_buffer = cpu_to_le32(d_bus + sizeof(*db)); |
373b2edd | 2135 | |
0642b657 DM |
2136 | if (p->skip && rest == p->payload_length) |
2137 | length = 4; | |
2138 | else if (offset + rest < PAGE_SIZE) | |
295e3feb KH |
2139 | length = rest; |
2140 | else | |
2141 | length = PAGE_SIZE - offset; | |
2142 | ||
1e1d196b KH |
2143 | db->second_req_count = cpu_to_le16(length); |
2144 | db->second_res_count = db->second_req_count; | |
295e3feb KH |
2145 | page_bus = page_private(buffer->pages[page]); |
2146 | db->second_buffer = cpu_to_le32(page_bus + offset); | |
2147 | ||
cb2d2cdb | 2148 | if (p->interrupt && length == rest) |
a77754a7 | 2149 | db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
cb2d2cdb | 2150 | |
295e3feb KH |
2151 | context_append(&ctx->context, d, z, header_z); |
2152 | offset = (offset + length) & ~PAGE_MASK; | |
2153 | rest -= length; | |
0642b657 DM |
2154 | if (offset == 0) |
2155 | page++; | |
295e3feb KH |
2156 | } |
2157 | ||
d2746dc1 KH |
2158 | return 0; |
2159 | } | |
21efb3cf | 2160 | |
a186b4a6 JW |
2161 | static int |
2162 | ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base, | |
2163 | struct fw_iso_packet *packet, | |
2164 | struct fw_iso_buffer *buffer, | |
2165 | unsigned long payload) | |
2166 | { | |
2167 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
2168 | struct descriptor *d = NULL, *pd = NULL; | |
bcee893c | 2169 | struct fw_iso_packet *p = packet; |
a186b4a6 JW |
2170 | dma_addr_t d_bus, page_bus; |
2171 | u32 z, header_z, rest; | |
bcee893c DM |
2172 | int i, j, length; |
2173 | int page, offset, packet_count, header_size, payload_per_buffer; | |
a186b4a6 JW |
2174 | |
2175 | /* | |
2176 | * The OHCI controller puts the status word in the | |
2177 | * buffer too, so we need 4 extra bytes per packet. | |
2178 | */ | |
2179 | packet_count = p->header_length / ctx->base.header_size; | |
bcee893c | 2180 | header_size = ctx->base.header_size + 4; |
a186b4a6 JW |
2181 | |
2182 | /* Get header size in number of descriptors. */ | |
2183 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); | |
2184 | page = payload >> PAGE_SHIFT; | |
2185 | offset = payload & ~PAGE_MASK; | |
bcee893c | 2186 | payload_per_buffer = p->payload_length / packet_count; |
a186b4a6 JW |
2187 | |
2188 | for (i = 0; i < packet_count; i++) { | |
2189 | /* d points to the header descriptor */ | |
bcee893c | 2190 | z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; |
a186b4a6 | 2191 | d = context_get_descriptors(&ctx->context, |
bcee893c | 2192 | z + header_z, &d_bus); |
a186b4a6 JW |
2193 | if (d == NULL) |
2194 | return -ENOMEM; | |
2195 | ||
bcee893c DM |
2196 | d->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2197 | DESCRIPTOR_INPUT_MORE); | |
2198 | if (p->skip && i == 0) | |
2199 | d->control |= cpu_to_le16(DESCRIPTOR_WAIT); | |
a186b4a6 JW |
2200 | d->req_count = cpu_to_le16(header_size); |
2201 | d->res_count = d->req_count; | |
bcee893c | 2202 | d->transfer_status = 0; |
a186b4a6 JW |
2203 | d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); |
2204 | ||
bcee893c DM |
2205 | rest = payload_per_buffer; |
2206 | for (j = 1; j < z; j++) { | |
2207 | pd = d + j; | |
2208 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | | |
2209 | DESCRIPTOR_INPUT_MORE); | |
2210 | ||
2211 | if (offset + rest < PAGE_SIZE) | |
2212 | length = rest; | |
2213 | else | |
2214 | length = PAGE_SIZE - offset; | |
2215 | pd->req_count = cpu_to_le16(length); | |
2216 | pd->res_count = pd->req_count; | |
2217 | pd->transfer_status = 0; | |
2218 | ||
2219 | page_bus = page_private(buffer->pages[page]); | |
2220 | pd->data_address = cpu_to_le32(page_bus + offset); | |
2221 | ||
2222 | offset = (offset + length) & ~PAGE_MASK; | |
2223 | rest -= length; | |
2224 | if (offset == 0) | |
2225 | page++; | |
2226 | } | |
a186b4a6 JW |
2227 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2228 | DESCRIPTOR_INPUT_LAST | | |
2229 | DESCRIPTOR_BRANCH_ALWAYS); | |
bcee893c | 2230 | if (p->interrupt && i == packet_count - 1) |
a186b4a6 JW |
2231 | pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
2232 | ||
a186b4a6 JW |
2233 | context_append(&ctx->context, d, z, header_z); |
2234 | } | |
2235 | ||
2236 | return 0; | |
2237 | } | |
2238 | ||
295e3feb KH |
2239 | static int |
2240 | ohci_queue_iso(struct fw_iso_context *base, | |
2241 | struct fw_iso_packet *packet, | |
2242 | struct fw_iso_buffer *buffer, | |
2243 | unsigned long payload) | |
2244 | { | |
e364cf4e | 2245 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
fe5ca634 DM |
2246 | unsigned long flags; |
2247 | int retval; | |
e364cf4e | 2248 | |
fe5ca634 | 2249 | spin_lock_irqsave(&ctx->context.ohci->lock, flags); |
295e3feb | 2250 | if (base->type == FW_ISO_CONTEXT_TRANSMIT) |
fe5ca634 | 2251 | retval = ohci_queue_iso_transmit(base, packet, buffer, payload); |
e364cf4e | 2252 | else if (ctx->context.ohci->version >= OHCI_VERSION_1_1) |
fe5ca634 | 2253 | retval = ohci_queue_iso_receive_dualbuffer(base, packet, |
d2746dc1 | 2254 | buffer, payload); |
e364cf4e | 2255 | else |
fe5ca634 | 2256 | retval = ohci_queue_iso_receive_packet_per_buffer(base, packet, |
a186b4a6 JW |
2257 | buffer, |
2258 | payload); | |
fe5ca634 DM |
2259 | spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); |
2260 | ||
2261 | return retval; | |
295e3feb KH |
2262 | } |
2263 | ||
21ebcd12 | 2264 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
2265 | .name = ohci_driver_name, |
2266 | .enable = ohci_enable, | |
2267 | .update_phy_reg = ohci_update_phy_reg, | |
2268 | .set_config_rom = ohci_set_config_rom, | |
2269 | .send_request = ohci_send_request, | |
2270 | .send_response = ohci_send_response, | |
730c32f5 | 2271 | .cancel_packet = ohci_cancel_packet, |
ed568912 | 2272 | .enable_phys_dma = ohci_enable_phys_dma, |
d60d7f1d | 2273 | .get_bus_time = ohci_get_bus_time, |
ed568912 KH |
2274 | |
2275 | .allocate_iso_context = ohci_allocate_iso_context, | |
2276 | .free_iso_context = ohci_free_iso_context, | |
2277 | .queue_iso = ohci_queue_iso, | |
69cdb726 | 2278 | .start_iso = ohci_start_iso, |
b8295668 | 2279 | .stop_iso = ohci_stop_iso, |
ed568912 KH |
2280 | }; |
2281 | ||
ea8d006b | 2282 | #ifdef CONFIG_PPC_PMAC |
2ed0f181 SR |
2283 | static void ohci_pmac_on(struct pci_dev *dev) |
2284 | { | |
ea8d006b SR |
2285 | if (machine_is(powermac)) { |
2286 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2287 | ||
2288 | if (ofn) { | |
2289 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); | |
2290 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); | |
2291 | } | |
2292 | } | |
2ed0f181 SR |
2293 | } |
2294 | ||
2295 | static void ohci_pmac_off(struct pci_dev *dev) | |
2296 | { | |
2297 | if (machine_is(powermac)) { | |
2298 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2299 | ||
2300 | if (ofn) { | |
2301 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); | |
2302 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); | |
2303 | } | |
2304 | } | |
2305 | } | |
2306 | #else | |
2307 | #define ohci_pmac_on(dev) | |
2308 | #define ohci_pmac_off(dev) | |
ea8d006b SR |
2309 | #endif /* CONFIG_PPC_PMAC */ |
2310 | ||
2ed0f181 SR |
2311 | static int __devinit |
2312 | pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |
2313 | { | |
2314 | struct fw_ohci *ohci; | |
2315 | u32 bus_options, max_receive, link_speed; | |
2316 | u64 guid; | |
2317 | int err; | |
2318 | size_t size; | |
2319 | ||
2d826cc5 | 2320 | ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); |
ed568912 KH |
2321 | if (ohci == NULL) { |
2322 | fw_error("Could not malloc fw_ohci data.\n"); | |
2323 | return -ENOMEM; | |
2324 | } | |
2325 | ||
2326 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
2327 | ||
130d5496 SR |
2328 | ohci_pmac_on(dev); |
2329 | ||
d79406dd KH |
2330 | err = pci_enable_device(dev); |
2331 | if (err) { | |
ed568912 | 2332 | fw_error("Failed to enable OHCI hardware.\n"); |
bd7dee63 | 2333 | goto fail_free; |
ed568912 KH |
2334 | } |
2335 | ||
2336 | pci_set_master(dev); | |
2337 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
2338 | pci_set_drvdata(dev, ohci); | |
2339 | ||
11bf20ad SR |
2340 | #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) |
2341 | ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE && | |
2342 | dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW; | |
2343 | #endif | |
ed568912 KH |
2344 | spin_lock_init(&ohci->lock); |
2345 | ||
2346 | tasklet_init(&ohci->bus_reset_tasklet, | |
2347 | bus_reset_tasklet, (unsigned long)ohci); | |
2348 | ||
d79406dd KH |
2349 | err = pci_request_region(dev, 0, ohci_driver_name); |
2350 | if (err) { | |
ed568912 | 2351 | fw_error("MMIO resource unavailable\n"); |
d79406dd | 2352 | goto fail_disable; |
ed568912 KH |
2353 | } |
2354 | ||
2355 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
2356 | if (ohci->registers == NULL) { | |
2357 | fw_error("Failed to remap registers\n"); | |
d79406dd KH |
2358 | err = -ENXIO; |
2359 | goto fail_iomem; | |
ed568912 KH |
2360 | } |
2361 | ||
ed568912 KH |
2362 | ar_context_init(&ohci->ar_request_ctx, ohci, |
2363 | OHCI1394_AsReqRcvContextControlSet); | |
2364 | ||
2365 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
2366 | OHCI1394_AsRspRcvContextControlSet); | |
2367 | ||
fe5ca634 | 2368 | context_init(&ohci->at_request_ctx, ohci, |
f319b6a0 | 2369 | OHCI1394_AsReqTrContextControlSet, handle_at_packet); |
ed568912 | 2370 | |
fe5ca634 | 2371 | context_init(&ohci->at_response_ctx, ohci, |
f319b6a0 | 2372 | OHCI1394_AsRspTrContextControlSet, handle_at_packet); |
ed568912 | 2373 | |
ed568912 KH |
2374 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); |
2375 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
2376 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
2377 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
2378 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
2379 | ||
2380 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
2381 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); | |
2382 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
2383 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
2384 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
2385 | ||
2386 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
2387 | fw_error("Out of memory for it/ir contexts.\n"); | |
d79406dd KH |
2388 | err = -ENOMEM; |
2389 | goto fail_registers; | |
ed568912 KH |
2390 | } |
2391 | ||
2392 | /* self-id dma buffer allocation */ | |
2393 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
2394 | SELF_ID_BUF_SIZE, | |
2395 | &ohci->self_id_bus, | |
2396 | GFP_KERNEL); | |
2397 | if (ohci->self_id_cpu == NULL) { | |
2398 | fw_error("Out of memory for self ID buffer.\n"); | |
d79406dd KH |
2399 | err = -ENOMEM; |
2400 | goto fail_registers; | |
ed568912 KH |
2401 | } |
2402 | ||
ed568912 KH |
2403 | bus_options = reg_read(ohci, OHCI1394_BusOptions); |
2404 | max_receive = (bus_options >> 12) & 0xf; | |
2405 | link_speed = bus_options & 0x7; | |
2406 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
2407 | reg_read(ohci, OHCI1394_GUIDLo); | |
2408 | ||
d79406dd KH |
2409 | err = fw_card_add(&ohci->card, max_receive, link_speed, guid); |
2410 | if (err < 0) | |
2411 | goto fail_self_id; | |
ed568912 | 2412 | |
e364cf4e | 2413 | ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
500be725 | 2414 | fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n", |
e364cf4e | 2415 | dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff); |
ed568912 | 2416 | return 0; |
d79406dd KH |
2417 | |
2418 | fail_self_id: | |
2419 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
2420 | ohci->self_id_cpu, ohci->self_id_bus); | |
2421 | fail_registers: | |
2422 | kfree(ohci->it_context_list); | |
2423 | kfree(ohci->ir_context_list); | |
2424 | pci_iounmap(dev, ohci->registers); | |
2425 | fail_iomem: | |
2426 | pci_release_region(dev, 0); | |
2427 | fail_disable: | |
2428 | pci_disable_device(dev); | |
bd7dee63 SR |
2429 | fail_free: |
2430 | kfree(&ohci->card); | |
130d5496 | 2431 | ohci_pmac_off(dev); |
d79406dd KH |
2432 | |
2433 | return err; | |
ed568912 KH |
2434 | } |
2435 | ||
2436 | static void pci_remove(struct pci_dev *dev) | |
2437 | { | |
2438 | struct fw_ohci *ohci; | |
2439 | ||
2440 | ohci = pci_get_drvdata(dev); | |
e254a4b4 KH |
2441 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); |
2442 | flush_writes(ohci); | |
ed568912 KH |
2443 | fw_core_remove_card(&ohci->card); |
2444 | ||
c781c06d KH |
2445 | /* |
2446 | * FIXME: Fail all pending packets here, now that the upper | |
2447 | * layers can't queue any more. | |
2448 | */ | |
ed568912 KH |
2449 | |
2450 | software_reset(ohci); | |
2451 | free_irq(dev->irq, ohci); | |
d79406dd KH |
2452 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, |
2453 | ohci->self_id_cpu, ohci->self_id_bus); | |
2454 | kfree(ohci->it_context_list); | |
2455 | kfree(ohci->ir_context_list); | |
2456 | pci_iounmap(dev, ohci->registers); | |
2457 | pci_release_region(dev, 0); | |
2458 | pci_disable_device(dev); | |
bd7dee63 | 2459 | kfree(&ohci->card); |
2ed0f181 | 2460 | ohci_pmac_off(dev); |
ea8d006b | 2461 | |
ed568912 KH |
2462 | fw_notify("Removed fw-ohci device.\n"); |
2463 | } | |
2464 | ||
2aef469a | 2465 | #ifdef CONFIG_PM |
2ed0f181 | 2466 | static int pci_suspend(struct pci_dev *dev, pm_message_t state) |
2aef469a | 2467 | { |
2ed0f181 | 2468 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
2469 | int err; |
2470 | ||
2471 | software_reset(ohci); | |
2ed0f181 SR |
2472 | free_irq(dev->irq, ohci); |
2473 | err = pci_save_state(dev); | |
2aef469a | 2474 | if (err) { |
8a8cea27 | 2475 | fw_error("pci_save_state failed\n"); |
2aef469a KH |
2476 | return err; |
2477 | } | |
2ed0f181 | 2478 | err = pci_set_power_state(dev, pci_choose_state(dev, state)); |
55111428 SR |
2479 | if (err) |
2480 | fw_error("pci_set_power_state failed with %d\n", err); | |
2ed0f181 | 2481 | ohci_pmac_off(dev); |
ea8d006b | 2482 | |
2aef469a KH |
2483 | return 0; |
2484 | } | |
2485 | ||
2ed0f181 | 2486 | static int pci_resume(struct pci_dev *dev) |
2aef469a | 2487 | { |
2ed0f181 | 2488 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
2489 | int err; |
2490 | ||
2ed0f181 SR |
2491 | ohci_pmac_on(dev); |
2492 | pci_set_power_state(dev, PCI_D0); | |
2493 | pci_restore_state(dev); | |
2494 | err = pci_enable_device(dev); | |
2aef469a | 2495 | if (err) { |
8a8cea27 | 2496 | fw_error("pci_enable_device failed\n"); |
2aef469a KH |
2497 | return err; |
2498 | } | |
2499 | ||
0bd243c4 | 2500 | return ohci_enable(&ohci->card, NULL, 0); |
2aef469a KH |
2501 | } |
2502 | #endif | |
2503 | ||
ed568912 KH |
2504 | static struct pci_device_id pci_table[] = { |
2505 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
2506 | { } | |
2507 | }; | |
2508 | ||
2509 | MODULE_DEVICE_TABLE(pci, pci_table); | |
2510 | ||
2511 | static struct pci_driver fw_ohci_pci_driver = { | |
2512 | .name = ohci_driver_name, | |
2513 | .id_table = pci_table, | |
2514 | .probe = pci_probe, | |
2515 | .remove = pci_remove, | |
2aef469a KH |
2516 | #ifdef CONFIG_PM |
2517 | .resume = pci_resume, | |
2518 | .suspend = pci_suspend, | |
2519 | #endif | |
ed568912 KH |
2520 | }; |
2521 | ||
2522 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
2523 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
2524 | MODULE_LICENSE("GPL"); | |
2525 | ||
1e4c7b0d OH |
2526 | /* Provide a module alias so root-on-sbp2 initrds don't break. */ |
2527 | #ifndef CONFIG_IEEE1394_OHCI1394_MODULE | |
2528 | MODULE_ALIAS("ohci1394"); | |
2529 | #endif | |
2530 | ||
ed568912 KH |
2531 | static int __init fw_ohci_init(void) |
2532 | { | |
2533 | return pci_register_driver(&fw_ohci_pci_driver); | |
2534 | } | |
2535 | ||
2536 | static void __exit fw_ohci_cleanup(void) | |
2537 | { | |
2538 | pci_unregister_driver(&fw_ohci_pci_driver); | |
2539 | } | |
2540 | ||
2541 | module_init(fw_ohci_init); | |
2542 | module_exit(fw_ohci_cleanup); |