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ed568912 KH |
1 | /* -*- c-basic-offset: 8 -*- |
2 | * | |
3 | * fw-ohci.c - Driver for OHCI 1394 boards | |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/poll.h> | |
cf3e72fd AM |
28 | #include <linux/dma-mapping.h> |
29 | ||
ed568912 KH |
30 | #include <asm/uaccess.h> |
31 | #include <asm/semaphore.h> | |
32 | ||
33 | #include "fw-transaction.h" | |
34 | #include "fw-ohci.h" | |
35 | ||
36 | #define descriptor_output_more 0 | |
37 | #define descriptor_output_last (1 << 12) | |
38 | #define descriptor_input_more (2 << 12) | |
39 | #define descriptor_input_last (3 << 12) | |
40 | #define descriptor_status (1 << 11) | |
41 | #define descriptor_key_immediate (2 << 8) | |
42 | #define descriptor_ping (1 << 7) | |
43 | #define descriptor_yy (1 << 6) | |
44 | #define descriptor_no_irq (0 << 4) | |
45 | #define descriptor_irq_error (1 << 4) | |
46 | #define descriptor_irq_always (3 << 4) | |
47 | #define descriptor_branch_always (3 << 2) | |
48 | ||
49 | struct descriptor { | |
50 | __le16 req_count; | |
51 | __le16 control; | |
52 | __le32 data_address; | |
53 | __le32 branch_address; | |
54 | __le16 res_count; | |
55 | __le16 transfer_status; | |
56 | } __attribute__((aligned(16))); | |
57 | ||
58 | struct ar_context { | |
59 | struct fw_ohci *ohci; | |
60 | struct descriptor descriptor; | |
61 | __le32 buffer[512]; | |
62 | dma_addr_t descriptor_bus; | |
63 | dma_addr_t buffer_bus; | |
64 | ||
65 | u32 command_ptr; | |
66 | u32 control_set; | |
67 | u32 control_clear; | |
68 | ||
69 | struct tasklet_struct tasklet; | |
70 | }; | |
71 | ||
72 | struct at_context { | |
73 | struct fw_ohci *ohci; | |
74 | dma_addr_t descriptor_bus; | |
75 | dma_addr_t buffer_bus; | |
76 | ||
77 | struct list_head list; | |
78 | ||
79 | struct { | |
80 | struct descriptor more; | |
81 | __le32 header[4]; | |
82 | struct descriptor last; | |
83 | } d; | |
84 | ||
85 | u32 command_ptr; | |
86 | u32 control_set; | |
87 | u32 control_clear; | |
88 | ||
89 | struct tasklet_struct tasklet; | |
90 | }; | |
91 | ||
92 | #define it_header_sy(v) ((v) << 0) | |
93 | #define it_header_tcode(v) ((v) << 4) | |
94 | #define it_header_channel(v) ((v) << 8) | |
95 | #define it_header_tag(v) ((v) << 14) | |
96 | #define it_header_speed(v) ((v) << 16) | |
97 | #define it_header_data_length(v) ((v) << 16) | |
98 | ||
99 | struct iso_context { | |
100 | struct fw_iso_context base; | |
101 | struct tasklet_struct tasklet; | |
102 | u32 control_set; | |
103 | u32 control_clear; | |
104 | u32 command_ptr; | |
105 | u32 context_match; | |
106 | ||
107 | struct descriptor *buffer; | |
108 | dma_addr_t buffer_bus; | |
109 | struct descriptor *head_descriptor; | |
110 | struct descriptor *tail_descriptor; | |
111 | struct descriptor *tail_descriptor_last; | |
112 | struct descriptor *prev_descriptor; | |
113 | }; | |
114 | ||
115 | #define CONFIG_ROM_SIZE 1024 | |
116 | ||
117 | struct fw_ohci { | |
118 | struct fw_card card; | |
119 | ||
120 | __iomem char *registers; | |
121 | dma_addr_t self_id_bus; | |
122 | __le32 *self_id_cpu; | |
123 | struct tasklet_struct bus_reset_tasklet; | |
e636fe25 | 124 | int node_id; |
ed568912 KH |
125 | int generation; |
126 | int request_generation; | |
127 | ||
128 | /* Spinlock for accessing fw_ohci data. Never call out of | |
129 | * this driver with this lock held. */ | |
130 | spinlock_t lock; | |
131 | u32 self_id_buffer[512]; | |
132 | ||
133 | /* Config rom buffers */ | |
134 | __be32 *config_rom; | |
135 | dma_addr_t config_rom_bus; | |
136 | __be32 *next_config_rom; | |
137 | dma_addr_t next_config_rom_bus; | |
138 | u32 next_header; | |
139 | ||
140 | struct ar_context ar_request_ctx; | |
141 | struct ar_context ar_response_ctx; | |
142 | struct at_context at_request_ctx; | |
143 | struct at_context at_response_ctx; | |
144 | ||
145 | u32 it_context_mask; | |
146 | struct iso_context *it_context_list; | |
147 | u32 ir_context_mask; | |
148 | struct iso_context *ir_context_list; | |
149 | }; | |
150 | ||
95688e97 | 151 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
152 | { |
153 | return container_of(card, struct fw_ohci, card); | |
154 | } | |
155 | ||
156 | #define CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 | |
157 | ||
158 | #define CONTEXT_RUN 0x8000 | |
159 | #define CONTEXT_WAKE 0x1000 | |
160 | #define CONTEXT_DEAD 0x0800 | |
161 | #define CONTEXT_ACTIVE 0x0400 | |
162 | ||
163 | #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 | |
164 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
165 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
166 | ||
167 | #define FW_OHCI_MAJOR 240 | |
168 | #define OHCI1394_REGISTER_SIZE 0x800 | |
169 | #define OHCI_LOOP_COUNT 500 | |
170 | #define OHCI1394_PCI_HCI_Control 0x40 | |
171 | #define SELF_ID_BUF_SIZE 0x800 | |
172 | ||
ed568912 KH |
173 | static char ohci_driver_name[] = KBUILD_MODNAME; |
174 | ||
95688e97 | 175 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
176 | { |
177 | writel(data, ohci->registers + offset); | |
178 | } | |
179 | ||
95688e97 | 180 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
181 | { |
182 | return readl(ohci->registers + offset); | |
183 | } | |
184 | ||
95688e97 | 185 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
186 | { |
187 | /* Do a dummy read to flush writes. */ | |
188 | reg_read(ohci, OHCI1394_Version); | |
189 | } | |
190 | ||
191 | static int | |
192 | ohci_update_phy_reg(struct fw_card *card, int addr, | |
193 | int clear_bits, int set_bits) | |
194 | { | |
195 | struct fw_ohci *ohci = fw_ohci(card); | |
196 | u32 val, old; | |
197 | ||
198 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
199 | msleep(2); | |
200 | val = reg_read(ohci, OHCI1394_PhyControl); | |
201 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
202 | fw_error("failed to set phy reg bits.\n"); | |
203 | return -EBUSY; | |
204 | } | |
205 | ||
206 | old = OHCI1394_PhyControl_ReadData(val); | |
207 | old = (old & ~clear_bits) | set_bits; | |
208 | reg_write(ohci, OHCI1394_PhyControl, | |
209 | OHCI1394_PhyControl_Write(addr, old)); | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | static void ar_context_run(struct ar_context *ctx) | |
215 | { | |
216 | reg_write(ctx->ohci, ctx->command_ptr, ctx->descriptor_bus | 1); | |
217 | reg_write(ctx->ohci, ctx->control_set, CONTEXT_RUN); | |
218 | flush_writes(ctx->ohci); | |
219 | } | |
220 | ||
221 | static void ar_context_tasklet(unsigned long data) | |
222 | { | |
223 | struct ar_context *ctx = (struct ar_context *)data; | |
224 | struct fw_ohci *ohci = ctx->ohci; | |
2639a6fb KH |
225 | struct fw_packet p; |
226 | u32 status, length, tcode; | |
ed568912 KH |
227 | |
228 | /* FIXME: What to do about evt_* errors? */ | |
229 | length = le16_to_cpu(ctx->descriptor.req_count) - | |
230 | le16_to_cpu(ctx->descriptor.res_count) - 4; | |
231 | status = le32_to_cpu(ctx->buffer[length / 4]); | |
ed568912 | 232 | |
2639a6fb KH |
233 | p.ack = ((status >> 16) & 0x1f) - 16; |
234 | p.speed = (status >> 21) & 0x7; | |
235 | p.timestamp = status & 0xffff; | |
236 | p.generation = ohci->request_generation; | |
237 | ||
238 | p.header[0] = le32_to_cpu(ctx->buffer[0]); | |
239 | p.header[1] = le32_to_cpu(ctx->buffer[1]); | |
240 | p.header[2] = le32_to_cpu(ctx->buffer[2]); | |
241 | ||
242 | tcode = (p.header[0] >> 4) & 0x0f; | |
243 | switch (tcode) { | |
244 | case TCODE_WRITE_QUADLET_REQUEST: | |
245 | case TCODE_READ_QUADLET_RESPONSE: | |
246 | p.header[3] = ctx->buffer[3]; | |
247 | p.header_length = 16; | |
248 | break; | |
249 | ||
250 | case TCODE_WRITE_BLOCK_REQUEST: | |
251 | case TCODE_READ_BLOCK_REQUEST : | |
252 | case TCODE_READ_BLOCK_RESPONSE: | |
253 | case TCODE_LOCK_REQUEST: | |
254 | case TCODE_LOCK_RESPONSE: | |
255 | p.header[3] = le32_to_cpu(ctx->buffer[3]); | |
256 | p.header_length = 16; | |
257 | break; | |
258 | ||
259 | case TCODE_WRITE_RESPONSE: | |
260 | case TCODE_READ_QUADLET_REQUEST: | |
261 | p.header_length = 12; | |
262 | break; | |
263 | } | |
ed568912 | 264 | |
2639a6fb KH |
265 | p.payload = (void *) ctx->buffer + p.header_length; |
266 | p.payload_length = length - p.header_length; | |
ed568912 KH |
267 | |
268 | /* The OHCI bus reset handler synthesizes a phy packet with | |
269 | * the new generation number when a bus reset happens (see | |
270 | * section 8.4.2.3). This helps us determine when a request | |
271 | * was received and make sure we send the response in the same | |
272 | * generation. We only need this for requests; for responses | |
273 | * we use the unique tlabel for finding the matching | |
274 | * request. */ | |
275 | ||
2639a6fb | 276 | if (p.ack + 16 == 0x09) |
ed568912 KH |
277 | ohci->request_generation = (ctx->buffer[2] >> 16) & 0xff; |
278 | else if (ctx == &ohci->ar_request_ctx) | |
2639a6fb | 279 | fw_core_handle_request(&ohci->card, &p); |
ed568912 | 280 | else |
2639a6fb | 281 | fw_core_handle_response(&ohci->card, &p); |
ed568912 KH |
282 | |
283 | ctx->descriptor.data_address = cpu_to_le32(ctx->buffer_bus); | |
284 | ctx->descriptor.req_count = cpu_to_le16(sizeof ctx->buffer); | |
285 | ctx->descriptor.res_count = cpu_to_le16(sizeof ctx->buffer); | |
286 | ||
287 | dma_sync_single_for_device(ohci->card.device, ctx->descriptor_bus, | |
288 | sizeof ctx->descriptor_bus, DMA_TO_DEVICE); | |
289 | ||
290 | /* FIXME: We stop and restart the ar context here, what if we | |
291 | * stop while a receive is in progress? Maybe we could just | |
292 | * loop the context back to itself and use it in buffer fill | |
293 | * mode as intended... */ | |
294 | ||
295 | reg_write(ctx->ohci, ctx->control_clear, CONTEXT_RUN); | |
296 | ar_context_run(ctx); | |
297 | } | |
298 | ||
299 | static int | |
300 | ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 control_set) | |
301 | { | |
302 | ctx->descriptor_bus = | |
303 | dma_map_single(ohci->card.device, &ctx->descriptor, | |
304 | sizeof ctx->descriptor, DMA_TO_DEVICE); | |
305 | if (ctx->descriptor_bus == 0) | |
306 | return -ENOMEM; | |
307 | ||
308 | if (ctx->descriptor_bus & 0xf) | |
fcf7770a AM |
309 | fw_notify("descriptor not 16-byte aligned: 0x%08lx\n", |
310 | (unsigned long)ctx->descriptor_bus); | |
ed568912 KH |
311 | |
312 | ctx->buffer_bus = | |
313 | dma_map_single(ohci->card.device, ctx->buffer, | |
314 | sizeof ctx->buffer, DMA_FROM_DEVICE); | |
315 | ||
316 | if (ctx->buffer_bus == 0) { | |
317 | dma_unmap_single(ohci->card.device, ctx->descriptor_bus, | |
318 | sizeof ctx->descriptor, DMA_TO_DEVICE); | |
319 | return -ENOMEM; | |
320 | } | |
321 | ||
322 | memset(&ctx->descriptor, 0, sizeof ctx->descriptor); | |
323 | ctx->descriptor.control = cpu_to_le16(descriptor_input_more | | |
324 | descriptor_status | | |
325 | descriptor_branch_always); | |
326 | ctx->descriptor.req_count = cpu_to_le16(sizeof ctx->buffer); | |
327 | ctx->descriptor.data_address = cpu_to_le32(ctx->buffer_bus); | |
328 | ctx->descriptor.res_count = cpu_to_le16(sizeof ctx->buffer); | |
329 | ||
330 | ctx->control_set = control_set; | |
331 | ctx->control_clear = control_set + 4; | |
332 | ctx->command_ptr = control_set + 12; | |
333 | ctx->ohci = ohci; | |
334 | ||
335 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); | |
336 | ||
337 | ar_context_run(ctx); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | static void | |
343 | do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list) | |
344 | { | |
345 | struct fw_packet *p, *next; | |
346 | ||
347 | list_for_each_entry_safe(p, next, list, link) | |
2639a6fb | 348 | p->callback(p, &ohci->card, p->ack); |
ed568912 KH |
349 | } |
350 | ||
351 | static void | |
352 | complete_transmission(struct fw_packet *packet, | |
2639a6fb | 353 | int ack, struct list_head *list) |
ed568912 KH |
354 | { |
355 | list_move_tail(&packet->link, list); | |
2639a6fb | 356 | packet->ack = ack; |
ed568912 KH |
357 | } |
358 | ||
359 | /* This function prepares the first packet in the context queue for | |
360 | * transmission. Must always be called with the ochi->lock held to | |
361 | * ensure proper generation handling and locking around packet queue | |
362 | * manipulation. */ | |
363 | static void | |
364 | at_context_setup_packet(struct at_context *ctx, struct list_head *list) | |
365 | { | |
366 | struct fw_packet *packet; | |
367 | struct fw_ohci *ohci = ctx->ohci; | |
368 | int z, tcode; | |
369 | ||
370 | packet = fw_packet(ctx->list.next); | |
371 | ||
372 | memset(&ctx->d, 0, sizeof ctx->d); | |
373 | if (packet->payload_length > 0) { | |
374 | packet->payload_bus = dma_map_single(ohci->card.device, | |
375 | packet->payload, | |
376 | packet->payload_length, | |
377 | DMA_TO_DEVICE); | |
378 | if (packet->payload_bus == 0) { | |
379 | complete_transmission(packet, -ENOMEM, list); | |
380 | return; | |
381 | } | |
382 | ||
383 | ctx->d.more.control = | |
384 | cpu_to_le16(descriptor_output_more | | |
385 | descriptor_key_immediate); | |
386 | ctx->d.more.req_count = cpu_to_le16(packet->header_length); | |
387 | ctx->d.more.res_count = cpu_to_le16(packet->timestamp); | |
388 | ctx->d.last.control = | |
389 | cpu_to_le16(descriptor_output_last | | |
390 | descriptor_irq_always | | |
391 | descriptor_branch_always); | |
392 | ctx->d.last.req_count = cpu_to_le16(packet->payload_length); | |
393 | ctx->d.last.data_address = cpu_to_le32(packet->payload_bus); | |
394 | z = 3; | |
395 | } else { | |
396 | ctx->d.more.control = | |
397 | cpu_to_le16(descriptor_output_last | | |
398 | descriptor_key_immediate | | |
399 | descriptor_irq_always | | |
400 | descriptor_branch_always); | |
401 | ctx->d.more.req_count = cpu_to_le16(packet->header_length); | |
402 | ctx->d.more.res_count = cpu_to_le16(packet->timestamp); | |
403 | z = 2; | |
404 | } | |
405 | ||
406 | /* The DMA format for asyncronous link packets is different | |
407 | * from the IEEE1394 layout, so shift the fields around | |
408 | * accordingly. If header_length is 8, it's a PHY packet, to | |
409 | * which we need to prepend an extra quadlet. */ | |
410 | if (packet->header_length > 8) { | |
411 | ctx->d.header[0] = cpu_to_le32((packet->header[0] & 0xffff) | | |
412 | (packet->speed << 16)); | |
413 | ctx->d.header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
414 | (packet->header[0] & 0xffff0000)); | |
415 | ctx->d.header[2] = cpu_to_le32(packet->header[2]); | |
416 | ||
417 | tcode = (packet->header[0] >> 4) & 0x0f; | |
418 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
419 | ctx->d.header[3] = cpu_to_le32(packet->header[3]); | |
420 | else | |
421 | ctx->d.header[3] = packet->header[3]; | |
422 | } else { | |
423 | ctx->d.header[0] = | |
424 | cpu_to_le32((OHCI1394_phy_tcode << 4) | | |
425 | (packet->speed << 16)); | |
426 | ctx->d.header[1] = cpu_to_le32(packet->header[0]); | |
427 | ctx->d.header[2] = cpu_to_le32(packet->header[1]); | |
428 | ctx->d.more.req_count = cpu_to_le16(12); | |
429 | } | |
430 | ||
431 | /* FIXME: Document how the locking works. */ | |
432 | if (ohci->generation == packet->generation) { | |
433 | reg_write(ctx->ohci, ctx->command_ptr, | |
434 | ctx->descriptor_bus | z); | |
435 | reg_write(ctx->ohci, ctx->control_set, | |
436 | CONTEXT_RUN | CONTEXT_WAKE); | |
437 | } else { | |
438 | /* We dont return error codes from this function; all | |
439 | * transmission errors are reported through the | |
440 | * callback. */ | |
441 | complete_transmission(packet, -ESTALE, list); | |
442 | } | |
443 | } | |
444 | ||
445 | static void at_context_stop(struct at_context *ctx) | |
446 | { | |
447 | u32 reg; | |
448 | ||
449 | reg_write(ctx->ohci, ctx->control_clear, CONTEXT_RUN); | |
450 | ||
451 | reg = reg_read(ctx->ohci, ctx->control_set); | |
452 | if (reg & CONTEXT_ACTIVE) | |
453 | fw_notify("Tried to stop context, but it is still active " | |
454 | "(0x%08x).\n", reg); | |
455 | } | |
456 | ||
457 | static void at_context_tasklet(unsigned long data) | |
458 | { | |
459 | struct at_context *ctx = (struct at_context *)data; | |
460 | struct fw_ohci *ohci = ctx->ohci; | |
461 | struct fw_packet *packet; | |
462 | LIST_HEAD(list); | |
463 | unsigned long flags; | |
464 | int evt; | |
465 | ||
466 | spin_lock_irqsave(&ohci->lock, flags); | |
467 | ||
468 | packet = fw_packet(ctx->list.next); | |
469 | ||
470 | at_context_stop(ctx); | |
471 | ||
472 | if (packet->payload_length > 0) { | |
473 | dma_unmap_single(ohci->card.device, packet->payload_bus, | |
474 | packet->payload_length, DMA_TO_DEVICE); | |
475 | evt = le16_to_cpu(ctx->d.last.transfer_status) & 0x1f; | |
476 | packet->timestamp = le16_to_cpu(ctx->d.last.res_count); | |
477 | } | |
478 | else { | |
479 | evt = le16_to_cpu(ctx->d.more.transfer_status) & 0x1f; | |
480 | packet->timestamp = le16_to_cpu(ctx->d.more.res_count); | |
481 | } | |
482 | ||
483 | if (evt < 16) { | |
484 | switch (evt) { | |
485 | case OHCI1394_evt_timeout: | |
486 | /* Async response transmit timed out. */ | |
487 | complete_transmission(packet, -ETIMEDOUT, &list); | |
488 | break; | |
489 | ||
490 | case OHCI1394_evt_flushed: | |
491 | /* The packet was flushed should give same | |
492 | * error as when we try to use a stale | |
493 | * generation count. */ | |
494 | complete_transmission(packet, -ESTALE, &list); | |
495 | break; | |
496 | ||
497 | case OHCI1394_evt_missing_ack: | |
498 | /* This would be a higher level software | |
499 | * error, it is using a valid (current) | |
500 | * generation count, but the node is not on | |
501 | * the bus. */ | |
502 | complete_transmission(packet, -ENODEV, &list); | |
503 | break; | |
504 | ||
505 | default: | |
506 | complete_transmission(packet, -EIO, &list); | |
507 | break; | |
508 | } | |
509 | } else | |
510 | complete_transmission(packet, evt - 16, &list); | |
511 | ||
512 | /* If more packets are queued, set up the next one. */ | |
513 | if (!list_empty(&ctx->list)) | |
514 | at_context_setup_packet(ctx, &list); | |
515 | ||
516 | spin_unlock_irqrestore(&ohci->lock, flags); | |
517 | ||
518 | do_packet_callbacks(ohci, &list); | |
519 | } | |
520 | ||
521 | static int | |
522 | at_context_init(struct at_context *ctx, struct fw_ohci *ohci, u32 control_set) | |
523 | { | |
524 | INIT_LIST_HEAD(&ctx->list); | |
525 | ||
526 | ctx->descriptor_bus = | |
527 | dma_map_single(ohci->card.device, &ctx->d, | |
528 | sizeof ctx->d, DMA_TO_DEVICE); | |
529 | if (ctx->descriptor_bus == 0) | |
530 | return -ENOMEM; | |
531 | ||
532 | ctx->control_set = control_set; | |
533 | ctx->control_clear = control_set + 4; | |
534 | ctx->command_ptr = control_set + 12; | |
535 | ctx->ohci = ohci; | |
536 | ||
537 | tasklet_init(&ctx->tasklet, at_context_tasklet, (unsigned long)ctx); | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
e636fe25 KH |
542 | #define header_get_destination(q) (((q) >> 16) & 0xffff) |
543 | ||
ed568912 KH |
544 | static void |
545 | at_context_transmit(struct at_context *ctx, struct fw_packet *packet) | |
546 | { | |
547 | LIST_HEAD(list); | |
548 | unsigned long flags; | |
e636fe25 | 549 | int local; |
ed568912 KH |
550 | |
551 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
552 | ||
e636fe25 KH |
553 | if (header_get_destination(packet->header[0]) == ctx->ohci->node_id && |
554 | ctx->ohci->generation == packet->generation) { | |
555 | local = 1; | |
556 | } else { | |
557 | list_add_tail(&packet->link, &ctx->list); | |
558 | if (ctx->list.next == &packet->link) | |
559 | at_context_setup_packet(ctx, &list); | |
560 | local = 0; | |
561 | } | |
ed568912 KH |
562 | |
563 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); | |
564 | ||
565 | do_packet_callbacks(ctx->ohci, &list); | |
e636fe25 KH |
566 | |
567 | if (local) { | |
568 | packet->ack = ACK_PENDING; | |
569 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
570 | if (ctx == &ctx->ohci->at_request_ctx) | |
571 | fw_core_handle_request(&ctx->ohci->card, packet); | |
572 | else | |
573 | fw_core_handle_response(&ctx->ohci->card, packet); | |
574 | } | |
ed568912 KH |
575 | } |
576 | ||
577 | static void bus_reset_tasklet(unsigned long data) | |
578 | { | |
579 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 580 | int self_id_count, i, j, reg; |
ed568912 KH |
581 | int generation, new_generation; |
582 | unsigned long flags; | |
583 | ||
584 | reg = reg_read(ohci, OHCI1394_NodeID); | |
585 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
586 | fw_error("node ID not valid, new bus reset in progress\n"); | |
587 | return; | |
588 | } | |
e636fe25 | 589 | ohci->node_id = reg & 0xffff; |
ed568912 KH |
590 | |
591 | /* The count in the SelfIDCount register is the number of | |
592 | * bytes in the self ID receive buffer. Since we also receive | |
593 | * the inverted quadlets and a header quadlet, we shift one | |
594 | * bit extra to get the actual number of self IDs. */ | |
595 | ||
596 | self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff; | |
597 | generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; | |
598 | ||
599 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
600 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) | |
601 | fw_error("inconsistent self IDs\n"); | |
602 | ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]); | |
603 | } | |
604 | ||
605 | /* Check the consistency of the self IDs we just read. The | |
606 | * problem we face is that a new bus reset can start while we | |
607 | * read out the self IDs from the DMA buffer. If this happens, | |
608 | * the DMA buffer will be overwritten with new self IDs and we | |
609 | * will read out inconsistent data. The OHCI specification | |
610 | * (section 11.2) recommends a technique similar to | |
611 | * linux/seqlock.h, where we remember the generation of the | |
612 | * self IDs in the buffer before reading them out and compare | |
613 | * it to the current generation after reading them out. If | |
614 | * the two generations match we know we have a consistent set | |
615 | * of self IDs. */ | |
616 | ||
617 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
618 | if (new_generation != generation) { | |
619 | fw_notify("recursive bus reset detected, " | |
620 | "discarding self ids\n"); | |
621 | return; | |
622 | } | |
623 | ||
624 | /* FIXME: Document how the locking works. */ | |
625 | spin_lock_irqsave(&ohci->lock, flags); | |
626 | ||
627 | ohci->generation = generation; | |
628 | at_context_stop(&ohci->at_request_ctx); | |
629 | at_context_stop(&ohci->at_response_ctx); | |
630 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); | |
631 | ||
632 | /* This next bit is unrelated to the AT context stuff but we | |
633 | * have to do it under the spinlock also. If a new config rom | |
634 | * was set up before this reset, the old one is now no longer | |
635 | * in use and we can free it. Update the config rom pointers | |
636 | * to point to the current config rom and clear the | |
637 | * next_config_rom pointer so a new udpate can take place. */ | |
638 | ||
639 | if (ohci->next_config_rom != NULL) { | |
640 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
641 | ohci->config_rom, ohci->config_rom_bus); | |
642 | ohci->config_rom = ohci->next_config_rom; | |
643 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
644 | ohci->next_config_rom = NULL; | |
645 | ||
646 | /* Restore config_rom image and manually update | |
647 | * config_rom registers. Writing the header quadlet | |
648 | * will indicate that the config rom is ready, so we | |
649 | * do that last. */ | |
650 | reg_write(ohci, OHCI1394_BusOptions, | |
651 | be32_to_cpu(ohci->config_rom[2])); | |
652 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
653 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
654 | } | |
655 | ||
656 | spin_unlock_irqrestore(&ohci->lock, flags); | |
657 | ||
e636fe25 | 658 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
659 | self_id_count, ohci->self_id_buffer); |
660 | } | |
661 | ||
662 | static irqreturn_t irq_handler(int irq, void *data) | |
663 | { | |
664 | struct fw_ohci *ohci = data; | |
665 | u32 event, iso_event; | |
666 | int i; | |
667 | ||
668 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
669 | ||
670 | if (!event) | |
671 | return IRQ_NONE; | |
672 | ||
673 | reg_write(ohci, OHCI1394_IntEventClear, event); | |
674 | ||
675 | if (event & OHCI1394_selfIDComplete) | |
676 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
677 | ||
678 | if (event & OHCI1394_RQPkt) | |
679 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
680 | ||
681 | if (event & OHCI1394_RSPkt) | |
682 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
683 | ||
684 | if (event & OHCI1394_reqTxComplete) | |
685 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
686 | ||
687 | if (event & OHCI1394_respTxComplete) | |
688 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
689 | ||
690 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet); | |
691 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); | |
692 | ||
693 | while (iso_event) { | |
694 | i = ffs(iso_event) - 1; | |
695 | tasklet_schedule(&ohci->ir_context_list[i].tasklet); | |
696 | iso_event &= ~(1 << i); | |
697 | } | |
698 | ||
699 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet); | |
700 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); | |
701 | ||
702 | while (iso_event) { | |
703 | i = ffs(iso_event) - 1; | |
704 | tasklet_schedule(&ohci->it_context_list[i].tasklet); | |
705 | iso_event &= ~(1 << i); | |
706 | } | |
707 | ||
708 | return IRQ_HANDLED; | |
709 | } | |
710 | ||
711 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) | |
712 | { | |
713 | struct fw_ohci *ohci = fw_ohci(card); | |
714 | struct pci_dev *dev = to_pci_dev(card->device); | |
715 | ||
716 | /* When the link is not yet enabled, the atomic config rom | |
717 | * update mechanism described below in ohci_set_config_rom() | |
718 | * is not active. We have to update ConfigRomHeader and | |
719 | * BusOptions manually, and the write to ConfigROMmap takes | |
720 | * effect immediately. We tie this to the enabling of the | |
721 | * link, so we have a valid config rom before enabling - the | |
722 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
723 | * values before enabling. | |
724 | * | |
725 | * However, when the ConfigROMmap is written, some controllers | |
726 | * always read back quadlets 0 and 2 from the config rom to | |
727 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
728 | * They shouldn't do that in this initial case where the link | |
729 | * isn't enabled. This means we have to use the same | |
730 | * workaround here, setting the bus header to 0 and then write | |
731 | * the right values in the bus reset tasklet. | |
732 | */ | |
733 | ||
734 | ohci->next_config_rom = | |
735 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
736 | &ohci->next_config_rom_bus, GFP_KERNEL); | |
737 | if (ohci->next_config_rom == NULL) | |
738 | return -ENOMEM; | |
739 | ||
740 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
741 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
742 | ||
743 | ohci->next_header = config_rom[0]; | |
744 | ohci->next_config_rom[0] = 0; | |
745 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
746 | reg_write(ohci, OHCI1394_BusOptions, config_rom[2]); | |
747 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); | |
748 | ||
749 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
750 | ||
751 | if (request_irq(dev->irq, irq_handler, | |
752 | SA_SHIRQ, ohci_driver_name, ohci)) { | |
753 | fw_error("Failed to allocate shared interrupt %d.\n", | |
754 | dev->irq); | |
755 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
756 | ohci->config_rom, ohci->config_rom_bus); | |
757 | return -EIO; | |
758 | } | |
759 | ||
760 | reg_write(ohci, OHCI1394_HCControlSet, | |
761 | OHCI1394_HCControl_linkEnable | | |
762 | OHCI1394_HCControl_BIBimageValid); | |
763 | flush_writes(ohci); | |
764 | ||
765 | /* We are ready to go, initiate bus reset to finish the | |
766 | * initialization. */ | |
767 | ||
768 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
773 | static int | |
774 | ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) | |
775 | { | |
776 | struct fw_ohci *ohci; | |
777 | unsigned long flags; | |
778 | int retval = 0; | |
779 | __be32 *next_config_rom; | |
780 | dma_addr_t next_config_rom_bus; | |
781 | ||
782 | ohci = fw_ohci(card); | |
783 | ||
784 | /* When the OHCI controller is enabled, the config rom update | |
785 | * mechanism is a bit tricky, but easy enough to use. See | |
786 | * section 5.5.6 in the OHCI specification. | |
787 | * | |
788 | * The OHCI controller caches the new config rom address in a | |
789 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
790 | * for the changes to take place. When the bus reset is | |
791 | * detected, the controller loads the new values for the | |
792 | * ConfigRomHeader and BusOptions registers from the specified | |
793 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
794 | * shadow register. All automatically and atomically. | |
795 | * | |
796 | * Now, there's a twist to this story. The automatic load of | |
797 | * ConfigRomHeader and BusOptions doesn't honor the | |
798 | * noByteSwapData bit, so with a be32 config rom, the | |
799 | * controller will load be32 values in to these registers | |
800 | * during the atomic update, even on litte endian | |
801 | * architectures. The workaround we use is to put a 0 in the | |
802 | * header quadlet; 0 is endian agnostic and means that the | |
803 | * config rom isn't ready yet. In the bus reset tasklet we | |
804 | * then set up the real values for the two registers. | |
805 | * | |
806 | * We use ohci->lock to avoid racing with the code that sets | |
807 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
808 | */ | |
809 | ||
810 | next_config_rom = | |
811 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
812 | &next_config_rom_bus, GFP_KERNEL); | |
813 | if (next_config_rom == NULL) | |
814 | return -ENOMEM; | |
815 | ||
816 | spin_lock_irqsave(&ohci->lock, flags); | |
817 | ||
818 | if (ohci->next_config_rom == NULL) { | |
819 | ohci->next_config_rom = next_config_rom; | |
820 | ohci->next_config_rom_bus = next_config_rom_bus; | |
821 | ||
822 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
823 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
824 | length * 4); | |
825 | ||
826 | ohci->next_header = config_rom[0]; | |
827 | ohci->next_config_rom[0] = 0; | |
828 | ||
829 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
830 | ohci->next_config_rom_bus); | |
831 | } else { | |
832 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
833 | next_config_rom, next_config_rom_bus); | |
834 | retval = -EBUSY; | |
835 | } | |
836 | ||
837 | spin_unlock_irqrestore(&ohci->lock, flags); | |
838 | ||
839 | /* Now initiate a bus reset to have the changes take | |
840 | * effect. We clean up the old config rom memory and DMA | |
841 | * mappings in the bus reset tasklet, since the OHCI | |
842 | * controller could need to access it before the bus reset | |
843 | * takes effect. */ | |
844 | if (retval == 0) | |
845 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
846 | ||
847 | return retval; | |
848 | } | |
849 | ||
850 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
851 | { | |
852 | struct fw_ohci *ohci = fw_ohci(card); | |
853 | ||
854 | at_context_transmit(&ohci->at_request_ctx, packet); | |
855 | } | |
856 | ||
857 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
858 | { | |
859 | struct fw_ohci *ohci = fw_ohci(card); | |
860 | ||
861 | at_context_transmit(&ohci->at_response_ctx, packet); | |
862 | } | |
863 | ||
864 | static int | |
865 | ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) | |
866 | { | |
867 | struct fw_ohci *ohci = fw_ohci(card); | |
868 | unsigned long flags; | |
907293d7 | 869 | int n, retval = 0; |
ed568912 | 870 | |
907293d7 SR |
871 | /* FIXME: Make sure this bitmask is cleared when we clear the busReset |
872 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. */ | |
ed568912 KH |
873 | |
874 | spin_lock_irqsave(&ohci->lock, flags); | |
875 | ||
876 | if (ohci->generation != generation) { | |
877 | retval = -ESTALE; | |
878 | goto out; | |
879 | } | |
880 | ||
907293d7 SR |
881 | /* NOTE, if the node ID contains a non-local bus ID, physical DMA is |
882 | * enabled for _all_ nodes on remote buses. */ | |
883 | ||
884 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
885 | if (n < 32) | |
886 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
887 | else | |
888 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
889 | ||
ed568912 | 890 | flush_writes(ohci); |
ed568912 | 891 | out: |
6cad95fe | 892 | spin_unlock_irqrestore(&ohci->lock, flags); |
ed568912 KH |
893 | return retval; |
894 | } | |
895 | ||
896 | static void ir_context_tasklet(unsigned long data) | |
897 | { | |
898 | struct iso_context *ctx = (struct iso_context *)data; | |
899 | ||
900 | (void)ctx; | |
901 | } | |
902 | ||
903 | #define ISO_BUFFER_SIZE (64 * 1024) | |
904 | ||
905 | static void flush_iso_context(struct iso_context *ctx) | |
906 | { | |
907 | struct fw_ohci *ohci = fw_ohci(ctx->base.card); | |
908 | struct descriptor *d, *last; | |
909 | u32 address; | |
910 | int z; | |
911 | ||
912 | dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus, | |
913 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
914 | ||
915 | d = ctx->tail_descriptor; | |
916 | last = ctx->tail_descriptor_last; | |
917 | ||
918 | while (last->branch_address != 0 && last->transfer_status != 0) { | |
919 | address = le32_to_cpu(last->branch_address); | |
920 | z = address & 0xf; | |
921 | d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d; | |
922 | ||
923 | if (z == 2) | |
924 | last = d; | |
925 | else | |
926 | last = d + z - 1; | |
927 | ||
928 | if (le16_to_cpu(last->control) & descriptor_irq_always) | |
929 | ctx->base.callback(&ctx->base, | |
930 | 0, le16_to_cpu(last->res_count), | |
931 | ctx->base.callback_data); | |
932 | } | |
933 | ||
934 | ctx->tail_descriptor = d; | |
935 | ctx->tail_descriptor_last = last; | |
936 | } | |
937 | ||
938 | static void it_context_tasklet(unsigned long data) | |
939 | { | |
940 | struct iso_context *ctx = (struct iso_context *)data; | |
941 | ||
942 | flush_iso_context(ctx); | |
943 | } | |
944 | ||
945 | static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, | |
946 | int type) | |
947 | { | |
948 | struct fw_ohci *ohci = fw_ohci(card); | |
949 | struct iso_context *ctx, *list; | |
950 | void (*tasklet) (unsigned long data); | |
951 | u32 *mask; | |
952 | unsigned long flags; | |
953 | int index; | |
954 | ||
955 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
956 | mask = &ohci->it_context_mask; | |
957 | list = ohci->it_context_list; | |
958 | tasklet = it_context_tasklet; | |
959 | } else { | |
960 | mask = &ohci->ir_context_mask; | |
961 | list = ohci->ir_context_list; | |
962 | tasklet = ir_context_tasklet; | |
963 | } | |
964 | ||
965 | spin_lock_irqsave(&ohci->lock, flags); | |
966 | index = ffs(*mask) - 1; | |
967 | if (index >= 0) | |
968 | *mask &= ~(1 << index); | |
969 | spin_unlock_irqrestore(&ohci->lock, flags); | |
970 | ||
971 | if (index < 0) | |
972 | return ERR_PTR(-EBUSY); | |
973 | ||
974 | ctx = &list[index]; | |
975 | memset(ctx, 0, sizeof *ctx); | |
976 | tasklet_init(&ctx->tasklet, tasklet, (unsigned long)ctx); | |
977 | ||
978 | ctx->buffer = kmalloc(ISO_BUFFER_SIZE, GFP_KERNEL); | |
979 | if (ctx->buffer == NULL) { | |
980 | spin_lock_irqsave(&ohci->lock, flags); | |
981 | *mask |= 1 << index; | |
982 | spin_unlock_irqrestore(&ohci->lock, flags); | |
983 | return ERR_PTR(-ENOMEM); | |
984 | } | |
985 | ||
986 | ctx->buffer_bus = | |
987 | dma_map_single(card->device, ctx->buffer, | |
988 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
989 | ||
990 | ctx->head_descriptor = ctx->buffer; | |
991 | ctx->prev_descriptor = ctx->buffer; | |
992 | ctx->tail_descriptor = ctx->buffer; | |
993 | ctx->tail_descriptor_last = ctx->buffer; | |
994 | ||
995 | /* We put a dummy descriptor in the buffer that has a NULL | |
996 | * branch address and looks like it's been sent. That way we | |
997 | * have a descriptor to append DMA programs to. Also, the | |
998 | * ring buffer invariant is that it always has at least one | |
999 | * element so that head == tail means buffer full. */ | |
1000 | ||
1001 | memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor); | |
5e20c282 SR |
1002 | ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last); |
1003 | ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011); | |
ed568912 KH |
1004 | ctx->head_descriptor++; |
1005 | ||
1006 | return &ctx->base; | |
1007 | } | |
1008 | ||
1009 | static int ohci_send_iso(struct fw_iso_context *base, s32 cycle) | |
1010 | { | |
1011 | struct iso_context *ctx = (struct iso_context *)base; | |
1012 | struct fw_ohci *ohci = fw_ohci(ctx->base.card); | |
1013 | u32 cycle_match = 0; | |
1014 | int index; | |
1015 | ||
1016 | index = ctx - ohci->it_context_list; | |
1017 | if (cycle > 0) | |
1018 | cycle_match = CONTEXT_CYCLE_MATCH_ENABLE | | |
1019 | (cycle & 0x7fff) << 16; | |
1020 | ||
1021 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
1022 | reg_write(ohci, OHCI1394_IsoXmitCommandPtr(index), | |
1023 | le32_to_cpu(ctx->tail_descriptor_last->branch_address)); | |
1024 | reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0); | |
1025 | reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index), | |
1026 | CONTEXT_RUN | cycle_match); | |
1027 | flush_writes(ohci); | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | ||
1032 | static void ohci_free_iso_context(struct fw_iso_context *base) | |
1033 | { | |
1034 | struct fw_ohci *ohci = fw_ohci(base->card); | |
1035 | struct iso_context *ctx = (struct iso_context *)base; | |
1036 | unsigned long flags; | |
1037 | int index; | |
1038 | ||
1039 | flush_iso_context(ctx); | |
1040 | ||
1041 | spin_lock_irqsave(&ohci->lock, flags); | |
1042 | ||
1043 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1044 | index = ctx - ohci->it_context_list; | |
1045 | reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0); | |
1046 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
1047 | ohci->it_context_mask |= 1 << index; | |
1048 | } else { | |
1049 | index = ctx - ohci->ir_context_list; | |
1050 | reg_write(ohci, OHCI1394_IsoRcvContextControlClear(index), ~0); | |
1051 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
1052 | ohci->ir_context_mask |= 1 << index; | |
1053 | } | |
1054 | flush_writes(ohci); | |
1055 | ||
1056 | dma_unmap_single(ohci->card.device, ctx->buffer_bus, | |
1057 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
1058 | ||
1059 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1060 | } | |
1061 | ||
1062 | static int | |
1063 | ohci_queue_iso(struct fw_iso_context *base, | |
1064 | struct fw_iso_packet *packet, void *payload) | |
1065 | { | |
1066 | struct iso_context *ctx = (struct iso_context *)base; | |
1067 | struct fw_ohci *ohci = fw_ohci(ctx->base.card); | |
1068 | struct descriptor *d, *end, *last, *tail, *pd; | |
1069 | struct fw_iso_packet *p; | |
1070 | __le32 *header; | |
1071 | dma_addr_t d_bus; | |
1072 | u32 z, header_z, payload_z, irq; | |
1073 | u32 payload_index, payload_end_index, next_page_index; | |
1074 | int index, page, end_page, i, length, offset; | |
1075 | ||
1076 | /* FIXME: Cycle lost behavior should be configurable: lose | |
1077 | * packet, retransmit or terminate.. */ | |
1078 | ||
1079 | p = packet; | |
1080 | payload_index = payload - ctx->base.buffer; | |
1081 | d = ctx->head_descriptor; | |
1082 | tail = ctx->tail_descriptor; | |
1083 | end = ctx->buffer + ISO_BUFFER_SIZE / sizeof(struct descriptor); | |
1084 | ||
1085 | if (p->skip) | |
1086 | z = 1; | |
1087 | else | |
1088 | z = 2; | |
1089 | if (p->header_length > 0) | |
1090 | z++; | |
1091 | ||
1092 | /* Determine the first page the payload isn't contained in. */ | |
1093 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
1094 | if (p->payload_length > 0) | |
1095 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
1096 | else | |
1097 | payload_z = 0; | |
1098 | ||
1099 | z += payload_z; | |
1100 | ||
1101 | /* Get header size in number of descriptors. */ | |
1102 | header_z = DIV_ROUND_UP(p->header_length, sizeof *d); | |
1103 | ||
1104 | if (d + z + header_z <= tail) { | |
1105 | goto has_space; | |
1106 | } else if (d > tail && d + z + header_z <= end) { | |
1107 | goto has_space; | |
1108 | } else if (d > tail && ctx->buffer + z + header_z <= tail) { | |
1109 | d = ctx->buffer; | |
1110 | goto has_space; | |
1111 | } | |
1112 | ||
1113 | /* No space in buffer */ | |
1114 | return -1; | |
1115 | ||
1116 | has_space: | |
1117 | memset(d, 0, (z + header_z) * sizeof *d); | |
1118 | d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d; | |
1119 | ||
1120 | if (!p->skip) { | |
1121 | d[0].control = cpu_to_le16(descriptor_key_immediate); | |
1122 | d[0].req_count = cpu_to_le16(8); | |
1123 | ||
1124 | header = (__le32 *) &d[1]; | |
1125 | header[0] = cpu_to_le32(it_header_sy(p->sy) | | |
1126 | it_header_tag(p->tag) | | |
1127 | it_header_tcode(TCODE_STREAM_DATA) | | |
1128 | it_header_channel(ctx->base.channel) | | |
1129 | it_header_speed(ctx->base.speed)); | |
1130 | header[1] = | |
1131 | cpu_to_le32(it_header_data_length(p->header_length + | |
1132 | p->payload_length)); | |
1133 | } | |
1134 | ||
1135 | if (p->header_length > 0) { | |
1136 | d[2].req_count = cpu_to_le16(p->header_length); | |
1137 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d); | |
1138 | memcpy(&d[z], p->header, p->header_length); | |
1139 | } | |
1140 | ||
1141 | pd = d + z - payload_z; | |
1142 | payload_end_index = payload_index + p->payload_length; | |
1143 | for (i = 0; i < payload_z; i++) { | |
1144 | page = payload_index >> PAGE_SHIFT; | |
1145 | offset = payload_index & ~PAGE_MASK; | |
1146 | next_page_index = (page + 1) << PAGE_SHIFT; | |
1147 | length = | |
1148 | min(next_page_index, payload_end_index) - payload_index; | |
1149 | pd[i].req_count = cpu_to_le16(length); | |
1150 | pd[i].data_address = cpu_to_le32(ctx->base.pages[page] + offset); | |
1151 | ||
1152 | payload_index += length; | |
1153 | } | |
1154 | ||
1155 | if (z == 2) | |
1156 | last = d; | |
1157 | else | |
1158 | last = d + z - 1; | |
1159 | ||
1160 | if (p->interrupt) | |
1161 | irq = descriptor_irq_always; | |
1162 | else | |
1163 | irq = descriptor_no_irq; | |
1164 | ||
1165 | last->control = cpu_to_le16(descriptor_output_last | | |
1166 | descriptor_status | | |
1167 | descriptor_branch_always | | |
1168 | irq); | |
1169 | ||
1170 | dma_sync_single_for_device(ohci->card.device, ctx->buffer_bus, | |
1171 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
1172 | ||
1173 | ctx->head_descriptor = d + z + header_z; | |
1174 | ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z); | |
1175 | ctx->prev_descriptor = last; | |
1176 | ||
1177 | index = ctx - ohci->it_context_list; | |
1178 | reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index), CONTEXT_WAKE); | |
1179 | flush_writes(ohci); | |
1180 | ||
1181 | return 0; | |
1182 | } | |
1183 | ||
21ebcd12 | 1184 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
1185 | .name = ohci_driver_name, |
1186 | .enable = ohci_enable, | |
1187 | .update_phy_reg = ohci_update_phy_reg, | |
1188 | .set_config_rom = ohci_set_config_rom, | |
1189 | .send_request = ohci_send_request, | |
1190 | .send_response = ohci_send_response, | |
1191 | .enable_phys_dma = ohci_enable_phys_dma, | |
1192 | ||
1193 | .allocate_iso_context = ohci_allocate_iso_context, | |
1194 | .free_iso_context = ohci_free_iso_context, | |
1195 | .queue_iso = ohci_queue_iso, | |
5af4e5ea | 1196 | .send_iso = ohci_send_iso, |
ed568912 KH |
1197 | }; |
1198 | ||
1199 | static int software_reset(struct fw_ohci *ohci) | |
1200 | { | |
1201 | int i; | |
1202 | ||
1203 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1204 | ||
1205 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1206 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1207 | OHCI1394_HCControl_softReset) == 0) | |
1208 | return 0; | |
1209 | msleep(1); | |
1210 | } | |
1211 | ||
1212 | return -EBUSY; | |
1213 | } | |
1214 | ||
1215 | /* ---------- pci subsystem interface ---------- */ | |
1216 | ||
1217 | enum { | |
1218 | CLEANUP_SELF_ID, | |
1219 | CLEANUP_REGISTERS, | |
1220 | CLEANUP_IOMEM, | |
1221 | CLEANUP_DISABLE, | |
1222 | CLEANUP_PUT_CARD, | |
1223 | }; | |
1224 | ||
1225 | static int cleanup(struct fw_ohci *ohci, int stage, int code) | |
1226 | { | |
1227 | struct pci_dev *dev = to_pci_dev(ohci->card.device); | |
1228 | ||
1229 | switch (stage) { | |
1230 | case CLEANUP_SELF_ID: | |
1231 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
1232 | ohci->self_id_cpu, ohci->self_id_bus); | |
1233 | case CLEANUP_REGISTERS: | |
1234 | kfree(ohci->it_context_list); | |
1235 | kfree(ohci->ir_context_list); | |
1236 | pci_iounmap(dev, ohci->registers); | |
1237 | case CLEANUP_IOMEM: | |
1238 | pci_release_region(dev, 0); | |
1239 | case CLEANUP_DISABLE: | |
1240 | pci_disable_device(dev); | |
1241 | case CLEANUP_PUT_CARD: | |
1242 | fw_card_put(&ohci->card); | |
1243 | } | |
1244 | ||
1245 | return code; | |
1246 | } | |
1247 | ||
1248 | static int __devinit | |
1249 | pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |
1250 | { | |
1251 | struct fw_ohci *ohci; | |
1252 | u32 bus_options, max_receive, link_speed; | |
1253 | u64 guid; | |
1254 | int error_code; | |
1255 | size_t size; | |
1256 | ||
1257 | ohci = kzalloc(sizeof *ohci, GFP_KERNEL); | |
1258 | if (ohci == NULL) { | |
1259 | fw_error("Could not malloc fw_ohci data.\n"); | |
1260 | return -ENOMEM; | |
1261 | } | |
1262 | ||
1263 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
1264 | ||
1265 | if (pci_enable_device(dev)) { | |
1266 | fw_error("Failed to enable OHCI hardware.\n"); | |
1267 | return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV); | |
1268 | } | |
1269 | ||
1270 | pci_set_master(dev); | |
1271 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
1272 | pci_set_drvdata(dev, ohci); | |
1273 | ||
1274 | spin_lock_init(&ohci->lock); | |
1275 | ||
1276 | tasklet_init(&ohci->bus_reset_tasklet, | |
1277 | bus_reset_tasklet, (unsigned long)ohci); | |
1278 | ||
1279 | if (pci_request_region(dev, 0, ohci_driver_name)) { | |
1280 | fw_error("MMIO resource unavailable\n"); | |
1281 | return cleanup(ohci, CLEANUP_DISABLE, -EBUSY); | |
1282 | } | |
1283 | ||
1284 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
1285 | if (ohci->registers == NULL) { | |
1286 | fw_error("Failed to remap registers\n"); | |
1287 | return cleanup(ohci, CLEANUP_IOMEM, -ENXIO); | |
1288 | } | |
1289 | ||
1290 | if (software_reset(ohci)) { | |
1291 | fw_error("Failed to reset ohci card.\n"); | |
1292 | return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY); | |
1293 | } | |
1294 | ||
1295 | /* Now enable LPS, which we need in order to start accessing | |
1296 | * most of the registers. In fact, on some cards (ALI M5251), | |
1297 | * accessing registers in the SClk domain without LPS enabled | |
1298 | * will lock up the machine. Wait 50msec to make sure we have | |
1299 | * full link enabled. */ | |
1300 | reg_write(ohci, OHCI1394_HCControlSet, | |
1301 | OHCI1394_HCControl_LPS | | |
1302 | OHCI1394_HCControl_postedWriteEnable); | |
1303 | flush_writes(ohci); | |
1304 | msleep(50); | |
1305 | ||
1306 | reg_write(ohci, OHCI1394_HCControlClear, | |
1307 | OHCI1394_HCControl_noByteSwapData); | |
1308 | ||
1309 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1310 | OHCI1394_LinkControl_rcvSelfID | | |
1311 | OHCI1394_LinkControl_cycleTimerEnable | | |
1312 | OHCI1394_LinkControl_cycleMaster); | |
1313 | ||
1314 | ar_context_init(&ohci->ar_request_ctx, ohci, | |
1315 | OHCI1394_AsReqRcvContextControlSet); | |
1316 | ||
1317 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
1318 | OHCI1394_AsRspRcvContextControlSet); | |
1319 | ||
1320 | at_context_init(&ohci->at_request_ctx, ohci, | |
1321 | OHCI1394_AsReqTrContextControlSet); | |
1322 | ||
1323 | at_context_init(&ohci->at_response_ctx, ohci, | |
1324 | OHCI1394_AsRspTrContextControlSet); | |
1325 | ||
1326 | reg_write(ohci, OHCI1394_ATRetries, | |
1327 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1328 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1329 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1330 | ||
1331 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); | |
1332 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
1333 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
1334 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
1335 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
1336 | ||
1337 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
1338 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); | |
1339 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
1340 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
1341 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
1342 | ||
1343 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
1344 | fw_error("Out of memory for it/ir contexts.\n"); | |
1345 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1346 | } | |
1347 | ||
1348 | /* self-id dma buffer allocation */ | |
1349 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
1350 | SELF_ID_BUF_SIZE, | |
1351 | &ohci->self_id_bus, | |
1352 | GFP_KERNEL); | |
1353 | if (ohci->self_id_cpu == NULL) { | |
1354 | fw_error("Out of memory for self ID buffer.\n"); | |
1355 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1356 | } | |
1357 | ||
1358 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | |
1359 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); | |
1360 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1361 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1362 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1363 | OHCI1394_selfIDComplete | | |
1364 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1365 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1366 | OHCI1394_isochRx | OHCI1394_isochTx | | |
1367 | OHCI1394_masterIntEnable); | |
1368 | ||
1369 | bus_options = reg_read(ohci, OHCI1394_BusOptions); | |
1370 | max_receive = (bus_options >> 12) & 0xf; | |
1371 | link_speed = bus_options & 0x7; | |
1372 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
1373 | reg_read(ohci, OHCI1394_GUIDLo); | |
1374 | ||
1375 | error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid); | |
1376 | if (error_code < 0) | |
1377 | return cleanup(ohci, CLEANUP_SELF_ID, error_code); | |
1378 | ||
1379 | fw_notify("Added fw-ohci device %s.\n", dev->dev.bus_id); | |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | static void pci_remove(struct pci_dev *dev) | |
1385 | { | |
1386 | struct fw_ohci *ohci; | |
1387 | ||
1388 | ohci = pci_get_drvdata(dev); | |
1389 | reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_masterIntEnable); | |
1390 | fw_core_remove_card(&ohci->card); | |
1391 | ||
1392 | /* FIXME: Fail all pending packets here, now that the upper | |
1393 | * layers can't queue any more. */ | |
1394 | ||
1395 | software_reset(ohci); | |
1396 | free_irq(dev->irq, ohci); | |
1397 | cleanup(ohci, CLEANUP_SELF_ID, 0); | |
1398 | ||
1399 | fw_notify("Removed fw-ohci device.\n"); | |
1400 | } | |
1401 | ||
1402 | static struct pci_device_id pci_table[] = { | |
1403 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
1404 | { } | |
1405 | }; | |
1406 | ||
1407 | MODULE_DEVICE_TABLE(pci, pci_table); | |
1408 | ||
1409 | static struct pci_driver fw_ohci_pci_driver = { | |
1410 | .name = ohci_driver_name, | |
1411 | .id_table = pci_table, | |
1412 | .probe = pci_probe, | |
1413 | .remove = pci_remove, | |
1414 | }; | |
1415 | ||
1416 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
1417 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
1418 | MODULE_LICENSE("GPL"); | |
1419 | ||
1420 | static int __init fw_ohci_init(void) | |
1421 | { | |
1422 | return pci_register_driver(&fw_ohci_pci_driver); | |
1423 | } | |
1424 | ||
1425 | static void __exit fw_ohci_cleanup(void) | |
1426 | { | |
1427 | pci_unregister_driver(&fw_ohci_pci_driver); | |
1428 | } | |
1429 | ||
1430 | module_init(fw_ohci_init); | |
1431 | module_exit(fw_ohci_cleanup); |