Commit | Line | Data |
---|---|---|
c781c06d KH |
1 | /* |
2 | * Driver for OHCI 1394 controllers | |
ed568912 | 3 | * |
ed568912 KH |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
e524f616 | 21 | #include <linux/compiler.h> |
ed568912 | 22 | #include <linux/delay.h> |
cf3e72fd | 23 | #include <linux/dma-mapping.h> |
c26f0234 | 24 | #include <linux/gfp.h> |
a7fb60db SR |
25 | #include <linux/init.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/kernel.h> | |
faa2fb4e | 28 | #include <linux/mm.h> |
a7fb60db SR |
29 | #include <linux/module.h> |
30 | #include <linux/pci.h> | |
c26f0234 | 31 | #include <linux/spinlock.h> |
cf3e72fd | 32 | |
c26f0234 | 33 | #include <asm/page.h> |
ee71c2f9 | 34 | #include <asm/system.h> |
ed568912 | 35 | |
ea8d006b SR |
36 | #ifdef CONFIG_PPC_PMAC |
37 | #include <asm/pmac_feature.h> | |
38 | #endif | |
39 | ||
ed568912 | 40 | #include "fw-ohci.h" |
a7fb60db | 41 | #include "fw-transaction.h" |
ed568912 | 42 | |
a77754a7 KH |
43 | #define DESCRIPTOR_OUTPUT_MORE 0 |
44 | #define DESCRIPTOR_OUTPUT_LAST (1 << 12) | |
45 | #define DESCRIPTOR_INPUT_MORE (2 << 12) | |
46 | #define DESCRIPTOR_INPUT_LAST (3 << 12) | |
47 | #define DESCRIPTOR_STATUS (1 << 11) | |
48 | #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) | |
49 | #define DESCRIPTOR_PING (1 << 7) | |
50 | #define DESCRIPTOR_YY (1 << 6) | |
51 | #define DESCRIPTOR_NO_IRQ (0 << 4) | |
52 | #define DESCRIPTOR_IRQ_ERROR (1 << 4) | |
53 | #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) | |
54 | #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) | |
55 | #define DESCRIPTOR_WAIT (3 << 0) | |
ed568912 KH |
56 | |
57 | struct descriptor { | |
58 | __le16 req_count; | |
59 | __le16 control; | |
60 | __le32 data_address; | |
61 | __le32 branch_address; | |
62 | __le16 res_count; | |
63 | __le16 transfer_status; | |
64 | } __attribute__((aligned(16))); | |
65 | ||
295e3feb KH |
66 | struct db_descriptor { |
67 | __le16 first_size; | |
68 | __le16 control; | |
69 | __le16 second_req_count; | |
70 | __le16 first_req_count; | |
71 | __le32 branch_address; | |
72 | __le16 second_res_count; | |
73 | __le16 first_res_count; | |
74 | __le32 reserved0; | |
75 | __le32 first_buffer; | |
76 | __le32 second_buffer; | |
77 | __le32 reserved1; | |
78 | } __attribute__((aligned(16))); | |
79 | ||
a77754a7 KH |
80 | #define CONTROL_SET(regs) (regs) |
81 | #define CONTROL_CLEAR(regs) ((regs) + 4) | |
82 | #define COMMAND_PTR(regs) ((regs) + 12) | |
83 | #define CONTEXT_MATCH(regs) ((regs) + 16) | |
72e318e0 | 84 | |
32b46093 | 85 | struct ar_buffer { |
ed568912 | 86 | struct descriptor descriptor; |
32b46093 KH |
87 | struct ar_buffer *next; |
88 | __le32 data[0]; | |
89 | }; | |
ed568912 | 90 | |
32b46093 KH |
91 | struct ar_context { |
92 | struct fw_ohci *ohci; | |
93 | struct ar_buffer *current_buffer; | |
94 | struct ar_buffer *last_buffer; | |
95 | void *pointer; | |
72e318e0 | 96 | u32 regs; |
ed568912 KH |
97 | struct tasklet_struct tasklet; |
98 | }; | |
99 | ||
30200739 KH |
100 | struct context; |
101 | ||
102 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
103 | struct descriptor *d, | |
104 | struct descriptor *last); | |
fe5ca634 DM |
105 | |
106 | /* | |
107 | * A buffer that contains a block of DMA-able coherent memory used for | |
108 | * storing a portion of a DMA descriptor program. | |
109 | */ | |
110 | struct descriptor_buffer { | |
111 | struct list_head list; | |
112 | dma_addr_t buffer_bus; | |
113 | size_t buffer_size; | |
114 | size_t used; | |
115 | struct descriptor buffer[0]; | |
116 | }; | |
117 | ||
30200739 | 118 | struct context { |
373b2edd | 119 | struct fw_ohci *ohci; |
30200739 | 120 | u32 regs; |
fe5ca634 | 121 | int total_allocation; |
373b2edd | 122 | |
fe5ca634 DM |
123 | /* |
124 | * List of page-sized buffers for storing DMA descriptors. | |
125 | * Head of list contains buffers in use and tail of list contains | |
126 | * free buffers. | |
127 | */ | |
128 | struct list_head buffer_list; | |
129 | ||
130 | /* | |
131 | * Pointer to a buffer inside buffer_list that contains the tail | |
132 | * end of the current DMA program. | |
133 | */ | |
134 | struct descriptor_buffer *buffer_tail; | |
135 | ||
136 | /* | |
137 | * The descriptor containing the branch address of the first | |
138 | * descriptor that has not yet been filled by the device. | |
139 | */ | |
140 | struct descriptor *last; | |
141 | ||
142 | /* | |
143 | * The last descriptor in the DMA program. It contains the branch | |
144 | * address that must be updated upon appending a new descriptor. | |
145 | */ | |
146 | struct descriptor *prev; | |
30200739 KH |
147 | |
148 | descriptor_callback_t callback; | |
149 | ||
373b2edd | 150 | struct tasklet_struct tasklet; |
30200739 | 151 | }; |
30200739 | 152 | |
a77754a7 KH |
153 | #define IT_HEADER_SY(v) ((v) << 0) |
154 | #define IT_HEADER_TCODE(v) ((v) << 4) | |
155 | #define IT_HEADER_CHANNEL(v) ((v) << 8) | |
156 | #define IT_HEADER_TAG(v) ((v) << 14) | |
157 | #define IT_HEADER_SPEED(v) ((v) << 16) | |
158 | #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) | |
ed568912 KH |
159 | |
160 | struct iso_context { | |
161 | struct fw_iso_context base; | |
30200739 | 162 | struct context context; |
0642b657 | 163 | int excess_bytes; |
9b32d5f3 KH |
164 | void *header; |
165 | size_t header_length; | |
ed568912 KH |
166 | }; |
167 | ||
168 | #define CONFIG_ROM_SIZE 1024 | |
169 | ||
170 | struct fw_ohci { | |
171 | struct fw_card card; | |
172 | ||
e364cf4e | 173 | u32 version; |
ed568912 KH |
174 | __iomem char *registers; |
175 | dma_addr_t self_id_bus; | |
176 | __le32 *self_id_cpu; | |
177 | struct tasklet_struct bus_reset_tasklet; | |
e636fe25 | 178 | int node_id; |
ed568912 KH |
179 | int generation; |
180 | int request_generation; | |
d60d7f1d | 181 | u32 bus_seconds; |
11bf20ad | 182 | bool old_uninorth; |
ed568912 | 183 | |
c781c06d KH |
184 | /* |
185 | * Spinlock for accessing fw_ohci data. Never call out of | |
186 | * this driver with this lock held. | |
187 | */ | |
ed568912 KH |
188 | spinlock_t lock; |
189 | u32 self_id_buffer[512]; | |
190 | ||
191 | /* Config rom buffers */ | |
192 | __be32 *config_rom; | |
193 | dma_addr_t config_rom_bus; | |
194 | __be32 *next_config_rom; | |
195 | dma_addr_t next_config_rom_bus; | |
196 | u32 next_header; | |
197 | ||
198 | struct ar_context ar_request_ctx; | |
199 | struct ar_context ar_response_ctx; | |
f319b6a0 KH |
200 | struct context at_request_ctx; |
201 | struct context at_response_ctx; | |
ed568912 KH |
202 | |
203 | u32 it_context_mask; | |
204 | struct iso_context *it_context_list; | |
205 | u32 ir_context_mask; | |
206 | struct iso_context *ir_context_list; | |
207 | }; | |
208 | ||
95688e97 | 209 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
210 | { |
211 | return container_of(card, struct fw_ohci, card); | |
212 | } | |
213 | ||
295e3feb KH |
214 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
215 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
216 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
217 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
218 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
219 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
220 | |
221 | #define CONTEXT_RUN 0x8000 | |
222 | #define CONTEXT_WAKE 0x1000 | |
223 | #define CONTEXT_DEAD 0x0800 | |
224 | #define CONTEXT_ACTIVE 0x0400 | |
225 | ||
226 | #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 | |
227 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
228 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
229 | ||
230 | #define FW_OHCI_MAJOR 240 | |
231 | #define OHCI1394_REGISTER_SIZE 0x800 | |
232 | #define OHCI_LOOP_COUNT 500 | |
233 | #define OHCI1394_PCI_HCI_Control 0x40 | |
234 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 235 | #define OHCI_TCODE_PHY_PACKET 0x0e |
e364cf4e | 236 | #define OHCI_VERSION_1_1 0x010010 |
0edeefd9 | 237 | |
ed568912 KH |
238 | static char ohci_driver_name[] = KBUILD_MODNAME; |
239 | ||
95688e97 | 240 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
241 | { |
242 | writel(data, ohci->registers + offset); | |
243 | } | |
244 | ||
95688e97 | 245 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
246 | { |
247 | return readl(ohci->registers + offset); | |
248 | } | |
249 | ||
95688e97 | 250 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
251 | { |
252 | /* Do a dummy read to flush writes. */ | |
253 | reg_read(ohci, OHCI1394_Version); | |
254 | } | |
255 | ||
256 | static int | |
257 | ohci_update_phy_reg(struct fw_card *card, int addr, | |
258 | int clear_bits, int set_bits) | |
259 | { | |
260 | struct fw_ohci *ohci = fw_ohci(card); | |
261 | u32 val, old; | |
262 | ||
263 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
362e901c | 264 | flush_writes(ohci); |
ed568912 KH |
265 | msleep(2); |
266 | val = reg_read(ohci, OHCI1394_PhyControl); | |
267 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
268 | fw_error("failed to set phy reg bits.\n"); | |
269 | return -EBUSY; | |
270 | } | |
271 | ||
272 | old = OHCI1394_PhyControl_ReadData(val); | |
273 | old = (old & ~clear_bits) | set_bits; | |
274 | reg_write(ohci, OHCI1394_PhyControl, | |
275 | OHCI1394_PhyControl_Write(addr, old)); | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
32b46093 | 280 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 281 | { |
32b46093 KH |
282 | struct device *dev = ctx->ohci->card.device; |
283 | struct ar_buffer *ab; | |
284 | dma_addr_t ab_bus; | |
285 | size_t offset; | |
286 | ||
287 | ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC); | |
288 | if (ab == NULL) | |
289 | return -ENOMEM; | |
290 | ||
291 | ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
292 | if (dma_mapping_error(ab_bus)) { | |
293 | free_page((unsigned long) ab); | |
294 | return -ENOMEM; | |
295 | } | |
296 | ||
2d826cc5 | 297 | memset(&ab->descriptor, 0, sizeof(ab->descriptor)); |
a77754a7 KH |
298 | ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | |
299 | DESCRIPTOR_STATUS | | |
300 | DESCRIPTOR_BRANCH_ALWAYS); | |
32b46093 KH |
301 | offset = offsetof(struct ar_buffer, data); |
302 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
303 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
304 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
305 | ab->descriptor.branch_address = 0; | |
306 | ||
307 | dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
308 | ||
ec839e43 | 309 | ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1); |
32b46093 KH |
310 | ctx->last_buffer->next = ab; |
311 | ctx->last_buffer = ab; | |
312 | ||
a77754a7 | 313 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
ed568912 | 314 | flush_writes(ctx->ohci); |
32b46093 KH |
315 | |
316 | return 0; | |
ed568912 KH |
317 | } |
318 | ||
11bf20ad SR |
319 | #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) |
320 | #define cond_le32_to_cpu(v) \ | |
321 | (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v)) | |
322 | #else | |
323 | #define cond_le32_to_cpu(v) le32_to_cpu(v) | |
324 | #endif | |
325 | ||
32b46093 | 326 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 327 | { |
ed568912 | 328 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
329 | struct fw_packet p; |
330 | u32 status, length, tcode; | |
2639a6fb | 331 | |
11bf20ad SR |
332 | p.header[0] = cond_le32_to_cpu(buffer[0]); |
333 | p.header[1] = cond_le32_to_cpu(buffer[1]); | |
334 | p.header[2] = cond_le32_to_cpu(buffer[2]); | |
2639a6fb KH |
335 | |
336 | tcode = (p.header[0] >> 4) & 0x0f; | |
337 | switch (tcode) { | |
338 | case TCODE_WRITE_QUADLET_REQUEST: | |
339 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 340 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 341 | p.header_length = 16; |
32b46093 | 342 | p.payload_length = 0; |
2639a6fb KH |
343 | break; |
344 | ||
2639a6fb | 345 | case TCODE_READ_BLOCK_REQUEST : |
11bf20ad | 346 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
32b46093 KH |
347 | p.header_length = 16; |
348 | p.payload_length = 0; | |
349 | break; | |
350 | ||
351 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
352 | case TCODE_READ_BLOCK_RESPONSE: |
353 | case TCODE_LOCK_REQUEST: | |
354 | case TCODE_LOCK_RESPONSE: | |
11bf20ad | 355 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
2639a6fb | 356 | p.header_length = 16; |
32b46093 | 357 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
358 | break; |
359 | ||
360 | case TCODE_WRITE_RESPONSE: | |
361 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 362 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 363 | p.header_length = 12; |
32b46093 | 364 | p.payload_length = 0; |
2639a6fb KH |
365 | break; |
366 | } | |
ed568912 | 367 | |
32b46093 KH |
368 | p.payload = (void *) buffer + p.header_length; |
369 | ||
370 | /* FIXME: What to do about evt_* errors? */ | |
371 | length = (p.header_length + p.payload_length + 3) / 4; | |
11bf20ad | 372 | status = cond_le32_to_cpu(buffer[length]); |
32b46093 KH |
373 | |
374 | p.ack = ((status >> 16) & 0x1f) - 16; | |
375 | p.speed = (status >> 21) & 0x7; | |
376 | p.timestamp = status & 0xffff; | |
377 | p.generation = ohci->request_generation; | |
ed568912 | 378 | |
c781c06d KH |
379 | /* |
380 | * The OHCI bus reset handler synthesizes a phy packet with | |
ed568912 KH |
381 | * the new generation number when a bus reset happens (see |
382 | * section 8.4.2.3). This helps us determine when a request | |
383 | * was received and make sure we send the response in the same | |
384 | * generation. We only need this for requests; for responses | |
385 | * we use the unique tlabel for finding the matching | |
c781c06d KH |
386 | * request. |
387 | */ | |
ed568912 | 388 | |
2639a6fb | 389 | if (p.ack + 16 == 0x09) |
25df287d | 390 | ohci->request_generation = (p.header[2] >> 16) & 0xff; |
ed568912 | 391 | else if (ctx == &ohci->ar_request_ctx) |
2639a6fb | 392 | fw_core_handle_request(&ohci->card, &p); |
ed568912 | 393 | else |
2639a6fb | 394 | fw_core_handle_response(&ohci->card, &p); |
ed568912 | 395 | |
32b46093 KH |
396 | return buffer + length + 1; |
397 | } | |
ed568912 | 398 | |
32b46093 KH |
399 | static void ar_context_tasklet(unsigned long data) |
400 | { | |
401 | struct ar_context *ctx = (struct ar_context *)data; | |
402 | struct fw_ohci *ohci = ctx->ohci; | |
403 | struct ar_buffer *ab; | |
404 | struct descriptor *d; | |
405 | void *buffer, *end; | |
406 | ||
407 | ab = ctx->current_buffer; | |
408 | d = &ab->descriptor; | |
409 | ||
410 | if (d->res_count == 0) { | |
411 | size_t size, rest, offset; | |
412 | ||
c781c06d KH |
413 | /* |
414 | * This descriptor is finished and we may have a | |
32b46093 | 415 | * packet split across this and the next buffer. We |
c781c06d KH |
416 | * reuse the page for reassembling the split packet. |
417 | */ | |
32b46093 KH |
418 | |
419 | offset = offsetof(struct ar_buffer, data); | |
420 | dma_unmap_single(ohci->card.device, | |
0a9972ba SR |
421 | le32_to_cpu(ab->descriptor.data_address) - offset, |
422 | PAGE_SIZE, DMA_BIDIRECTIONAL); | |
32b46093 KH |
423 | |
424 | buffer = ab; | |
425 | ab = ab->next; | |
426 | d = &ab->descriptor; | |
427 | size = buffer + PAGE_SIZE - ctx->pointer; | |
428 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
429 | memmove(buffer, ctx->pointer, size); | |
430 | memcpy(buffer + size, ab->data, rest); | |
431 | ctx->current_buffer = ab; | |
432 | ctx->pointer = (void *) ab->data + rest; | |
433 | end = buffer + size + rest; | |
434 | ||
435 | while (buffer < end) | |
436 | buffer = handle_ar_packet(ctx, buffer); | |
437 | ||
438 | free_page((unsigned long)buffer); | |
439 | ar_context_add_page(ctx); | |
440 | } else { | |
441 | buffer = ctx->pointer; | |
442 | ctx->pointer = end = | |
443 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
444 | ||
445 | while (buffer < end) | |
446 | buffer = handle_ar_packet(ctx, buffer); | |
447 | } | |
ed568912 KH |
448 | } |
449 | ||
450 | static int | |
72e318e0 | 451 | ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs) |
ed568912 | 452 | { |
32b46093 | 453 | struct ar_buffer ab; |
ed568912 | 454 | |
72e318e0 KH |
455 | ctx->regs = regs; |
456 | ctx->ohci = ohci; | |
457 | ctx->last_buffer = &ab; | |
ed568912 KH |
458 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
459 | ||
32b46093 KH |
460 | ar_context_add_page(ctx); |
461 | ar_context_add_page(ctx); | |
462 | ctx->current_buffer = ab.next; | |
463 | ctx->pointer = ctx->current_buffer->data; | |
464 | ||
2aef469a KH |
465 | return 0; |
466 | } | |
467 | ||
468 | static void ar_context_run(struct ar_context *ctx) | |
469 | { | |
470 | struct ar_buffer *ab = ctx->current_buffer; | |
471 | dma_addr_t ab_bus; | |
472 | size_t offset; | |
473 | ||
474 | offset = offsetof(struct ar_buffer, data); | |
0a9972ba | 475 | ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; |
2aef469a KH |
476 | |
477 | reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1); | |
a77754a7 | 478 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); |
32b46093 | 479 | flush_writes(ctx->ohci); |
ed568912 | 480 | } |
373b2edd | 481 | |
a186b4a6 JW |
482 | static struct descriptor * |
483 | find_branch_descriptor(struct descriptor *d, int z) | |
484 | { | |
485 | int b, key; | |
486 | ||
487 | b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; | |
488 | key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; | |
489 | ||
490 | /* figure out which descriptor the branch address goes in */ | |
491 | if (z == 2 && (b == 3 || key == 2)) | |
492 | return d; | |
493 | else | |
494 | return d + z - 1; | |
495 | } | |
496 | ||
30200739 KH |
497 | static void context_tasklet(unsigned long data) |
498 | { | |
499 | struct context *ctx = (struct context *) data; | |
30200739 KH |
500 | struct descriptor *d, *last; |
501 | u32 address; | |
502 | int z; | |
fe5ca634 | 503 | struct descriptor_buffer *desc; |
30200739 | 504 | |
fe5ca634 DM |
505 | desc = list_entry(ctx->buffer_list.next, |
506 | struct descriptor_buffer, list); | |
507 | last = ctx->last; | |
30200739 | 508 | while (last->branch_address != 0) { |
fe5ca634 | 509 | struct descriptor_buffer *old_desc = desc; |
30200739 KH |
510 | address = le32_to_cpu(last->branch_address); |
511 | z = address & 0xf; | |
fe5ca634 DM |
512 | address &= ~0xf; |
513 | ||
514 | /* If the branch address points to a buffer outside of the | |
515 | * current buffer, advance to the next buffer. */ | |
516 | if (address < desc->buffer_bus || | |
517 | address >= desc->buffer_bus + desc->used) | |
518 | desc = list_entry(desc->list.next, | |
519 | struct descriptor_buffer, list); | |
520 | d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); | |
a186b4a6 | 521 | last = find_branch_descriptor(d, z); |
30200739 KH |
522 | |
523 | if (!ctx->callback(ctx, d, last)) | |
524 | break; | |
525 | ||
fe5ca634 DM |
526 | if (old_desc != desc) { |
527 | /* If we've advanced to the next buffer, move the | |
528 | * previous buffer to the free list. */ | |
529 | unsigned long flags; | |
530 | old_desc->used = 0; | |
531 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
532 | list_move_tail(&old_desc->list, &ctx->buffer_list); | |
533 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); | |
534 | } | |
535 | ctx->last = last; | |
30200739 KH |
536 | } |
537 | } | |
538 | ||
fe5ca634 DM |
539 | /* |
540 | * Allocate a new buffer and add it to the list of free buffers for this | |
541 | * context. Must be called with ohci->lock held. | |
542 | */ | |
543 | static int | |
544 | context_add_buffer(struct context *ctx) | |
545 | { | |
546 | struct descriptor_buffer *desc; | |
547 | dma_addr_t bus_addr; | |
548 | int offset; | |
549 | ||
550 | /* | |
551 | * 16MB of descriptors should be far more than enough for any DMA | |
552 | * program. This will catch run-away userspace or DoS attacks. | |
553 | */ | |
554 | if (ctx->total_allocation >= 16*1024*1024) | |
555 | return -ENOMEM; | |
556 | ||
557 | desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, | |
558 | &bus_addr, GFP_ATOMIC); | |
559 | if (!desc) | |
560 | return -ENOMEM; | |
561 | ||
562 | offset = (void *)&desc->buffer - (void *)desc; | |
563 | desc->buffer_size = PAGE_SIZE - offset; | |
564 | desc->buffer_bus = bus_addr + offset; | |
565 | desc->used = 0; | |
566 | ||
567 | list_add_tail(&desc->list, &ctx->buffer_list); | |
568 | ctx->total_allocation += PAGE_SIZE; | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
30200739 KH |
573 | static int |
574 | context_init(struct context *ctx, struct fw_ohci *ohci, | |
fe5ca634 | 575 | u32 regs, descriptor_callback_t callback) |
30200739 KH |
576 | { |
577 | ctx->ohci = ohci; | |
578 | ctx->regs = regs; | |
fe5ca634 DM |
579 | ctx->total_allocation = 0; |
580 | ||
581 | INIT_LIST_HEAD(&ctx->buffer_list); | |
582 | if (context_add_buffer(ctx) < 0) | |
30200739 KH |
583 | return -ENOMEM; |
584 | ||
fe5ca634 DM |
585 | ctx->buffer_tail = list_entry(ctx->buffer_list.next, |
586 | struct descriptor_buffer, list); | |
587 | ||
30200739 KH |
588 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); |
589 | ctx->callback = callback; | |
590 | ||
c781c06d KH |
591 | /* |
592 | * We put a dummy descriptor in the buffer that has a NULL | |
30200739 | 593 | * branch address and looks like it's been sent. That way we |
fe5ca634 | 594 | * have a descriptor to append DMA programs to. |
c781c06d | 595 | */ |
fe5ca634 DM |
596 | memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); |
597 | ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); | |
598 | ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); | |
599 | ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); | |
600 | ctx->last = ctx->buffer_tail->buffer; | |
601 | ctx->prev = ctx->buffer_tail->buffer; | |
30200739 KH |
602 | |
603 | return 0; | |
604 | } | |
605 | ||
9b32d5f3 | 606 | static void |
30200739 KH |
607 | context_release(struct context *ctx) |
608 | { | |
609 | struct fw_card *card = &ctx->ohci->card; | |
fe5ca634 | 610 | struct descriptor_buffer *desc, *tmp; |
30200739 | 611 | |
fe5ca634 DM |
612 | list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) |
613 | dma_free_coherent(card->device, PAGE_SIZE, desc, | |
614 | desc->buffer_bus - | |
615 | ((void *)&desc->buffer - (void *)desc)); | |
30200739 KH |
616 | } |
617 | ||
fe5ca634 | 618 | /* Must be called with ohci->lock held */ |
30200739 KH |
619 | static struct descriptor * |
620 | context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus) | |
621 | { | |
fe5ca634 DM |
622 | struct descriptor *d = NULL; |
623 | struct descriptor_buffer *desc = ctx->buffer_tail; | |
624 | ||
625 | if (z * sizeof(*d) > desc->buffer_size) | |
626 | return NULL; | |
627 | ||
628 | if (z * sizeof(*d) > desc->buffer_size - desc->used) { | |
629 | /* No room for the descriptor in this buffer, so advance to the | |
630 | * next one. */ | |
30200739 | 631 | |
fe5ca634 DM |
632 | if (desc->list.next == &ctx->buffer_list) { |
633 | /* If there is no free buffer next in the list, | |
634 | * allocate one. */ | |
635 | if (context_add_buffer(ctx) < 0) | |
636 | return NULL; | |
637 | } | |
638 | desc = list_entry(desc->list.next, | |
639 | struct descriptor_buffer, list); | |
640 | ctx->buffer_tail = desc; | |
641 | } | |
30200739 | 642 | |
fe5ca634 | 643 | d = desc->buffer + desc->used / sizeof(*d); |
2d826cc5 | 644 | memset(d, 0, z * sizeof(*d)); |
fe5ca634 | 645 | *d_bus = desc->buffer_bus + desc->used; |
30200739 KH |
646 | |
647 | return d; | |
648 | } | |
649 | ||
295e3feb | 650 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
651 | { |
652 | struct fw_ohci *ohci = ctx->ohci; | |
653 | ||
a77754a7 | 654 | reg_write(ohci, COMMAND_PTR(ctx->regs), |
fe5ca634 | 655 | le32_to_cpu(ctx->last->branch_address)); |
a77754a7 KH |
656 | reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); |
657 | reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); | |
30200739 KH |
658 | flush_writes(ohci); |
659 | } | |
660 | ||
661 | static void context_append(struct context *ctx, | |
662 | struct descriptor *d, int z, int extra) | |
663 | { | |
664 | dma_addr_t d_bus; | |
fe5ca634 | 665 | struct descriptor_buffer *desc = ctx->buffer_tail; |
30200739 | 666 | |
fe5ca634 | 667 | d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); |
30200739 | 668 | |
fe5ca634 DM |
669 | desc->used += (z + extra) * sizeof(*d); |
670 | ctx->prev->branch_address = cpu_to_le32(d_bus | z); | |
671 | ctx->prev = find_branch_descriptor(d, z); | |
30200739 | 672 | |
a77754a7 | 673 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
30200739 KH |
674 | flush_writes(ctx->ohci); |
675 | } | |
676 | ||
677 | static void context_stop(struct context *ctx) | |
678 | { | |
679 | u32 reg; | |
b8295668 | 680 | int i; |
30200739 | 681 | |
a77754a7 | 682 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); |
b8295668 | 683 | flush_writes(ctx->ohci); |
30200739 | 684 | |
b8295668 | 685 | for (i = 0; i < 10; i++) { |
a77754a7 | 686 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
b8295668 KH |
687 | if ((reg & CONTEXT_ACTIVE) == 0) |
688 | break; | |
689 | ||
690 | fw_notify("context_stop: still active (0x%08x)\n", reg); | |
b980f5a2 | 691 | mdelay(1); |
b8295668 | 692 | } |
30200739 | 693 | } |
ed568912 | 694 | |
f319b6a0 KH |
695 | struct driver_data { |
696 | struct fw_packet *packet; | |
697 | }; | |
ed568912 | 698 | |
c781c06d KH |
699 | /* |
700 | * This function apppends a packet to the DMA queue for transmission. | |
f319b6a0 | 701 | * Must always be called with the ochi->lock held to ensure proper |
c781c06d KH |
702 | * generation handling and locking around packet queue manipulation. |
703 | */ | |
f319b6a0 KH |
704 | static int |
705 | at_context_queue_packet(struct context *ctx, struct fw_packet *packet) | |
ed568912 | 706 | { |
ed568912 | 707 | struct fw_ohci *ohci = ctx->ohci; |
4b6d51ec | 708 | dma_addr_t d_bus, uninitialized_var(payload_bus); |
f319b6a0 KH |
709 | struct driver_data *driver_data; |
710 | struct descriptor *d, *last; | |
711 | __le32 *header; | |
ed568912 | 712 | int z, tcode; |
f319b6a0 | 713 | u32 reg; |
ed568912 | 714 | |
f319b6a0 KH |
715 | d = context_get_descriptors(ctx, 4, &d_bus); |
716 | if (d == NULL) { | |
717 | packet->ack = RCODE_SEND_ERROR; | |
718 | return -1; | |
ed568912 KH |
719 | } |
720 | ||
a77754a7 | 721 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
f319b6a0 KH |
722 | d[0].res_count = cpu_to_le16(packet->timestamp); |
723 | ||
c781c06d KH |
724 | /* |
725 | * The DMA format for asyncronous link packets is different | |
ed568912 KH |
726 | * from the IEEE1394 layout, so shift the fields around |
727 | * accordingly. If header_length is 8, it's a PHY packet, to | |
c781c06d KH |
728 | * which we need to prepend an extra quadlet. |
729 | */ | |
f319b6a0 KH |
730 | |
731 | header = (__le32 *) &d[1]; | |
ed568912 | 732 | if (packet->header_length > 8) { |
f319b6a0 KH |
733 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | |
734 | (packet->speed << 16)); | |
735 | header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
736 | (packet->header[0] & 0xffff0000)); | |
737 | header[2] = cpu_to_le32(packet->header[2]); | |
ed568912 KH |
738 | |
739 | tcode = (packet->header[0] >> 4) & 0x0f; | |
740 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
f319b6a0 | 741 | header[3] = cpu_to_le32(packet->header[3]); |
ed568912 | 742 | else |
f319b6a0 KH |
743 | header[3] = (__force __le32) packet->header[3]; |
744 | ||
745 | d[0].req_count = cpu_to_le16(packet->header_length); | |
ed568912 | 746 | } else { |
f319b6a0 KH |
747 | header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | |
748 | (packet->speed << 16)); | |
749 | header[1] = cpu_to_le32(packet->header[0]); | |
750 | header[2] = cpu_to_le32(packet->header[1]); | |
751 | d[0].req_count = cpu_to_le16(12); | |
ed568912 KH |
752 | } |
753 | ||
f319b6a0 KH |
754 | driver_data = (struct driver_data *) &d[3]; |
755 | driver_data->packet = packet; | |
20d11673 | 756 | packet->driver_data = driver_data; |
a186b4a6 | 757 | |
f319b6a0 KH |
758 | if (packet->payload_length > 0) { |
759 | payload_bus = | |
760 | dma_map_single(ohci->card.device, packet->payload, | |
761 | packet->payload_length, DMA_TO_DEVICE); | |
762 | if (dma_mapping_error(payload_bus)) { | |
763 | packet->ack = RCODE_SEND_ERROR; | |
764 | return -1; | |
765 | } | |
766 | ||
767 | d[2].req_count = cpu_to_le16(packet->payload_length); | |
768 | d[2].data_address = cpu_to_le32(payload_bus); | |
769 | last = &d[2]; | |
770 | z = 3; | |
ed568912 | 771 | } else { |
f319b6a0 KH |
772 | last = &d[0]; |
773 | z = 2; | |
ed568912 | 774 | } |
ed568912 | 775 | |
a77754a7 KH |
776 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
777 | DESCRIPTOR_IRQ_ALWAYS | | |
778 | DESCRIPTOR_BRANCH_ALWAYS); | |
ed568912 | 779 | |
f319b6a0 KH |
780 | /* FIXME: Document how the locking works. */ |
781 | if (ohci->generation != packet->generation) { | |
ab88ca48 SR |
782 | if (packet->payload_length > 0) |
783 | dma_unmap_single(ohci->card.device, payload_bus, | |
784 | packet->payload_length, DMA_TO_DEVICE); | |
f319b6a0 KH |
785 | packet->ack = RCODE_GENERATION; |
786 | return -1; | |
787 | } | |
788 | ||
789 | context_append(ctx, d, z, 4 - z); | |
ed568912 | 790 | |
f319b6a0 | 791 | /* If the context isn't already running, start it up. */ |
a77754a7 | 792 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
053b3080 | 793 | if ((reg & CONTEXT_RUN) == 0) |
f319b6a0 KH |
794 | context_run(ctx, 0); |
795 | ||
796 | return 0; | |
ed568912 KH |
797 | } |
798 | ||
f319b6a0 KH |
799 | static int handle_at_packet(struct context *context, |
800 | struct descriptor *d, | |
801 | struct descriptor *last) | |
ed568912 | 802 | { |
f319b6a0 | 803 | struct driver_data *driver_data; |
ed568912 | 804 | struct fw_packet *packet; |
f319b6a0 KH |
805 | struct fw_ohci *ohci = context->ohci; |
806 | dma_addr_t payload_bus; | |
ed568912 KH |
807 | int evt; |
808 | ||
f319b6a0 KH |
809 | if (last->transfer_status == 0) |
810 | /* This descriptor isn't done yet, stop iteration. */ | |
811 | return 0; | |
ed568912 | 812 | |
f319b6a0 KH |
813 | driver_data = (struct driver_data *) &d[3]; |
814 | packet = driver_data->packet; | |
815 | if (packet == NULL) | |
816 | /* This packet was cancelled, just continue. */ | |
817 | return 1; | |
730c32f5 | 818 | |
f319b6a0 KH |
819 | payload_bus = le32_to_cpu(last->data_address); |
820 | if (payload_bus != 0) | |
821 | dma_unmap_single(ohci->card.device, payload_bus, | |
ed568912 | 822 | packet->payload_length, DMA_TO_DEVICE); |
ed568912 | 823 | |
f319b6a0 KH |
824 | evt = le16_to_cpu(last->transfer_status) & 0x1f; |
825 | packet->timestamp = le16_to_cpu(last->res_count); | |
ed568912 | 826 | |
f319b6a0 KH |
827 | switch (evt) { |
828 | case OHCI1394_evt_timeout: | |
829 | /* Async response transmit timed out. */ | |
830 | packet->ack = RCODE_CANCELLED; | |
831 | break; | |
ed568912 | 832 | |
f319b6a0 | 833 | case OHCI1394_evt_flushed: |
c781c06d KH |
834 | /* |
835 | * The packet was flushed should give same error as | |
836 | * when we try to use a stale generation count. | |
837 | */ | |
f319b6a0 KH |
838 | packet->ack = RCODE_GENERATION; |
839 | break; | |
ed568912 | 840 | |
f319b6a0 | 841 | case OHCI1394_evt_missing_ack: |
c781c06d KH |
842 | /* |
843 | * Using a valid (current) generation count, but the | |
844 | * node is not on the bus or not sending acks. | |
845 | */ | |
f319b6a0 KH |
846 | packet->ack = RCODE_NO_ACK; |
847 | break; | |
ed568912 | 848 | |
f319b6a0 KH |
849 | case ACK_COMPLETE + 0x10: |
850 | case ACK_PENDING + 0x10: | |
851 | case ACK_BUSY_X + 0x10: | |
852 | case ACK_BUSY_A + 0x10: | |
853 | case ACK_BUSY_B + 0x10: | |
854 | case ACK_DATA_ERROR + 0x10: | |
855 | case ACK_TYPE_ERROR + 0x10: | |
856 | packet->ack = evt - 0x10; | |
857 | break; | |
ed568912 | 858 | |
f319b6a0 KH |
859 | default: |
860 | packet->ack = RCODE_SEND_ERROR; | |
861 | break; | |
862 | } | |
ed568912 | 863 | |
f319b6a0 | 864 | packet->callback(packet, &ohci->card, packet->ack); |
ed568912 | 865 | |
f319b6a0 | 866 | return 1; |
ed568912 KH |
867 | } |
868 | ||
a77754a7 KH |
869 | #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) |
870 | #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) | |
871 | #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) | |
872 | #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) | |
873 | #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) | |
93c4cceb KH |
874 | |
875 | static void | |
876 | handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
877 | { | |
878 | struct fw_packet response; | |
879 | int tcode, length, i; | |
880 | ||
a77754a7 | 881 | tcode = HEADER_GET_TCODE(packet->header[0]); |
93c4cceb | 882 | if (TCODE_IS_BLOCK_PACKET(tcode)) |
a77754a7 | 883 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); |
93c4cceb KH |
884 | else |
885 | length = 4; | |
886 | ||
887 | i = csr - CSR_CONFIG_ROM; | |
888 | if (i + length > CONFIG_ROM_SIZE) { | |
889 | fw_fill_response(&response, packet->header, | |
890 | RCODE_ADDRESS_ERROR, NULL, 0); | |
891 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
892 | fw_fill_response(&response, packet->header, | |
893 | RCODE_TYPE_ERROR, NULL, 0); | |
894 | } else { | |
895 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
896 | (void *) ohci->config_rom + i, length); | |
897 | } | |
898 | ||
899 | fw_core_handle_response(&ohci->card, &response); | |
900 | } | |
901 | ||
902 | static void | |
903 | handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
904 | { | |
905 | struct fw_packet response; | |
906 | int tcode, length, ext_tcode, sel; | |
907 | __be32 *payload, lock_old; | |
908 | u32 lock_arg, lock_data; | |
909 | ||
a77754a7 KH |
910 | tcode = HEADER_GET_TCODE(packet->header[0]); |
911 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); | |
93c4cceb | 912 | payload = packet->payload; |
a77754a7 | 913 | ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); |
93c4cceb KH |
914 | |
915 | if (tcode == TCODE_LOCK_REQUEST && | |
916 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
917 | lock_arg = be32_to_cpu(payload[0]); | |
918 | lock_data = be32_to_cpu(payload[1]); | |
919 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
920 | lock_arg = 0; | |
921 | lock_data = 0; | |
922 | } else { | |
923 | fw_fill_response(&response, packet->header, | |
924 | RCODE_TYPE_ERROR, NULL, 0); | |
925 | goto out; | |
926 | } | |
927 | ||
928 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
929 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
930 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
931 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
932 | ||
933 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
934 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
935 | else | |
936 | fw_notify("swap not done yet\n"); | |
937 | ||
938 | fw_fill_response(&response, packet->header, | |
2d826cc5 | 939 | RCODE_COMPLETE, &lock_old, sizeof(lock_old)); |
93c4cceb KH |
940 | out: |
941 | fw_core_handle_response(&ohci->card, &response); | |
942 | } | |
943 | ||
944 | static void | |
f319b6a0 | 945 | handle_local_request(struct context *ctx, struct fw_packet *packet) |
93c4cceb KH |
946 | { |
947 | u64 offset; | |
948 | u32 csr; | |
949 | ||
473d28c7 KH |
950 | if (ctx == &ctx->ohci->at_request_ctx) { |
951 | packet->ack = ACK_PENDING; | |
952 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
953 | } | |
93c4cceb KH |
954 | |
955 | offset = | |
956 | ((unsigned long long) | |
a77754a7 | 957 | HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | |
93c4cceb KH |
958 | packet->header[2]; |
959 | csr = offset - CSR_REGISTER_BASE; | |
960 | ||
961 | /* Handle config rom reads. */ | |
962 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
963 | handle_local_rom(ctx->ohci, packet, csr); | |
964 | else switch (csr) { | |
965 | case CSR_BUS_MANAGER_ID: | |
966 | case CSR_BANDWIDTH_AVAILABLE: | |
967 | case CSR_CHANNELS_AVAILABLE_HI: | |
968 | case CSR_CHANNELS_AVAILABLE_LO: | |
969 | handle_local_lock(ctx->ohci, packet, csr); | |
970 | break; | |
971 | default: | |
972 | if (ctx == &ctx->ohci->at_request_ctx) | |
973 | fw_core_handle_request(&ctx->ohci->card, packet); | |
974 | else | |
975 | fw_core_handle_response(&ctx->ohci->card, packet); | |
976 | break; | |
977 | } | |
473d28c7 KH |
978 | |
979 | if (ctx == &ctx->ohci->at_response_ctx) { | |
980 | packet->ack = ACK_COMPLETE; | |
981 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
982 | } | |
93c4cceb | 983 | } |
e636fe25 | 984 | |
ed568912 | 985 | static void |
f319b6a0 | 986 | at_context_transmit(struct context *ctx, struct fw_packet *packet) |
ed568912 | 987 | { |
ed568912 | 988 | unsigned long flags; |
f319b6a0 | 989 | int retval; |
ed568912 KH |
990 | |
991 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
992 | ||
a77754a7 | 993 | if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && |
e636fe25 | 994 | ctx->ohci->generation == packet->generation) { |
93c4cceb KH |
995 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
996 | handle_local_request(ctx, packet); | |
997 | return; | |
e636fe25 | 998 | } |
ed568912 | 999 | |
f319b6a0 | 1000 | retval = at_context_queue_packet(ctx, packet); |
ed568912 KH |
1001 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1002 | ||
f319b6a0 KH |
1003 | if (retval < 0) |
1004 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
a186b4a6 | 1005 | |
ed568912 KH |
1006 | } |
1007 | ||
1008 | static void bus_reset_tasklet(unsigned long data) | |
1009 | { | |
1010 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 1011 | int self_id_count, i, j, reg; |
ed568912 KH |
1012 | int generation, new_generation; |
1013 | unsigned long flags; | |
4eaff7d6 SR |
1014 | void *free_rom = NULL; |
1015 | dma_addr_t free_rom_bus = 0; | |
ed568912 KH |
1016 | |
1017 | reg = reg_read(ohci, OHCI1394_NodeID); | |
1018 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
02ff8f8e | 1019 | fw_notify("node ID not valid, new bus reset in progress\n"); |
ed568912 KH |
1020 | return; |
1021 | } | |
02ff8f8e SR |
1022 | if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { |
1023 | fw_notify("malconfigured bus\n"); | |
1024 | return; | |
1025 | } | |
1026 | ohci->node_id = reg & (OHCI1394_NodeID_busNumber | | |
1027 | OHCI1394_NodeID_nodeNumber); | |
ed568912 | 1028 | |
c781c06d KH |
1029 | /* |
1030 | * The count in the SelfIDCount register is the number of | |
ed568912 KH |
1031 | * bytes in the self ID receive buffer. Since we also receive |
1032 | * the inverted quadlets and a header quadlet, we shift one | |
c781c06d KH |
1033 | * bit extra to get the actual number of self IDs. |
1034 | */ | |
ed568912 KH |
1035 | |
1036 | self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff; | |
11bf20ad | 1037 | generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; |
ee71c2f9 | 1038 | rmb(); |
ed568912 KH |
1039 | |
1040 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
1041 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) | |
1042 | fw_error("inconsistent self IDs\n"); | |
11bf20ad SR |
1043 | ohci->self_id_buffer[j] = |
1044 | cond_le32_to_cpu(ohci->self_id_cpu[i]); | |
ed568912 | 1045 | } |
ee71c2f9 | 1046 | rmb(); |
ed568912 | 1047 | |
c781c06d KH |
1048 | /* |
1049 | * Check the consistency of the self IDs we just read. The | |
ed568912 KH |
1050 | * problem we face is that a new bus reset can start while we |
1051 | * read out the self IDs from the DMA buffer. If this happens, | |
1052 | * the DMA buffer will be overwritten with new self IDs and we | |
1053 | * will read out inconsistent data. The OHCI specification | |
1054 | * (section 11.2) recommends a technique similar to | |
1055 | * linux/seqlock.h, where we remember the generation of the | |
1056 | * self IDs in the buffer before reading them out and compare | |
1057 | * it to the current generation after reading them out. If | |
1058 | * the two generations match we know we have a consistent set | |
c781c06d KH |
1059 | * of self IDs. |
1060 | */ | |
ed568912 KH |
1061 | |
1062 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
1063 | if (new_generation != generation) { | |
1064 | fw_notify("recursive bus reset detected, " | |
1065 | "discarding self ids\n"); | |
1066 | return; | |
1067 | } | |
1068 | ||
1069 | /* FIXME: Document how the locking works. */ | |
1070 | spin_lock_irqsave(&ohci->lock, flags); | |
1071 | ||
1072 | ohci->generation = generation; | |
f319b6a0 KH |
1073 | context_stop(&ohci->at_request_ctx); |
1074 | context_stop(&ohci->at_response_ctx); | |
ed568912 KH |
1075 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
1076 | ||
c781c06d KH |
1077 | /* |
1078 | * This next bit is unrelated to the AT context stuff but we | |
ed568912 KH |
1079 | * have to do it under the spinlock also. If a new config rom |
1080 | * was set up before this reset, the old one is now no longer | |
1081 | * in use and we can free it. Update the config rom pointers | |
1082 | * to point to the current config rom and clear the | |
c781c06d KH |
1083 | * next_config_rom pointer so a new udpate can take place. |
1084 | */ | |
ed568912 KH |
1085 | |
1086 | if (ohci->next_config_rom != NULL) { | |
0bd243c4 KH |
1087 | if (ohci->next_config_rom != ohci->config_rom) { |
1088 | free_rom = ohci->config_rom; | |
1089 | free_rom_bus = ohci->config_rom_bus; | |
1090 | } | |
ed568912 KH |
1091 | ohci->config_rom = ohci->next_config_rom; |
1092 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
1093 | ohci->next_config_rom = NULL; | |
1094 | ||
c781c06d KH |
1095 | /* |
1096 | * Restore config_rom image and manually update | |
ed568912 KH |
1097 | * config_rom registers. Writing the header quadlet |
1098 | * will indicate that the config rom is ready, so we | |
c781c06d KH |
1099 | * do that last. |
1100 | */ | |
ed568912 KH |
1101 | reg_write(ohci, OHCI1394_BusOptions, |
1102 | be32_to_cpu(ohci->config_rom[2])); | |
1103 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
1104 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
1105 | } | |
1106 | ||
1107 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1108 | ||
4eaff7d6 SR |
1109 | if (free_rom) |
1110 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1111 | free_rom, free_rom_bus); | |
1112 | ||
e636fe25 | 1113 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
1114 | self_id_count, ohci->self_id_buffer); |
1115 | } | |
1116 | ||
1117 | static irqreturn_t irq_handler(int irq, void *data) | |
1118 | { | |
1119 | struct fw_ohci *ohci = data; | |
d60d7f1d | 1120 | u32 event, iso_event, cycle_time; |
ed568912 KH |
1121 | int i; |
1122 | ||
1123 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
1124 | ||
a515958d | 1125 | if (!event || !~event) |
ed568912 KH |
1126 | return IRQ_NONE; |
1127 | ||
1128 | reg_write(ohci, OHCI1394_IntEventClear, event); | |
1129 | ||
1130 | if (event & OHCI1394_selfIDComplete) | |
1131 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
1132 | ||
1133 | if (event & OHCI1394_RQPkt) | |
1134 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
1135 | ||
1136 | if (event & OHCI1394_RSPkt) | |
1137 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
1138 | ||
1139 | if (event & OHCI1394_reqTxComplete) | |
1140 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
1141 | ||
1142 | if (event & OHCI1394_respTxComplete) | |
1143 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
1144 | ||
c889475f | 1145 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed568912 KH |
1146 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); |
1147 | ||
1148 | while (iso_event) { | |
1149 | i = ffs(iso_event) - 1; | |
30200739 | 1150 | tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed568912 KH |
1151 | iso_event &= ~(1 << i); |
1152 | } | |
1153 | ||
c889475f | 1154 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed568912 KH |
1155 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); |
1156 | ||
1157 | while (iso_event) { | |
1158 | i = ffs(iso_event) - 1; | |
30200739 | 1159 | tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed568912 KH |
1160 | iso_event &= ~(1 << i); |
1161 | } | |
1162 | ||
e524f616 SR |
1163 | if (unlikely(event & OHCI1394_postedWriteErr)) |
1164 | fw_error("PCI posted write error\n"); | |
1165 | ||
bb9f2206 SR |
1166 | if (unlikely(event & OHCI1394_cycleTooLong)) { |
1167 | if (printk_ratelimit()) | |
1168 | fw_notify("isochronous cycle too long\n"); | |
1169 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1170 | OHCI1394_LinkControl_cycleMaster); | |
1171 | } | |
1172 | ||
d60d7f1d KH |
1173 | if (event & OHCI1394_cycle64Seconds) { |
1174 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1175 | if ((cycle_time & 0x80000000) == 0) | |
1176 | ohci->bus_seconds++; | |
1177 | } | |
1178 | ||
ed568912 KH |
1179 | return IRQ_HANDLED; |
1180 | } | |
1181 | ||
2aef469a KH |
1182 | static int software_reset(struct fw_ohci *ohci) |
1183 | { | |
1184 | int i; | |
1185 | ||
1186 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1187 | ||
1188 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1189 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1190 | OHCI1394_HCControl_softReset) == 0) | |
1191 | return 0; | |
1192 | msleep(1); | |
1193 | } | |
1194 | ||
1195 | return -EBUSY; | |
1196 | } | |
1197 | ||
ed568912 KH |
1198 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) |
1199 | { | |
1200 | struct fw_ohci *ohci = fw_ohci(card); | |
1201 | struct pci_dev *dev = to_pci_dev(card->device); | |
1202 | ||
2aef469a KH |
1203 | if (software_reset(ohci)) { |
1204 | fw_error("Failed to reset ohci card.\n"); | |
1205 | return -EBUSY; | |
1206 | } | |
1207 | ||
1208 | /* | |
1209 | * Now enable LPS, which we need in order to start accessing | |
1210 | * most of the registers. In fact, on some cards (ALI M5251), | |
1211 | * accessing registers in the SClk domain without LPS enabled | |
1212 | * will lock up the machine. Wait 50msec to make sure we have | |
1213 | * full link enabled. | |
1214 | */ | |
1215 | reg_write(ohci, OHCI1394_HCControlSet, | |
1216 | OHCI1394_HCControl_LPS | | |
1217 | OHCI1394_HCControl_postedWriteEnable); | |
1218 | flush_writes(ohci); | |
1219 | msleep(50); | |
1220 | ||
1221 | reg_write(ohci, OHCI1394_HCControlClear, | |
1222 | OHCI1394_HCControl_noByteSwapData); | |
1223 | ||
1224 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1225 | OHCI1394_LinkControl_rcvSelfID | | |
1226 | OHCI1394_LinkControl_cycleTimerEnable | | |
1227 | OHCI1394_LinkControl_cycleMaster); | |
1228 | ||
1229 | reg_write(ohci, OHCI1394_ATRetries, | |
1230 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1231 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1232 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1233 | ||
1234 | ar_context_run(&ohci->ar_request_ctx); | |
1235 | ar_context_run(&ohci->ar_response_ctx); | |
1236 | ||
1237 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | |
1238 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); | |
1239 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1240 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1241 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1242 | OHCI1394_selfIDComplete | | |
1243 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1244 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1245 | OHCI1394_isochRx | OHCI1394_isochTx | | |
bb9f2206 SR |
1246 | OHCI1394_postedWriteErr | OHCI1394_cycleTooLong | |
1247 | OHCI1394_cycle64Seconds | OHCI1394_masterIntEnable); | |
2aef469a KH |
1248 | |
1249 | /* Activate link_on bit and contender bit in our self ID packets.*/ | |
1250 | if (ohci_update_phy_reg(card, 4, 0, | |
1251 | PHY_LINK_ACTIVE | PHY_CONTENDER) < 0) | |
1252 | return -EIO; | |
1253 | ||
c781c06d KH |
1254 | /* |
1255 | * When the link is not yet enabled, the atomic config rom | |
ed568912 KH |
1256 | * update mechanism described below in ohci_set_config_rom() |
1257 | * is not active. We have to update ConfigRomHeader and | |
1258 | * BusOptions manually, and the write to ConfigROMmap takes | |
1259 | * effect immediately. We tie this to the enabling of the | |
1260 | * link, so we have a valid config rom before enabling - the | |
1261 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
1262 | * values before enabling. | |
1263 | * | |
1264 | * However, when the ConfigROMmap is written, some controllers | |
1265 | * always read back quadlets 0 and 2 from the config rom to | |
1266 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
1267 | * They shouldn't do that in this initial case where the link | |
1268 | * isn't enabled. This means we have to use the same | |
1269 | * workaround here, setting the bus header to 0 and then write | |
1270 | * the right values in the bus reset tasklet. | |
1271 | */ | |
1272 | ||
0bd243c4 KH |
1273 | if (config_rom) { |
1274 | ohci->next_config_rom = | |
1275 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1276 | &ohci->next_config_rom_bus, | |
1277 | GFP_KERNEL); | |
1278 | if (ohci->next_config_rom == NULL) | |
1279 | return -ENOMEM; | |
ed568912 | 1280 | |
0bd243c4 KH |
1281 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); |
1282 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
1283 | } else { | |
1284 | /* | |
1285 | * In the suspend case, config_rom is NULL, which | |
1286 | * means that we just reuse the old config rom. | |
1287 | */ | |
1288 | ohci->next_config_rom = ohci->config_rom; | |
1289 | ohci->next_config_rom_bus = ohci->config_rom_bus; | |
1290 | } | |
ed568912 | 1291 | |
0bd243c4 | 1292 | ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]); |
ed568912 KH |
1293 | ohci->next_config_rom[0] = 0; |
1294 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
0bd243c4 KH |
1295 | reg_write(ohci, OHCI1394_BusOptions, |
1296 | be32_to_cpu(ohci->next_config_rom[2])); | |
ed568912 KH |
1297 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); |
1298 | ||
1299 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
1300 | ||
1301 | if (request_irq(dev->irq, irq_handler, | |
65efffa8 | 1302 | IRQF_SHARED, ohci_driver_name, ohci)) { |
ed568912 KH |
1303 | fw_error("Failed to allocate shared interrupt %d.\n", |
1304 | dev->irq); | |
1305 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1306 | ohci->config_rom, ohci->config_rom_bus); | |
1307 | return -EIO; | |
1308 | } | |
1309 | ||
1310 | reg_write(ohci, OHCI1394_HCControlSet, | |
1311 | OHCI1394_HCControl_linkEnable | | |
1312 | OHCI1394_HCControl_BIBimageValid); | |
1313 | flush_writes(ohci); | |
1314 | ||
c781c06d KH |
1315 | /* |
1316 | * We are ready to go, initiate bus reset to finish the | |
1317 | * initialization. | |
1318 | */ | |
ed568912 KH |
1319 | |
1320 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
1325 | static int | |
1326 | ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) | |
1327 | { | |
1328 | struct fw_ohci *ohci; | |
1329 | unsigned long flags; | |
4eaff7d6 | 1330 | int retval = -EBUSY; |
ed568912 KH |
1331 | __be32 *next_config_rom; |
1332 | dma_addr_t next_config_rom_bus; | |
1333 | ||
1334 | ohci = fw_ohci(card); | |
1335 | ||
c781c06d KH |
1336 | /* |
1337 | * When the OHCI controller is enabled, the config rom update | |
ed568912 KH |
1338 | * mechanism is a bit tricky, but easy enough to use. See |
1339 | * section 5.5.6 in the OHCI specification. | |
1340 | * | |
1341 | * The OHCI controller caches the new config rom address in a | |
1342 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
1343 | * for the changes to take place. When the bus reset is | |
1344 | * detected, the controller loads the new values for the | |
1345 | * ConfigRomHeader and BusOptions registers from the specified | |
1346 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
1347 | * shadow register. All automatically and atomically. | |
1348 | * | |
1349 | * Now, there's a twist to this story. The automatic load of | |
1350 | * ConfigRomHeader and BusOptions doesn't honor the | |
1351 | * noByteSwapData bit, so with a be32 config rom, the | |
1352 | * controller will load be32 values in to these registers | |
1353 | * during the atomic update, even on litte endian | |
1354 | * architectures. The workaround we use is to put a 0 in the | |
1355 | * header quadlet; 0 is endian agnostic and means that the | |
1356 | * config rom isn't ready yet. In the bus reset tasklet we | |
1357 | * then set up the real values for the two registers. | |
1358 | * | |
1359 | * We use ohci->lock to avoid racing with the code that sets | |
1360 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
1361 | */ | |
1362 | ||
1363 | next_config_rom = | |
1364 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1365 | &next_config_rom_bus, GFP_KERNEL); | |
1366 | if (next_config_rom == NULL) | |
1367 | return -ENOMEM; | |
1368 | ||
1369 | spin_lock_irqsave(&ohci->lock, flags); | |
1370 | ||
1371 | if (ohci->next_config_rom == NULL) { | |
1372 | ohci->next_config_rom = next_config_rom; | |
1373 | ohci->next_config_rom_bus = next_config_rom_bus; | |
1374 | ||
1375 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1376 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
1377 | length * 4); | |
1378 | ||
1379 | ohci->next_header = config_rom[0]; | |
1380 | ohci->next_config_rom[0] = 0; | |
1381 | ||
1382 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
1383 | ohci->next_config_rom_bus); | |
4eaff7d6 | 1384 | retval = 0; |
ed568912 KH |
1385 | } |
1386 | ||
1387 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1388 | ||
c781c06d KH |
1389 | /* |
1390 | * Now initiate a bus reset to have the changes take | |
ed568912 KH |
1391 | * effect. We clean up the old config rom memory and DMA |
1392 | * mappings in the bus reset tasklet, since the OHCI | |
1393 | * controller could need to access it before the bus reset | |
c781c06d KH |
1394 | * takes effect. |
1395 | */ | |
ed568912 KH |
1396 | if (retval == 0) |
1397 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
4eaff7d6 SR |
1398 | else |
1399 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1400 | next_config_rom, next_config_rom_bus); | |
ed568912 KH |
1401 | |
1402 | return retval; | |
1403 | } | |
1404 | ||
1405 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1406 | { | |
1407 | struct fw_ohci *ohci = fw_ohci(card); | |
1408 | ||
1409 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1410 | } | |
1411 | ||
1412 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1413 | { | |
1414 | struct fw_ohci *ohci = fw_ohci(card); | |
1415 | ||
1416 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1417 | } | |
1418 | ||
730c32f5 KH |
1419 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
1420 | { | |
1421 | struct fw_ohci *ohci = fw_ohci(card); | |
f319b6a0 KH |
1422 | struct context *ctx = &ohci->at_request_ctx; |
1423 | struct driver_data *driver_data = packet->driver_data; | |
1424 | int retval = -ENOENT; | |
730c32f5 | 1425 | |
f319b6a0 | 1426 | tasklet_disable(&ctx->tasklet); |
730c32f5 | 1427 | |
f319b6a0 KH |
1428 | if (packet->ack != 0) |
1429 | goto out; | |
730c32f5 | 1430 | |
f319b6a0 KH |
1431 | driver_data->packet = NULL; |
1432 | packet->ack = RCODE_CANCELLED; | |
1433 | packet->callback(packet, &ohci->card, packet->ack); | |
1434 | retval = 0; | |
730c32f5 | 1435 | |
f319b6a0 KH |
1436 | out: |
1437 | tasklet_enable(&ctx->tasklet); | |
730c32f5 | 1438 | |
f319b6a0 | 1439 | return retval; |
730c32f5 KH |
1440 | } |
1441 | ||
ed568912 KH |
1442 | static int |
1443 | ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) | |
1444 | { | |
1445 | struct fw_ohci *ohci = fw_ohci(card); | |
1446 | unsigned long flags; | |
907293d7 | 1447 | int n, retval = 0; |
ed568912 | 1448 | |
c781c06d KH |
1449 | /* |
1450 | * FIXME: Make sure this bitmask is cleared when we clear the busReset | |
1451 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. | |
1452 | */ | |
ed568912 KH |
1453 | |
1454 | spin_lock_irqsave(&ohci->lock, flags); | |
1455 | ||
1456 | if (ohci->generation != generation) { | |
1457 | retval = -ESTALE; | |
1458 | goto out; | |
1459 | } | |
1460 | ||
c781c06d KH |
1461 | /* |
1462 | * Note, if the node ID contains a non-local bus ID, physical DMA is | |
1463 | * enabled for _all_ nodes on remote buses. | |
1464 | */ | |
907293d7 SR |
1465 | |
1466 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
1467 | if (n < 32) | |
1468 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
1469 | else | |
1470 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
1471 | ||
ed568912 | 1472 | flush_writes(ohci); |
ed568912 | 1473 | out: |
6cad95fe | 1474 | spin_unlock_irqrestore(&ohci->lock, flags); |
ed568912 KH |
1475 | return retval; |
1476 | } | |
373b2edd | 1477 | |
d60d7f1d KH |
1478 | static u64 |
1479 | ohci_get_bus_time(struct fw_card *card) | |
1480 | { | |
1481 | struct fw_ohci *ohci = fw_ohci(card); | |
1482 | u32 cycle_time; | |
1483 | u64 bus_time; | |
1484 | ||
1485 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1486 | bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time; | |
1487 | ||
1488 | return bus_time; | |
1489 | } | |
1490 | ||
d2746dc1 KH |
1491 | static int handle_ir_dualbuffer_packet(struct context *context, |
1492 | struct descriptor *d, | |
1493 | struct descriptor *last) | |
ed568912 | 1494 | { |
295e3feb KH |
1495 | struct iso_context *ctx = |
1496 | container_of(context, struct iso_context, context); | |
1497 | struct db_descriptor *db = (struct db_descriptor *) d; | |
c70dc788 | 1498 | __le32 *ir_header; |
9b32d5f3 | 1499 | size_t header_length; |
c70dc788 KH |
1500 | void *p, *end; |
1501 | int i; | |
d2746dc1 | 1502 | |
efbf390a | 1503 | if (db->first_res_count != 0 && db->second_res_count != 0) { |
0642b657 DM |
1504 | if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) { |
1505 | /* This descriptor isn't done yet, stop iteration. */ | |
1506 | return 0; | |
1507 | } | |
1508 | ctx->excess_bytes -= le16_to_cpu(db->second_req_count); | |
1509 | } | |
295e3feb | 1510 | |
c70dc788 KH |
1511 | header_length = le16_to_cpu(db->first_req_count) - |
1512 | le16_to_cpu(db->first_res_count); | |
1513 | ||
1514 | i = ctx->header_length; | |
1515 | p = db + 1; | |
1516 | end = p + header_length; | |
1517 | while (p < end && i + ctx->base.header_size <= PAGE_SIZE) { | |
c781c06d KH |
1518 | /* |
1519 | * The iso header is byteswapped to little endian by | |
15536221 KH |
1520 | * the controller, but the remaining header quadlets |
1521 | * are big endian. We want to present all the headers | |
1522 | * as big endian, so we have to swap the first | |
c781c06d KH |
1523 | * quadlet. |
1524 | */ | |
15536221 KH |
1525 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); |
1526 | memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); | |
c70dc788 | 1527 | i += ctx->base.header_size; |
0642b657 | 1528 | ctx->excess_bytes += |
efbf390a | 1529 | (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff; |
c70dc788 KH |
1530 | p += ctx->base.header_size + 4; |
1531 | } | |
c70dc788 | 1532 | ctx->header_length = i; |
9b32d5f3 | 1533 | |
0642b657 DM |
1534 | ctx->excess_bytes -= le16_to_cpu(db->second_req_count) - |
1535 | le16_to_cpu(db->second_res_count); | |
1536 | ||
a77754a7 | 1537 | if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) { |
c70dc788 KH |
1538 | ir_header = (__le32 *) (db + 1); |
1539 | ctx->base.callback(&ctx->base, | |
1540 | le32_to_cpu(ir_header[0]) & 0xffff, | |
9b32d5f3 | 1541 | ctx->header_length, ctx->header, |
295e3feb | 1542 | ctx->base.callback_data); |
9b32d5f3 KH |
1543 | ctx->header_length = 0; |
1544 | } | |
ed568912 | 1545 | |
295e3feb | 1546 | return 1; |
ed568912 KH |
1547 | } |
1548 | ||
a186b4a6 JW |
1549 | static int handle_ir_packet_per_buffer(struct context *context, |
1550 | struct descriptor *d, | |
1551 | struct descriptor *last) | |
1552 | { | |
1553 | struct iso_context *ctx = | |
1554 | container_of(context, struct iso_context, context); | |
bcee893c | 1555 | struct descriptor *pd; |
a186b4a6 | 1556 | __le32 *ir_header; |
bcee893c DM |
1557 | void *p; |
1558 | int i; | |
a186b4a6 | 1559 | |
bcee893c DM |
1560 | for (pd = d; pd <= last; pd++) { |
1561 | if (pd->transfer_status) | |
1562 | break; | |
1563 | } | |
1564 | if (pd > last) | |
a186b4a6 JW |
1565 | /* Descriptor(s) not done yet, stop iteration */ |
1566 | return 0; | |
1567 | ||
a186b4a6 | 1568 | i = ctx->header_length; |
bcee893c | 1569 | p = last + 1; |
a186b4a6 | 1570 | |
bcee893c DM |
1571 | if (ctx->base.header_size > 0 && |
1572 | i + ctx->base.header_size <= PAGE_SIZE) { | |
a186b4a6 JW |
1573 | /* |
1574 | * The iso header is byteswapped to little endian by | |
1575 | * the controller, but the remaining header quadlets | |
1576 | * are big endian. We want to present all the headers | |
1577 | * as big endian, so we have to swap the first quadlet. | |
1578 | */ | |
1579 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); | |
1580 | memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); | |
bcee893c | 1581 | ctx->header_length += ctx->base.header_size; |
a186b4a6 JW |
1582 | } |
1583 | ||
bcee893c DM |
1584 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { |
1585 | ir_header = (__le32 *) p; | |
a186b4a6 JW |
1586 | ctx->base.callback(&ctx->base, |
1587 | le32_to_cpu(ir_header[0]) & 0xffff, | |
1588 | ctx->header_length, ctx->header, | |
1589 | ctx->base.callback_data); | |
1590 | ctx->header_length = 0; | |
1591 | } | |
1592 | ||
a186b4a6 JW |
1593 | return 1; |
1594 | } | |
1595 | ||
30200739 KH |
1596 | static int handle_it_packet(struct context *context, |
1597 | struct descriptor *d, | |
1598 | struct descriptor *last) | |
ed568912 | 1599 | { |
30200739 KH |
1600 | struct iso_context *ctx = |
1601 | container_of(context, struct iso_context, context); | |
373b2edd | 1602 | |
30200739 KH |
1603 | if (last->transfer_status == 0) |
1604 | /* This descriptor isn't done yet, stop iteration. */ | |
1605 | return 0; | |
1606 | ||
a77754a7 | 1607 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) |
9b32d5f3 KH |
1608 | ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count), |
1609 | 0, NULL, ctx->base.callback_data); | |
30200739 KH |
1610 | |
1611 | return 1; | |
ed568912 KH |
1612 | } |
1613 | ||
30200739 | 1614 | static struct fw_iso_context * |
eb0306ea | 1615 | ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size) |
ed568912 KH |
1616 | { |
1617 | struct fw_ohci *ohci = fw_ohci(card); | |
1618 | struct iso_context *ctx, *list; | |
30200739 | 1619 | descriptor_callback_t callback; |
295e3feb | 1620 | u32 *mask, regs; |
ed568912 | 1621 | unsigned long flags; |
9b32d5f3 | 1622 | int index, retval = -ENOMEM; |
ed568912 KH |
1623 | |
1624 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
1625 | mask = &ohci->it_context_mask; | |
1626 | list = ohci->it_context_list; | |
30200739 | 1627 | callback = handle_it_packet; |
ed568912 | 1628 | } else { |
373b2edd SR |
1629 | mask = &ohci->ir_context_mask; |
1630 | list = ohci->ir_context_list; | |
a186b4a6 JW |
1631 | if (ohci->version >= OHCI_VERSION_1_1) |
1632 | callback = handle_ir_dualbuffer_packet; | |
1633 | else | |
1634 | callback = handle_ir_packet_per_buffer; | |
ed568912 KH |
1635 | } |
1636 | ||
1637 | spin_lock_irqsave(&ohci->lock, flags); | |
1638 | index = ffs(*mask) - 1; | |
1639 | if (index >= 0) | |
1640 | *mask &= ~(1 << index); | |
1641 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1642 | ||
1643 | if (index < 0) | |
1644 | return ERR_PTR(-EBUSY); | |
1645 | ||
373b2edd SR |
1646 | if (type == FW_ISO_CONTEXT_TRANSMIT) |
1647 | regs = OHCI1394_IsoXmitContextBase(index); | |
1648 | else | |
1649 | regs = OHCI1394_IsoRcvContextBase(index); | |
1650 | ||
ed568912 | 1651 | ctx = &list[index]; |
2d826cc5 | 1652 | memset(ctx, 0, sizeof(*ctx)); |
9b32d5f3 KH |
1653 | ctx->header_length = 0; |
1654 | ctx->header = (void *) __get_free_page(GFP_KERNEL); | |
1655 | if (ctx->header == NULL) | |
1656 | goto out; | |
1657 | ||
fe5ca634 | 1658 | retval = context_init(&ctx->context, ohci, regs, callback); |
9b32d5f3 KH |
1659 | if (retval < 0) |
1660 | goto out_with_header; | |
ed568912 KH |
1661 | |
1662 | return &ctx->base; | |
9b32d5f3 KH |
1663 | |
1664 | out_with_header: | |
1665 | free_page((unsigned long)ctx->header); | |
1666 | out: | |
1667 | spin_lock_irqsave(&ohci->lock, flags); | |
1668 | *mask |= 1 << index; | |
1669 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1670 | ||
1671 | return ERR_PTR(retval); | |
ed568912 KH |
1672 | } |
1673 | ||
eb0306ea KH |
1674 | static int ohci_start_iso(struct fw_iso_context *base, |
1675 | s32 cycle, u32 sync, u32 tags) | |
ed568912 | 1676 | { |
373b2edd | 1677 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1678 | struct fw_ohci *ohci = ctx->context.ohci; |
8a2f7d93 | 1679 | u32 control, match; |
ed568912 KH |
1680 | int index; |
1681 | ||
295e3feb KH |
1682 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { |
1683 | index = ctx - ohci->it_context_list; | |
8a2f7d93 KH |
1684 | match = 0; |
1685 | if (cycle >= 0) | |
1686 | match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
295e3feb | 1687 | (cycle & 0x7fff) << 16; |
21efb3cf | 1688 | |
295e3feb KH |
1689 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); |
1690 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
8a2f7d93 | 1691 | context_run(&ctx->context, match); |
295e3feb KH |
1692 | } else { |
1693 | index = ctx - ohci->ir_context_list; | |
a186b4a6 JW |
1694 | control = IR_CONTEXT_ISOCH_HEADER; |
1695 | if (ohci->version >= OHCI_VERSION_1_1) | |
1696 | control |= IR_CONTEXT_DUAL_BUFFER_MODE; | |
8a2f7d93 KH |
1697 | match = (tags << 28) | (sync << 8) | ctx->base.channel; |
1698 | if (cycle >= 0) { | |
1699 | match |= (cycle & 0x07fff) << 12; | |
1700 | control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; | |
1701 | } | |
ed568912 | 1702 | |
295e3feb KH |
1703 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
1704 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
a77754a7 | 1705 | reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); |
8a2f7d93 | 1706 | context_run(&ctx->context, control); |
295e3feb | 1707 | } |
ed568912 KH |
1708 | |
1709 | return 0; | |
1710 | } | |
1711 | ||
b8295668 KH |
1712 | static int ohci_stop_iso(struct fw_iso_context *base) |
1713 | { | |
1714 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1715 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
b8295668 KH |
1716 | int index; |
1717 | ||
1718 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1719 | index = ctx - ohci->it_context_list; | |
1720 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
1721 | } else { | |
1722 | index = ctx - ohci->ir_context_list; | |
1723 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
1724 | } | |
1725 | flush_writes(ohci); | |
1726 | context_stop(&ctx->context); | |
1727 | ||
1728 | return 0; | |
1729 | } | |
1730 | ||
ed568912 KH |
1731 | static void ohci_free_iso_context(struct fw_iso_context *base) |
1732 | { | |
1733 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1734 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
1735 | unsigned long flags; |
1736 | int index; | |
1737 | ||
b8295668 KH |
1738 | ohci_stop_iso(base); |
1739 | context_release(&ctx->context); | |
9b32d5f3 | 1740 | free_page((unsigned long)ctx->header); |
b8295668 | 1741 | |
ed568912 KH |
1742 | spin_lock_irqsave(&ohci->lock, flags); |
1743 | ||
1744 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1745 | index = ctx - ohci->it_context_list; | |
ed568912 KH |
1746 | ohci->it_context_mask |= 1 << index; |
1747 | } else { | |
1748 | index = ctx - ohci->ir_context_list; | |
ed568912 KH |
1749 | ohci->ir_context_mask |= 1 << index; |
1750 | } | |
ed568912 KH |
1751 | |
1752 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1753 | } | |
1754 | ||
1755 | static int | |
295e3feb KH |
1756 | ohci_queue_iso_transmit(struct fw_iso_context *base, |
1757 | struct fw_iso_packet *packet, | |
1758 | struct fw_iso_buffer *buffer, | |
1759 | unsigned long payload) | |
ed568912 | 1760 | { |
373b2edd | 1761 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1762 | struct descriptor *d, *last, *pd; |
ed568912 KH |
1763 | struct fw_iso_packet *p; |
1764 | __le32 *header; | |
9aad8125 | 1765 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
1766 | u32 z, header_z, payload_z, irq; |
1767 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 1768 | int page, end_page, i, length, offset; |
ed568912 | 1769 | |
c781c06d KH |
1770 | /* |
1771 | * FIXME: Cycle lost behavior should be configurable: lose | |
1772 | * packet, retransmit or terminate.. | |
1773 | */ | |
ed568912 KH |
1774 | |
1775 | p = packet; | |
9aad8125 | 1776 | payload_index = payload; |
ed568912 KH |
1777 | |
1778 | if (p->skip) | |
1779 | z = 1; | |
1780 | else | |
1781 | z = 2; | |
1782 | if (p->header_length > 0) | |
1783 | z++; | |
1784 | ||
1785 | /* Determine the first page the payload isn't contained in. */ | |
1786 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
1787 | if (p->payload_length > 0) | |
1788 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
1789 | else | |
1790 | payload_z = 0; | |
1791 | ||
1792 | z += payload_z; | |
1793 | ||
1794 | /* Get header size in number of descriptors. */ | |
2d826cc5 | 1795 | header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); |
ed568912 | 1796 | |
30200739 KH |
1797 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
1798 | if (d == NULL) | |
1799 | return -ENOMEM; | |
ed568912 KH |
1800 | |
1801 | if (!p->skip) { | |
a77754a7 | 1802 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
ed568912 KH |
1803 | d[0].req_count = cpu_to_le16(8); |
1804 | ||
1805 | header = (__le32 *) &d[1]; | |
a77754a7 KH |
1806 | header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | |
1807 | IT_HEADER_TAG(p->tag) | | |
1808 | IT_HEADER_TCODE(TCODE_STREAM_DATA) | | |
1809 | IT_HEADER_CHANNEL(ctx->base.channel) | | |
1810 | IT_HEADER_SPEED(ctx->base.speed)); | |
ed568912 | 1811 | header[1] = |
a77754a7 | 1812 | cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + |
ed568912 KH |
1813 | p->payload_length)); |
1814 | } | |
1815 | ||
1816 | if (p->header_length > 0) { | |
1817 | d[2].req_count = cpu_to_le16(p->header_length); | |
2d826cc5 | 1818 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); |
ed568912 KH |
1819 | memcpy(&d[z], p->header, p->header_length); |
1820 | } | |
1821 | ||
1822 | pd = d + z - payload_z; | |
1823 | payload_end_index = payload_index + p->payload_length; | |
1824 | for (i = 0; i < payload_z; i++) { | |
1825 | page = payload_index >> PAGE_SHIFT; | |
1826 | offset = payload_index & ~PAGE_MASK; | |
1827 | next_page_index = (page + 1) << PAGE_SHIFT; | |
1828 | length = | |
1829 | min(next_page_index, payload_end_index) - payload_index; | |
1830 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
1831 | |
1832 | page_bus = page_private(buffer->pages[page]); | |
1833 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
1834 | |
1835 | payload_index += length; | |
1836 | } | |
1837 | ||
ed568912 | 1838 | if (p->interrupt) |
a77754a7 | 1839 | irq = DESCRIPTOR_IRQ_ALWAYS; |
ed568912 | 1840 | else |
a77754a7 | 1841 | irq = DESCRIPTOR_NO_IRQ; |
ed568912 | 1842 | |
30200739 | 1843 | last = z == 2 ? d : d + z - 1; |
a77754a7 KH |
1844 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
1845 | DESCRIPTOR_STATUS | | |
1846 | DESCRIPTOR_BRANCH_ALWAYS | | |
cbb59da7 | 1847 | irq); |
ed568912 | 1848 | |
30200739 | 1849 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
1850 | |
1851 | return 0; | |
1852 | } | |
373b2edd | 1853 | |
295e3feb | 1854 | static int |
d2746dc1 KH |
1855 | ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base, |
1856 | struct fw_iso_packet *packet, | |
1857 | struct fw_iso_buffer *buffer, | |
1858 | unsigned long payload) | |
295e3feb KH |
1859 | { |
1860 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
1861 | struct db_descriptor *db = NULL; | |
1862 | struct descriptor *d; | |
1863 | struct fw_iso_packet *p; | |
1864 | dma_addr_t d_bus, page_bus; | |
1865 | u32 z, header_z, length, rest; | |
c70dc788 | 1866 | int page, offset, packet_count, header_size; |
373b2edd | 1867 | |
c781c06d KH |
1868 | /* |
1869 | * FIXME: Cycle lost behavior should be configurable: lose | |
1870 | * packet, retransmit or terminate.. | |
1871 | */ | |
295e3feb KH |
1872 | |
1873 | p = packet; | |
1874 | z = 2; | |
1875 | ||
c781c06d KH |
1876 | /* |
1877 | * The OHCI controller puts the status word in the header | |
1878 | * buffer too, so we need 4 extra bytes per packet. | |
1879 | */ | |
c70dc788 KH |
1880 | packet_count = p->header_length / ctx->base.header_size; |
1881 | header_size = packet_count * (ctx->base.header_size + 4); | |
1882 | ||
295e3feb | 1883 | /* Get header size in number of descriptors. */ |
2d826cc5 | 1884 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); |
295e3feb KH |
1885 | page = payload >> PAGE_SHIFT; |
1886 | offset = payload & ~PAGE_MASK; | |
1887 | rest = p->payload_length; | |
1888 | ||
295e3feb KH |
1889 | /* FIXME: make packet-per-buffer/dual-buffer a context option */ |
1890 | while (rest > 0) { | |
1891 | d = context_get_descriptors(&ctx->context, | |
1892 | z + header_z, &d_bus); | |
1893 | if (d == NULL) | |
1894 | return -ENOMEM; | |
1895 | ||
1896 | db = (struct db_descriptor *) d; | |
a77754a7 KH |
1897 | db->control = cpu_to_le16(DESCRIPTOR_STATUS | |
1898 | DESCRIPTOR_BRANCH_ALWAYS); | |
c70dc788 | 1899 | db->first_size = cpu_to_le16(ctx->base.header_size + 4); |
0642b657 DM |
1900 | if (p->skip && rest == p->payload_length) { |
1901 | db->control |= cpu_to_le16(DESCRIPTOR_WAIT); | |
1902 | db->first_req_count = db->first_size; | |
1903 | } else { | |
1904 | db->first_req_count = cpu_to_le16(header_size); | |
1905 | } | |
1e1d196b | 1906 | db->first_res_count = db->first_req_count; |
2d826cc5 | 1907 | db->first_buffer = cpu_to_le32(d_bus + sizeof(*db)); |
373b2edd | 1908 | |
0642b657 DM |
1909 | if (p->skip && rest == p->payload_length) |
1910 | length = 4; | |
1911 | else if (offset + rest < PAGE_SIZE) | |
295e3feb KH |
1912 | length = rest; |
1913 | else | |
1914 | length = PAGE_SIZE - offset; | |
1915 | ||
1e1d196b KH |
1916 | db->second_req_count = cpu_to_le16(length); |
1917 | db->second_res_count = db->second_req_count; | |
295e3feb KH |
1918 | page_bus = page_private(buffer->pages[page]); |
1919 | db->second_buffer = cpu_to_le32(page_bus + offset); | |
1920 | ||
cb2d2cdb | 1921 | if (p->interrupt && length == rest) |
a77754a7 | 1922 | db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
cb2d2cdb | 1923 | |
295e3feb KH |
1924 | context_append(&ctx->context, d, z, header_z); |
1925 | offset = (offset + length) & ~PAGE_MASK; | |
1926 | rest -= length; | |
0642b657 DM |
1927 | if (offset == 0) |
1928 | page++; | |
295e3feb KH |
1929 | } |
1930 | ||
d2746dc1 KH |
1931 | return 0; |
1932 | } | |
21efb3cf | 1933 | |
a186b4a6 JW |
1934 | static int |
1935 | ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base, | |
1936 | struct fw_iso_packet *packet, | |
1937 | struct fw_iso_buffer *buffer, | |
1938 | unsigned long payload) | |
1939 | { | |
1940 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
1941 | struct descriptor *d = NULL, *pd = NULL; | |
bcee893c | 1942 | struct fw_iso_packet *p = packet; |
a186b4a6 JW |
1943 | dma_addr_t d_bus, page_bus; |
1944 | u32 z, header_z, rest; | |
bcee893c DM |
1945 | int i, j, length; |
1946 | int page, offset, packet_count, header_size, payload_per_buffer; | |
a186b4a6 JW |
1947 | |
1948 | /* | |
1949 | * The OHCI controller puts the status word in the | |
1950 | * buffer too, so we need 4 extra bytes per packet. | |
1951 | */ | |
1952 | packet_count = p->header_length / ctx->base.header_size; | |
bcee893c | 1953 | header_size = ctx->base.header_size + 4; |
a186b4a6 JW |
1954 | |
1955 | /* Get header size in number of descriptors. */ | |
1956 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); | |
1957 | page = payload >> PAGE_SHIFT; | |
1958 | offset = payload & ~PAGE_MASK; | |
bcee893c | 1959 | payload_per_buffer = p->payload_length / packet_count; |
a186b4a6 JW |
1960 | |
1961 | for (i = 0; i < packet_count; i++) { | |
1962 | /* d points to the header descriptor */ | |
bcee893c | 1963 | z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; |
a186b4a6 | 1964 | d = context_get_descriptors(&ctx->context, |
bcee893c | 1965 | z + header_z, &d_bus); |
a186b4a6 JW |
1966 | if (d == NULL) |
1967 | return -ENOMEM; | |
1968 | ||
bcee893c DM |
1969 | d->control = cpu_to_le16(DESCRIPTOR_STATUS | |
1970 | DESCRIPTOR_INPUT_MORE); | |
1971 | if (p->skip && i == 0) | |
1972 | d->control |= cpu_to_le16(DESCRIPTOR_WAIT); | |
a186b4a6 JW |
1973 | d->req_count = cpu_to_le16(header_size); |
1974 | d->res_count = d->req_count; | |
bcee893c | 1975 | d->transfer_status = 0; |
a186b4a6 JW |
1976 | d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); |
1977 | ||
bcee893c DM |
1978 | rest = payload_per_buffer; |
1979 | for (j = 1; j < z; j++) { | |
1980 | pd = d + j; | |
1981 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | | |
1982 | DESCRIPTOR_INPUT_MORE); | |
1983 | ||
1984 | if (offset + rest < PAGE_SIZE) | |
1985 | length = rest; | |
1986 | else | |
1987 | length = PAGE_SIZE - offset; | |
1988 | pd->req_count = cpu_to_le16(length); | |
1989 | pd->res_count = pd->req_count; | |
1990 | pd->transfer_status = 0; | |
1991 | ||
1992 | page_bus = page_private(buffer->pages[page]); | |
1993 | pd->data_address = cpu_to_le32(page_bus + offset); | |
1994 | ||
1995 | offset = (offset + length) & ~PAGE_MASK; | |
1996 | rest -= length; | |
1997 | if (offset == 0) | |
1998 | page++; | |
1999 | } | |
a186b4a6 JW |
2000 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2001 | DESCRIPTOR_INPUT_LAST | | |
2002 | DESCRIPTOR_BRANCH_ALWAYS); | |
bcee893c | 2003 | if (p->interrupt && i == packet_count - 1) |
a186b4a6 JW |
2004 | pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
2005 | ||
a186b4a6 JW |
2006 | context_append(&ctx->context, d, z, header_z); |
2007 | } | |
2008 | ||
2009 | return 0; | |
2010 | } | |
2011 | ||
295e3feb KH |
2012 | static int |
2013 | ohci_queue_iso(struct fw_iso_context *base, | |
2014 | struct fw_iso_packet *packet, | |
2015 | struct fw_iso_buffer *buffer, | |
2016 | unsigned long payload) | |
2017 | { | |
e364cf4e | 2018 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
fe5ca634 DM |
2019 | unsigned long flags; |
2020 | int retval; | |
e364cf4e | 2021 | |
fe5ca634 | 2022 | spin_lock_irqsave(&ctx->context.ohci->lock, flags); |
295e3feb | 2023 | if (base->type == FW_ISO_CONTEXT_TRANSMIT) |
fe5ca634 | 2024 | retval = ohci_queue_iso_transmit(base, packet, buffer, payload); |
e364cf4e | 2025 | else if (ctx->context.ohci->version >= OHCI_VERSION_1_1) |
fe5ca634 | 2026 | retval = ohci_queue_iso_receive_dualbuffer(base, packet, |
d2746dc1 | 2027 | buffer, payload); |
e364cf4e | 2028 | else |
fe5ca634 | 2029 | retval = ohci_queue_iso_receive_packet_per_buffer(base, packet, |
a186b4a6 JW |
2030 | buffer, |
2031 | payload); | |
fe5ca634 DM |
2032 | spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); |
2033 | ||
2034 | return retval; | |
295e3feb KH |
2035 | } |
2036 | ||
21ebcd12 | 2037 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
2038 | .name = ohci_driver_name, |
2039 | .enable = ohci_enable, | |
2040 | .update_phy_reg = ohci_update_phy_reg, | |
2041 | .set_config_rom = ohci_set_config_rom, | |
2042 | .send_request = ohci_send_request, | |
2043 | .send_response = ohci_send_response, | |
730c32f5 | 2044 | .cancel_packet = ohci_cancel_packet, |
ed568912 | 2045 | .enable_phys_dma = ohci_enable_phys_dma, |
d60d7f1d | 2046 | .get_bus_time = ohci_get_bus_time, |
ed568912 KH |
2047 | |
2048 | .allocate_iso_context = ohci_allocate_iso_context, | |
2049 | .free_iso_context = ohci_free_iso_context, | |
2050 | .queue_iso = ohci_queue_iso, | |
69cdb726 | 2051 | .start_iso = ohci_start_iso, |
b8295668 | 2052 | .stop_iso = ohci_stop_iso, |
ed568912 KH |
2053 | }; |
2054 | ||
ed568912 KH |
2055 | static int __devinit |
2056 | pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |
2057 | { | |
2058 | struct fw_ohci *ohci; | |
e364cf4e | 2059 | u32 bus_options, max_receive, link_speed; |
ed568912 | 2060 | u64 guid; |
d79406dd | 2061 | int err; |
ed568912 KH |
2062 | size_t size; |
2063 | ||
ea8d006b SR |
2064 | #ifdef CONFIG_PPC_PMAC |
2065 | /* Necessary on some machines if fw-ohci was loaded/ unloaded before */ | |
2066 | if (machine_is(powermac)) { | |
2067 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2068 | ||
2069 | if (ofn) { | |
2070 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); | |
2071 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); | |
2072 | } | |
2073 | } | |
2074 | #endif /* CONFIG_PPC_PMAC */ | |
2075 | ||
2d826cc5 | 2076 | ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); |
ed568912 KH |
2077 | if (ohci == NULL) { |
2078 | fw_error("Could not malloc fw_ohci data.\n"); | |
2079 | return -ENOMEM; | |
2080 | } | |
2081 | ||
2082 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
2083 | ||
d79406dd KH |
2084 | err = pci_enable_device(dev); |
2085 | if (err) { | |
ed568912 | 2086 | fw_error("Failed to enable OHCI hardware.\n"); |
d79406dd | 2087 | goto fail_put_card; |
ed568912 KH |
2088 | } |
2089 | ||
2090 | pci_set_master(dev); | |
2091 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
2092 | pci_set_drvdata(dev, ohci); | |
2093 | ||
11bf20ad SR |
2094 | #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) |
2095 | ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE && | |
2096 | dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW; | |
2097 | #endif | |
ed568912 KH |
2098 | spin_lock_init(&ohci->lock); |
2099 | ||
2100 | tasklet_init(&ohci->bus_reset_tasklet, | |
2101 | bus_reset_tasklet, (unsigned long)ohci); | |
2102 | ||
d79406dd KH |
2103 | err = pci_request_region(dev, 0, ohci_driver_name); |
2104 | if (err) { | |
ed568912 | 2105 | fw_error("MMIO resource unavailable\n"); |
d79406dd | 2106 | goto fail_disable; |
ed568912 KH |
2107 | } |
2108 | ||
2109 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
2110 | if (ohci->registers == NULL) { | |
2111 | fw_error("Failed to remap registers\n"); | |
d79406dd KH |
2112 | err = -ENXIO; |
2113 | goto fail_iomem; | |
ed568912 KH |
2114 | } |
2115 | ||
ed568912 KH |
2116 | ar_context_init(&ohci->ar_request_ctx, ohci, |
2117 | OHCI1394_AsReqRcvContextControlSet); | |
2118 | ||
2119 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
2120 | OHCI1394_AsRspRcvContextControlSet); | |
2121 | ||
fe5ca634 | 2122 | context_init(&ohci->at_request_ctx, ohci, |
f319b6a0 | 2123 | OHCI1394_AsReqTrContextControlSet, handle_at_packet); |
ed568912 | 2124 | |
fe5ca634 | 2125 | context_init(&ohci->at_response_ctx, ohci, |
f319b6a0 | 2126 | OHCI1394_AsRspTrContextControlSet, handle_at_packet); |
ed568912 | 2127 | |
ed568912 KH |
2128 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); |
2129 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
2130 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
2131 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
2132 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
2133 | ||
2134 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
2135 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); | |
2136 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
2137 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
2138 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
2139 | ||
2140 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
2141 | fw_error("Out of memory for it/ir contexts.\n"); | |
d79406dd KH |
2142 | err = -ENOMEM; |
2143 | goto fail_registers; | |
ed568912 KH |
2144 | } |
2145 | ||
2146 | /* self-id dma buffer allocation */ | |
2147 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
2148 | SELF_ID_BUF_SIZE, | |
2149 | &ohci->self_id_bus, | |
2150 | GFP_KERNEL); | |
2151 | if (ohci->self_id_cpu == NULL) { | |
2152 | fw_error("Out of memory for self ID buffer.\n"); | |
d79406dd KH |
2153 | err = -ENOMEM; |
2154 | goto fail_registers; | |
ed568912 KH |
2155 | } |
2156 | ||
ed568912 KH |
2157 | bus_options = reg_read(ohci, OHCI1394_BusOptions); |
2158 | max_receive = (bus_options >> 12) & 0xf; | |
2159 | link_speed = bus_options & 0x7; | |
2160 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
2161 | reg_read(ohci, OHCI1394_GUIDLo); | |
2162 | ||
d79406dd KH |
2163 | err = fw_card_add(&ohci->card, max_receive, link_speed, guid); |
2164 | if (err < 0) | |
2165 | goto fail_self_id; | |
ed568912 | 2166 | |
e364cf4e | 2167 | ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
500be725 | 2168 | fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n", |
e364cf4e | 2169 | dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff); |
ed568912 | 2170 | return 0; |
d79406dd KH |
2171 | |
2172 | fail_self_id: | |
2173 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
2174 | ohci->self_id_cpu, ohci->self_id_bus); | |
2175 | fail_registers: | |
2176 | kfree(ohci->it_context_list); | |
2177 | kfree(ohci->ir_context_list); | |
2178 | pci_iounmap(dev, ohci->registers); | |
2179 | fail_iomem: | |
2180 | pci_release_region(dev, 0); | |
2181 | fail_disable: | |
2182 | pci_disable_device(dev); | |
2183 | fail_put_card: | |
2184 | fw_card_put(&ohci->card); | |
2185 | ||
2186 | return err; | |
ed568912 KH |
2187 | } |
2188 | ||
2189 | static void pci_remove(struct pci_dev *dev) | |
2190 | { | |
2191 | struct fw_ohci *ohci; | |
2192 | ||
2193 | ohci = pci_get_drvdata(dev); | |
e254a4b4 KH |
2194 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); |
2195 | flush_writes(ohci); | |
ed568912 KH |
2196 | fw_core_remove_card(&ohci->card); |
2197 | ||
c781c06d KH |
2198 | /* |
2199 | * FIXME: Fail all pending packets here, now that the upper | |
2200 | * layers can't queue any more. | |
2201 | */ | |
ed568912 KH |
2202 | |
2203 | software_reset(ohci); | |
2204 | free_irq(dev->irq, ohci); | |
d79406dd KH |
2205 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, |
2206 | ohci->self_id_cpu, ohci->self_id_bus); | |
2207 | kfree(ohci->it_context_list); | |
2208 | kfree(ohci->ir_context_list); | |
2209 | pci_iounmap(dev, ohci->registers); | |
2210 | pci_release_region(dev, 0); | |
2211 | pci_disable_device(dev); | |
2212 | fw_card_put(&ohci->card); | |
ed568912 | 2213 | |
ea8d006b SR |
2214 | #ifdef CONFIG_PPC_PMAC |
2215 | /* On UniNorth, power down the cable and turn off the chip clock | |
2216 | * to save power on laptops */ | |
2217 | if (machine_is(powermac)) { | |
2218 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2219 | ||
2220 | if (ofn) { | |
2221 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); | |
2222 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); | |
2223 | } | |
2224 | } | |
2225 | #endif /* CONFIG_PPC_PMAC */ | |
2226 | ||
ed568912 KH |
2227 | fw_notify("Removed fw-ohci device.\n"); |
2228 | } | |
2229 | ||
2aef469a KH |
2230 | #ifdef CONFIG_PM |
2231 | static int pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
2232 | { | |
2233 | struct fw_ohci *ohci = pci_get_drvdata(pdev); | |
2234 | int err; | |
2235 | ||
2236 | software_reset(ohci); | |
2237 | free_irq(pdev->irq, ohci); | |
2238 | err = pci_save_state(pdev); | |
2239 | if (err) { | |
8a8cea27 | 2240 | fw_error("pci_save_state failed\n"); |
2aef469a KH |
2241 | return err; |
2242 | } | |
2243 | err = pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
55111428 SR |
2244 | if (err) |
2245 | fw_error("pci_set_power_state failed with %d\n", err); | |
2aef469a | 2246 | |
ea8d006b SR |
2247 | /* PowerMac suspend code comes last */ |
2248 | #ifdef CONFIG_PPC_PMAC | |
2249 | if (machine_is(powermac)) { | |
2250 | struct device_node *ofn = pci_device_to_OF_node(pdev); | |
2251 | ||
2252 | if (ofn) | |
2253 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); | |
2254 | } | |
2255 | #endif /* CONFIG_PPC_PMAC */ | |
2256 | ||
2aef469a KH |
2257 | return 0; |
2258 | } | |
2259 | ||
2260 | static int pci_resume(struct pci_dev *pdev) | |
2261 | { | |
2262 | struct fw_ohci *ohci = pci_get_drvdata(pdev); | |
2263 | int err; | |
2264 | ||
ea8d006b SR |
2265 | /* PowerMac resume code comes first */ |
2266 | #ifdef CONFIG_PPC_PMAC | |
2267 | if (machine_is(powermac)) { | |
2268 | struct device_node *ofn = pci_device_to_OF_node(pdev); | |
2269 | ||
2270 | if (ofn) | |
2271 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); | |
2272 | } | |
2273 | #endif /* CONFIG_PPC_PMAC */ | |
2274 | ||
2aef469a KH |
2275 | pci_set_power_state(pdev, PCI_D0); |
2276 | pci_restore_state(pdev); | |
2277 | err = pci_enable_device(pdev); | |
2278 | if (err) { | |
8a8cea27 | 2279 | fw_error("pci_enable_device failed\n"); |
2aef469a KH |
2280 | return err; |
2281 | } | |
2282 | ||
0bd243c4 | 2283 | return ohci_enable(&ohci->card, NULL, 0); |
2aef469a KH |
2284 | } |
2285 | #endif | |
2286 | ||
ed568912 KH |
2287 | static struct pci_device_id pci_table[] = { |
2288 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
2289 | { } | |
2290 | }; | |
2291 | ||
2292 | MODULE_DEVICE_TABLE(pci, pci_table); | |
2293 | ||
2294 | static struct pci_driver fw_ohci_pci_driver = { | |
2295 | .name = ohci_driver_name, | |
2296 | .id_table = pci_table, | |
2297 | .probe = pci_probe, | |
2298 | .remove = pci_remove, | |
2aef469a KH |
2299 | #ifdef CONFIG_PM |
2300 | .resume = pci_resume, | |
2301 | .suspend = pci_suspend, | |
2302 | #endif | |
ed568912 KH |
2303 | }; |
2304 | ||
2305 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
2306 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
2307 | MODULE_LICENSE("GPL"); | |
2308 | ||
1e4c7b0d OH |
2309 | /* Provide a module alias so root-on-sbp2 initrds don't break. */ |
2310 | #ifndef CONFIG_IEEE1394_OHCI1394_MODULE | |
2311 | MODULE_ALIAS("ohci1394"); | |
2312 | #endif | |
2313 | ||
ed568912 KH |
2314 | static int __init fw_ohci_init(void) |
2315 | { | |
2316 | return pci_register_driver(&fw_ohci_pci_driver); | |
2317 | } | |
2318 | ||
2319 | static void __exit fw_ohci_cleanup(void) | |
2320 | { | |
2321 | pci_unregister_driver(&fw_ohci_pci_driver); | |
2322 | } | |
2323 | ||
2324 | module_init(fw_ohci_init); | |
2325 | module_exit(fw_ohci_cleanup); |