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ed568912 KH |
1 | /* -*- c-basic-offset: 8 -*- |
2 | * | |
3 | * fw-ohci.c - Driver for OHCI 1394 boards | |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/poll.h> | |
cf3e72fd AM |
28 | #include <linux/dma-mapping.h> |
29 | ||
ed568912 KH |
30 | #include <asm/uaccess.h> |
31 | #include <asm/semaphore.h> | |
32 | ||
33 | #include "fw-transaction.h" | |
34 | #include "fw-ohci.h" | |
35 | ||
36 | #define descriptor_output_more 0 | |
37 | #define descriptor_output_last (1 << 12) | |
38 | #define descriptor_input_more (2 << 12) | |
39 | #define descriptor_input_last (3 << 12) | |
40 | #define descriptor_status (1 << 11) | |
41 | #define descriptor_key_immediate (2 << 8) | |
42 | #define descriptor_ping (1 << 7) | |
43 | #define descriptor_yy (1 << 6) | |
44 | #define descriptor_no_irq (0 << 4) | |
45 | #define descriptor_irq_error (1 << 4) | |
46 | #define descriptor_irq_always (3 << 4) | |
47 | #define descriptor_branch_always (3 << 2) | |
295e3feb | 48 | #define descriptor_wait (3 << 0) |
ed568912 KH |
49 | |
50 | struct descriptor { | |
51 | __le16 req_count; | |
52 | __le16 control; | |
53 | __le32 data_address; | |
54 | __le32 branch_address; | |
55 | __le16 res_count; | |
56 | __le16 transfer_status; | |
57 | } __attribute__((aligned(16))); | |
58 | ||
295e3feb KH |
59 | struct db_descriptor { |
60 | __le16 first_size; | |
61 | __le16 control; | |
62 | __le16 second_req_count; | |
63 | __le16 first_req_count; | |
64 | __le32 branch_address; | |
65 | __le16 second_res_count; | |
66 | __le16 first_res_count; | |
67 | __le32 reserved0; | |
68 | __le32 first_buffer; | |
69 | __le32 second_buffer; | |
70 | __le32 reserved1; | |
71 | } __attribute__((aligned(16))); | |
72 | ||
72e318e0 KH |
73 | #define control_set(regs) (regs) |
74 | #define control_clear(regs) ((regs) + 4) | |
75 | #define command_ptr(regs) ((regs) + 12) | |
76 | #define context_match(regs) ((regs) + 16) | |
77 | ||
32b46093 | 78 | struct ar_buffer { |
ed568912 | 79 | struct descriptor descriptor; |
32b46093 KH |
80 | struct ar_buffer *next; |
81 | __le32 data[0]; | |
82 | }; | |
ed568912 | 83 | |
32b46093 KH |
84 | struct ar_context { |
85 | struct fw_ohci *ohci; | |
86 | struct ar_buffer *current_buffer; | |
87 | struct ar_buffer *last_buffer; | |
88 | void *pointer; | |
72e318e0 | 89 | u32 regs; |
ed568912 KH |
90 | struct tasklet_struct tasklet; |
91 | }; | |
92 | ||
30200739 KH |
93 | struct context; |
94 | ||
95 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
96 | struct descriptor *d, | |
97 | struct descriptor *last); | |
98 | struct context { | |
373b2edd | 99 | struct fw_ohci *ohci; |
30200739 | 100 | u32 regs; |
373b2edd | 101 | |
30200739 KH |
102 | struct descriptor *buffer; |
103 | dma_addr_t buffer_bus; | |
104 | size_t buffer_size; | |
105 | struct descriptor *head_descriptor; | |
106 | struct descriptor *tail_descriptor; | |
107 | struct descriptor *tail_descriptor_last; | |
108 | struct descriptor *prev_descriptor; | |
109 | ||
110 | descriptor_callback_t callback; | |
111 | ||
373b2edd | 112 | struct tasklet_struct tasklet; |
30200739 | 113 | }; |
30200739 | 114 | |
ed568912 KH |
115 | #define it_header_sy(v) ((v) << 0) |
116 | #define it_header_tcode(v) ((v) << 4) | |
117 | #define it_header_channel(v) ((v) << 8) | |
118 | #define it_header_tag(v) ((v) << 14) | |
119 | #define it_header_speed(v) ((v) << 16) | |
120 | #define it_header_data_length(v) ((v) << 16) | |
121 | ||
122 | struct iso_context { | |
123 | struct fw_iso_context base; | |
30200739 | 124 | struct context context; |
9b32d5f3 KH |
125 | void *header; |
126 | size_t header_length; | |
ed568912 KH |
127 | }; |
128 | ||
129 | #define CONFIG_ROM_SIZE 1024 | |
130 | ||
131 | struct fw_ohci { | |
132 | struct fw_card card; | |
133 | ||
e364cf4e | 134 | u32 version; |
ed568912 KH |
135 | __iomem char *registers; |
136 | dma_addr_t self_id_bus; | |
137 | __le32 *self_id_cpu; | |
138 | struct tasklet_struct bus_reset_tasklet; | |
e636fe25 | 139 | int node_id; |
ed568912 KH |
140 | int generation; |
141 | int request_generation; | |
142 | ||
143 | /* Spinlock for accessing fw_ohci data. Never call out of | |
144 | * this driver with this lock held. */ | |
145 | spinlock_t lock; | |
146 | u32 self_id_buffer[512]; | |
147 | ||
148 | /* Config rom buffers */ | |
149 | __be32 *config_rom; | |
150 | dma_addr_t config_rom_bus; | |
151 | __be32 *next_config_rom; | |
152 | dma_addr_t next_config_rom_bus; | |
153 | u32 next_header; | |
154 | ||
155 | struct ar_context ar_request_ctx; | |
156 | struct ar_context ar_response_ctx; | |
f319b6a0 KH |
157 | struct context at_request_ctx; |
158 | struct context at_response_ctx; | |
ed568912 KH |
159 | |
160 | u32 it_context_mask; | |
161 | struct iso_context *it_context_list; | |
162 | u32 ir_context_mask; | |
163 | struct iso_context *ir_context_list; | |
164 | }; | |
165 | ||
95688e97 | 166 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
167 | { |
168 | return container_of(card, struct fw_ohci, card); | |
169 | } | |
170 | ||
295e3feb KH |
171 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
172 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
173 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
174 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
175 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
176 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
177 | |
178 | #define CONTEXT_RUN 0x8000 | |
179 | #define CONTEXT_WAKE 0x1000 | |
180 | #define CONTEXT_DEAD 0x0800 | |
181 | #define CONTEXT_ACTIVE 0x0400 | |
182 | ||
183 | #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 | |
184 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
185 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
186 | ||
187 | #define FW_OHCI_MAJOR 240 | |
188 | #define OHCI1394_REGISTER_SIZE 0x800 | |
189 | #define OHCI_LOOP_COUNT 500 | |
190 | #define OHCI1394_PCI_HCI_Control 0x40 | |
191 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 192 | #define OHCI_TCODE_PHY_PACKET 0x0e |
e364cf4e | 193 | #define OHCI_VERSION_1_1 0x010010 |
f319b6a0 KH |
194 | #define ISO_BUFFER_SIZE (64 * 1024) |
195 | #define AT_BUFFER_SIZE 4096 | |
0edeefd9 | 196 | |
ed568912 KH |
197 | static char ohci_driver_name[] = KBUILD_MODNAME; |
198 | ||
95688e97 | 199 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
200 | { |
201 | writel(data, ohci->registers + offset); | |
202 | } | |
203 | ||
95688e97 | 204 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
205 | { |
206 | return readl(ohci->registers + offset); | |
207 | } | |
208 | ||
95688e97 | 209 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
210 | { |
211 | /* Do a dummy read to flush writes. */ | |
212 | reg_read(ohci, OHCI1394_Version); | |
213 | } | |
214 | ||
215 | static int | |
216 | ohci_update_phy_reg(struct fw_card *card, int addr, | |
217 | int clear_bits, int set_bits) | |
218 | { | |
219 | struct fw_ohci *ohci = fw_ohci(card); | |
220 | u32 val, old; | |
221 | ||
222 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
223 | msleep(2); | |
224 | val = reg_read(ohci, OHCI1394_PhyControl); | |
225 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
226 | fw_error("failed to set phy reg bits.\n"); | |
227 | return -EBUSY; | |
228 | } | |
229 | ||
230 | old = OHCI1394_PhyControl_ReadData(val); | |
231 | old = (old & ~clear_bits) | set_bits; | |
232 | reg_write(ohci, OHCI1394_PhyControl, | |
233 | OHCI1394_PhyControl_Write(addr, old)); | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
32b46093 | 238 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 239 | { |
32b46093 KH |
240 | struct device *dev = ctx->ohci->card.device; |
241 | struct ar_buffer *ab; | |
242 | dma_addr_t ab_bus; | |
243 | size_t offset; | |
244 | ||
245 | ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC); | |
246 | if (ab == NULL) | |
247 | return -ENOMEM; | |
248 | ||
249 | ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
250 | if (dma_mapping_error(ab_bus)) { | |
251 | free_page((unsigned long) ab); | |
252 | return -ENOMEM; | |
253 | } | |
254 | ||
255 | memset(&ab->descriptor, 0, sizeof ab->descriptor); | |
256 | ab->descriptor.control = cpu_to_le16(descriptor_input_more | | |
257 | descriptor_status | | |
258 | descriptor_branch_always); | |
259 | offset = offsetof(struct ar_buffer, data); | |
260 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
261 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
262 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
263 | ab->descriptor.branch_address = 0; | |
264 | ||
265 | dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
266 | ||
267 | ctx->last_buffer->descriptor.branch_address = ab_bus | 1; | |
268 | ctx->last_buffer->next = ab; | |
269 | ctx->last_buffer = ab; | |
270 | ||
72e318e0 | 271 | reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE); |
ed568912 | 272 | flush_writes(ctx->ohci); |
32b46093 KH |
273 | |
274 | return 0; | |
ed568912 KH |
275 | } |
276 | ||
32b46093 | 277 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 278 | { |
ed568912 | 279 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
280 | struct fw_packet p; |
281 | u32 status, length, tcode; | |
2639a6fb | 282 | |
32b46093 KH |
283 | p.header[0] = le32_to_cpu(buffer[0]); |
284 | p.header[1] = le32_to_cpu(buffer[1]); | |
285 | p.header[2] = le32_to_cpu(buffer[2]); | |
2639a6fb KH |
286 | |
287 | tcode = (p.header[0] >> 4) & 0x0f; | |
288 | switch (tcode) { | |
289 | case TCODE_WRITE_QUADLET_REQUEST: | |
290 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 291 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 292 | p.header_length = 16; |
32b46093 | 293 | p.payload_length = 0; |
2639a6fb KH |
294 | break; |
295 | ||
2639a6fb | 296 | case TCODE_READ_BLOCK_REQUEST : |
32b46093 KH |
297 | p.header[3] = le32_to_cpu(buffer[3]); |
298 | p.header_length = 16; | |
299 | p.payload_length = 0; | |
300 | break; | |
301 | ||
302 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
303 | case TCODE_READ_BLOCK_RESPONSE: |
304 | case TCODE_LOCK_REQUEST: | |
305 | case TCODE_LOCK_RESPONSE: | |
32b46093 | 306 | p.header[3] = le32_to_cpu(buffer[3]); |
2639a6fb | 307 | p.header_length = 16; |
32b46093 | 308 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
309 | break; |
310 | ||
311 | case TCODE_WRITE_RESPONSE: | |
312 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 313 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 314 | p.header_length = 12; |
32b46093 | 315 | p.payload_length = 0; |
2639a6fb KH |
316 | break; |
317 | } | |
ed568912 | 318 | |
32b46093 KH |
319 | p.payload = (void *) buffer + p.header_length; |
320 | ||
321 | /* FIXME: What to do about evt_* errors? */ | |
322 | length = (p.header_length + p.payload_length + 3) / 4; | |
323 | status = le32_to_cpu(buffer[length]); | |
324 | ||
325 | p.ack = ((status >> 16) & 0x1f) - 16; | |
326 | p.speed = (status >> 21) & 0x7; | |
327 | p.timestamp = status & 0xffff; | |
328 | p.generation = ohci->request_generation; | |
ed568912 KH |
329 | |
330 | /* The OHCI bus reset handler synthesizes a phy packet with | |
331 | * the new generation number when a bus reset happens (see | |
332 | * section 8.4.2.3). This helps us determine when a request | |
333 | * was received and make sure we send the response in the same | |
334 | * generation. We only need this for requests; for responses | |
335 | * we use the unique tlabel for finding the matching | |
336 | * request. */ | |
337 | ||
2639a6fb | 338 | if (p.ack + 16 == 0x09) |
32b46093 | 339 | ohci->request_generation = (buffer[2] >> 16) & 0xff; |
ed568912 | 340 | else if (ctx == &ohci->ar_request_ctx) |
2639a6fb | 341 | fw_core_handle_request(&ohci->card, &p); |
ed568912 | 342 | else |
2639a6fb | 343 | fw_core_handle_response(&ohci->card, &p); |
ed568912 | 344 | |
32b46093 KH |
345 | return buffer + length + 1; |
346 | } | |
ed568912 | 347 | |
32b46093 KH |
348 | static void ar_context_tasklet(unsigned long data) |
349 | { | |
350 | struct ar_context *ctx = (struct ar_context *)data; | |
351 | struct fw_ohci *ohci = ctx->ohci; | |
352 | struct ar_buffer *ab; | |
353 | struct descriptor *d; | |
354 | void *buffer, *end; | |
355 | ||
356 | ab = ctx->current_buffer; | |
357 | d = &ab->descriptor; | |
358 | ||
359 | if (d->res_count == 0) { | |
360 | size_t size, rest, offset; | |
361 | ||
362 | /* This descriptor is finished and we may have a | |
363 | * packet split across this and the next buffer. We | |
364 | * reuse the page for reassembling the split packet. */ | |
365 | ||
366 | offset = offsetof(struct ar_buffer, data); | |
367 | dma_unmap_single(ohci->card.device, | |
368 | ab->descriptor.data_address - offset, | |
369 | PAGE_SIZE, DMA_BIDIRECTIONAL); | |
370 | ||
371 | buffer = ab; | |
372 | ab = ab->next; | |
373 | d = &ab->descriptor; | |
374 | size = buffer + PAGE_SIZE - ctx->pointer; | |
375 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
376 | memmove(buffer, ctx->pointer, size); | |
377 | memcpy(buffer + size, ab->data, rest); | |
378 | ctx->current_buffer = ab; | |
379 | ctx->pointer = (void *) ab->data + rest; | |
380 | end = buffer + size + rest; | |
381 | ||
382 | while (buffer < end) | |
383 | buffer = handle_ar_packet(ctx, buffer); | |
384 | ||
385 | free_page((unsigned long)buffer); | |
386 | ar_context_add_page(ctx); | |
387 | } else { | |
388 | buffer = ctx->pointer; | |
389 | ctx->pointer = end = | |
390 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
391 | ||
392 | while (buffer < end) | |
393 | buffer = handle_ar_packet(ctx, buffer); | |
394 | } | |
ed568912 KH |
395 | } |
396 | ||
397 | static int | |
72e318e0 | 398 | ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs) |
ed568912 | 399 | { |
32b46093 | 400 | struct ar_buffer ab; |
ed568912 | 401 | |
72e318e0 KH |
402 | ctx->regs = regs; |
403 | ctx->ohci = ohci; | |
404 | ctx->last_buffer = &ab; | |
ed568912 KH |
405 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
406 | ||
32b46093 KH |
407 | ar_context_add_page(ctx); |
408 | ar_context_add_page(ctx); | |
409 | ctx->current_buffer = ab.next; | |
410 | ctx->pointer = ctx->current_buffer->data; | |
411 | ||
72e318e0 KH |
412 | reg_write(ctx->ohci, command_ptr(ctx->regs), ab.descriptor.branch_address); |
413 | reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_RUN); | |
32b46093 | 414 | flush_writes(ctx->ohci); |
ed568912 KH |
415 | |
416 | return 0; | |
417 | } | |
373b2edd | 418 | |
30200739 KH |
419 | static void context_tasklet(unsigned long data) |
420 | { | |
421 | struct context *ctx = (struct context *) data; | |
422 | struct fw_ohci *ohci = ctx->ohci; | |
423 | struct descriptor *d, *last; | |
424 | u32 address; | |
425 | int z; | |
426 | ||
427 | dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus, | |
428 | ctx->buffer_size, DMA_TO_DEVICE); | |
429 | ||
430 | d = ctx->tail_descriptor; | |
431 | last = ctx->tail_descriptor_last; | |
432 | ||
433 | while (last->branch_address != 0) { | |
434 | address = le32_to_cpu(last->branch_address); | |
435 | z = address & 0xf; | |
436 | d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d; | |
437 | last = (z == 2) ? d : d + z - 1; | |
438 | ||
439 | if (!ctx->callback(ctx, d, last)) | |
440 | break; | |
441 | ||
442 | ctx->tail_descriptor = d; | |
443 | ctx->tail_descriptor_last = last; | |
444 | } | |
445 | } | |
446 | ||
447 | static int | |
448 | context_init(struct context *ctx, struct fw_ohci *ohci, | |
449 | size_t buffer_size, u32 regs, | |
450 | descriptor_callback_t callback) | |
451 | { | |
452 | ctx->ohci = ohci; | |
453 | ctx->regs = regs; | |
454 | ctx->buffer_size = buffer_size; | |
455 | ctx->buffer = kmalloc(buffer_size, GFP_KERNEL); | |
456 | if (ctx->buffer == NULL) | |
457 | return -ENOMEM; | |
458 | ||
459 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); | |
460 | ctx->callback = callback; | |
461 | ||
462 | ctx->buffer_bus = | |
463 | dma_map_single(ohci->card.device, ctx->buffer, | |
464 | buffer_size, DMA_TO_DEVICE); | |
465 | if (dma_mapping_error(ctx->buffer_bus)) { | |
466 | kfree(ctx->buffer); | |
467 | return -ENOMEM; | |
468 | } | |
469 | ||
470 | ctx->head_descriptor = ctx->buffer; | |
471 | ctx->prev_descriptor = ctx->buffer; | |
472 | ctx->tail_descriptor = ctx->buffer; | |
473 | ctx->tail_descriptor_last = ctx->buffer; | |
474 | ||
475 | /* We put a dummy descriptor in the buffer that has a NULL | |
476 | * branch address and looks like it's been sent. That way we | |
477 | * have a descriptor to append DMA programs to. Also, the | |
478 | * ring buffer invariant is that it always has at least one | |
479 | * element so that head == tail means buffer full. */ | |
480 | ||
481 | memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor); | |
482 | ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last); | |
483 | ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011); | |
484 | ctx->head_descriptor++; | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
9b32d5f3 | 489 | static void |
30200739 KH |
490 | context_release(struct context *ctx) |
491 | { | |
492 | struct fw_card *card = &ctx->ohci->card; | |
493 | ||
494 | dma_unmap_single(card->device, ctx->buffer_bus, | |
495 | ctx->buffer_size, DMA_TO_DEVICE); | |
496 | kfree(ctx->buffer); | |
497 | } | |
498 | ||
499 | static struct descriptor * | |
500 | context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus) | |
501 | { | |
502 | struct descriptor *d, *tail, *end; | |
503 | ||
504 | d = ctx->head_descriptor; | |
505 | tail = ctx->tail_descriptor; | |
506 | end = ctx->buffer + ctx->buffer_size / sizeof(struct descriptor); | |
507 | ||
508 | if (d + z <= tail) { | |
509 | goto has_space; | |
510 | } else if (d > tail && d + z <= end) { | |
511 | goto has_space; | |
512 | } else if (d > tail && ctx->buffer + z <= tail) { | |
513 | d = ctx->buffer; | |
514 | goto has_space; | |
515 | } | |
516 | ||
517 | return NULL; | |
518 | ||
519 | has_space: | |
520 | memset(d, 0, z * sizeof *d); | |
521 | *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d; | |
522 | ||
523 | return d; | |
524 | } | |
525 | ||
295e3feb | 526 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
527 | { |
528 | struct fw_ohci *ohci = ctx->ohci; | |
529 | ||
530 | reg_write(ohci, command_ptr(ctx->regs), | |
531 | le32_to_cpu(ctx->tail_descriptor_last->branch_address)); | |
532 | reg_write(ohci, control_clear(ctx->regs), ~0); | |
295e3feb | 533 | reg_write(ohci, control_set(ctx->regs), CONTEXT_RUN | extra); |
30200739 KH |
534 | flush_writes(ohci); |
535 | } | |
536 | ||
537 | static void context_append(struct context *ctx, | |
538 | struct descriptor *d, int z, int extra) | |
539 | { | |
540 | dma_addr_t d_bus; | |
541 | ||
542 | d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d; | |
543 | ||
544 | ctx->head_descriptor = d + z + extra; | |
545 | ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z); | |
546 | ctx->prev_descriptor = z == 2 ? d : d + z - 1; | |
547 | ||
548 | dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus, | |
549 | ctx->buffer_size, DMA_TO_DEVICE); | |
550 | ||
551 | reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE); | |
552 | flush_writes(ctx->ohci); | |
553 | } | |
554 | ||
555 | static void context_stop(struct context *ctx) | |
556 | { | |
557 | u32 reg; | |
b8295668 | 558 | int i; |
30200739 KH |
559 | |
560 | reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN); | |
b8295668 | 561 | flush_writes(ctx->ohci); |
30200739 | 562 | |
b8295668 KH |
563 | for (i = 0; i < 10; i++) { |
564 | reg = reg_read(ctx->ohci, control_set(ctx->regs)); | |
565 | if ((reg & CONTEXT_ACTIVE) == 0) | |
566 | break; | |
567 | ||
568 | fw_notify("context_stop: still active (0x%08x)\n", reg); | |
569 | msleep(1); | |
570 | } | |
30200739 | 571 | } |
ed568912 | 572 | |
f319b6a0 KH |
573 | struct driver_data { |
574 | struct fw_packet *packet; | |
575 | }; | |
ed568912 | 576 | |
f319b6a0 KH |
577 | /* This function apppends a packet to the DMA queue for transmission. |
578 | * Must always be called with the ochi->lock held to ensure proper | |
579 | * generation handling and locking around packet queue manipulation. */ | |
580 | static int | |
581 | at_context_queue_packet(struct context *ctx, struct fw_packet *packet) | |
ed568912 | 582 | { |
ed568912 | 583 | struct fw_ohci *ohci = ctx->ohci; |
f319b6a0 KH |
584 | dma_addr_t d_bus, payload_bus; |
585 | struct driver_data *driver_data; | |
586 | struct descriptor *d, *last; | |
587 | __le32 *header; | |
ed568912 | 588 | int z, tcode; |
f319b6a0 | 589 | u32 reg; |
ed568912 | 590 | |
f319b6a0 KH |
591 | d = context_get_descriptors(ctx, 4, &d_bus); |
592 | if (d == NULL) { | |
593 | packet->ack = RCODE_SEND_ERROR; | |
594 | return -1; | |
ed568912 KH |
595 | } |
596 | ||
f319b6a0 KH |
597 | d[0].control = cpu_to_le16(descriptor_key_immediate); |
598 | d[0].res_count = cpu_to_le16(packet->timestamp); | |
599 | ||
ed568912 KH |
600 | /* The DMA format for asyncronous link packets is different |
601 | * from the IEEE1394 layout, so shift the fields around | |
602 | * accordingly. If header_length is 8, it's a PHY packet, to | |
603 | * which we need to prepend an extra quadlet. */ | |
f319b6a0 KH |
604 | |
605 | header = (__le32 *) &d[1]; | |
ed568912 | 606 | if (packet->header_length > 8) { |
f319b6a0 KH |
607 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | |
608 | (packet->speed << 16)); | |
609 | header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
610 | (packet->header[0] & 0xffff0000)); | |
611 | header[2] = cpu_to_le32(packet->header[2]); | |
ed568912 KH |
612 | |
613 | tcode = (packet->header[0] >> 4) & 0x0f; | |
614 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
f319b6a0 | 615 | header[3] = cpu_to_le32(packet->header[3]); |
ed568912 | 616 | else |
f319b6a0 KH |
617 | header[3] = (__force __le32) packet->header[3]; |
618 | ||
619 | d[0].req_count = cpu_to_le16(packet->header_length); | |
ed568912 | 620 | } else { |
f319b6a0 KH |
621 | header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | |
622 | (packet->speed << 16)); | |
623 | header[1] = cpu_to_le32(packet->header[0]); | |
624 | header[2] = cpu_to_le32(packet->header[1]); | |
625 | d[0].req_count = cpu_to_le16(12); | |
ed568912 KH |
626 | } |
627 | ||
f319b6a0 KH |
628 | driver_data = (struct driver_data *) &d[3]; |
629 | driver_data->packet = packet; | |
630 | ||
631 | if (packet->payload_length > 0) { | |
632 | payload_bus = | |
633 | dma_map_single(ohci->card.device, packet->payload, | |
634 | packet->payload_length, DMA_TO_DEVICE); | |
635 | if (dma_mapping_error(payload_bus)) { | |
636 | packet->ack = RCODE_SEND_ERROR; | |
637 | return -1; | |
638 | } | |
639 | ||
640 | d[2].req_count = cpu_to_le16(packet->payload_length); | |
641 | d[2].data_address = cpu_to_le32(payload_bus); | |
642 | last = &d[2]; | |
643 | z = 3; | |
ed568912 | 644 | } else { |
f319b6a0 KH |
645 | last = &d[0]; |
646 | z = 2; | |
ed568912 | 647 | } |
ed568912 | 648 | |
f319b6a0 KH |
649 | last->control |= cpu_to_le16(descriptor_output_last | |
650 | descriptor_irq_always | | |
651 | descriptor_branch_always); | |
ed568912 | 652 | |
f319b6a0 KH |
653 | /* FIXME: Document how the locking works. */ |
654 | if (ohci->generation != packet->generation) { | |
655 | packet->ack = RCODE_GENERATION; | |
656 | return -1; | |
657 | } | |
658 | ||
659 | context_append(ctx, d, z, 4 - z); | |
ed568912 | 660 | |
f319b6a0 | 661 | /* If the context isn't already running, start it up. */ |
72e318e0 | 662 | reg = reg_read(ctx->ohci, control_set(ctx->regs)); |
f319b6a0 KH |
663 | if ((reg & CONTEXT_ACTIVE) == 0) |
664 | context_run(ctx, 0); | |
665 | ||
666 | return 0; | |
ed568912 KH |
667 | } |
668 | ||
f319b6a0 KH |
669 | static int handle_at_packet(struct context *context, |
670 | struct descriptor *d, | |
671 | struct descriptor *last) | |
ed568912 | 672 | { |
f319b6a0 | 673 | struct driver_data *driver_data; |
ed568912 | 674 | struct fw_packet *packet; |
f319b6a0 KH |
675 | struct fw_ohci *ohci = context->ohci; |
676 | dma_addr_t payload_bus; | |
ed568912 KH |
677 | int evt; |
678 | ||
f319b6a0 KH |
679 | if (last->transfer_status == 0) |
680 | /* This descriptor isn't done yet, stop iteration. */ | |
681 | return 0; | |
ed568912 | 682 | |
f319b6a0 KH |
683 | driver_data = (struct driver_data *) &d[3]; |
684 | packet = driver_data->packet; | |
685 | if (packet == NULL) | |
686 | /* This packet was cancelled, just continue. */ | |
687 | return 1; | |
730c32f5 | 688 | |
f319b6a0 KH |
689 | payload_bus = le32_to_cpu(last->data_address); |
690 | if (payload_bus != 0) | |
691 | dma_unmap_single(ohci->card.device, payload_bus, | |
ed568912 | 692 | packet->payload_length, DMA_TO_DEVICE); |
ed568912 | 693 | |
f319b6a0 KH |
694 | evt = le16_to_cpu(last->transfer_status) & 0x1f; |
695 | packet->timestamp = le16_to_cpu(last->res_count); | |
ed568912 | 696 | |
f319b6a0 KH |
697 | switch (evt) { |
698 | case OHCI1394_evt_timeout: | |
699 | /* Async response transmit timed out. */ | |
700 | packet->ack = RCODE_CANCELLED; | |
701 | break; | |
ed568912 | 702 | |
f319b6a0 KH |
703 | case OHCI1394_evt_flushed: |
704 | /* The packet was flushed should give same error as | |
705 | * when we try to use a stale generation count. */ | |
706 | packet->ack = RCODE_GENERATION; | |
707 | break; | |
ed568912 | 708 | |
f319b6a0 KH |
709 | case OHCI1394_evt_missing_ack: |
710 | /* Using a valid (current) generation count, but the | |
711 | * node is not on the bus or not sending acks. */ | |
712 | packet->ack = RCODE_NO_ACK; | |
713 | break; | |
ed568912 | 714 | |
f319b6a0 KH |
715 | case ACK_COMPLETE + 0x10: |
716 | case ACK_PENDING + 0x10: | |
717 | case ACK_BUSY_X + 0x10: | |
718 | case ACK_BUSY_A + 0x10: | |
719 | case ACK_BUSY_B + 0x10: | |
720 | case ACK_DATA_ERROR + 0x10: | |
721 | case ACK_TYPE_ERROR + 0x10: | |
722 | packet->ack = evt - 0x10; | |
723 | break; | |
ed568912 | 724 | |
f319b6a0 KH |
725 | default: |
726 | packet->ack = RCODE_SEND_ERROR; | |
727 | break; | |
728 | } | |
ed568912 | 729 | |
f319b6a0 | 730 | packet->callback(packet, &ohci->card, packet->ack); |
ed568912 | 731 | |
f319b6a0 | 732 | return 1; |
ed568912 KH |
733 | } |
734 | ||
e636fe25 | 735 | #define header_get_destination(q) (((q) >> 16) & 0xffff) |
93c4cceb KH |
736 | #define header_get_tcode(q) (((q) >> 4) & 0x0f) |
737 | #define header_get_offset_high(q) (((q) >> 0) & 0xffff) | |
738 | #define header_get_data_length(q) (((q) >> 16) & 0xffff) | |
739 | #define header_get_extended_tcode(q) (((q) >> 0) & 0xffff) | |
740 | ||
741 | static void | |
742 | handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
743 | { | |
744 | struct fw_packet response; | |
745 | int tcode, length, i; | |
746 | ||
747 | tcode = header_get_tcode(packet->header[0]); | |
748 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
749 | length = header_get_data_length(packet->header[3]); | |
750 | else | |
751 | length = 4; | |
752 | ||
753 | i = csr - CSR_CONFIG_ROM; | |
754 | if (i + length > CONFIG_ROM_SIZE) { | |
755 | fw_fill_response(&response, packet->header, | |
756 | RCODE_ADDRESS_ERROR, NULL, 0); | |
757 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
758 | fw_fill_response(&response, packet->header, | |
759 | RCODE_TYPE_ERROR, NULL, 0); | |
760 | } else { | |
761 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
762 | (void *) ohci->config_rom + i, length); | |
763 | } | |
764 | ||
765 | fw_core_handle_response(&ohci->card, &response); | |
766 | } | |
767 | ||
768 | static void | |
769 | handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
770 | { | |
771 | struct fw_packet response; | |
772 | int tcode, length, ext_tcode, sel; | |
773 | __be32 *payload, lock_old; | |
774 | u32 lock_arg, lock_data; | |
775 | ||
776 | tcode = header_get_tcode(packet->header[0]); | |
777 | length = header_get_data_length(packet->header[3]); | |
778 | payload = packet->payload; | |
779 | ext_tcode = header_get_extended_tcode(packet->header[3]); | |
780 | ||
781 | if (tcode == TCODE_LOCK_REQUEST && | |
782 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
783 | lock_arg = be32_to_cpu(payload[0]); | |
784 | lock_data = be32_to_cpu(payload[1]); | |
785 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
786 | lock_arg = 0; | |
787 | lock_data = 0; | |
788 | } else { | |
789 | fw_fill_response(&response, packet->header, | |
790 | RCODE_TYPE_ERROR, NULL, 0); | |
791 | goto out; | |
792 | } | |
793 | ||
794 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
795 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
796 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
797 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
798 | ||
799 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
800 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
801 | else | |
802 | fw_notify("swap not done yet\n"); | |
803 | ||
804 | fw_fill_response(&response, packet->header, | |
805 | RCODE_COMPLETE, &lock_old, sizeof lock_old); | |
806 | out: | |
807 | fw_core_handle_response(&ohci->card, &response); | |
808 | } | |
809 | ||
810 | static void | |
f319b6a0 | 811 | handle_local_request(struct context *ctx, struct fw_packet *packet) |
93c4cceb KH |
812 | { |
813 | u64 offset; | |
814 | u32 csr; | |
815 | ||
473d28c7 KH |
816 | if (ctx == &ctx->ohci->at_request_ctx) { |
817 | packet->ack = ACK_PENDING; | |
818 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
819 | } | |
93c4cceb KH |
820 | |
821 | offset = | |
822 | ((unsigned long long) | |
823 | header_get_offset_high(packet->header[1]) << 32) | | |
824 | packet->header[2]; | |
825 | csr = offset - CSR_REGISTER_BASE; | |
826 | ||
827 | /* Handle config rom reads. */ | |
828 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
829 | handle_local_rom(ctx->ohci, packet, csr); | |
830 | else switch (csr) { | |
831 | case CSR_BUS_MANAGER_ID: | |
832 | case CSR_BANDWIDTH_AVAILABLE: | |
833 | case CSR_CHANNELS_AVAILABLE_HI: | |
834 | case CSR_CHANNELS_AVAILABLE_LO: | |
835 | handle_local_lock(ctx->ohci, packet, csr); | |
836 | break; | |
837 | default: | |
838 | if (ctx == &ctx->ohci->at_request_ctx) | |
839 | fw_core_handle_request(&ctx->ohci->card, packet); | |
840 | else | |
841 | fw_core_handle_response(&ctx->ohci->card, packet); | |
842 | break; | |
843 | } | |
473d28c7 KH |
844 | |
845 | if (ctx == &ctx->ohci->at_response_ctx) { | |
846 | packet->ack = ACK_COMPLETE; | |
847 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
848 | } | |
93c4cceb | 849 | } |
e636fe25 | 850 | |
ed568912 | 851 | static void |
f319b6a0 | 852 | at_context_transmit(struct context *ctx, struct fw_packet *packet) |
ed568912 | 853 | { |
ed568912 | 854 | unsigned long flags; |
f319b6a0 | 855 | int retval; |
ed568912 KH |
856 | |
857 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
858 | ||
e636fe25 KH |
859 | if (header_get_destination(packet->header[0]) == ctx->ohci->node_id && |
860 | ctx->ohci->generation == packet->generation) { | |
93c4cceb KH |
861 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
862 | handle_local_request(ctx, packet); | |
863 | return; | |
e636fe25 | 864 | } |
ed568912 | 865 | |
f319b6a0 | 866 | retval = at_context_queue_packet(ctx, packet); |
ed568912 KH |
867 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
868 | ||
f319b6a0 KH |
869 | if (retval < 0) |
870 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
871 | ||
ed568912 KH |
872 | } |
873 | ||
874 | static void bus_reset_tasklet(unsigned long data) | |
875 | { | |
876 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 877 | int self_id_count, i, j, reg; |
ed568912 KH |
878 | int generation, new_generation; |
879 | unsigned long flags; | |
880 | ||
881 | reg = reg_read(ohci, OHCI1394_NodeID); | |
882 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
883 | fw_error("node ID not valid, new bus reset in progress\n"); | |
884 | return; | |
885 | } | |
e636fe25 | 886 | ohci->node_id = reg & 0xffff; |
ed568912 KH |
887 | |
888 | /* The count in the SelfIDCount register is the number of | |
889 | * bytes in the self ID receive buffer. Since we also receive | |
890 | * the inverted quadlets and a header quadlet, we shift one | |
891 | * bit extra to get the actual number of self IDs. */ | |
892 | ||
893 | self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff; | |
894 | generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; | |
895 | ||
896 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
897 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) | |
898 | fw_error("inconsistent self IDs\n"); | |
899 | ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]); | |
900 | } | |
901 | ||
902 | /* Check the consistency of the self IDs we just read. The | |
903 | * problem we face is that a new bus reset can start while we | |
904 | * read out the self IDs from the DMA buffer. If this happens, | |
905 | * the DMA buffer will be overwritten with new self IDs and we | |
906 | * will read out inconsistent data. The OHCI specification | |
907 | * (section 11.2) recommends a technique similar to | |
908 | * linux/seqlock.h, where we remember the generation of the | |
909 | * self IDs in the buffer before reading them out and compare | |
910 | * it to the current generation after reading them out. If | |
911 | * the two generations match we know we have a consistent set | |
912 | * of self IDs. */ | |
913 | ||
914 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
915 | if (new_generation != generation) { | |
916 | fw_notify("recursive bus reset detected, " | |
917 | "discarding self ids\n"); | |
918 | return; | |
919 | } | |
920 | ||
921 | /* FIXME: Document how the locking works. */ | |
922 | spin_lock_irqsave(&ohci->lock, flags); | |
923 | ||
924 | ohci->generation = generation; | |
f319b6a0 KH |
925 | context_stop(&ohci->at_request_ctx); |
926 | context_stop(&ohci->at_response_ctx); | |
ed568912 KH |
927 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
928 | ||
929 | /* This next bit is unrelated to the AT context stuff but we | |
930 | * have to do it under the spinlock also. If a new config rom | |
931 | * was set up before this reset, the old one is now no longer | |
932 | * in use and we can free it. Update the config rom pointers | |
933 | * to point to the current config rom and clear the | |
934 | * next_config_rom pointer so a new udpate can take place. */ | |
935 | ||
936 | if (ohci->next_config_rom != NULL) { | |
937 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
938 | ohci->config_rom, ohci->config_rom_bus); | |
939 | ohci->config_rom = ohci->next_config_rom; | |
940 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
941 | ohci->next_config_rom = NULL; | |
942 | ||
943 | /* Restore config_rom image and manually update | |
944 | * config_rom registers. Writing the header quadlet | |
945 | * will indicate that the config rom is ready, so we | |
946 | * do that last. */ | |
947 | reg_write(ohci, OHCI1394_BusOptions, | |
948 | be32_to_cpu(ohci->config_rom[2])); | |
949 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
950 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
951 | } | |
952 | ||
953 | spin_unlock_irqrestore(&ohci->lock, flags); | |
954 | ||
e636fe25 | 955 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
956 | self_id_count, ohci->self_id_buffer); |
957 | } | |
958 | ||
959 | static irqreturn_t irq_handler(int irq, void *data) | |
960 | { | |
961 | struct fw_ohci *ohci = data; | |
962 | u32 event, iso_event; | |
963 | int i; | |
964 | ||
965 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
966 | ||
967 | if (!event) | |
968 | return IRQ_NONE; | |
969 | ||
970 | reg_write(ohci, OHCI1394_IntEventClear, event); | |
971 | ||
972 | if (event & OHCI1394_selfIDComplete) | |
973 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
974 | ||
975 | if (event & OHCI1394_RQPkt) | |
976 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
977 | ||
978 | if (event & OHCI1394_RSPkt) | |
979 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
980 | ||
981 | if (event & OHCI1394_reqTxComplete) | |
982 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
983 | ||
984 | if (event & OHCI1394_respTxComplete) | |
985 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
986 | ||
c889475f | 987 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed568912 KH |
988 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); |
989 | ||
990 | while (iso_event) { | |
991 | i = ffs(iso_event) - 1; | |
30200739 | 992 | tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed568912 KH |
993 | iso_event &= ~(1 << i); |
994 | } | |
995 | ||
c889475f | 996 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed568912 KH |
997 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); |
998 | ||
999 | while (iso_event) { | |
1000 | i = ffs(iso_event) - 1; | |
30200739 | 1001 | tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed568912 KH |
1002 | iso_event &= ~(1 << i); |
1003 | } | |
1004 | ||
1005 | return IRQ_HANDLED; | |
1006 | } | |
1007 | ||
1008 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) | |
1009 | { | |
1010 | struct fw_ohci *ohci = fw_ohci(card); | |
1011 | struct pci_dev *dev = to_pci_dev(card->device); | |
1012 | ||
1013 | /* When the link is not yet enabled, the atomic config rom | |
1014 | * update mechanism described below in ohci_set_config_rom() | |
1015 | * is not active. We have to update ConfigRomHeader and | |
1016 | * BusOptions manually, and the write to ConfigROMmap takes | |
1017 | * effect immediately. We tie this to the enabling of the | |
1018 | * link, so we have a valid config rom before enabling - the | |
1019 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
1020 | * values before enabling. | |
1021 | * | |
1022 | * However, when the ConfigROMmap is written, some controllers | |
1023 | * always read back quadlets 0 and 2 from the config rom to | |
1024 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
1025 | * They shouldn't do that in this initial case where the link | |
1026 | * isn't enabled. This means we have to use the same | |
1027 | * workaround here, setting the bus header to 0 and then write | |
1028 | * the right values in the bus reset tasklet. | |
1029 | */ | |
1030 | ||
1031 | ohci->next_config_rom = | |
1032 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1033 | &ohci->next_config_rom_bus, GFP_KERNEL); | |
1034 | if (ohci->next_config_rom == NULL) | |
1035 | return -ENOMEM; | |
1036 | ||
1037 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1038 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
1039 | ||
1040 | ohci->next_header = config_rom[0]; | |
1041 | ohci->next_config_rom[0] = 0; | |
1042 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
1043 | reg_write(ohci, OHCI1394_BusOptions, config_rom[2]); | |
1044 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); | |
1045 | ||
1046 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
1047 | ||
1048 | if (request_irq(dev->irq, irq_handler, | |
65efffa8 | 1049 | IRQF_SHARED, ohci_driver_name, ohci)) { |
ed568912 KH |
1050 | fw_error("Failed to allocate shared interrupt %d.\n", |
1051 | dev->irq); | |
1052 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1053 | ohci->config_rom, ohci->config_rom_bus); | |
1054 | return -EIO; | |
1055 | } | |
1056 | ||
1057 | reg_write(ohci, OHCI1394_HCControlSet, | |
1058 | OHCI1394_HCControl_linkEnable | | |
1059 | OHCI1394_HCControl_BIBimageValid); | |
1060 | flush_writes(ohci); | |
1061 | ||
1062 | /* We are ready to go, initiate bus reset to finish the | |
1063 | * initialization. */ | |
1064 | ||
1065 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | static int | |
1071 | ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) | |
1072 | { | |
1073 | struct fw_ohci *ohci; | |
1074 | unsigned long flags; | |
1075 | int retval = 0; | |
1076 | __be32 *next_config_rom; | |
1077 | dma_addr_t next_config_rom_bus; | |
1078 | ||
1079 | ohci = fw_ohci(card); | |
1080 | ||
1081 | /* When the OHCI controller is enabled, the config rom update | |
1082 | * mechanism is a bit tricky, but easy enough to use. See | |
1083 | * section 5.5.6 in the OHCI specification. | |
1084 | * | |
1085 | * The OHCI controller caches the new config rom address in a | |
1086 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
1087 | * for the changes to take place. When the bus reset is | |
1088 | * detected, the controller loads the new values for the | |
1089 | * ConfigRomHeader and BusOptions registers from the specified | |
1090 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
1091 | * shadow register. All automatically and atomically. | |
1092 | * | |
1093 | * Now, there's a twist to this story. The automatic load of | |
1094 | * ConfigRomHeader and BusOptions doesn't honor the | |
1095 | * noByteSwapData bit, so with a be32 config rom, the | |
1096 | * controller will load be32 values in to these registers | |
1097 | * during the atomic update, even on litte endian | |
1098 | * architectures. The workaround we use is to put a 0 in the | |
1099 | * header quadlet; 0 is endian agnostic and means that the | |
1100 | * config rom isn't ready yet. In the bus reset tasklet we | |
1101 | * then set up the real values for the two registers. | |
1102 | * | |
1103 | * We use ohci->lock to avoid racing with the code that sets | |
1104 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
1105 | */ | |
1106 | ||
1107 | next_config_rom = | |
1108 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1109 | &next_config_rom_bus, GFP_KERNEL); | |
1110 | if (next_config_rom == NULL) | |
1111 | return -ENOMEM; | |
1112 | ||
1113 | spin_lock_irqsave(&ohci->lock, flags); | |
1114 | ||
1115 | if (ohci->next_config_rom == NULL) { | |
1116 | ohci->next_config_rom = next_config_rom; | |
1117 | ohci->next_config_rom_bus = next_config_rom_bus; | |
1118 | ||
1119 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1120 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
1121 | length * 4); | |
1122 | ||
1123 | ohci->next_header = config_rom[0]; | |
1124 | ohci->next_config_rom[0] = 0; | |
1125 | ||
1126 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
1127 | ohci->next_config_rom_bus); | |
1128 | } else { | |
1129 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1130 | next_config_rom, next_config_rom_bus); | |
1131 | retval = -EBUSY; | |
1132 | } | |
1133 | ||
1134 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1135 | ||
1136 | /* Now initiate a bus reset to have the changes take | |
1137 | * effect. We clean up the old config rom memory and DMA | |
1138 | * mappings in the bus reset tasklet, since the OHCI | |
1139 | * controller could need to access it before the bus reset | |
1140 | * takes effect. */ | |
1141 | if (retval == 0) | |
1142 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1143 | ||
1144 | return retval; | |
1145 | } | |
1146 | ||
1147 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1148 | { | |
1149 | struct fw_ohci *ohci = fw_ohci(card); | |
1150 | ||
1151 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1152 | } | |
1153 | ||
1154 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1155 | { | |
1156 | struct fw_ohci *ohci = fw_ohci(card); | |
1157 | ||
1158 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1159 | } | |
1160 | ||
730c32f5 KH |
1161 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
1162 | { | |
1163 | struct fw_ohci *ohci = fw_ohci(card); | |
f319b6a0 KH |
1164 | struct context *ctx = &ohci->at_request_ctx; |
1165 | struct driver_data *driver_data = packet->driver_data; | |
1166 | int retval = -ENOENT; | |
730c32f5 | 1167 | |
f319b6a0 | 1168 | tasklet_disable(&ctx->tasklet); |
730c32f5 | 1169 | |
f319b6a0 KH |
1170 | if (packet->ack != 0) |
1171 | goto out; | |
730c32f5 | 1172 | |
f319b6a0 KH |
1173 | driver_data->packet = NULL; |
1174 | packet->ack = RCODE_CANCELLED; | |
1175 | packet->callback(packet, &ohci->card, packet->ack); | |
1176 | retval = 0; | |
730c32f5 | 1177 | |
f319b6a0 KH |
1178 | out: |
1179 | tasklet_enable(&ctx->tasklet); | |
730c32f5 | 1180 | |
f319b6a0 | 1181 | return retval; |
730c32f5 KH |
1182 | } |
1183 | ||
ed568912 KH |
1184 | static int |
1185 | ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) | |
1186 | { | |
1187 | struct fw_ohci *ohci = fw_ohci(card); | |
1188 | unsigned long flags; | |
907293d7 | 1189 | int n, retval = 0; |
ed568912 | 1190 | |
907293d7 SR |
1191 | /* FIXME: Make sure this bitmask is cleared when we clear the busReset |
1192 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. */ | |
ed568912 KH |
1193 | |
1194 | spin_lock_irqsave(&ohci->lock, flags); | |
1195 | ||
1196 | if (ohci->generation != generation) { | |
1197 | retval = -ESTALE; | |
1198 | goto out; | |
1199 | } | |
1200 | ||
907293d7 SR |
1201 | /* NOTE, if the node ID contains a non-local bus ID, physical DMA is |
1202 | * enabled for _all_ nodes on remote buses. */ | |
1203 | ||
1204 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
1205 | if (n < 32) | |
1206 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
1207 | else | |
1208 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
1209 | ||
ed568912 | 1210 | flush_writes(ohci); |
ed568912 | 1211 | out: |
6cad95fe | 1212 | spin_unlock_irqrestore(&ohci->lock, flags); |
ed568912 KH |
1213 | return retval; |
1214 | } | |
373b2edd | 1215 | |
d2746dc1 KH |
1216 | static int handle_ir_bufferfill_packet(struct context *context, |
1217 | struct descriptor *d, | |
1218 | struct descriptor *last) | |
1219 | { | |
1220 | struct iso_context *ctx = | |
1221 | container_of(context, struct iso_context, context); | |
ed568912 | 1222 | |
d2746dc1 KH |
1223 | if (d->res_count > 0) |
1224 | return 0; | |
1225 | ||
1226 | if (le16_to_cpu(last->control) & descriptor_irq_always) | |
1227 | ctx->base.callback(&ctx->base, | |
1228 | le16_to_cpu(last->res_count), | |
1229 | 0, NULL, ctx->base.callback_data); | |
1230 | ||
1231 | return 1; | |
1232 | } | |
1233 | ||
1234 | static int handle_ir_dualbuffer_packet(struct context *context, | |
1235 | struct descriptor *d, | |
1236 | struct descriptor *last) | |
ed568912 | 1237 | { |
295e3feb KH |
1238 | struct iso_context *ctx = |
1239 | container_of(context, struct iso_context, context); | |
1240 | struct db_descriptor *db = (struct db_descriptor *) d; | |
9b32d5f3 | 1241 | size_t header_length; |
d2746dc1 | 1242 | |
295e3feb KH |
1243 | if (db->first_res_count > 0 && db->second_res_count > 0) |
1244 | /* This descriptor isn't done yet, stop iteration. */ | |
1245 | return 0; | |
1246 | ||
9b32d5f3 KH |
1247 | header_length = db->first_req_count - db->first_res_count; |
1248 | if (ctx->header_length + header_length <= PAGE_SIZE) | |
1249 | memcpy(ctx->header + ctx->header_length, db + 1, header_length); | |
1250 | ctx->header_length += header_length; | |
1251 | ||
1252 | if (le16_to_cpu(db->control) & descriptor_irq_always) { | |
1253 | ctx->base.callback(&ctx->base, 0, | |
1254 | ctx->header_length, ctx->header, | |
295e3feb | 1255 | ctx->base.callback_data); |
9b32d5f3 KH |
1256 | ctx->header_length = 0; |
1257 | } | |
ed568912 | 1258 | |
295e3feb | 1259 | return 1; |
ed568912 KH |
1260 | } |
1261 | ||
30200739 KH |
1262 | static int handle_it_packet(struct context *context, |
1263 | struct descriptor *d, | |
1264 | struct descriptor *last) | |
ed568912 | 1265 | { |
30200739 KH |
1266 | struct iso_context *ctx = |
1267 | container_of(context, struct iso_context, context); | |
373b2edd | 1268 | |
30200739 KH |
1269 | if (last->transfer_status == 0) |
1270 | /* This descriptor isn't done yet, stop iteration. */ | |
1271 | return 0; | |
1272 | ||
1273 | if (le16_to_cpu(last->control) & descriptor_irq_always) | |
9b32d5f3 KH |
1274 | ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count), |
1275 | 0, NULL, ctx->base.callback_data); | |
30200739 KH |
1276 | |
1277 | return 1; | |
ed568912 KH |
1278 | } |
1279 | ||
30200739 | 1280 | static struct fw_iso_context * |
98b6cbe8 KH |
1281 | ohci_allocate_iso_context(struct fw_card *card, int type, |
1282 | int sync, int tags, size_t header_size) | |
ed568912 KH |
1283 | { |
1284 | struct fw_ohci *ohci = fw_ohci(card); | |
1285 | struct iso_context *ctx, *list; | |
30200739 | 1286 | descriptor_callback_t callback; |
295e3feb | 1287 | u32 *mask, regs; |
ed568912 | 1288 | unsigned long flags; |
9b32d5f3 | 1289 | int index, retval = -ENOMEM; |
ed568912 KH |
1290 | |
1291 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
1292 | mask = &ohci->it_context_mask; | |
1293 | list = ohci->it_context_list; | |
30200739 | 1294 | callback = handle_it_packet; |
ed568912 | 1295 | } else { |
373b2edd SR |
1296 | mask = &ohci->ir_context_mask; |
1297 | list = ohci->ir_context_list; | |
d2746dc1 KH |
1298 | if (header_size > 0) |
1299 | callback = handle_ir_dualbuffer_packet; | |
1300 | else | |
1301 | callback = handle_ir_bufferfill_packet; | |
ed568912 KH |
1302 | } |
1303 | ||
e364cf4e KH |
1304 | if (callback == handle_ir_dualbuffer_packet && |
1305 | ohci->version < OHCI_VERSION_1_1) | |
1306 | return ERR_PTR(-EINVAL); | |
1307 | ||
ed568912 KH |
1308 | spin_lock_irqsave(&ohci->lock, flags); |
1309 | index = ffs(*mask) - 1; | |
1310 | if (index >= 0) | |
1311 | *mask &= ~(1 << index); | |
1312 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1313 | ||
1314 | if (index < 0) | |
1315 | return ERR_PTR(-EBUSY); | |
1316 | ||
373b2edd SR |
1317 | if (type == FW_ISO_CONTEXT_TRANSMIT) |
1318 | regs = OHCI1394_IsoXmitContextBase(index); | |
1319 | else | |
1320 | regs = OHCI1394_IsoRcvContextBase(index); | |
1321 | ||
ed568912 KH |
1322 | ctx = &list[index]; |
1323 | memset(ctx, 0, sizeof *ctx); | |
9b32d5f3 KH |
1324 | ctx->header_length = 0; |
1325 | ctx->header = (void *) __get_free_page(GFP_KERNEL); | |
1326 | if (ctx->header == NULL) | |
1327 | goto out; | |
1328 | ||
30200739 | 1329 | retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE, |
295e3feb | 1330 | regs, callback); |
9b32d5f3 KH |
1331 | if (retval < 0) |
1332 | goto out_with_header; | |
ed568912 KH |
1333 | |
1334 | return &ctx->base; | |
9b32d5f3 KH |
1335 | |
1336 | out_with_header: | |
1337 | free_page((unsigned long)ctx->header); | |
1338 | out: | |
1339 | spin_lock_irqsave(&ohci->lock, flags); | |
1340 | *mask |= 1 << index; | |
1341 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1342 | ||
1343 | return ERR_PTR(retval); | |
ed568912 KH |
1344 | } |
1345 | ||
69cdb726 | 1346 | static int ohci_start_iso(struct fw_iso_context *base, s32 cycle) |
ed568912 | 1347 | { |
373b2edd | 1348 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1349 | struct fw_ohci *ohci = ctx->context.ohci; |
d2746dc1 | 1350 | u32 cycle_match = 0, mode; |
ed568912 KH |
1351 | int index; |
1352 | ||
295e3feb KH |
1353 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { |
1354 | index = ctx - ohci->it_context_list; | |
1355 | if (cycle > 0) | |
1356 | cycle_match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
1357 | (cycle & 0x7fff) << 16; | |
21efb3cf | 1358 | |
295e3feb KH |
1359 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); |
1360 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
1361 | context_run(&ctx->context, cycle_match); | |
1362 | } else { | |
1363 | index = ctx - ohci->ir_context_list; | |
ed568912 | 1364 | |
d2746dc1 KH |
1365 | if (ctx->base.header_size > 0) |
1366 | mode = IR_CONTEXT_DUAL_BUFFER_MODE; | |
1367 | else | |
1368 | mode = IR_CONTEXT_BUFFER_FILL; | |
295e3feb KH |
1369 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
1370 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
1371 | reg_write(ohci, context_match(ctx->context.regs), | |
98b6cbe8 KH |
1372 | (ctx->base.tags << 28) | |
1373 | (ctx->base.sync << 8) | ctx->base.channel); | |
d2746dc1 | 1374 | context_run(&ctx->context, mode); |
295e3feb | 1375 | } |
ed568912 KH |
1376 | |
1377 | return 0; | |
1378 | } | |
1379 | ||
b8295668 KH |
1380 | static int ohci_stop_iso(struct fw_iso_context *base) |
1381 | { | |
1382 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1383 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
b8295668 KH |
1384 | int index; |
1385 | ||
1386 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1387 | index = ctx - ohci->it_context_list; | |
1388 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
1389 | } else { | |
1390 | index = ctx - ohci->ir_context_list; | |
1391 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
1392 | } | |
1393 | flush_writes(ohci); | |
1394 | context_stop(&ctx->context); | |
1395 | ||
1396 | return 0; | |
1397 | } | |
1398 | ||
ed568912 KH |
1399 | static void ohci_free_iso_context(struct fw_iso_context *base) |
1400 | { | |
1401 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 1402 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
1403 | unsigned long flags; |
1404 | int index; | |
1405 | ||
b8295668 KH |
1406 | ohci_stop_iso(base); |
1407 | context_release(&ctx->context); | |
9b32d5f3 | 1408 | free_page((unsigned long)ctx->header); |
b8295668 | 1409 | |
ed568912 KH |
1410 | spin_lock_irqsave(&ohci->lock, flags); |
1411 | ||
1412 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1413 | index = ctx - ohci->it_context_list; | |
ed568912 KH |
1414 | ohci->it_context_mask |= 1 << index; |
1415 | } else { | |
1416 | index = ctx - ohci->ir_context_list; | |
ed568912 KH |
1417 | ohci->ir_context_mask |= 1 << index; |
1418 | } | |
ed568912 KH |
1419 | |
1420 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1421 | } | |
1422 | ||
1423 | static int | |
295e3feb KH |
1424 | ohci_queue_iso_transmit(struct fw_iso_context *base, |
1425 | struct fw_iso_packet *packet, | |
1426 | struct fw_iso_buffer *buffer, | |
1427 | unsigned long payload) | |
ed568912 | 1428 | { |
373b2edd | 1429 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1430 | struct descriptor *d, *last, *pd; |
ed568912 KH |
1431 | struct fw_iso_packet *p; |
1432 | __le32 *header; | |
9aad8125 | 1433 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
1434 | u32 z, header_z, payload_z, irq; |
1435 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 1436 | int page, end_page, i, length, offset; |
ed568912 KH |
1437 | |
1438 | /* FIXME: Cycle lost behavior should be configurable: lose | |
1439 | * packet, retransmit or terminate.. */ | |
1440 | ||
1441 | p = packet; | |
9aad8125 | 1442 | payload_index = payload; |
ed568912 KH |
1443 | |
1444 | if (p->skip) | |
1445 | z = 1; | |
1446 | else | |
1447 | z = 2; | |
1448 | if (p->header_length > 0) | |
1449 | z++; | |
1450 | ||
1451 | /* Determine the first page the payload isn't contained in. */ | |
1452 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
1453 | if (p->payload_length > 0) | |
1454 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
1455 | else | |
1456 | payload_z = 0; | |
1457 | ||
1458 | z += payload_z; | |
1459 | ||
1460 | /* Get header size in number of descriptors. */ | |
1461 | header_z = DIV_ROUND_UP(p->header_length, sizeof *d); | |
1462 | ||
30200739 KH |
1463 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
1464 | if (d == NULL) | |
1465 | return -ENOMEM; | |
ed568912 KH |
1466 | |
1467 | if (!p->skip) { | |
1468 | d[0].control = cpu_to_le16(descriptor_key_immediate); | |
1469 | d[0].req_count = cpu_to_le16(8); | |
1470 | ||
1471 | header = (__le32 *) &d[1]; | |
1472 | header[0] = cpu_to_le32(it_header_sy(p->sy) | | |
1473 | it_header_tag(p->tag) | | |
1474 | it_header_tcode(TCODE_STREAM_DATA) | | |
1475 | it_header_channel(ctx->base.channel) | | |
1476 | it_header_speed(ctx->base.speed)); | |
1477 | header[1] = | |
1478 | cpu_to_le32(it_header_data_length(p->header_length + | |
1479 | p->payload_length)); | |
1480 | } | |
1481 | ||
1482 | if (p->header_length > 0) { | |
1483 | d[2].req_count = cpu_to_le16(p->header_length); | |
1484 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d); | |
1485 | memcpy(&d[z], p->header, p->header_length); | |
1486 | } | |
1487 | ||
1488 | pd = d + z - payload_z; | |
1489 | payload_end_index = payload_index + p->payload_length; | |
1490 | for (i = 0; i < payload_z; i++) { | |
1491 | page = payload_index >> PAGE_SHIFT; | |
1492 | offset = payload_index & ~PAGE_MASK; | |
1493 | next_page_index = (page + 1) << PAGE_SHIFT; | |
1494 | length = | |
1495 | min(next_page_index, payload_end_index) - payload_index; | |
1496 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
1497 | |
1498 | page_bus = page_private(buffer->pages[page]); | |
1499 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
1500 | |
1501 | payload_index += length; | |
1502 | } | |
1503 | ||
ed568912 KH |
1504 | if (p->interrupt) |
1505 | irq = descriptor_irq_always; | |
1506 | else | |
1507 | irq = descriptor_no_irq; | |
1508 | ||
30200739 | 1509 | last = z == 2 ? d : d + z - 1; |
cbb59da7 KH |
1510 | last->control |= cpu_to_le16(descriptor_output_last | |
1511 | descriptor_status | | |
1512 | descriptor_branch_always | | |
1513 | irq); | |
ed568912 | 1514 | |
30200739 | 1515 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
1516 | |
1517 | return 0; | |
1518 | } | |
373b2edd | 1519 | |
98b6cbe8 KH |
1520 | static int |
1521 | setup_wait_descriptor(struct context *ctx) | |
1522 | { | |
1523 | struct descriptor *d; | |
1524 | dma_addr_t d_bus; | |
1525 | ||
1526 | d = context_get_descriptors(ctx, 1, &d_bus); | |
1527 | if (d == NULL) | |
1528 | return -ENOMEM; | |
1529 | ||
1530 | d->control = cpu_to_le16(descriptor_input_more | | |
1531 | descriptor_status | | |
1532 | descriptor_branch_always | | |
1533 | descriptor_wait); | |
1534 | ||
1535 | context_append(ctx, d, 1, 0); | |
1536 | ||
1537 | return 0; | |
1538 | } | |
ed568912 | 1539 | |
295e3feb | 1540 | static int |
d2746dc1 KH |
1541 | ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base, |
1542 | struct fw_iso_packet *packet, | |
1543 | struct fw_iso_buffer *buffer, | |
1544 | unsigned long payload) | |
295e3feb KH |
1545 | { |
1546 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
1547 | struct db_descriptor *db = NULL; | |
1548 | struct descriptor *d; | |
1549 | struct fw_iso_packet *p; | |
1550 | dma_addr_t d_bus, page_bus; | |
1551 | u32 z, header_z, length, rest; | |
1552 | int page, offset; | |
373b2edd | 1553 | |
295e3feb KH |
1554 | /* FIXME: Cycle lost behavior should be configurable: lose |
1555 | * packet, retransmit or terminate.. */ | |
1556 | ||
98b6cbe8 KH |
1557 | if (packet->skip && setup_wait_descriptor(&ctx->context) < 0) |
1558 | return -ENOMEM; | |
1559 | ||
295e3feb KH |
1560 | p = packet; |
1561 | z = 2; | |
1562 | ||
1563 | /* Get header size in number of descriptors. */ | |
1564 | header_z = DIV_ROUND_UP(p->header_length, sizeof *d); | |
1565 | page = payload >> PAGE_SHIFT; | |
1566 | offset = payload & ~PAGE_MASK; | |
1567 | rest = p->payload_length; | |
1568 | ||
1569 | /* FIXME: OHCI 1.0 doesn't support dual buffer receive */ | |
1570 | /* FIXME: handle descriptor_wait */ | |
1571 | /* FIXME: make packet-per-buffer/dual-buffer a context option */ | |
1572 | while (rest > 0) { | |
1573 | d = context_get_descriptors(&ctx->context, | |
1574 | z + header_z, &d_bus); | |
1575 | if (d == NULL) | |
1576 | return -ENOMEM; | |
1577 | ||
1578 | db = (struct db_descriptor *) d; | |
1579 | db->control = cpu_to_le16(descriptor_status | | |
1580 | descriptor_branch_always); | |
1581 | db->first_size = cpu_to_le16(ctx->base.header_size); | |
1582 | db->first_req_count = cpu_to_le16(p->header_length); | |
1e1d196b | 1583 | db->first_res_count = db->first_req_count; |
295e3feb | 1584 | db->first_buffer = cpu_to_le32(d_bus + sizeof *db); |
373b2edd | 1585 | |
295e3feb KH |
1586 | if (offset + rest < PAGE_SIZE) |
1587 | length = rest; | |
1588 | else | |
1589 | length = PAGE_SIZE - offset; | |
1590 | ||
1e1d196b KH |
1591 | db->second_req_count = cpu_to_le16(length); |
1592 | db->second_res_count = db->second_req_count; | |
295e3feb KH |
1593 | page_bus = page_private(buffer->pages[page]); |
1594 | db->second_buffer = cpu_to_le32(page_bus + offset); | |
1595 | ||
cb2d2cdb KH |
1596 | if (p->interrupt && length == rest) |
1597 | db->control |= cpu_to_le16(descriptor_irq_always); | |
1598 | ||
295e3feb KH |
1599 | context_append(&ctx->context, d, z, header_z); |
1600 | offset = (offset + length) & ~PAGE_MASK; | |
1601 | rest -= length; | |
1602 | page++; | |
1603 | } | |
1604 | ||
d2746dc1 KH |
1605 | return 0; |
1606 | } | |
21efb3cf | 1607 | |
d2746dc1 KH |
1608 | static int |
1609 | ohci_queue_iso_receive_bufferfill(struct fw_iso_context *base, | |
1610 | struct fw_iso_packet *packet, | |
1611 | struct fw_iso_buffer *buffer, | |
1612 | unsigned long payload) | |
1613 | { | |
1614 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
1615 | struct descriptor *d = NULL; | |
1616 | dma_addr_t d_bus, page_bus; | |
1617 | u32 length, rest; | |
1618 | int page, offset; | |
373b2edd | 1619 | |
d2746dc1 KH |
1620 | page = payload >> PAGE_SHIFT; |
1621 | offset = payload & ~PAGE_MASK; | |
1622 | rest = packet->payload_length; | |
1623 | ||
98b6cbe8 KH |
1624 | if (packet->skip && setup_wait_descriptor(&ctx->context) < 0) |
1625 | return -ENOMEM; | |
1626 | ||
d2746dc1 KH |
1627 | while (rest > 0) { |
1628 | d = context_get_descriptors(&ctx->context, 1, &d_bus); | |
1629 | if (d == NULL) | |
1630 | return -ENOMEM; | |
1631 | ||
1632 | d->control = cpu_to_le16(descriptor_input_more | | |
1633 | descriptor_status | | |
1634 | descriptor_branch_always); | |
373b2edd | 1635 | |
d2746dc1 KH |
1636 | if (offset + rest < PAGE_SIZE) |
1637 | length = rest; | |
1638 | else | |
1639 | length = PAGE_SIZE - offset; | |
1640 | ||
1641 | page_bus = page_private(buffer->pages[page]); | |
1642 | d->data_address = cpu_to_le32(page_bus + offset); | |
1643 | d->req_count = cpu_to_le16(length); | |
1644 | d->res_count = cpu_to_le16(length); | |
1645 | ||
cb2d2cdb KH |
1646 | if (packet->interrupt && length == rest) |
1647 | d->control |= cpu_to_le16(descriptor_irq_always); | |
1648 | ||
d2746dc1 KH |
1649 | context_append(&ctx->context, d, 1, 0); |
1650 | ||
1651 | offset = (offset + length) & ~PAGE_MASK; | |
1652 | rest -= length; | |
1653 | page++; | |
1654 | } | |
1655 | ||
d2746dc1 KH |
1656 | return 0; |
1657 | } | |
1658 | ||
295e3feb KH |
1659 | static int |
1660 | ohci_queue_iso(struct fw_iso_context *base, | |
1661 | struct fw_iso_packet *packet, | |
1662 | struct fw_iso_buffer *buffer, | |
1663 | unsigned long payload) | |
1664 | { | |
e364cf4e KH |
1665 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
1666 | ||
295e3feb KH |
1667 | if (base->type == FW_ISO_CONTEXT_TRANSMIT) |
1668 | return ohci_queue_iso_transmit(base, packet, buffer, payload); | |
d2746dc1 KH |
1669 | else if (base->header_size == 0) |
1670 | return ohci_queue_iso_receive_bufferfill(base, packet, | |
1671 | buffer, payload); | |
e364cf4e | 1672 | else if (ctx->context.ohci->version >= OHCI_VERSION_1_1) |
d2746dc1 KH |
1673 | return ohci_queue_iso_receive_dualbuffer(base, packet, |
1674 | buffer, payload); | |
e364cf4e KH |
1675 | else |
1676 | /* FIXME: Implement fallback for OHCI 1.0 controllers. */ | |
1677 | return -EINVAL; | |
295e3feb KH |
1678 | } |
1679 | ||
21ebcd12 | 1680 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
1681 | .name = ohci_driver_name, |
1682 | .enable = ohci_enable, | |
1683 | .update_phy_reg = ohci_update_phy_reg, | |
1684 | .set_config_rom = ohci_set_config_rom, | |
1685 | .send_request = ohci_send_request, | |
1686 | .send_response = ohci_send_response, | |
730c32f5 | 1687 | .cancel_packet = ohci_cancel_packet, |
ed568912 KH |
1688 | .enable_phys_dma = ohci_enable_phys_dma, |
1689 | ||
1690 | .allocate_iso_context = ohci_allocate_iso_context, | |
1691 | .free_iso_context = ohci_free_iso_context, | |
1692 | .queue_iso = ohci_queue_iso, | |
69cdb726 | 1693 | .start_iso = ohci_start_iso, |
b8295668 | 1694 | .stop_iso = ohci_stop_iso, |
ed568912 KH |
1695 | }; |
1696 | ||
1697 | static int software_reset(struct fw_ohci *ohci) | |
1698 | { | |
1699 | int i; | |
1700 | ||
1701 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1702 | ||
1703 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1704 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1705 | OHCI1394_HCControl_softReset) == 0) | |
1706 | return 0; | |
1707 | msleep(1); | |
1708 | } | |
1709 | ||
1710 | return -EBUSY; | |
1711 | } | |
1712 | ||
1713 | /* ---------- pci subsystem interface ---------- */ | |
1714 | ||
1715 | enum { | |
1716 | CLEANUP_SELF_ID, | |
1717 | CLEANUP_REGISTERS, | |
1718 | CLEANUP_IOMEM, | |
1719 | CLEANUP_DISABLE, | |
1720 | CLEANUP_PUT_CARD, | |
1721 | }; | |
1722 | ||
1723 | static int cleanup(struct fw_ohci *ohci, int stage, int code) | |
1724 | { | |
1725 | struct pci_dev *dev = to_pci_dev(ohci->card.device); | |
1726 | ||
1727 | switch (stage) { | |
1728 | case CLEANUP_SELF_ID: | |
1729 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
1730 | ohci->self_id_cpu, ohci->self_id_bus); | |
1731 | case CLEANUP_REGISTERS: | |
1732 | kfree(ohci->it_context_list); | |
1733 | kfree(ohci->ir_context_list); | |
1734 | pci_iounmap(dev, ohci->registers); | |
1735 | case CLEANUP_IOMEM: | |
1736 | pci_release_region(dev, 0); | |
1737 | case CLEANUP_DISABLE: | |
1738 | pci_disable_device(dev); | |
1739 | case CLEANUP_PUT_CARD: | |
1740 | fw_card_put(&ohci->card); | |
1741 | } | |
1742 | ||
1743 | return code; | |
1744 | } | |
1745 | ||
1746 | static int __devinit | |
1747 | pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |
1748 | { | |
1749 | struct fw_ohci *ohci; | |
e364cf4e | 1750 | u32 bus_options, max_receive, link_speed; |
ed568912 KH |
1751 | u64 guid; |
1752 | int error_code; | |
1753 | size_t size; | |
1754 | ||
1755 | ohci = kzalloc(sizeof *ohci, GFP_KERNEL); | |
1756 | if (ohci == NULL) { | |
1757 | fw_error("Could not malloc fw_ohci data.\n"); | |
1758 | return -ENOMEM; | |
1759 | } | |
1760 | ||
1761 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
1762 | ||
1763 | if (pci_enable_device(dev)) { | |
1764 | fw_error("Failed to enable OHCI hardware.\n"); | |
1765 | return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV); | |
1766 | } | |
1767 | ||
1768 | pci_set_master(dev); | |
1769 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
1770 | pci_set_drvdata(dev, ohci); | |
1771 | ||
1772 | spin_lock_init(&ohci->lock); | |
1773 | ||
1774 | tasklet_init(&ohci->bus_reset_tasklet, | |
1775 | bus_reset_tasklet, (unsigned long)ohci); | |
1776 | ||
1777 | if (pci_request_region(dev, 0, ohci_driver_name)) { | |
1778 | fw_error("MMIO resource unavailable\n"); | |
1779 | return cleanup(ohci, CLEANUP_DISABLE, -EBUSY); | |
1780 | } | |
1781 | ||
1782 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
1783 | if (ohci->registers == NULL) { | |
1784 | fw_error("Failed to remap registers\n"); | |
1785 | return cleanup(ohci, CLEANUP_IOMEM, -ENXIO); | |
1786 | } | |
1787 | ||
1788 | if (software_reset(ohci)) { | |
1789 | fw_error("Failed to reset ohci card.\n"); | |
1790 | return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY); | |
1791 | } | |
1792 | ||
1793 | /* Now enable LPS, which we need in order to start accessing | |
1794 | * most of the registers. In fact, on some cards (ALI M5251), | |
1795 | * accessing registers in the SClk domain without LPS enabled | |
1796 | * will lock up the machine. Wait 50msec to make sure we have | |
1797 | * full link enabled. */ | |
1798 | reg_write(ohci, OHCI1394_HCControlSet, | |
1799 | OHCI1394_HCControl_LPS | | |
1800 | OHCI1394_HCControl_postedWriteEnable); | |
1801 | flush_writes(ohci); | |
1802 | msleep(50); | |
1803 | ||
1804 | reg_write(ohci, OHCI1394_HCControlClear, | |
1805 | OHCI1394_HCControl_noByteSwapData); | |
1806 | ||
1807 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1808 | OHCI1394_LinkControl_rcvSelfID | | |
1809 | OHCI1394_LinkControl_cycleTimerEnable | | |
1810 | OHCI1394_LinkControl_cycleMaster); | |
1811 | ||
1812 | ar_context_init(&ohci->ar_request_ctx, ohci, | |
1813 | OHCI1394_AsReqRcvContextControlSet); | |
1814 | ||
1815 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
1816 | OHCI1394_AsRspRcvContextControlSet); | |
1817 | ||
f319b6a0 KH |
1818 | context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE, |
1819 | OHCI1394_AsReqTrContextControlSet, handle_at_packet); | |
ed568912 | 1820 | |
f319b6a0 KH |
1821 | context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE, |
1822 | OHCI1394_AsRspTrContextControlSet, handle_at_packet); | |
ed568912 KH |
1823 | |
1824 | reg_write(ohci, OHCI1394_ATRetries, | |
1825 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1826 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1827 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1828 | ||
1829 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); | |
1830 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
1831 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
1832 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
1833 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
1834 | ||
1835 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
1836 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); | |
1837 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
1838 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
1839 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
1840 | ||
1841 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
1842 | fw_error("Out of memory for it/ir contexts.\n"); | |
1843 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1844 | } | |
1845 | ||
1846 | /* self-id dma buffer allocation */ | |
1847 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
1848 | SELF_ID_BUF_SIZE, | |
1849 | &ohci->self_id_bus, | |
1850 | GFP_KERNEL); | |
1851 | if (ohci->self_id_cpu == NULL) { | |
1852 | fw_error("Out of memory for self ID buffer.\n"); | |
1853 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1854 | } | |
1855 | ||
1856 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | |
1857 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); | |
1858 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1859 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1860 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1861 | OHCI1394_selfIDComplete | | |
1862 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1863 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1864 | OHCI1394_isochRx | OHCI1394_isochTx | | |
1865 | OHCI1394_masterIntEnable); | |
1866 | ||
1867 | bus_options = reg_read(ohci, OHCI1394_BusOptions); | |
1868 | max_receive = (bus_options >> 12) & 0xf; | |
1869 | link_speed = bus_options & 0x7; | |
1870 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
1871 | reg_read(ohci, OHCI1394_GUIDLo); | |
1872 | ||
1873 | error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid); | |
1874 | if (error_code < 0) | |
1875 | return cleanup(ohci, CLEANUP_SELF_ID, error_code); | |
1876 | ||
e364cf4e | 1877 | ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
500be725 | 1878 | fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n", |
e364cf4e | 1879 | dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff); |
ed568912 KH |
1880 | |
1881 | return 0; | |
1882 | } | |
1883 | ||
1884 | static void pci_remove(struct pci_dev *dev) | |
1885 | { | |
1886 | struct fw_ohci *ohci; | |
1887 | ||
1888 | ohci = pci_get_drvdata(dev); | |
e254a4b4 KH |
1889 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); |
1890 | flush_writes(ohci); | |
ed568912 KH |
1891 | fw_core_remove_card(&ohci->card); |
1892 | ||
1893 | /* FIXME: Fail all pending packets here, now that the upper | |
1894 | * layers can't queue any more. */ | |
1895 | ||
1896 | software_reset(ohci); | |
1897 | free_irq(dev->irq, ohci); | |
1898 | cleanup(ohci, CLEANUP_SELF_ID, 0); | |
1899 | ||
1900 | fw_notify("Removed fw-ohci device.\n"); | |
1901 | } | |
1902 | ||
1903 | static struct pci_device_id pci_table[] = { | |
1904 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
1905 | { } | |
1906 | }; | |
1907 | ||
1908 | MODULE_DEVICE_TABLE(pci, pci_table); | |
1909 | ||
1910 | static struct pci_driver fw_ohci_pci_driver = { | |
1911 | .name = ohci_driver_name, | |
1912 | .id_table = pci_table, | |
1913 | .probe = pci_probe, | |
1914 | .remove = pci_remove, | |
1915 | }; | |
1916 | ||
1917 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
1918 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
1919 | MODULE_LICENSE("GPL"); | |
1920 | ||
1921 | static int __init fw_ohci_init(void) | |
1922 | { | |
1923 | return pci_register_driver(&fw_ohci_pci_driver); | |
1924 | } | |
1925 | ||
1926 | static void __exit fw_ohci_cleanup(void) | |
1927 | { | |
1928 | pci_unregister_driver(&fw_ohci_pci_driver); | |
1929 | } | |
1930 | ||
1931 | module_init(fw_ohci_init); | |
1932 | module_exit(fw_ohci_cleanup); |