[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / extcon / extcon-intel-cht-wc.c

/*
 * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC
 * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
 *
 * Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
 * Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/extcon.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#define CHT_WC_PHYCTRL			0x5e07

#define CHT_WC_CHGRCTRL0		0x5e16
#define CHT_WC_CHGRCTRL0_CHGRRESET	BIT(0)
#define CHT_WC_CHGRCTRL0_EMRGCHREN	BIT(1)
#define CHT_WC_CHGRCTRL0_EXTCHRDIS	BIT(2)
#define CHT_WC_CHGRCTRL0_SWCONTROL	BIT(3)
#define CHT_WC_CHGRCTRL0_TTLCK_MASK	BIT(4)
#define CHT_WC_CHGRCTRL0_CCSM_OFF_MASK	BIT(5)
#define CHT_WC_CHGRCTRL0_DBPOFF_MASK	BIT(6)
#define CHT_WC_CHGRCTRL0_WDT_NOKICK	BIT(7)

#define CHT_WC_CHGRCTRL1		0x5e17

#define CHT_WC_USBSRC			0x5e29
#define CHT_WC_USBSRC_STS_MASK		GENMASK(1, 0)
#define CHT_WC_USBSRC_STS_SUCCESS	2
#define CHT_WC_USBSRC_STS_FAIL		3
#define CHT_WC_USBSRC_TYPE_SHIFT	2
#define CHT_WC_USBSRC_TYPE_MASK		GENMASK(5, 2)
#define CHT_WC_USBSRC_TYPE_NONE		0
#define CHT_WC_USBSRC_TYPE_SDP		1
#define CHT_WC_USBSRC_TYPE_DCP		2
#define CHT_WC_USBSRC_TYPE_CDP		3
#define CHT_WC_USBSRC_TYPE_ACA		4
#define CHT_WC_USBSRC_TYPE_SE1		5
#define CHT_WC_USBSRC_TYPE_MHL		6
#define CHT_WC_USBSRC_TYPE_FLOAT_DP_DN	7
#define CHT_WC_USBSRC_TYPE_OTHER	8
#define CHT_WC_USBSRC_TYPE_DCP_EXTPHY	9

#define CHT_WC_PWRSRC_IRQ		0x6e03
#define CHT_WC_PWRSRC_IRQ_MASK		0x6e0f
#define CHT_WC_PWRSRC_STS		0x6e1e
#define CHT_WC_PWRSRC_VBUS		BIT(0)
#define CHT_WC_PWRSRC_DC		BIT(1)
#define CHT_WC_PWRSRC_BAT		BIT(2)
#define CHT_WC_PWRSRC_ID_GND		BIT(3)
#define CHT_WC_PWRSRC_ID_FLOAT		BIT(4)

#define CHT_WC_VBUS_GPIO_CTLO		0x6e2d
#define CHT_WC_VBUS_GPIO_CTLO_OUTPUT	BIT(0)

enum cht_wc_usb_id {
	USB_ID_OTG,
	USB_ID_GND,
	USB_ID_FLOAT,
	USB_RID_A,
	USB_RID_B,
	USB_RID_C,
};

enum cht_wc_mux_select {
	MUX_SEL_PMIC = 0,
	MUX_SEL_SOC,
};

static const unsigned int cht_wc_extcon_cables[] = {
	EXTCON_USB,
	EXTCON_USB_HOST,
	EXTCON_CHG_USB_SDP,
	EXTCON_CHG_USB_CDP,
	EXTCON_CHG_USB_DCP,
	EXTCON_CHG_USB_ACA,
	EXTCON_NONE,
};

struct cht_wc_extcon_data {
	struct device *dev;
	struct regmap *regmap;
	struct extcon_dev *edev;
	unsigned int previous_cable;
};

static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts)
{
	if (pwrsrc_sts & CHT_WC_PWRSRC_ID_GND)
		return USB_ID_GND;
	if (pwrsrc_sts & CHT_WC_PWRSRC_ID_FLOAT)
		return USB_ID_FLOAT;

	/*
	 * Once we have iio support for the gpadc we should read the USBID
	 * gpadc channel here and determine ACA role based on that.
	 */
	return USB_ID_FLOAT;
}

static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext)
{
	int ret, usbsrc, status;
	unsigned long timeout;

	/* Charger detection can take upto 600ms, wait 800ms max. */
	timeout = jiffies + msecs_to_jiffies(800);
	do {
		ret = regmap_read(ext->regmap, CHT_WC_USBSRC, &usbsrc);
		if (ret) {
			dev_err(ext->dev, "Error reading usbsrc: %d\n", ret);
			return ret;
		}

		status = usbsrc & CHT_WC_USBSRC_STS_MASK;
		if (status == CHT_WC_USBSRC_STS_SUCCESS ||
		    status == CHT_WC_USBSRC_STS_FAIL)
			break;

		msleep(50); /* Wait a bit before retrying */
	} while (time_before(jiffies, timeout));

	if (status != CHT_WC_USBSRC_STS_SUCCESS) {
		if (status == CHT_WC_USBSRC_STS_FAIL)
			dev_warn(ext->dev, "Could not detect charger type\n");
		else
			dev_warn(ext->dev, "Timeout detecting charger type\n");
		return EXTCON_CHG_USB_SDP; /* Save fallback */
	}

	usbsrc = (usbsrc & CHT_WC_USBSRC_TYPE_MASK) >> CHT_WC_USBSRC_TYPE_SHIFT;
	switch (usbsrc) {
	default:
		dev_warn(ext->dev,
			"Unhandled charger type %d, defaulting to SDP\n",
			 ret);
		/* Fall through, treat as SDP */
	case CHT_WC_USBSRC_TYPE_SDP:
	case CHT_WC_USBSRC_TYPE_FLOAT_DP_DN:
	case CHT_WC_USBSRC_TYPE_OTHER:
		return EXTCON_CHG_USB_SDP;
	case CHT_WC_USBSRC_TYPE_CDP:
		return EXTCON_CHG_USB_CDP;
	case CHT_WC_USBSRC_TYPE_DCP:
	case CHT_WC_USBSRC_TYPE_DCP_EXTPHY:
	case CHT_WC_USBSRC_TYPE_MHL: /* MHL2+ delivers upto 2A, treat as DCP */
		return EXTCON_CHG_USB_DCP;
	case CHT_WC_USBSRC_TYPE_ACA:
		return EXTCON_CHG_USB_ACA;
	}
}

static void cht_wc_extcon_set_phymux(struct cht_wc_extcon_data *ext, u8 state)
{
	int ret;

	ret = regmap_write(ext->regmap, CHT_WC_PHYCTRL, state);
	if (ret)
		dev_err(ext->dev, "Error writing phyctrl: %d\n", ret);
}

static void cht_wc_extcon_set_5v_boost(struct cht_wc_extcon_data *ext,
				       bool enable)
{
	int ret, val;

	val = enable ? CHT_WC_VBUS_GPIO_CTLO_OUTPUT : 0;

	/*
	 * The 5V boost converter is enabled through a gpio on the PMIC, since
	 * there currently is no gpio driver we access the gpio reg directly.
	 */
	ret = regmap_update_bits(ext->regmap, CHT_WC_VBUS_GPIO_CTLO,
				 CHT_WC_VBUS_GPIO_CTLO_OUTPUT, val);
	if (ret)
		dev_err(ext->dev, "Error writing Vbus GPIO CTLO: %d\n", ret);
}

/* Small helper to sync EXTCON_CHG_USB_SDP and EXTCON_USB state */
static void cht_wc_extcon_set_state(struct cht_wc_extcon_data *ext,
				    unsigned int cable, bool state)
{
	extcon_set_state_sync(ext->edev, cable, state);
	if (cable == EXTCON_CHG_USB_SDP)
		extcon_set_state_sync(ext->edev, EXTCON_USB, state);
}

static void cht_wc_extcon_pwrsrc_event(struct cht_wc_extcon_data *ext)
{
	int ret, pwrsrc_sts, id;
	unsigned int cable = EXTCON_NONE;

	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
	if (ret) {
		dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
		return;
	}

	id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
	if (id == USB_ID_GND) {
		/* The 5v boost causes a false VBUS / SDP detect, skip */
		goto charger_det_done;
	}

	/* Plugged into a host/charger or not connected? */
	if (!(pwrsrc_sts & CHT_WC_PWRSRC_VBUS)) {
		/* Route D+ and D- to PMIC for future charger detection */
		cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
		goto set_state;
	}

	ret = cht_wc_extcon_get_charger(ext);
	if (ret >= 0)
		cable = ret;

charger_det_done:
	/* Route D+ and D- to SoC for the host or gadget controller */
	cht_wc_extcon_set_phymux(ext, MUX_SEL_SOC);

set_state:
	if (cable != ext->previous_cable) {
		cht_wc_extcon_set_state(ext, cable, true);
		cht_wc_extcon_set_state(ext, ext->previous_cable, false);
		ext->previous_cable = cable;
	}

	extcon_set_state_sync(ext->edev, EXTCON_USB_HOST,
			      id == USB_ID_GND || id == USB_RID_A);
}

static irqreturn_t cht_wc_extcon_isr(int irq, void *data)
{
	struct cht_wc_extcon_data *ext = data;
	int ret, irqs;

	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs);
	if (ret) {
		dev_err(ext->dev, "Error reading irqs: %d\n", ret);
		return IRQ_NONE;
	}

	cht_wc_extcon_pwrsrc_event(ext);

	ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs);
	if (ret) {
		dev_err(ext->dev, "Error writing irqs: %d\n", ret);
		return IRQ_NONE;
	}

	return IRQ_HANDLED;
}

static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable)
{
	int ret, mask, val;

	mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF_MASK;
	val = enable ? mask : 0;
	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val);
	if (ret)
		dev_err(ext->dev, "Error setting sw control: %d\n", ret);

	return ret;
}

static int cht_wc_extcon_probe(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
	struct cht_wc_extcon_data *ext;
	int irq, ret;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	ext = devm_kzalloc(&pdev->dev, sizeof(*ext), GFP_KERNEL);
	if (!ext)
		return -ENOMEM;

	ext->dev = &pdev->dev;
	ext->regmap = pmic->regmap;
	ext->previous_cable = EXTCON_NONE;

	/* Initialize extcon device */
	ext->edev = devm_extcon_dev_allocate(ext->dev, cht_wc_extcon_cables);
	if (IS_ERR(ext->edev))
		return PTR_ERR(ext->edev);

	/*
	 * When a host-cable is detected the BIOS enables an external 5v boost
	 * converter to power connected devices there are 2 problems with this:
	 * 1) This gets seen by the external battery charger as a valid Vbus
	 *    supply and it then tries to feed Vsys from this creating a
	 *    feedback loop which causes aprox. 300 mA extra battery drain
	 *    (and unless we drive the external-charger-disable pin high it
	 *    also tries to charge the battery causing even more feedback).
	 * 2) This gets seen by the pwrsrc block as a SDP USB Vbus supply
	 * Since the external battery charger has its own 5v boost converter
	 * which does not have these issues, we simply turn the separate
	 * external 5v boost converter off and leave it off entirely.
	 */
	cht_wc_extcon_set_5v_boost(ext, false);

	/* Enable sw control */
	ret = cht_wc_extcon_sw_control(ext, true);
	if (ret)
		return ret;

	/* Register extcon device */
	ret = devm_extcon_dev_register(ext->dev, ext->edev);
	if (ret) {
		dev_err(ext->dev, "Error registering extcon device: %d\n", ret);
		goto disable_sw_control;
	}

	/* Route D+ and D- to PMIC for initial charger detection */
	cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);

	/* Get initial state */
	cht_wc_extcon_pwrsrc_event(ext);

	ret = devm_request_threaded_irq(ext->dev, irq, NULL, cht_wc_extcon_isr,
					IRQF_ONESHOT, pdev->name, ext);
	if (ret) {
		dev_err(ext->dev, "Error requesting interrupt: %d\n", ret);
		goto disable_sw_control;
	}

	/* Unmask irqs */
	ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK,
			   (int)~(CHT_WC_PWRSRC_VBUS | CHT_WC_PWRSRC_ID_GND |
				  CHT_WC_PWRSRC_ID_FLOAT));
	if (ret) {
		dev_err(ext->dev, "Error writing irq-mask: %d\n", ret);
		goto disable_sw_control;
	}

	platform_set_drvdata(pdev, ext);

	return 0;

disable_sw_control:
	cht_wc_extcon_sw_control(ext, false);
	return ret;
}

static int cht_wc_extcon_remove(struct platform_device *pdev)
{
	struct cht_wc_extcon_data *ext = platform_get_drvdata(pdev);

	cht_wc_extcon_sw_control(ext, false);

	return 0;
}

static const struct platform_device_id cht_wc_extcon_table[] = {
	{ .name = "cht_wcove_pwrsrc" },
	{},
};
MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);

static struct platform_driver cht_wc_extcon_driver = {
	.probe = cht_wc_extcon_probe,
	.remove = cht_wc_extcon_remove,
	.id_table = cht_wc_extcon_table,
	.driver = {
		.name = "cht_wcove_pwrsrc",
	},
};
module_platform_driver(cht_wc_extcon_driver);

MODULE_DESCRIPTION("Intel Cherrytrail Whiskey Cove PMIC extcon driver");
MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
db0f3baa HG	1	/*
	2	* Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC
	3	* Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
	4	*
	5	* Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
	6	* Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2, as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*/
	17
	18	#include <linux/extcon.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/kernel.h>
	21	#include <linux/mfd/intel_soc_pmic.h>
	22	#include <linux/module.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/regmap.h>
	25	#include <linux/slab.h>
	26
	27	#define CHT_WC_PHYCTRL 0x5e07
	28
	29	#define CHT_WC_CHGRCTRL0 0x5e16
	30	#define CHT_WC_CHGRCTRL0_CHGRRESET BIT(0)
	31	#define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1)
	32	#define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2)
	33	#define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3)
	34	#define CHT_WC_CHGRCTRL0_TTLCK_MASK BIT(4)
	35	#define CHT_WC_CHGRCTRL0_CCSM_OFF_MASK BIT(5)
	36	#define CHT_WC_CHGRCTRL0_DBPOFF_MASK BIT(6)
	37	#define CHT_WC_CHGRCTRL0_WDT_NOKICK BIT(7)
	38
	39	#define CHT_WC_CHGRCTRL1 0x5e17
	40
	41	#define CHT_WC_USBSRC 0x5e29
	42	#define CHT_WC_USBSRC_STS_MASK GENMASK(1, 0)
	43	#define CHT_WC_USBSRC_STS_SUCCESS 2
	44	#define CHT_WC_USBSRC_STS_FAIL 3
	45	#define CHT_WC_USBSRC_TYPE_SHIFT 2
	46	#define CHT_WC_USBSRC_TYPE_MASK GENMASK(5, 2)
	47	#define CHT_WC_USBSRC_TYPE_NONE 0
	48	#define CHT_WC_USBSRC_TYPE_SDP 1
	49	#define CHT_WC_USBSRC_TYPE_DCP 2
	50	#define CHT_WC_USBSRC_TYPE_CDP 3
	51	#define CHT_WC_USBSRC_TYPE_ACA 4
	52	#define CHT_WC_USBSRC_TYPE_SE1 5
	53	#define CHT_WC_USBSRC_TYPE_MHL 6
	54	#define CHT_WC_USBSRC_TYPE_FLOAT_DP_DN 7
	55	#define CHT_WC_USBSRC_TYPE_OTHER 8
	56	#define CHT_WC_USBSRC_TYPE_DCP_EXTPHY 9
	57
	58	#define CHT_WC_PWRSRC_IRQ 0x6e03
	59	#define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f
	60	#define CHT_WC_PWRSRC_STS 0x6e1e
	61	#define CHT_WC_PWRSRC_VBUS BIT(0)
	62	#define CHT_WC_PWRSRC_DC BIT(1)
	63	#define CHT_WC_PWRSRC_BAT BIT(2)
	64	#define CHT_WC_PWRSRC_ID_GND BIT(3)
65	#define CHT_WC_PWRSRC_ID_FLOAT BIT(4)
66
585cb239 HG	67	#define CHT_WC_VBUS_GPIO_CTLO 0x6e2d
	68	#define CHT_WC_VBUS_GPIO_CTLO_OUTPUT BIT(0)
	69
db0f3baa HG	70	enum cht_wc_usb_id {
	71	USB_ID_OTG,
	72	USB_ID_GND,
	73	USB_ID_FLOAT,
	74	USB_RID_A,
	75	USB_RID_B,
	76	USB_RID_C,
	77	};
	78
	79	enum cht_wc_mux_select {
	80	MUX_SEL_PMIC = 0,
	81	MUX_SEL_SOC,
	82	};
	83
	84	static const unsigned int cht_wc_extcon_cables[] = {
	85	EXTCON_USB,
	86	EXTCON_USB_HOST,
	87	EXTCON_CHG_USB_SDP,
	88	EXTCON_CHG_USB_CDP,
	89	EXTCON_CHG_USB_DCP,
	90	EXTCON_CHG_USB_ACA,
	91	EXTCON_NONE,
	92	};
	93
	94	struct cht_wc_extcon_data {
	95	struct device *dev;
	96	struct regmap *regmap;
	97	struct extcon_dev *edev;
	98	unsigned int previous_cable;
	99	};
	100
	101	static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts)
	102	{
	103	if (pwrsrc_sts & CHT_WC_PWRSRC_ID_GND)
	104	return USB_ID_GND;
	105	if (pwrsrc_sts & CHT_WC_PWRSRC_ID_FLOAT)
	106	return USB_ID_FLOAT;
	107
	108	/*
	109	* Once we have iio support for the gpadc we should read the USBID
	110	* gpadc channel here and determine ACA role based on that.
	111	*/
	112	return USB_ID_FLOAT;
	113	}
	114
	115	static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext)
	116	{
	117	int ret, usbsrc, status;
	118	unsigned long timeout;
	119
	120	/* Charger detection can take upto 600ms, wait 800ms max. */
	121	timeout = jiffies + msecs_to_jiffies(800);
	122	do {
	123	ret = regmap_read(ext->regmap, CHT_WC_USBSRC, &usbsrc);
	124	if (ret) {
	125	dev_err(ext->dev, "Error reading usbsrc: %d\n", ret);
	126	return ret;
	127	}
	128
	129	status = usbsrc & CHT_WC_USBSRC_STS_MASK;
	130	if (status == CHT_WC_USBSRC_STS_SUCCESS \|\|
	131	status == CHT_WC_USBSRC_STS_FAIL)
	132	break;
	133
134	msleep(50); /* Wait a bit before retrying */
135	} while (time_before(jiffies, timeout));
136
137	if (status != CHT_WC_USBSRC_STS_SUCCESS) {
138	if (status == CHT_WC_USBSRC_STS_FAIL)
139	dev_warn(ext->dev, "Could not detect charger type\n");
140	else
141	dev_warn(ext->dev, "Timeout detecting charger type\n");
142	return EXTCON_CHG_USB_SDP; /* Save fallback */
143	}
144
145	usbsrc = (usbsrc & CHT_WC_USBSRC_TYPE_MASK) >> CHT_WC_USBSRC_TYPE_SHIFT;
146	switch (usbsrc) {
147	default:
148	dev_warn(ext->dev,
149	"Unhandled charger type %d, defaulting to SDP\n",
150	ret);
151	/* Fall through, treat as SDP */
152	case CHT_WC_USBSRC_TYPE_SDP:
153	case CHT_WC_USBSRC_TYPE_FLOAT_DP_DN:
154	case CHT_WC_USBSRC_TYPE_OTHER:
155	return EXTCON_CHG_USB_SDP;
156	case CHT_WC_USBSRC_TYPE_CDP:
157	return EXTCON_CHG_USB_CDP;
158	case CHT_WC_USBSRC_TYPE_DCP:
159	case CHT_WC_USBSRC_TYPE_DCP_EXTPHY:
160	case CHT_WC_USBSRC_TYPE_MHL: /* MHL2+ delivers upto 2A, treat as DCP */
161	return EXTCON_CHG_USB_DCP;
162	case CHT_WC_USBSRC_TYPE_ACA:
163	return EXTCON_CHG_USB_ACA;
164	}
165	}
166
167	static void cht_wc_extcon_set_phymux(struct cht_wc_extcon_data *ext, u8 state)
168	{
169	int ret;
170
171	ret = regmap_write(ext->regmap, CHT_WC_PHYCTRL, state);
172	if (ret)
173	dev_err(ext->dev, "Error writing phyctrl: %d\n", ret);
174	}
175
585cb239 HG	176	static void cht_wc_extcon_set_5v_boost(struct cht_wc_extcon_data *ext,
	177	bool enable)
	178	{
	179	int ret, val;
	180
	181	val = enable ? CHT_WC_VBUS_GPIO_CTLO_OUTPUT : 0;
	182
	183	/*
	184	* The 5V boost converter is enabled through a gpio on the PMIC, since
	185	* there currently is no gpio driver we access the gpio reg directly.
	186	*/
	187	ret = regmap_update_bits(ext->regmap, CHT_WC_VBUS_GPIO_CTLO,
	188	CHT_WC_VBUS_GPIO_CTLO_OUTPUT, val);
	189	if (ret)
	190	dev_err(ext->dev, "Error writing Vbus GPIO CTLO: %d\n", ret);
	191	}
	192
db0f3baa HG	193	/* Small helper to sync EXTCON_CHG_USB_SDP and EXTCON_USB state */
	194	static void cht_wc_extcon_set_state(struct cht_wc_extcon_data *ext,
	195	unsigned int cable, bool state)
	196	{
	197	extcon_set_state_sync(ext->edev, cable, state);
	198	if (cable == EXTCON_CHG_USB_SDP)
	199	extcon_set_state_sync(ext->edev, EXTCON_USB, state);
	200	}
	201
	202	static void cht_wc_extcon_pwrsrc_event(struct cht_wc_extcon_data *ext)
	203	{
	204	int ret, pwrsrc_sts, id;
	205	unsigned int cable = EXTCON_NONE;
	206
	207	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
	208	if (ret) {
	209	dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
	210	return;
	211	}
	212
	213	id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
	214	if (id == USB_ID_GND) {
	215	/* The 5v boost causes a false VBUS / SDP detect, skip */
	216	goto charger_det_done;
	217	}
	218
	219	/* Plugged into a host/charger or not connected? */
	220	if (!(pwrsrc_sts & CHT_WC_PWRSRC_VBUS)) {
	221	/* Route D+ and D- to PMIC for future charger detection */
	222	cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
	223	goto set_state;
	224	}
	225
	226	ret = cht_wc_extcon_get_charger(ext);
	227	if (ret >= 0)
	228	cable = ret;
	229
	230	charger_det_done:
	231	/* Route D+ and D- to SoC for the host or gadget controller */
	232	cht_wc_extcon_set_phymux(ext, MUX_SEL_SOC);
	233
	234	set_state:
	235	if (cable != ext->previous_cable) {
	236	cht_wc_extcon_set_state(ext, cable, true);
	237	cht_wc_extcon_set_state(ext, ext->previous_cable, false);
	238	ext->previous_cable = cable;
	239	}
	240
	241	extcon_set_state_sync(ext->edev, EXTCON_USB_HOST,
	242	id == USB_ID_GND \|\| id == USB_RID_A);
	243	}
	244
	245	static irqreturn_t cht_wc_extcon_isr(int irq, void *data)
	246	{
	247	struct cht_wc_extcon_data *ext = data;
	248	int ret, irqs;
	249
	250	ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs);
	251	if (ret) {
	252	dev_err(ext->dev, "Error reading irqs: %d\n", ret);
	253	return IRQ_NONE;
	254	}
	255
	256	cht_wc_extcon_pwrsrc_event(ext);
257
258	ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs);
259	if (ret) {
260	dev_err(ext->dev, "Error writing irqs: %d\n", ret);
261	return IRQ_NONE;
262	}
263
264	return IRQ_HANDLED;
265	}
266
267	static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable)
268	{
269	int ret, mask, val;
270
271	mask = CHT_WC_CHGRCTRL0_SWCONTROL \| CHT_WC_CHGRCTRL0_CCSM_OFF_MASK;
272	val = enable ? mask : 0;
273	ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val);
274	if (ret)
275	dev_err(ext->dev, "Error setting sw control: %d\n", ret);
276
277	return ret;
278	}
279
280	static int cht_wc_extcon_probe(struct platform_device *pdev)
281	{
282	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
283	struct cht_wc_extcon_data *ext;
284	int irq, ret;
285
286	irq = platform_get_irq(pdev, 0);
287	if (irq < 0)
288	return irq;
289
290	ext = devm_kzalloc(&pdev->dev, sizeof(*ext), GFP_KERNEL);
291	if (!ext)
292	return -ENOMEM;
293
294	ext->dev = &pdev->dev;
295	ext->regmap = pmic->regmap;
296	ext->previous_cable = EXTCON_NONE;
297
298	/* Initialize extcon device */
299	ext->edev = devm_extcon_dev_allocate(ext->dev, cht_wc_extcon_cables);
300	if (IS_ERR(ext->edev))
301	return PTR_ERR(ext->edev);
302
585cb239 HG	303	/*
	304	* When a host-cable is detected the BIOS enables an external 5v boost
	305	* converter to power connected devices there are 2 problems with this:
	306	* 1) This gets seen by the external battery charger as a valid Vbus
	307	* supply and it then tries to feed Vsys from this creating a
	308	* feedback loop which causes aprox. 300 mA extra battery drain
	309	* (and unless we drive the external-charger-disable pin high it
	310	* also tries to charge the battery causing even more feedback).
	311	* 2) This gets seen by the pwrsrc block as a SDP USB Vbus supply
	312	* Since the external battery charger has its own 5v boost converter
	313	* which does not have these issues, we simply turn the separate
	314	* external 5v boost converter off and leave it off entirely.
	315	*/
	316	cht_wc_extcon_set_5v_boost(ext, false);
	317
db0f3baa HG	318	/* Enable sw control */
	319	ret = cht_wc_extcon_sw_control(ext, true);
	320	if (ret)
	321	return ret;
	322
	323	/* Register extcon device */
	324	ret = devm_extcon_dev_register(ext->dev, ext->edev);
	325	if (ret) {
	326	dev_err(ext->dev, "Error registering extcon device: %d\n", ret);
	327	goto disable_sw_control;
	328	}
	329
	330	/* Route D+ and D- to PMIC for initial charger detection */
	331	cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
	332
	333	/* Get initial state */
	334	cht_wc_extcon_pwrsrc_event(ext);
	335
	336	ret = devm_request_threaded_irq(ext->dev, irq, NULL, cht_wc_extcon_isr,
	337	IRQF_ONESHOT, pdev->name, ext);
	338	if (ret) {
	339	dev_err(ext->dev, "Error requesting interrupt: %d\n", ret);
	340	goto disable_sw_control;
	341	}
	342
	343	/* Unmask irqs */
	344	ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK,
	345	(int)~(CHT_WC_PWRSRC_VBUS \| CHT_WC_PWRSRC_ID_GND \|
	346	CHT_WC_PWRSRC_ID_FLOAT));
	347	if (ret) {
	348	dev_err(ext->dev, "Error writing irq-mask: %d\n", ret);
	349	goto disable_sw_control;
	350	}
	351
	352	platform_set_drvdata(pdev, ext);
	353
	354	return 0;
	355
	356	disable_sw_control:
	357	cht_wc_extcon_sw_control(ext, false);
	358	return ret;
	359	}
	360
	361	static int cht_wc_extcon_remove(struct platform_device *pdev)
	362	{
	363	struct cht_wc_extcon_data *ext = platform_get_drvdata(pdev);
	364
	365	cht_wc_extcon_sw_control(ext, false);
	366
	367	return 0;
	368	}
	369
	370	static const struct platform_device_id cht_wc_extcon_table[] = {
	371	{ .name = "cht_wcove_pwrsrc" },
	372	{},
	373	};
	374	MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);
	375
	376	static struct platform_driver cht_wc_extcon_driver = {
	377	.probe = cht_wc_extcon_probe,
	378	.remove = cht_wc_extcon_remove,
	379	.id_table = cht_wc_extcon_table,
	380	.driver = {
	381	.name = "cht_wcove_pwrsrc",
382	},
383	};
384	module_platform_driver(cht_wc_extcon_driver);
385
386	MODULE_DESCRIPTION("Intel Cherrytrail Whiskey Cove PMIC extcon driver");
387	MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
388	MODULE_LICENSE("GPL v2");