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ACPICA: Utilities: Cleanup to remove useless ACPI_PRINTF/FORMAT_xxx helpers.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / sb_edac.c
CommitLineData
eebf11a0
MCC		 1/* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab <mchehab@redhat.com>
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/pci_ids.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/edac.h>
20#include <linux/mmzone.h>
eebf11a0
MCC		 21#include <linux/smp.h>
22#include <linux/bitmap.h>
5b889e37 23#include <linux/math64.h>
eebf11a0 24#include <asm/processor.h>
3d78c9af 25#include <asm/mce.h>
eebf11a0
MCC		 26
27#include "edac_core.h"
28
29/* Static vars */
30static LIST_HEAD(sbridge_edac_list);
31static DEFINE_MUTEX(sbridge_edac_lock);
32static int probed;
33
34/*
35 * Alter this version for the module when modifications are made
36 */
37#define SBRIDGE_REVISION " Ver: 1.0.0 "
38#define EDAC_MOD_STR "sbridge_edac"
39
40/*
41 * Debug macros
42 */
43#define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
45
46#define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
48
49/*
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 */
52#define GET_BITFIELD(v, lo, hi) \
53 (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))
54
55/*
56 * sbridge Memory Controller Registers
57 */
58
59/*
60 * FIXME: For now, let's order by device function, as it makes
15ed103a 61 * easier for driver's development process. This table should be
eebf11a0
MCC		 62 * moved to pci_id.h when submitted upstream
63 */
64#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
65#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
66#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
67#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
68#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
69#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
70#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
71#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
72#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
73#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
74#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
75
76 /*
77 * Currently, unused, but will be needed in the future
78 * implementations, as they hold the error counters
79 */
80#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
81#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
82#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
83#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
84
85/* Devices 12 Function 6, Offsets 0x80 to 0xcc */
86static const u32 dram_rule[] = {
87 0x80, 0x88, 0x90, 0x98, 0xa0,
88 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
89};
90#define MAX_SAD ARRAY_SIZE(dram_rule)
91
92#define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
93#define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
94#define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
95#define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
96
97static char *get_dram_attr(u32 reg)
98{
99 switch(DRAM_ATTR(reg)) {
100 case 0:
101 return "DRAM";
102 case 1:
103 return "MMCFG";
104 case 2:
105 return "NXM";
106 default:
107 return "unknown";
108 }
109}
110
111static const u32 interleave_list[] = {
112 0x84, 0x8c, 0x94, 0x9c, 0xa4,
113 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
114};
115#define MAX_INTERLEAVE ARRAY_SIZE(interleave_list)
116
117#define SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2)
118#define SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5)
119#define SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10)
120#define SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13)
121#define SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18)
122#define SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21)
123#define SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26)
124#define SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29)
125
126static inline int sad_pkg(u32 reg, int interleave)
127{
128 switch (interleave) {
129 case 0:
130 return SAD_PKG0(reg);
131 case 1:
132 return SAD_PKG1(reg);
133 case 2:
134 return SAD_PKG2(reg);
135 case 3:
136 return SAD_PKG3(reg);
137 case 4:
138 return SAD_PKG4(reg);
139 case 5:
140 return SAD_PKG5(reg);
141 case 6:
142 return SAD_PKG6(reg);
143 case 7:
144 return SAD_PKG7(reg);
145 default:
146 return -EINVAL;
147 }
148}
149
150/* Devices 12 Function 7 */
151
152#define TOLM 0x80
153#define TOHM 0x84
154
155#define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
156#define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
157
158/* Device 13 Function 6 */
159
160#define SAD_TARGET 0xf0
161
162#define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
163
164#define SAD_CONTROL 0xf4
165
166#define NODE_ID(reg) GET_BITFIELD(reg, 0, 2)
167
168/* Device 14 function 0 */
169
170static const u32 tad_dram_rule[] = {
171 0x40, 0x44, 0x48, 0x4c,
172 0x50, 0x54, 0x58, 0x5c,
173 0x60, 0x64, 0x68, 0x6c,
174};
175#define MAX_TAD ARRAY_SIZE(tad_dram_rule)
176
177#define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
178#define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
179#define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
180#define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
181#define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
182#define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
183#define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
184
185/* Device 15, function 0 */
186
187#define MCMTR 0x7c
188
189#define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
190#define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
191#define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
192
193/* Device 15, function 1 */
194
195#define RASENABLES 0xac
196#define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
197
198/* Device 15, functions 2-5 */
199
200static const int mtr_regs[] = {
201 0x80, 0x84, 0x88,
202};
203
204#define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
205#define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
206#define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
207#define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
208#define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
209
210static const u32 tad_ch_nilv_offset[] = {
211 0x90, 0x94, 0x98, 0x9c,
212 0xa0, 0xa4, 0xa8, 0xac,
213 0xb0, 0xb4, 0xb8, 0xbc,
214};
215#define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
216#define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
217
218static const u32 rir_way_limit[] = {
219 0x108, 0x10c, 0x110, 0x114, 0x118,
220};
221#define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
222
223#define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
224#define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
225#define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff)
226
227#define MAX_RIR_WAY 8
228
229static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
230 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
231 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
232 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
233 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
234 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
235};
236
237#define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
238#define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
239
240/* Device 16, functions 2-7 */
241
242/*
243 * FIXME: Implement the error count reads directly
244 */
245
246static const u32 correrrcnt[] = {
247 0x104, 0x108, 0x10c, 0x110,
248};
249
250#define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
251#define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
252#define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
253#define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
254
255static const u32 correrrthrsld[] = {
256 0x11c, 0x120, 0x124, 0x128,
257};
258
259#define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
260#define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
261
262
263/* Device 17, function 0 */
264
265#define RANK_CFG_A 0x0328
266
267#define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11)
268
269/*
270 * sbridge structs
271 */
272
ebe7e30a
SJ		 273#define NUM_CHANNELS 4
274#define MAX_DIMMS 3 /* Max DIMMS per channel */
275#define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
eebf11a0
MCC		 276
277struct sbridge_info {
278 u32 mcmtr;
279};
280
281struct sbridge_channel {
282 u32 ranks;
283 u32 dimms;
284};
285
286struct pci_id_descr {
287 int dev;
288 int func;
289 int dev_id;
290 int optional;
291};
292
293struct pci_id_table {
294 const struct pci_id_descr *descr;
295 int n_devs;
296};
297
298struct sbridge_dev {
299 struct list_head list;
300 u8 bus, mc;
301 u8 node_id, source_id;
302 struct pci_dev **pdev;
303 int n_devs;
304 struct mem_ctl_info *mci;
305};
306
307struct sbridge_pvt {
308 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
309 struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0;
310 struct pci_dev *pci_br;
311 struct pci_dev *pci_tad[NUM_CHANNELS];
312
313 struct sbridge_dev *sbridge_dev;
314
315 struct sbridge_info info;
316 struct sbridge_channel channel[NUM_CHANNELS];
317
eebf11a0
MCC		 318 /* Memory type detection */
319 bool is_mirrored, is_lockstep, is_close_pg;
320
eebf11a0
MCC		 321 /* Fifo double buffers */
322 struct mce mce_entry[MCE_LOG_LEN];
323 struct mce mce_outentry[MCE_LOG_LEN];
324
325 /* Fifo in/out counters */
326 unsigned mce_in, mce_out;
327
328 /* Count indicator to show errors not got */
329 unsigned mce_overrun;
330
331 /* Memory description */
332 u64 tolm, tohm;
333};
334
de4772c6
TL		 335#define PCI_DESCR(device, function, device_id, opt) \
336 .dev = (device), \
337 .func = (function), \
338 .dev_id = (device_id), \
339 .optional = opt
eebf11a0
MCC		 340
341static const struct pci_id_descr pci_dev_descr_sbridge[] = {
342 /* Processor Home Agent */
de4772c6 343 { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) },
eebf11a0
MCC		 344
345 /* Memory controller */
de4772c6
TL		 346 { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) },
347 { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) },
348 { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) },
349 { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) },
350 { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) },
351 { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) },
352 { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) },
eebf11a0
MCC		 353
354 /* System Address Decoder */
de4772c6
TL		 355 { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) },
356 { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) },
eebf11a0
MCC		 357
358 /* Broadcast Registers */
de4772c6 359 { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) },
eebf11a0
MCC		 360};
361
362#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
363static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
364 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
365 {0,} /* 0 terminated list. */
366};
367
368/*
369 * pci_device_id table for which devices we are looking for
370 */
36c46f31 371static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl) = {
eebf11a0
MCC		 372 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
373 {0,} /* 0 terminated list. */
374};
375
376
377/****************************************************************************
15ed103a 378 Ancillary status routines
eebf11a0
MCC		 379 ****************************************************************************/
380
381static inline int numrank(u32 mtr)
382{
383 int ranks = (1 << RANK_CNT_BITS(mtr));
384
385 if (ranks > 4) {
956b9ba1
JP		 386 edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n",
387 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr);
eebf11a0
MCC		 388 return -EINVAL;
389 }
390
391 return ranks;
392}
393
394static inline int numrow(u32 mtr)
395{
396 int rows = (RANK_WIDTH_BITS(mtr) + 12);
397
398 if (rows < 13 || rows > 18) {
956b9ba1
JP		 399 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
400 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
eebf11a0
MCC		 401 return -EINVAL;
402 }
403
404 return 1 << rows;
405}
406
407static inline int numcol(u32 mtr)
408{
409 int cols = (COL_WIDTH_BITS(mtr) + 10);
410
411 if (cols > 12) {
956b9ba1
JP		 412 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
413 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
eebf11a0
MCC		 414 return -EINVAL;
415 }
416
417 return 1 << cols;
418}
419
420static struct sbridge_dev *get_sbridge_dev(u8 bus)
421{
422 struct sbridge_dev *sbridge_dev;
423
424 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
425 if (sbridge_dev->bus == bus)
426 return sbridge_dev;
427 }
428
429 return NULL;
430}
431
432static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
433 const struct pci_id_table *table)
434{
435 struct sbridge_dev *sbridge_dev;
436
437 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
438 if (!sbridge_dev)
439 return NULL;
440
441 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
442 GFP_KERNEL);
443 if (!sbridge_dev->pdev) {
444 kfree(sbridge_dev);
445 return NULL;
446 }
447
448 sbridge_dev->bus = bus;
449 sbridge_dev->n_devs = table->n_devs;
450 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
451
452 return sbridge_dev;
453}
454
455static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
456{
457 list_del(&sbridge_dev->list);
458 kfree(sbridge_dev->pdev);
459 kfree(sbridge_dev);
460}
461
462/****************************************************************************
463 Memory check routines
464 ****************************************************************************/
465static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot,
466 unsigned func)
467{
468 struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus);
469 int i;
470
471 if (!sbridge_dev)
472 return NULL;
473
474 for (i = 0; i < sbridge_dev->n_devs; i++) {
475 if (!sbridge_dev->pdev[i])
476 continue;
477
478 if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot &&
479 PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) {
956b9ba1
JP		 480 edac_dbg(1, "Associated %02x.%02x.%d with %p\n",
481 bus, slot, func, sbridge_dev->pdev[i]);
eebf11a0
MCC		 482 return sbridge_dev->pdev[i];
483 }
484 }
485
486 return NULL;
487}
488
489/**
c36e3e77 490 * check_if_ecc_is_active() - Checks if ECC is active
eebf11a0 491 * bus: Device bus
eebf11a0 492 */
c36e3e77 493static int check_if_ecc_is_active(const u8 bus)
eebf11a0
MCC		 494{
495 struct pci_dev *pdev = NULL;
eebf11a0
MCC		 496 u32 mcmtr;
497
eebf11a0
MCC		 498 pdev = get_pdev_slot_func(bus, 15, 0);
499 if (!pdev) {
500 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
501 "%2x.%02d.%d!!!\n",
502 bus, 15, 0);
503 return -ENODEV;
504 }
505
506 pci_read_config_dword(pdev, MCMTR, &mcmtr);
507 if (!IS_ECC_ENABLED(mcmtr)) {
508 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
509 return -ENODEV;
510 }
eebf11a0
MCC		 511 return 0;
512}
513
084a4fcc 514static int get_dimm_config(struct mem_ctl_info *mci)
eebf11a0
MCC		 515{
516 struct sbridge_pvt *pvt = mci->pvt_info;
c36e3e77 517 struct dimm_info *dimm;
deb09dda
MCC		 518 unsigned i, j, banks, ranks, rows, cols, npages;
519 u64 size;
eebf11a0
MCC		 520 u32 reg;
521 enum edac_type mode;
c6e13b52 522 enum mem_type mtype;
eebf11a0
MCC		 523
524 pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg);
525 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
526
527 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, &reg);
528 pvt->sbridge_dev->node_id = NODE_ID(reg);
956b9ba1
JP		 529 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
530 pvt->sbridge_dev->mc,
531 pvt->sbridge_dev->node_id,
532 pvt->sbridge_dev->source_id);
eebf11a0
MCC		 533
534 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
535 if (IS_MIRROR_ENABLED(reg)) {
956b9ba1 536 edac_dbg(0, "Memory mirror is enabled\n");
eebf11a0
MCC		 537 pvt->is_mirrored = true;
538 } else {
956b9ba1 539 edac_dbg(0, "Memory mirror is disabled\n");
eebf11a0
MCC		 540 pvt->is_mirrored = false;
541 }
542
543 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
544 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
956b9ba1 545 edac_dbg(0, "Lockstep is enabled\n");
eebf11a0
MCC		 546 mode = EDAC_S8ECD8ED;
547 pvt->is_lockstep = true;
548 } else {
956b9ba1 549 edac_dbg(0, "Lockstep is disabled\n");
eebf11a0
MCC		 550 mode = EDAC_S4ECD4ED;
551 pvt->is_lockstep = false;
552 }
553 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
956b9ba1 554 edac_dbg(0, "address map is on closed page mode\n");
eebf11a0
MCC		 555 pvt->is_close_pg = true;
556 } else {
956b9ba1 557 edac_dbg(0, "address map is on open page mode\n");
eebf11a0
MCC		 558 pvt->is_close_pg = false;
559 }
560
de4772c6
TL		 561 if (pvt->pci_ddrio) {
562 pci_read_config_dword(pvt->pci_ddrio, RANK_CFG_A, &reg);
563 if (IS_RDIMM_ENABLED(reg)) {
564 /* FIXME: Can also be LRDIMM */
565 edac_dbg(0, "Memory is registered\n");
566 mtype = MEM_RDDR3;
567 } else {
568 edac_dbg(0, "Memory is unregistered\n");
569 mtype = MEM_DDR3;
570 }
eebf11a0 571 } else {
de4772c6
TL		 572 edac_dbg(0, "Cannot determine memory type\n");
573 mtype = MEM_UNKNOWN;
eebf11a0
MCC		 574 }
575
576 /* On all supported DDR3 DIMM types, there are 8 banks available */
577 banks = 8;
578
579 for (i = 0; i < NUM_CHANNELS; i++) {
580 u32 mtr;
581
582 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
c36e3e77
MCC		 583 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
584 i, j, 0);
eebf11a0
MCC		 585 pci_read_config_dword(pvt->pci_tad[i],
586 mtr_regs[j], &mtr);
956b9ba1 587 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
eebf11a0
MCC		 588 if (IS_DIMM_PRESENT(mtr)) {
589 pvt->channel[i].dimms++;
590
591 ranks = numrank(mtr);
592 rows = numrow(mtr);
593 cols = numcol(mtr);
594
595 /* DDR3 has 8 I/O banks */
deb09dda 596 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
eebf11a0
MCC		 597 npages = MiB_TO_PAGES(size);
598
deb09dda 599 edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
956b9ba1
JP		 600 pvt->sbridge_dev->mc, i, j,
601 size, npages,
602 banks, ranks, rows, cols);
eebf11a0 603
a895bf8b 604 dimm->nr_pages = npages;
084a4fcc
MCC		 605 dimm->grain = 32;
606 dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
607 dimm->mtype = mtype;
608 dimm->edac_mode = mode;
609 snprintf(dimm->label, sizeof(dimm->label),
eebf11a0
MCC		 610 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
611 pvt->sbridge_dev->source_id, i, j);
eebf11a0
MCC		 612 }
613 }
614 }
615
616 return 0;
617}
618
619static void get_memory_layout(const struct mem_ctl_info *mci)
620{
621 struct sbridge_pvt *pvt = mci->pvt_info;
622 int i, j, k, n_sads, n_tads, sad_interl;
623 u32 reg;
624 u64 limit, prv = 0;
625 u64 tmp_mb;
5b889e37 626 u32 mb, kb;
eebf11a0
MCC		 627 u32 rir_way;
628
629 /*
630 * Step 1) Get TOLM/TOHM ranges
631 */
632
633 /* Address range is 32:28 */
634 pci_read_config_dword(pvt->pci_sad1, TOLM,
635 &reg);
636 pvt->tolm = GET_TOLM(reg);
637 tmp_mb = (1 + pvt->tolm) >> 20;
638
5b889e37 639 mb = div_u64_rem(tmp_mb, 1000, &kb);
956b9ba1 640 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tolm);
eebf11a0
MCC		 641
642 /* Address range is already 45:25 */
643 pci_read_config_dword(pvt->pci_sad1, TOHM,
644 &reg);
645 pvt->tohm = GET_TOHM(reg);
646 tmp_mb = (1 + pvt->tohm) >> 20;
647
5b889e37 648 mb = div_u64_rem(tmp_mb, 1000, &kb);
da14d93d 649 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tohm);
eebf11a0
MCC		 650
651 /*
652 * Step 2) Get SAD range and SAD Interleave list
653 * TAD registers contain the interleave wayness. However, it
654 * seems simpler to just discover it indirectly, with the
655 * algorithm bellow.
656 */
657 prv = 0;
658 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
659 /* SAD_LIMIT Address range is 45:26 */
660 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
661 &reg);
662 limit = SAD_LIMIT(reg);
663
664 if (!DRAM_RULE_ENABLE(reg))
665 continue;
666
667 if (limit <= prv)
668 break;
669
670 tmp_mb = (limit + 1) >> 20;
5b889e37 671 mb = div_u64_rem(tmp_mb, 1000, &kb);
956b9ba1
JP		 672 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
673 n_sads,
674 get_dram_attr(reg),
675 mb, kb,
676 ((u64)tmp_mb) << 20L,
677 INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
678 reg);
eebf11a0
MCC		 679 prv = limit;
680
681 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
682 &reg);
683 sad_interl = sad_pkg(reg, 0);
684 for (j = 0; j < 8; j++) {
685 if (j > 0 && sad_interl == sad_pkg(reg, j))
686 break;
687
956b9ba1
JP		 688 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
689 n_sads, j, sad_pkg(reg, j));
eebf11a0
MCC		 690 }
691 }
692
693 /*
694 * Step 3) Get TAD range
695 */
696 prv = 0;
697 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
698 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
699 &reg);
700 limit = TAD_LIMIT(reg);
701 if (limit <= prv)
702 break;
703 tmp_mb = (limit + 1) >> 20;
704
5b889e37 705 mb = div_u64_rem(tmp_mb, 1000, &kb);
956b9ba1
JP		 706 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
707 n_tads, mb, kb,
708 ((u64)tmp_mb) << 20L,
709 (u32)TAD_SOCK(reg),
710 (u32)TAD_CH(reg),
711 (u32)TAD_TGT0(reg),
712 (u32)TAD_TGT1(reg),
713 (u32)TAD_TGT2(reg),
714 (u32)TAD_TGT3(reg),
715 reg);
7fae0db4 716 prv = limit;
eebf11a0
MCC		 717 }
718
719 /*
720 * Step 4) Get TAD offsets, per each channel
721 */
722 for (i = 0; i < NUM_CHANNELS; i++) {
723 if (!pvt->channel[i].dimms)
724 continue;
725 for (j = 0; j < n_tads; j++) {
726 pci_read_config_dword(pvt->pci_tad[i],
727 tad_ch_nilv_offset[j],
728 &reg);
729 tmp_mb = TAD_OFFSET(reg) >> 20;
5b889e37 730 mb = div_u64_rem(tmp_mb, 1000, &kb);
956b9ba1
JP		 731 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
732 i, j,
733 mb, kb,
734 ((u64)tmp_mb) << 20L,
735 reg);
eebf11a0
MCC		 736 }
737 }
738
739 /*
740 * Step 6) Get RIR Wayness/Limit, per each channel
741 */
742 for (i = 0; i < NUM_CHANNELS; i++) {
743 if (!pvt->channel[i].dimms)
744 continue;
745 for (j = 0; j < MAX_RIR_RANGES; j++) {
746 pci_read_config_dword(pvt->pci_tad[i],
747 rir_way_limit[j],
748 &reg);
749
750 if (!IS_RIR_VALID(reg))
751 continue;
752
753 tmp_mb = RIR_LIMIT(reg) >> 20;
754 rir_way = 1 << RIR_WAY(reg);
5b889e37 755 mb = div_u64_rem(tmp_mb, 1000, &kb);
956b9ba1
JP		 756 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
757 i, j,
758 mb, kb,
759 ((u64)tmp_mb) << 20L,
760 rir_way,
761 reg);
eebf11a0
MCC		 762
763 for (k = 0; k < rir_way; k++) {
764 pci_read_config_dword(pvt->pci_tad[i],
765 rir_offset[j][k],
766 &reg);
767 tmp_mb = RIR_OFFSET(reg) << 6;
768
5b889e37 769 mb = div_u64_rem(tmp_mb, 1000, &kb);
956b9ba1
JP		 770 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
771 i, j, k,
772 mb, kb,
773 ((u64)tmp_mb) << 20L,
774 (u32)RIR_RNK_TGT(reg),
775 reg);
eebf11a0
MCC		 776 }
777 }
778 }
779}
780
781struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
782{
783 struct sbridge_dev *sbridge_dev;
784
785 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
786 if (sbridge_dev->node_id == node_id)
787 return sbridge_dev->mci;
788 }
789 return NULL;
790}
791
792static int get_memory_error_data(struct mem_ctl_info *mci,
793 u64 addr,
794 u8 *socket,
795 long *channel_mask,
796 u8 *rank,
e17a2f42 797 char **area_type, char *msg)
eebf11a0
MCC		 798{
799 struct mem_ctl_info *new_mci;
800 struct sbridge_pvt *pvt = mci->pvt_info;
eebf11a0
MCC		 801 int n_rir, n_sads, n_tads, sad_way, sck_xch;
802 int sad_interl, idx, base_ch;
803 int interleave_mode;
804 unsigned sad_interleave[MAX_INTERLEAVE];
805 u32 reg;
806 u8 ch_way,sck_way;
807 u32 tad_offset;
808 u32 rir_way;
5b889e37 809 u32 mb, kb;
eebf11a0
MCC		 810 u64 ch_addr, offset, limit, prv = 0;
811
812
813 /*
814 * Step 0) Check if the address is at special memory ranges
815 * The check bellow is probably enough to fill all cases where
816 * the error is not inside a memory, except for the legacy
817 * range (e. g. VGA addresses). It is unlikely, however, that the
818 * memory controller would generate an error on that range.
819 */
5b889e37 820 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
eebf11a0 821 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
eebf11a0
MCC		 822 return -EINVAL;
823 }
824 if (addr >= (u64)pvt->tohm) {
825 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
eebf11a0
MCC		 826 return -EINVAL;
827 }
828
829 /*
830 * Step 1) Get socket
831 */
832 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
833 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
834 &reg);
835
836 if (!DRAM_RULE_ENABLE(reg))
837 continue;
838
839 limit = SAD_LIMIT(reg);
840 if (limit <= prv) {
841 sprintf(msg, "Can't discover the memory socket");
eebf11a0
MCC		 842 return -EINVAL;
843 }
844 if (addr <= limit)
845 break;
846 prv = limit;
847 }
848 if (n_sads == MAX_SAD) {
849 sprintf(msg, "Can't discover the memory socket");
eebf11a0
MCC		 850 return -EINVAL;
851 }
e17a2f42 852 *area_type = get_dram_attr(reg);
eebf11a0
MCC		 853 interleave_mode = INTERLEAVE_MODE(reg);
854
855 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
856 &reg);
857 sad_interl = sad_pkg(reg, 0);
858 for (sad_way = 0; sad_way < 8; sad_way++) {
859 if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way))
860 break;
861 sad_interleave[sad_way] = sad_pkg(reg, sad_way);
956b9ba1
JP		 862 edac_dbg(0, "SAD interleave #%d: %d\n",
863 sad_way, sad_interleave[sad_way]);
eebf11a0 864 }
956b9ba1
JP		 865 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
866 pvt->sbridge_dev->mc,
867 n_sads,
868 addr,
869 limit,
870 sad_way + 7,
871 interleave_mode ? "" : "XOR[18:16]");
eebf11a0
MCC		 872 if (interleave_mode)
873 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
874 else
875 idx = (addr >> 6) & 7;
876 switch (sad_way) {
877 case 1:
878 idx = 0;
879 break;
880 case 2:
881 idx = idx & 1;
882 break;
883 case 4:
884 idx = idx & 3;
885 break;
886 case 8:
887 break;
888 default:
889 sprintf(msg, "Can't discover socket interleave");
eebf11a0
MCC		 890 return -EINVAL;
891 }
892 *socket = sad_interleave[idx];
956b9ba1
JP		 893 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
894 idx, sad_way, *socket);
eebf11a0
MCC		 895
896 /*
897 * Move to the proper node structure, in order to access the
898 * right PCI registers
899 */
900 new_mci = get_mci_for_node_id(*socket);
901 if (!new_mci) {
902 sprintf(msg, "Struct for socket #%u wasn't initialized",
903 *socket);
eebf11a0
MCC		 904 return -EINVAL;
905 }
906 mci = new_mci;
907 pvt = mci->pvt_info;
908
909 /*
910 * Step 2) Get memory channel
911 */
912 prv = 0;
913 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
914 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
915 &reg);
916 limit = TAD_LIMIT(reg);
917 if (limit <= prv) {
918 sprintf(msg, "Can't discover the memory channel");
eebf11a0
MCC		 919 return -EINVAL;
920 }
921 if (addr <= limit)
922 break;
923 prv = limit;
924 }
925 ch_way = TAD_CH(reg) + 1;
926 sck_way = TAD_SOCK(reg) + 1;
927 /*
928 * FIXME: Is it right to always use channel 0 for offsets?
929 */
930 pci_read_config_dword(pvt->pci_tad[0],
931 tad_ch_nilv_offset[n_tads],
932 &tad_offset);
933
934 if (ch_way == 3)
935 idx = addr >> 6;
936 else
937 idx = addr >> (6 + sck_way);
938 idx = idx % ch_way;
939
940 /*
941 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
942 */
943 switch (idx) {
944 case 0:
945 base_ch = TAD_TGT0(reg);
946 break;
947 case 1:
948 base_ch = TAD_TGT1(reg);
949 break;
950 case 2:
951 base_ch = TAD_TGT2(reg);
952 break;
953 case 3:
954 base_ch = TAD_TGT3(reg);
955 break;
956 default:
957 sprintf(msg, "Can't discover the TAD target");
eebf11a0
MCC		 958 return -EINVAL;
959 }
960 *channel_mask = 1 << base_ch;
961
962 if (pvt->is_mirrored) {
963 *channel_mask |= 1 << ((base_ch + 2) % 4);
964 switch(ch_way) {
965 case 2:
966 case 4:
967 sck_xch = 1 << sck_way * (ch_way >> 1);
968 break;
969 default:
970 sprintf(msg, "Invalid mirror set. Can't decode addr");
eebf11a0
MCC		 971 return -EINVAL;
972 }
973 } else
974 sck_xch = (1 << sck_way) * ch_way;
975
976 if (pvt->is_lockstep)
977 *channel_mask |= 1 << ((base_ch + 1) % 4);
978
979 offset = TAD_OFFSET(tad_offset);
980
956b9ba1
JP		 981 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
982 n_tads,
983 addr,
984 limit,
985 (u32)TAD_SOCK(reg),
986 ch_way,
987 offset,
988 idx,
989 base_ch,
990 *channel_mask);
eebf11a0
MCC		 991
992 /* Calculate channel address */
993 /* Remove the TAD offset */
994
995 if (offset > addr) {
996 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
997 offset, addr);
eebf11a0
MCC		 998 return -EINVAL;
999 }
1000 addr -= offset;
1001 /* Store the low bits [0:6] of the addr */
1002 ch_addr = addr & 0x7f;
1003 /* Remove socket wayness and remove 6 bits */
1004 addr >>= 6;
5b889e37 1005 addr = div_u64(addr, sck_xch);
eebf11a0
MCC		 1006#if 0
1007 /* Divide by channel way */
1008 addr = addr / ch_way;
1009#endif
1010 /* Recover the last 6 bits */
1011 ch_addr |= addr << 6;
1012
1013 /*
1014 * Step 3) Decode rank
1015 */
1016 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1017 pci_read_config_dword(pvt->pci_tad[base_ch],
1018 rir_way_limit[n_rir],
1019 &reg);
1020
1021 if (!IS_RIR_VALID(reg))
1022 continue;
1023
1024 limit = RIR_LIMIT(reg);
5b889e37 1025 mb = div_u64_rem(limit >> 20, 1000, &kb);
956b9ba1
JP		 1026 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1027 n_rir,
1028 mb, kb,
1029 limit,
1030 1 << RIR_WAY(reg));
eebf11a0
MCC		 1031 if (ch_addr <= limit)
1032 break;
1033 }
1034 if (n_rir == MAX_RIR_RANGES) {
1035 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1036 ch_addr);
eebf11a0
MCC		 1037 return -EINVAL;
1038 }
1039 rir_way = RIR_WAY(reg);
1040 if (pvt->is_close_pg)
1041 idx = (ch_addr >> 6);
1042 else
1043 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1044 idx %= 1 << rir_way;
1045
1046 pci_read_config_dword(pvt->pci_tad[base_ch],
1047 rir_offset[n_rir][idx],
1048 &reg);
1049 *rank = RIR_RNK_TGT(reg);
1050
956b9ba1
JP		 1051 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1052 n_rir,
1053 ch_addr,
1054 limit,
1055 rir_way,
1056 idx);
eebf11a0
MCC		 1057
1058 return 0;
1059}
1060
1061/****************************************************************************
1062 Device initialization routines: put/get, init/exit
1063 ****************************************************************************/
1064
1065/*
1066 * sbridge_put_all_devices 'put' all the devices that we have
1067 * reserved via 'get'
1068 */
1069static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1070{
1071 int i;
1072
956b9ba1 1073 edac_dbg(0, "\n");
eebf11a0
MCC		 1074 for (i = 0; i < sbridge_dev->n_devs; i++) {
1075 struct pci_dev *pdev = sbridge_dev->pdev[i];
1076 if (!pdev)
1077 continue;
956b9ba1
JP		 1078 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1079 pdev->bus->number,
1080 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
eebf11a0
MCC		 1081 pci_dev_put(pdev);
1082 }
1083}
1084
1085static void sbridge_put_all_devices(void)
1086{
1087 struct sbridge_dev *sbridge_dev, *tmp;
1088
1089 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1090 sbridge_put_devices(sbridge_dev);
1091 free_sbridge_dev(sbridge_dev);
1092 }
1093}
1094
1095/*
1096 * sbridge_get_all_devices Find and perform 'get' operation on the MCH's
1097 * device/functions we want to reference for this driver
1098 *
1099 * Need to 'get' device 16 func 1 and func 2
1100 */
1101static int sbridge_get_onedevice(struct pci_dev **prev,
1102 u8 *num_mc,
1103 const struct pci_id_table *table,
1104 const unsigned devno)
1105{
1106 struct sbridge_dev *sbridge_dev;
1107 const struct pci_id_descr *dev_descr = &table->descr[devno];
1108
1109 struct pci_dev *pdev = NULL;
1110 u8 bus = 0;
1111
1112 sbridge_printk(KERN_INFO,
1113 "Seeking for: dev %02x.%d PCI ID %04x:%04x\n",
1114 dev_descr->dev, dev_descr->func,
1115 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1116
1117 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1118 dev_descr->dev_id, *prev);
1119
1120 if (!pdev) {
1121 if (*prev) {
1122 *prev = pdev;
1123 return 0;
1124 }
1125
1126 if (dev_descr->optional)
1127 return 0;
1128
1129 if (devno == 0)
1130 return -ENODEV;
1131
1132 sbridge_printk(KERN_INFO,
1133 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1134 dev_descr->dev, dev_descr->func,
1135 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1136
1137 /* End of list, leave */
1138 return -ENODEV;
1139 }
1140 bus = pdev->bus->number;
1141
1142 sbridge_dev = get_sbridge_dev(bus);
1143 if (!sbridge_dev) {
1144 sbridge_dev = alloc_sbridge_dev(bus, table);
1145 if (!sbridge_dev) {
1146 pci_dev_put(pdev);
1147 return -ENOMEM;
1148 }
1149 (*num_mc)++;
1150 }
1151
1152 if (sbridge_dev->pdev[devno]) {
1153 sbridge_printk(KERN_ERR,
1154 "Duplicated device for "
1155 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1156 bus, dev_descr->dev, dev_descr->func,
1157 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1158 pci_dev_put(pdev);
1159 return -ENODEV;
1160 }
1161
1162 sbridge_dev->pdev[devno] = pdev;
1163
1164 /* Sanity check */
1165 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1166 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1167 sbridge_printk(KERN_ERR,
1168 "Device PCI ID %04x:%04x "
1169 "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n",
1170 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1171 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1172 bus, dev_descr->dev, dev_descr->func);
1173 return -ENODEV;
1174 }
1175
1176 /* Be sure that the device is enabled */
1177 if (unlikely(pci_enable_device(pdev) < 0)) {
1178 sbridge_printk(KERN_ERR,
1179 "Couldn't enable "
1180 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1181 bus, dev_descr->dev, dev_descr->func,
1182 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1183 return -ENODEV;
1184 }
1185
956b9ba1
JP		 1186 edac_dbg(0, "Detected dev %02x:%d.%d PCI ID %04x:%04x\n",
1187 bus, dev_descr->dev, dev_descr->func,
1188 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
eebf11a0
MCC		 1189
1190 /*
1191 * As stated on drivers/pci/search.c, the reference count for
1192 * @from is always decremented if it is not %NULL. So, as we need
1193 * to get all devices up to null, we need to do a get for the device
1194 */
1195 pci_dev_get(pdev);
1196
1197 *prev = pdev;
1198
1199 return 0;
1200}
1201
1202static int sbridge_get_all_devices(u8 *num_mc)
1203{
1204 int i, rc;
1205 struct pci_dev *pdev = NULL;
1206 const struct pci_id_table *table = pci_dev_descr_sbridge_table;
1207
1208 while (table && table->descr) {
1209 for (i = 0; i < table->n_devs; i++) {
1210 pdev = NULL;
1211 do {
1212 rc = sbridge_get_onedevice(&pdev, num_mc,
1213 table, i);
1214 if (rc < 0) {
1215 if (i == 0) {
1216 i = table->n_devs;
1217 break;
1218 }
1219 sbridge_put_all_devices();
1220 return -ENODEV;
1221 }
1222 } while (pdev);
1223 }
1224 table++;
1225 }
1226
1227 return 0;
1228}
1229
1230static int mci_bind_devs(struct mem_ctl_info *mci,
1231 struct sbridge_dev *sbridge_dev)
1232{
1233 struct sbridge_pvt *pvt = mci->pvt_info;
1234 struct pci_dev *pdev;
1235 int i, func, slot;
1236
1237 for (i = 0; i < sbridge_dev->n_devs; i++) {
1238 pdev = sbridge_dev->pdev[i];
1239 if (!pdev)
1240 continue;
1241 slot = PCI_SLOT(pdev->devfn);
1242 func = PCI_FUNC(pdev->devfn);
1243 switch (slot) {
1244 case 12:
1245 switch (func) {
1246 case 6:
1247 pvt->pci_sad0 = pdev;
1248 break;
1249 case 7:
1250 pvt->pci_sad1 = pdev;
1251 break;
1252 default:
1253 goto error;
1254 }
1255 break;
1256 case 13:
1257 switch (func) {
1258 case 6:
1259 pvt->pci_br = pdev;
1260 break;
1261 default:
1262 goto error;
1263 }
1264 break;
1265 case 14:
1266 switch (func) {
1267 case 0:
1268 pvt->pci_ha0 = pdev;
1269 break;
1270 default:
1271 goto error;
1272 }
1273 break;
1274 case 15:
1275 switch (func) {
1276 case 0:
1277 pvt->pci_ta = pdev;
1278 break;
1279 case 1:
1280 pvt->pci_ras = pdev;
1281 break;
1282 case 2:
1283 case 3:
1284 case 4:
1285 case 5:
1286 pvt->pci_tad[func - 2] = pdev;
1287 break;
1288 default:
1289 goto error;
1290 }
1291 break;
1292 case 17:
1293 switch (func) {
1294 case 0:
1295 pvt->pci_ddrio = pdev;
1296 break;
1297 default:
1298 goto error;
1299 }
1300 break;
1301 default:
1302 goto error;
1303 }
1304
956b9ba1
JP		 1305 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1306 sbridge_dev->bus,
1307 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1308 pdev);
eebf11a0
MCC		 1309 }
1310
1311 /* Check if everything were registered */
1312 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
de4772c6 1313 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
eebf11a0
MCC		 1314 goto enodev;
1315
1316 for (i = 0; i < NUM_CHANNELS; i++) {
1317 if (!pvt->pci_tad[i])
1318 goto enodev;
1319 }
1320 return 0;
1321
1322enodev:
1323 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1324 return -ENODEV;
1325
1326error:
1327 sbridge_printk(KERN_ERR, "Device %d, function %d "
1328 "is out of the expected range\n",
1329 slot, func);
1330 return -EINVAL;
1331}
1332
1333/****************************************************************************
1334 Error check routines
1335 ****************************************************************************/
1336
1337/*
1338 * While Sandy Bridge has error count registers, SMI BIOS read values from
1339 * and resets the counters. So, they are not reliable for the OS to read
1340 * from them. So, we have no option but to just trust on whatever MCE is
1341 * telling us about the errors.
1342 */
1343static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1344 const struct mce *m)
1345{
1346 struct mem_ctl_info *new_mci;
1347 struct sbridge_pvt *pvt = mci->pvt_info;
c36e3e77 1348 enum hw_event_mc_err_type tp_event;
e17a2f42 1349 char *type, *optype, msg[256];
eebf11a0
MCC		 1350 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1351 bool overflow = GET_BITFIELD(m->status, 62, 62);
1352 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1353 bool recoverable = GET_BITFIELD(m->status, 56, 56);
1354 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1355 u32 mscod = GET_BITFIELD(m->status, 16, 31);
1356 u32 errcode = GET_BITFIELD(m->status, 0, 15);
1357 u32 channel = GET_BITFIELD(m->status, 0, 3);
1358 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1359 long channel_mask, first_channel;
1360 u8 rank, socket;
c36e3e77 1361 int rc, dimm;
e17a2f42 1362 char *area_type = NULL;
eebf11a0 1363
c36e3e77
MCC		 1364 if (uncorrected_error) {
1365 if (ripv) {
1366 type = "FATAL";
1367 tp_event = HW_EVENT_ERR_FATAL;
1368 } else {
1369 type = "NON_FATAL";
1370 tp_event = HW_EVENT_ERR_UNCORRECTED;
1371 }
1372 } else {
1373 type = "CORRECTED";
1374 tp_event = HW_EVENT_ERR_CORRECTED;
1375 }
eebf11a0
MCC		 1376
1377 /*
15ed103a 1378 * According with Table 15-9 of the Intel Architecture spec vol 3A,
eebf11a0
MCC		 1379 * memory errors should fit in this mask:
1380 * 000f 0000 1mmm cccc (binary)
1381 * where:
1382 * f = Correction Report Filtering Bit. If 1, subsequent errors
1383 * won't be shown
1384 * mmm = error type
1385 * cccc = channel
1386 * If the mask doesn't match, report an error to the parsing logic
1387 */
1388 if (! ((errcode & 0xef80) == 0x80)) {
1389 optype = "Can't parse: it is not a mem";
1390 } else {
1391 switch (optypenum) {
1392 case 0:
c36e3e77 1393 optype = "generic undef request error";
eebf11a0
MCC		 1394 break;
1395 case 1:
c36e3e77 1396 optype = "memory read error";
eebf11a0
MCC		 1397 break;
1398 case 2:
c36e3e77 1399 optype = "memory write error";
eebf11a0
MCC		 1400 break;
1401 case 3:
c36e3e77 1402 optype = "addr/cmd error";
eebf11a0
MCC		 1403 break;
1404 case 4:
c36e3e77 1405 optype = "memory scrubbing error";
eebf11a0
MCC		 1406 break;
1407 default:
1408 optype = "reserved";
1409 break;
1410 }
1411 }
1412
1413 rc = get_memory_error_data(mci, m->addr, &socket,
e17a2f42 1414 &channel_mask, &rank, &area_type, msg);
eebf11a0 1415 if (rc < 0)
c36e3e77 1416 goto err_parsing;
eebf11a0
MCC		 1417 new_mci = get_mci_for_node_id(socket);
1418 if (!new_mci) {
c36e3e77
MCC		 1419 strcpy(msg, "Error: socket got corrupted!");
1420 goto err_parsing;
eebf11a0
MCC		 1421 }
1422 mci = new_mci;
1423 pvt = mci->pvt_info;
1424
1425 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
1426
1427 if (rank < 4)
1428 dimm = 0;
1429 else if (rank < 8)
1430 dimm = 1;
1431 else
1432 dimm = 2;
1433
eebf11a0
MCC		 1434
1435 /*
e17a2f42
MCC		 1436 * FIXME: On some memory configurations (mirror, lockstep), the
1437 * Memory Controller can't point the error to a single DIMM. The
1438 * EDAC core should be handling the channel mask, in order to point
1439 * to the group of dimm's where the error may be happening.
eebf11a0 1440 */
c36e3e77 1441 snprintf(msg, sizeof(msg),
c1053839 1442 "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d",
e17a2f42
MCC		 1443 overflow ? " OVERFLOW" : "",
1444 (uncorrected_error && recoverable) ? " recoverable" : "",
1445 area_type,
1446 mscod, errcode,
1447 socket,
1448 channel_mask,
1449 rank);
eebf11a0 1450
956b9ba1 1451 edac_dbg(0, "%s\n", msg);
eebf11a0 1452
c36e3e77
MCC		 1453 /* FIXME: need support for channel mask */
1454
ebe7e30a
SJ		 1455 if (channel == CHANNEL_UNSPECIFIED)
1456 channel = -1;
1457
eebf11a0 1458 /* Call the helper to output message */
c1053839 1459 edac_mc_handle_error(tp_event, mci, core_err_cnt,
c36e3e77
MCC		 1460 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
1461 channel, dimm, -1,
03f7eae8 1462 optype, msg);
c36e3e77
MCC		 1463 return;
1464err_parsing:
c1053839 1465 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
c36e3e77 1466 -1, -1, -1,
03f7eae8 1467 msg, "");
eebf11a0 1468
eebf11a0
MCC		 1469}
1470
1471/*
1472 * sbridge_check_error Retrieve and process errors reported by the
1473 * hardware. Called by the Core module.
1474 */
1475static void sbridge_check_error(struct mem_ctl_info *mci)
1476{
1477 struct sbridge_pvt *pvt = mci->pvt_info;
1478 int i;
1479 unsigned count = 0;
1480 struct mce *m;
1481
1482 /*
1483 * MCE first step: Copy all mce errors into a temporary buffer
1484 * We use a double buffering here, to reduce the risk of
1485 * loosing an error.
1486 */
1487 smp_rmb();
1488 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1489 % MCE_LOG_LEN;
1490 if (!count)
1491 return;
1492
1493 m = pvt->mce_outentry;
1494 if (pvt->mce_in + count > MCE_LOG_LEN) {
1495 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1496
1497 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1498 smp_wmb();
1499 pvt->mce_in = 0;
1500 count -= l;
1501 m += l;
1502 }
1503 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1504 smp_wmb();
1505 pvt->mce_in += count;
1506
1507 smp_rmb();
1508 if (pvt->mce_overrun) {
1509 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
1510 pvt->mce_overrun);
1511 smp_wmb();
1512 pvt->mce_overrun = 0;
1513 }
1514
1515 /*
1516 * MCE second step: parse errors and display
1517 */
1518 for (i = 0; i < count; i++)
1519 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
1520}
1521
1522/*
1523 * sbridge_mce_check_error Replicates mcelog routine to get errors
1524 * This routine simply queues mcelog errors, and
1525 * return. The error itself should be handled later
1526 * by sbridge_check_error.
1527 * WARNING: As this routine should be called at NMI time, extra care should
1528 * be taken to avoid deadlocks, and to be as fast as possible.
1529 */
3d78c9af
MCC		 1530static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
1531 void *data)
eebf11a0 1532{
3d78c9af
MCC		 1533 struct mce *mce = (struct mce *)data;
1534 struct mem_ctl_info *mci;
1535 struct sbridge_pvt *pvt;
1536
1537 mci = get_mci_for_node_id(mce->socketid);
1538 if (!mci)
1539 return NOTIFY_BAD;
1540 pvt = mci->pvt_info;
eebf11a0
MCC		 1541
1542 /*
1543 * Just let mcelog handle it if the error is
1544 * outside the memory controller. A memory error
1545 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
1546 * bit 12 has an special meaning.
1547 */
1548 if ((mce->status & 0xefff) >> 7 != 1)
3d78c9af 1549 return NOTIFY_DONE;
eebf11a0
MCC		 1550
1551 printk("sbridge: HANDLING MCE MEMORY ERROR\n");
1552
1553 printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
1554 mce->extcpu, mce->mcgstatus, mce->bank, mce->status);
1555 printk("TSC %llx ", mce->tsc);
1556 printk("ADDR %llx ", mce->addr);
1557 printk("MISC %llx ", mce->misc);
1558
1559 printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
1560 mce->cpuvendor, mce->cpuid, mce->time,
1561 mce->socketid, mce->apicid);
1562
eebf11a0
MCC		 1563 /* Only handle if it is the right mc controller */
1564 if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc)
3d78c9af 1565 return NOTIFY_DONE;
eebf11a0
MCC		 1566
1567 smp_rmb();
1568 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1569 smp_wmb();
1570 pvt->mce_overrun++;
3d78c9af 1571 return NOTIFY_DONE;
eebf11a0
MCC		 1572 }
1573
1574 /* Copy memory error at the ringbuffer */
1575 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1576 smp_wmb();
1577 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1578
1579 /* Handle fatal errors immediately */
1580 if (mce->mcgstatus & 1)
1581 sbridge_check_error(mci);
1582
1583 /* Advice mcelog that the error were handled */
3d78c9af 1584 return NOTIFY_STOP;
eebf11a0
MCC		 1585}
1586
3d78c9af
MCC		 1587static struct notifier_block sbridge_mce_dec = {
1588 .notifier_call = sbridge_mce_check_error,
1589};
1590
eebf11a0
MCC		 1591/****************************************************************************
1592 EDAC register/unregister logic
1593 ****************************************************************************/
1594
1595static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
1596{
1597 struct mem_ctl_info *mci = sbridge_dev->mci;
1598 struct sbridge_pvt *pvt;
1599
1600 if (unlikely(!mci || !mci->pvt_info)) {
956b9ba1 1601 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
eebf11a0
MCC		 1602
1603 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
1604 return;
1605 }
1606
1607 pvt = mci->pvt_info;
1608
956b9ba1
JP		 1609 edac_dbg(0, "MC: mci = %p, dev = %p\n",
1610 mci, &sbridge_dev->pdev[0]->dev);
eebf11a0 1611
eebf11a0 1612 /* Remove MC sysfs nodes */
fd687502 1613 edac_mc_del_mc(mci->pdev);
eebf11a0 1614
956b9ba1 1615 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
eebf11a0
MCC		 1616 kfree(mci->ctl_name);
1617 edac_mc_free(mci);
1618 sbridge_dev->mci = NULL;
1619}
1620
1621static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
1622{
1623 struct mem_ctl_info *mci;
c36e3e77 1624 struct edac_mc_layer layers[2];
eebf11a0 1625 struct sbridge_pvt *pvt;
c36e3e77 1626 int rc;
eebf11a0
MCC		 1627
1628 /* Check the number of active and not disabled channels */
c36e3e77 1629 rc = check_if_ecc_is_active(sbridge_dev->bus);
eebf11a0
MCC		 1630 if (unlikely(rc < 0))
1631 return rc;
1632
1633 /* allocate a new MC control structure */
c36e3e77
MCC		 1634 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1635 layers[0].size = NUM_CHANNELS;
1636 layers[0].is_virt_csrow = false;
1637 layers[1].type = EDAC_MC_LAYER_SLOT;
1638 layers[1].size = MAX_DIMMS;
1639 layers[1].is_virt_csrow = true;
ca0907b9 1640 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
c36e3e77
MCC		 1641 sizeof(*pvt));
1642
eebf11a0
MCC		 1643 if (unlikely(!mci))
1644 return -ENOMEM;
1645
956b9ba1
JP		 1646 edac_dbg(0, "MC: mci = %p, dev = %p\n",
1647 mci, &sbridge_dev->pdev[0]->dev);
eebf11a0
MCC		 1648
1649 pvt = mci->pvt_info;
1650 memset(pvt, 0, sizeof(*pvt));
1651
1652 /* Associate sbridge_dev and mci for future usage */
1653 pvt->sbridge_dev = sbridge_dev;
1654 sbridge_dev->mci = mci;
1655
1656 mci->mtype_cap = MEM_FLAG_DDR3;
1657 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1658 mci->edac_cap = EDAC_FLAG_NONE;
1659 mci->mod_name = "sbridge_edac.c";
1660 mci->mod_ver = SBRIDGE_REVISION;
1661 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
1662 mci->dev_name = pci_name(sbridge_dev->pdev[0]);
1663 mci->ctl_page_to_phys = NULL;
1664
1665 /* Set the function pointer to an actual operation function */
1666 mci->edac_check = sbridge_check_error;
1667
1668 /* Store pci devices at mci for faster access */
1669 rc = mci_bind_devs(mci, sbridge_dev);
1670 if (unlikely(rc < 0))
1671 goto fail0;
1672
1673 /* Get dimm basic config and the memory layout */
1674 get_dimm_config(mci);
1675 get_memory_layout(mci);
1676
1677 /* record ptr to the generic device */
fd687502 1678 mci->pdev = &sbridge_dev->pdev[0]->dev;
eebf11a0
MCC		 1679
1680 /* add this new MC control structure to EDAC's list of MCs */
1681 if (unlikely(edac_mc_add_mc(mci))) {
956b9ba1 1682 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
eebf11a0
MCC		 1683 rc = -EINVAL;
1684 goto fail0;
1685 }
1686
eebf11a0 1687 return 0;
eebf11a0
MCC		 1688
1689fail0:
1690 kfree(mci->ctl_name);
1691 edac_mc_free(mci);
1692 sbridge_dev->mci = NULL;
1693 return rc;
1694}
1695
1696/*
1697 * sbridge_probe Probe for ONE instance of device to see if it is
1698 * present.
1699 * return:
1700 * 0 for FOUND a device
1701 * < 0 for error code
1702 */
1703
9b3c6e85 1704static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
eebf11a0
MCC		 1705{
1706 int rc;
1707 u8 mc, num_mc = 0;
1708 struct sbridge_dev *sbridge_dev;
1709
1710 /* get the pci devices we want to reserve for our use */
1711 mutex_lock(&sbridge_edac_lock);
1712
1713 /*
1714 * All memory controllers are allocated at the first pass.
1715 */
1716 if (unlikely(probed >= 1)) {
1717 mutex_unlock(&sbridge_edac_lock);
1718 return -ENODEV;
1719 }
1720 probed++;
1721
1722 rc = sbridge_get_all_devices(&num_mc);
1723 if (unlikely(rc < 0))
1724 goto fail0;
1725 mc = 0;
1726
1727 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
956b9ba1
JP		 1728 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
1729 mc, mc + 1, num_mc);
eebf11a0
MCC		 1730 sbridge_dev->mc = mc++;
1731 rc = sbridge_register_mci(sbridge_dev);
1732 if (unlikely(rc < 0))
1733 goto fail1;
1734 }
1735
1736 sbridge_printk(KERN_INFO, "Driver loaded.\n");
1737
1738 mutex_unlock(&sbridge_edac_lock);
1739 return 0;
1740
1741fail1:
1742 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1743 sbridge_unregister_mci(sbridge_dev);
1744
1745 sbridge_put_all_devices();
1746fail0:
1747 mutex_unlock(&sbridge_edac_lock);
1748 return rc;
1749}
1750
1751/*
1752 * sbridge_remove destructor for one instance of device
1753 *
1754 */
9b3c6e85 1755static void sbridge_remove(struct pci_dev *pdev)
eebf11a0
MCC		 1756{
1757 struct sbridge_dev *sbridge_dev;
1758
956b9ba1 1759 edac_dbg(0, "\n");
eebf11a0
MCC		 1760
1761 /*
1762 * we have a trouble here: pdev value for removal will be wrong, since
1763 * it will point to the X58 register used to detect that the machine
1764 * is a Nehalem or upper design. However, due to the way several PCI
1765 * devices are grouped together to provide MC functionality, we need
1766 * to use a different method for releasing the devices
1767 */
1768
1769 mutex_lock(&sbridge_edac_lock);
1770
1771 if (unlikely(!probed)) {
1772 mutex_unlock(&sbridge_edac_lock);
1773 return;
1774 }
1775
1776 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1777 sbridge_unregister_mci(sbridge_dev);
1778
1779 /* Release PCI resources */
1780 sbridge_put_all_devices();
1781
1782 probed--;
1783
1784 mutex_unlock(&sbridge_edac_lock);
1785}
1786
1787MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
1788
1789/*
1790 * sbridge_driver pci_driver structure for this module
1791 *
1792 */
1793static struct pci_driver sbridge_driver = {
1794 .name = "sbridge_edac",
1795 .probe = sbridge_probe,
9b3c6e85 1796 .remove = sbridge_remove,
eebf11a0
MCC		 1797 .id_table = sbridge_pci_tbl,
1798};
1799
1800/*
1801 * sbridge_init Module entry function
1802 * Try to initialize this module for its devices
1803 */
1804static int __init sbridge_init(void)
1805{
1806 int pci_rc;
1807
956b9ba1 1808 edac_dbg(2, "\n");
eebf11a0
MCC		 1809
1810 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1811 opstate_init();
1812
1813 pci_rc = pci_register_driver(&sbridge_driver);
1814
e35fca47
CG		 1815 if (pci_rc >= 0) {
1816 mce_register_decode_chain(&sbridge_mce_dec);
eebf11a0 1817 return 0;
e35fca47 1818 }
eebf11a0
MCC		 1819
1820 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
1821 pci_rc);
1822
1823 return pci_rc;
1824}
1825
1826/*
1827 * sbridge_exit() Module exit function
1828 * Unregister the driver
1829 */
1830static void __exit sbridge_exit(void)
1831{
956b9ba1 1832 edac_dbg(2, "\n");
eebf11a0 1833 pci_unregister_driver(&sbridge_driver);
e35fca47 1834 mce_unregister_decode_chain(&sbridge_mce_dec);
eebf11a0
MCC		 1835}
1836
1837module_init(sbridge_init);
1838module_exit(sbridge_exit);
1839
1840module_param(edac_op_state, int, 0444);
1841MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1842
1843MODULE_LICENSE("GPL");
1844MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1845MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1846MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - "
1847 SBRIDGE_REVISION);
kernel source for telekom puls (alcatel/mediatek)