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a9a753d5 DJ |
1 | /* |
2 | * Freescale MPC85xx Memory Controller kenel module | |
3 | * | |
4 | * Author: Dave Jiang <djiang@mvista.com> | |
5 | * | |
6 | * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | * | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/ctype.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/mod_devicetable.h> | |
19 | #include <linux/edac.h> | |
60be7551 | 20 | #include <linux/smp.h> |
a9a753d5 DJ |
21 | |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/of_device.h> | |
a9a753d5 DJ |
24 | #include "edac_module.h" |
25 | #include "edac_core.h" | |
26 | #include "mpc85xx_edac.h" | |
27 | ||
28 | static int edac_dev_idx; | |
29 | static int edac_pci_idx; | |
30 | static int edac_mc_idx; | |
31 | ||
32 | static u32 orig_ddr_err_disable; | |
33 | static u32 orig_ddr_err_sbe; | |
34 | ||
35 | /* | |
36 | * PCI Err defines | |
37 | */ | |
38 | #ifdef CONFIG_PCI | |
39 | static u32 orig_pci_err_cap_dr; | |
40 | static u32 orig_pci_err_en; | |
41 | #endif | |
42 | ||
43 | static u32 orig_l2_err_disable; | |
60be7551 | 44 | static u32 orig_hid1[2]; |
a9a753d5 | 45 | |
a9a753d5 DJ |
46 | /************************ MC SYSFS parts ***********************************/ |
47 | ||
48 | static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci, | |
49 | char *data) | |
50 | { | |
51 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
52 | return sprintf(data, "0x%08x", | |
53 | in_be32(pdata->mc_vbase + | |
54 | MPC85XX_MC_DATA_ERR_INJECT_HI)); | |
55 | } | |
56 | ||
57 | static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci, | |
58 | char *data) | |
59 | { | |
60 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
61 | return sprintf(data, "0x%08x", | |
62 | in_be32(pdata->mc_vbase + | |
63 | MPC85XX_MC_DATA_ERR_INJECT_LO)); | |
64 | } | |
65 | ||
66 | static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data) | |
67 | { | |
68 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
69 | return sprintf(data, "0x%08x", | |
70 | in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); | |
71 | } | |
72 | ||
73 | static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci, | |
74 | const char *data, size_t count) | |
75 | { | |
76 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
77 | if (isdigit(*data)) { | |
78 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, | |
79 | simple_strtoul(data, NULL, 0)); | |
80 | return count; | |
81 | } | |
82 | return 0; | |
83 | } | |
84 | ||
85 | static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci, | |
86 | const char *data, size_t count) | |
87 | { | |
88 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
89 | if (isdigit(*data)) { | |
90 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, | |
91 | simple_strtoul(data, NULL, 0)); | |
92 | return count; | |
93 | } | |
94 | return 0; | |
95 | } | |
96 | ||
97 | static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci, | |
98 | const char *data, size_t count) | |
99 | { | |
100 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
101 | if (isdigit(*data)) { | |
102 | out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, | |
103 | simple_strtoul(data, NULL, 0)); | |
104 | return count; | |
105 | } | |
106 | return 0; | |
107 | } | |
108 | ||
109 | static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = { | |
110 | { | |
111 | .attr = { | |
112 | .name = "inject_data_hi", | |
113 | .mode = (S_IRUGO | S_IWUSR) | |
114 | }, | |
115 | .show = mpc85xx_mc_inject_data_hi_show, | |
116 | .store = mpc85xx_mc_inject_data_hi_store}, | |
117 | { | |
118 | .attr = { | |
119 | .name = "inject_data_lo", | |
120 | .mode = (S_IRUGO | S_IWUSR) | |
121 | }, | |
122 | .show = mpc85xx_mc_inject_data_lo_show, | |
123 | .store = mpc85xx_mc_inject_data_lo_store}, | |
124 | { | |
125 | .attr = { | |
126 | .name = "inject_ctrl", | |
127 | .mode = (S_IRUGO | S_IWUSR) | |
128 | }, | |
129 | .show = mpc85xx_mc_inject_ctrl_show, | |
130 | .store = mpc85xx_mc_inject_ctrl_store}, | |
131 | ||
132 | /* End of list */ | |
133 | { | |
134 | .attr = {.name = NULL} | |
135 | } | |
136 | }; | |
137 | ||
138 | static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci) | |
139 | { | |
140 | mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes; | |
141 | } | |
142 | ||
143 | /**************************** PCI Err device ***************************/ | |
144 | #ifdef CONFIG_PCI | |
145 | ||
146 | static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) | |
147 | { | |
148 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; | |
149 | u32 err_detect; | |
150 | ||
151 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); | |
152 | ||
153 | /* master aborts can happen during PCI config cycles */ | |
154 | if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { | |
155 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); | |
156 | return; | |
157 | } | |
158 | ||
159 | printk(KERN_ERR "PCI error(s) detected\n"); | |
160 | printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); | |
161 | ||
162 | printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", | |
163 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); | |
164 | printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", | |
165 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); | |
166 | printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", | |
167 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); | |
168 | printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", | |
169 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); | |
170 | printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", | |
171 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); | |
172 | ||
173 | /* clear error bits */ | |
174 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); | |
175 | ||
176 | if (err_detect & PCI_EDE_PERR_MASK) | |
177 | edac_pci_handle_pe(pci, pci->ctl_name); | |
178 | ||
179 | if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) | |
180 | edac_pci_handle_npe(pci, pci->ctl_name); | |
181 | } | |
182 | ||
183 | static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) | |
184 | { | |
185 | struct edac_pci_ctl_info *pci = dev_id; | |
186 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; | |
187 | u32 err_detect; | |
188 | ||
189 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); | |
190 | ||
191 | if (!err_detect) | |
192 | return IRQ_NONE; | |
193 | ||
194 | mpc85xx_pci_check(pci); | |
195 | ||
196 | return IRQ_HANDLED; | |
197 | } | |
198 | ||
f87bd330 DJ |
199 | static int __devinit mpc85xx_pci_err_probe(struct of_device *op, |
200 | const struct of_device_id *match) | |
a9a753d5 DJ |
201 | { |
202 | struct edac_pci_ctl_info *pci; | |
203 | struct mpc85xx_pci_pdata *pdata; | |
f87bd330 | 204 | struct resource r; |
a9a753d5 DJ |
205 | int res = 0; |
206 | ||
f87bd330 | 207 | if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) |
a9a753d5 DJ |
208 | return -ENOMEM; |
209 | ||
210 | pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); | |
211 | if (!pci) | |
212 | return -ENOMEM; | |
213 | ||
214 | pdata = pci->pvt_info; | |
215 | pdata->name = "mpc85xx_pci_err"; | |
216 | pdata->irq = NO_IRQ; | |
f87bd330 DJ |
217 | dev_set_drvdata(&op->dev, pci); |
218 | pci->dev = &op->dev; | |
a9a753d5 DJ |
219 | pci->mod_name = EDAC_MOD_STR; |
220 | pci->ctl_name = pdata->name; | |
031d5518 | 221 | pci->dev_name = dev_name(&op->dev); |
a9a753d5 DJ |
222 | |
223 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
224 | pci->edac_check = mpc85xx_pci_check; | |
225 | ||
226 | pdata->edac_idx = edac_pci_idx++; | |
227 | ||
f87bd330 DJ |
228 | res = of_address_to_resource(op->node, 0, &r); |
229 | if (res) { | |
a9a753d5 DJ |
230 | printk(KERN_ERR "%s: Unable to get resource for " |
231 | "PCI err regs\n", __func__); | |
232 | goto err; | |
233 | } | |
234 | ||
f87bd330 DJ |
235 | /* we only need the error registers */ |
236 | r.start += 0xe00; | |
237 | ||
238 | if (!devm_request_mem_region(&op->dev, r.start, | |
239 | r.end - r.start + 1, pdata->name)) { | |
a9a753d5 DJ |
240 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
241 | __func__); | |
242 | res = -EBUSY; | |
243 | goto err; | |
244 | } | |
245 | ||
f87bd330 DJ |
246 | pdata->pci_vbase = devm_ioremap(&op->dev, r.start, |
247 | r.end - r.start + 1); | |
a9a753d5 DJ |
248 | if (!pdata->pci_vbase) { |
249 | printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); | |
250 | res = -ENOMEM; | |
251 | goto err; | |
252 | } | |
253 | ||
254 | orig_pci_err_cap_dr = | |
255 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); | |
256 | ||
257 | /* PCI master abort is expected during config cycles */ | |
258 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); | |
259 | ||
260 | orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); | |
261 | ||
262 | /* disable master abort reporting */ | |
263 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); | |
264 | ||
265 | /* clear error bits */ | |
266 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); | |
267 | ||
268 | if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { | |
269 | debugf3("%s(): failed edac_pci_add_device()\n", __func__); | |
270 | goto err; | |
271 | } | |
272 | ||
273 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
f87bd330 DJ |
274 | pdata->irq = irq_of_parse_and_map(op->node, 0); |
275 | res = devm_request_irq(&op->dev, pdata->irq, | |
a9a753d5 DJ |
276 | mpc85xx_pci_isr, IRQF_DISABLED, |
277 | "[EDAC] PCI err", pci); | |
278 | if (res < 0) { | |
279 | printk(KERN_ERR | |
280 | "%s: Unable to requiest irq %d for " | |
281 | "MPC85xx PCI err\n", __func__, pdata->irq); | |
f87bd330 | 282 | irq_dispose_mapping(pdata->irq); |
a9a753d5 DJ |
283 | res = -ENODEV; |
284 | goto err2; | |
285 | } | |
286 | ||
287 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", | |
288 | pdata->irq); | |
289 | } | |
290 | ||
f87bd330 | 291 | devres_remove_group(&op->dev, mpc85xx_pci_err_probe); |
a9a753d5 DJ |
292 | debugf3("%s(): success\n", __func__); |
293 | printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); | |
294 | ||
295 | return 0; | |
296 | ||
297 | err2: | |
f87bd330 | 298 | edac_pci_del_device(&op->dev); |
a9a753d5 DJ |
299 | err: |
300 | edac_pci_free_ctl_info(pci); | |
f87bd330 | 301 | devres_release_group(&op->dev, mpc85xx_pci_err_probe); |
a9a753d5 DJ |
302 | return res; |
303 | } | |
304 | ||
f87bd330 | 305 | static int mpc85xx_pci_err_remove(struct of_device *op) |
a9a753d5 | 306 | { |
f87bd330 | 307 | struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev); |
a9a753d5 DJ |
308 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; |
309 | ||
310 | debugf0("%s()\n", __func__); | |
311 | ||
312 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, | |
313 | orig_pci_err_cap_dr); | |
314 | ||
315 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en); | |
316 | ||
317 | edac_pci_del_device(pci->dev); | |
318 | ||
319 | if (edac_op_state == EDAC_OPSTATE_INT) | |
320 | irq_dispose_mapping(pdata->irq); | |
321 | ||
322 | edac_pci_free_ctl_info(pci); | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
f87bd330 DJ |
327 | static struct of_device_id mpc85xx_pci_err_of_match[] = { |
328 | { | |
329 | .compatible = "fsl,mpc8540-pcix", | |
330 | }, | |
331 | { | |
332 | .compatible = "fsl,mpc8540-pci", | |
333 | }, | |
334 | {}, | |
335 | }; | |
336 | ||
337 | static struct of_platform_driver mpc85xx_pci_err_driver = { | |
338 | .owner = THIS_MODULE, | |
339 | .name = "mpc85xx_pci_err", | |
340 | .match_table = mpc85xx_pci_err_of_match, | |
a9a753d5 DJ |
341 | .probe = mpc85xx_pci_err_probe, |
342 | .remove = __devexit_p(mpc85xx_pci_err_remove), | |
343 | .driver = { | |
f87bd330 DJ |
344 | .name = "mpc85xx_pci_err", |
345 | .owner = THIS_MODULE, | |
346 | }, | |
a9a753d5 DJ |
347 | }; |
348 | ||
349 | #endif /* CONFIG_PCI */ | |
350 | ||
351 | /**************************** L2 Err device ***************************/ | |
352 | ||
353 | /************************ L2 SYSFS parts ***********************************/ | |
354 | ||
355 | static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info | |
356 | *edac_dev, char *data) | |
357 | { | |
358 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
359 | return sprintf(data, "0x%08x", | |
360 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); | |
361 | } | |
362 | ||
363 | static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info | |
364 | *edac_dev, char *data) | |
365 | { | |
366 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
367 | return sprintf(data, "0x%08x", | |
368 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); | |
369 | } | |
370 | ||
371 | static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info | |
372 | *edac_dev, char *data) | |
373 | { | |
374 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
375 | return sprintf(data, "0x%08x", | |
376 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); | |
377 | } | |
378 | ||
379 | static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info | |
380 | *edac_dev, const char *data, | |
381 | size_t count) | |
382 | { | |
383 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
384 | if (isdigit(*data)) { | |
385 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, | |
386 | simple_strtoul(data, NULL, 0)); | |
387 | return count; | |
388 | } | |
389 | return 0; | |
390 | } | |
391 | ||
392 | static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info | |
393 | *edac_dev, const char *data, | |
394 | size_t count) | |
395 | { | |
396 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
397 | if (isdigit(*data)) { | |
398 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, | |
399 | simple_strtoul(data, NULL, 0)); | |
400 | return count; | |
401 | } | |
402 | return 0; | |
403 | } | |
404 | ||
405 | static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info | |
406 | *edac_dev, const char *data, | |
407 | size_t count) | |
408 | { | |
409 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
410 | if (isdigit(*data)) { | |
411 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, | |
412 | simple_strtoul(data, NULL, 0)); | |
413 | return count; | |
414 | } | |
415 | return 0; | |
416 | } | |
417 | ||
418 | static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { | |
419 | { | |
420 | .attr = { | |
421 | .name = "inject_data_hi", | |
422 | .mode = (S_IRUGO | S_IWUSR) | |
423 | }, | |
424 | .show = mpc85xx_l2_inject_data_hi_show, | |
425 | .store = mpc85xx_l2_inject_data_hi_store}, | |
426 | { | |
427 | .attr = { | |
428 | .name = "inject_data_lo", | |
429 | .mode = (S_IRUGO | S_IWUSR) | |
430 | }, | |
431 | .show = mpc85xx_l2_inject_data_lo_show, | |
432 | .store = mpc85xx_l2_inject_data_lo_store}, | |
433 | { | |
434 | .attr = { | |
435 | .name = "inject_ctrl", | |
436 | .mode = (S_IRUGO | S_IWUSR) | |
437 | }, | |
438 | .show = mpc85xx_l2_inject_ctrl_show, | |
439 | .store = mpc85xx_l2_inject_ctrl_store}, | |
440 | ||
441 | /* End of list */ | |
442 | { | |
443 | .attr = {.name = NULL} | |
444 | } | |
445 | }; | |
446 | ||
447 | static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info | |
448 | *edac_dev) | |
449 | { | |
450 | edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; | |
451 | } | |
452 | ||
453 | /***************************** L2 ops ***********************************/ | |
454 | ||
455 | static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) | |
456 | { | |
457 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
458 | u32 err_detect; | |
459 | ||
460 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); | |
461 | ||
462 | if (!(err_detect & L2_EDE_MASK)) | |
463 | return; | |
464 | ||
465 | printk(KERN_ERR "ECC Error in CPU L2 cache\n"); | |
466 | printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); | |
467 | printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", | |
468 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); | |
469 | printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", | |
470 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); | |
471 | printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", | |
472 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); | |
473 | printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", | |
474 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); | |
475 | printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", | |
476 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); | |
477 | ||
478 | /* clear error detect register */ | |
479 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); | |
480 | ||
481 | if (err_detect & L2_EDE_CE_MASK) | |
482 | edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); | |
483 | ||
484 | if (err_detect & L2_EDE_UE_MASK) | |
485 | edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); | |
486 | } | |
487 | ||
488 | static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) | |
489 | { | |
490 | struct edac_device_ctl_info *edac_dev = dev_id; | |
491 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
492 | u32 err_detect; | |
493 | ||
494 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); | |
495 | ||
496 | if (!(err_detect & L2_EDE_MASK)) | |
497 | return IRQ_NONE; | |
498 | ||
499 | mpc85xx_l2_check(edac_dev); | |
500 | ||
501 | return IRQ_HANDLED; | |
502 | } | |
503 | ||
504 | static int __devinit mpc85xx_l2_err_probe(struct of_device *op, | |
505 | const struct of_device_id *match) | |
506 | { | |
507 | struct edac_device_ctl_info *edac_dev; | |
508 | struct mpc85xx_l2_pdata *pdata; | |
509 | struct resource r; | |
510 | int res; | |
511 | ||
512 | if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) | |
513 | return -ENOMEM; | |
514 | ||
515 | edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), | |
516 | "cpu", 1, "L", 1, 2, NULL, 0, | |
517 | edac_dev_idx); | |
518 | if (!edac_dev) { | |
519 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); | |
520 | return -ENOMEM; | |
521 | } | |
522 | ||
523 | pdata = edac_dev->pvt_info; | |
524 | pdata->name = "mpc85xx_l2_err"; | |
525 | pdata->irq = NO_IRQ; | |
526 | edac_dev->dev = &op->dev; | |
527 | dev_set_drvdata(edac_dev->dev, edac_dev); | |
528 | edac_dev->ctl_name = pdata->name; | |
529 | edac_dev->dev_name = pdata->name; | |
530 | ||
531 | res = of_address_to_resource(op->node, 0, &r); | |
532 | if (res) { | |
533 | printk(KERN_ERR "%s: Unable to get resource for " | |
534 | "L2 err regs\n", __func__); | |
535 | goto err; | |
536 | } | |
537 | ||
538 | /* we only need the error registers */ | |
539 | r.start += 0xe00; | |
540 | ||
541 | if (!devm_request_mem_region(&op->dev, r.start, | |
542 | r.end - r.start + 1, pdata->name)) { | |
543 | printk(KERN_ERR "%s: Error while requesting mem region\n", | |
544 | __func__); | |
545 | res = -EBUSY; | |
546 | goto err; | |
547 | } | |
548 | ||
549 | pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); | |
550 | if (!pdata->l2_vbase) { | |
551 | printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); | |
552 | res = -ENOMEM; | |
553 | goto err; | |
554 | } | |
555 | ||
556 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); | |
557 | ||
558 | orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); | |
559 | ||
560 | /* clear the err_dis */ | |
561 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); | |
562 | ||
563 | edac_dev->mod_name = EDAC_MOD_STR; | |
564 | ||
565 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
566 | edac_dev->edac_check = mpc85xx_l2_check; | |
567 | ||
568 | mpc85xx_set_l2_sysfs_attributes(edac_dev); | |
569 | ||
570 | pdata->edac_idx = edac_dev_idx++; | |
571 | ||
572 | if (edac_device_add_device(edac_dev) > 0) { | |
573 | debugf3("%s(): failed edac_device_add_device()\n", __func__); | |
574 | goto err; | |
575 | } | |
576 | ||
577 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
578 | pdata->irq = irq_of_parse_and_map(op->node, 0); | |
579 | res = devm_request_irq(&op->dev, pdata->irq, | |
580 | mpc85xx_l2_isr, IRQF_DISABLED, | |
581 | "[EDAC] L2 err", edac_dev); | |
582 | if (res < 0) { | |
583 | printk(KERN_ERR | |
584 | "%s: Unable to requiest irq %d for " | |
585 | "MPC85xx L2 err\n", __func__, pdata->irq); | |
586 | irq_dispose_mapping(pdata->irq); | |
587 | res = -ENODEV; | |
588 | goto err2; | |
589 | } | |
590 | ||
591 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", | |
592 | pdata->irq); | |
593 | ||
594 | edac_dev->op_state = OP_RUNNING_INTERRUPT; | |
595 | ||
596 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); | |
597 | } | |
598 | ||
599 | devres_remove_group(&op->dev, mpc85xx_l2_err_probe); | |
600 | ||
601 | debugf3("%s(): success\n", __func__); | |
602 | printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); | |
603 | ||
604 | return 0; | |
605 | ||
606 | err2: | |
607 | edac_device_del_device(&op->dev); | |
608 | err: | |
609 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); | |
610 | edac_device_free_ctl_info(edac_dev); | |
611 | return res; | |
612 | } | |
613 | ||
614 | static int mpc85xx_l2_err_remove(struct of_device *op) | |
615 | { | |
616 | struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); | |
617 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
618 | ||
619 | debugf0("%s()\n", __func__); | |
620 | ||
621 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
622 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); | |
623 | irq_dispose_mapping(pdata->irq); | |
624 | } | |
625 | ||
626 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); | |
627 | edac_device_del_device(&op->dev); | |
628 | edac_device_free_ctl_info(edac_dev); | |
629 | return 0; | |
630 | } | |
631 | ||
632 | static struct of_device_id mpc85xx_l2_err_of_match[] = { | |
29d6cf26 KG |
633 | /* deprecate the fsl,85.. forms in the future, 2.6.30? */ |
634 | { .compatible = "fsl,8540-l2-cache-controller", }, | |
635 | { .compatible = "fsl,8541-l2-cache-controller", }, | |
636 | { .compatible = "fsl,8544-l2-cache-controller", }, | |
637 | { .compatible = "fsl,8548-l2-cache-controller", }, | |
638 | { .compatible = "fsl,8555-l2-cache-controller", }, | |
639 | { .compatible = "fsl,8568-l2-cache-controller", }, | |
640 | { .compatible = "fsl,mpc8536-l2-cache-controller", }, | |
641 | { .compatible = "fsl,mpc8540-l2-cache-controller", }, | |
642 | { .compatible = "fsl,mpc8541-l2-cache-controller", }, | |
643 | { .compatible = "fsl,mpc8544-l2-cache-controller", }, | |
644 | { .compatible = "fsl,mpc8548-l2-cache-controller", }, | |
645 | { .compatible = "fsl,mpc8555-l2-cache-controller", }, | |
646 | { .compatible = "fsl,mpc8560-l2-cache-controller", }, | |
647 | { .compatible = "fsl,mpc8568-l2-cache-controller", }, | |
648 | { .compatible = "fsl,mpc8572-l2-cache-controller", }, | |
a014554e | 649 | { .compatible = "fsl,p2020-l2-cache-controller", }, |
a9a753d5 DJ |
650 | {}, |
651 | }; | |
652 | ||
653 | static struct of_platform_driver mpc85xx_l2_err_driver = { | |
654 | .owner = THIS_MODULE, | |
655 | .name = "mpc85xx_l2_err", | |
656 | .match_table = mpc85xx_l2_err_of_match, | |
657 | .probe = mpc85xx_l2_err_probe, | |
658 | .remove = mpc85xx_l2_err_remove, | |
659 | .driver = { | |
660 | .name = "mpc85xx_l2_err", | |
661 | .owner = THIS_MODULE, | |
662 | }, | |
663 | }; | |
664 | ||
665 | /**************************** MC Err device ***************************/ | |
666 | ||
667 | static void mpc85xx_mc_check(struct mem_ctl_info *mci) | |
668 | { | |
669 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
670 | struct csrow_info *csrow; | |
671 | u32 err_detect; | |
672 | u32 syndrome; | |
673 | u32 err_addr; | |
674 | u32 pfn; | |
675 | int row_index; | |
676 | ||
677 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); | |
55e5750b | 678 | if (!err_detect) |
a9a753d5 DJ |
679 | return; |
680 | ||
681 | mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", | |
682 | err_detect); | |
683 | ||
684 | /* no more processing if not ECC bit errors */ | |
685 | if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { | |
686 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); | |
687 | return; | |
688 | } | |
689 | ||
690 | syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); | |
691 | err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS); | |
692 | pfn = err_addr >> PAGE_SHIFT; | |
693 | ||
694 | for (row_index = 0; row_index < mci->nr_csrows; row_index++) { | |
695 | csrow = &mci->csrows[row_index]; | |
696 | if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) | |
697 | break; | |
698 | } | |
699 | ||
700 | mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data High: %#8.8x\n", | |
701 | in_be32(pdata->mc_vbase + | |
702 | MPC85XX_MC_CAPTURE_DATA_HI)); | |
703 | mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data Low: %#8.8x\n", | |
704 | in_be32(pdata->mc_vbase + | |
705 | MPC85XX_MC_CAPTURE_DATA_LO)); | |
706 | mpc85xx_mc_printk(mci, KERN_ERR, "syndrome: %#8.8x\n", syndrome); | |
707 | mpc85xx_mc_printk(mci, KERN_ERR, "err addr: %#8.8x\n", err_addr); | |
708 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); | |
709 | ||
710 | /* we are out of range */ | |
711 | if (row_index == mci->nr_csrows) | |
712 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); | |
713 | ||
714 | if (err_detect & DDR_EDE_SBE) | |
715 | edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK, | |
716 | syndrome, row_index, 0, mci->ctl_name); | |
717 | ||
718 | if (err_detect & DDR_EDE_MBE) | |
719 | edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK, | |
720 | row_index, mci->ctl_name); | |
721 | ||
722 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); | |
723 | } | |
724 | ||
725 | static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) | |
726 | { | |
727 | struct mem_ctl_info *mci = dev_id; | |
728 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
729 | u32 err_detect; | |
730 | ||
731 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); | |
732 | if (!err_detect) | |
733 | return IRQ_NONE; | |
734 | ||
735 | mpc85xx_mc_check(mci); | |
736 | ||
737 | return IRQ_HANDLED; | |
738 | } | |
739 | ||
740 | static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci) | |
741 | { | |
742 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
743 | struct csrow_info *csrow; | |
744 | u32 sdram_ctl; | |
745 | u32 sdtype; | |
746 | enum mem_type mtype; | |
747 | u32 cs_bnds; | |
748 | int index; | |
749 | ||
750 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); | |
751 | ||
752 | sdtype = sdram_ctl & DSC_SDTYPE_MASK; | |
753 | if (sdram_ctl & DSC_RD_EN) { | |
754 | switch (sdtype) { | |
755 | case DSC_SDTYPE_DDR: | |
756 | mtype = MEM_RDDR; | |
757 | break; | |
758 | case DSC_SDTYPE_DDR2: | |
759 | mtype = MEM_RDDR2; | |
760 | break; | |
b1cfebc9 YS |
761 | case DSC_SDTYPE_DDR3: |
762 | mtype = MEM_RDDR3; | |
763 | break; | |
a9a753d5 DJ |
764 | default: |
765 | mtype = MEM_UNKNOWN; | |
766 | break; | |
767 | } | |
768 | } else { | |
769 | switch (sdtype) { | |
770 | case DSC_SDTYPE_DDR: | |
771 | mtype = MEM_DDR; | |
772 | break; | |
773 | case DSC_SDTYPE_DDR2: | |
774 | mtype = MEM_DDR2; | |
775 | break; | |
b1cfebc9 YS |
776 | case DSC_SDTYPE_DDR3: |
777 | mtype = MEM_DDR3; | |
778 | break; | |
a9a753d5 DJ |
779 | default: |
780 | mtype = MEM_UNKNOWN; | |
781 | break; | |
782 | } | |
783 | } | |
784 | ||
785 | for (index = 0; index < mci->nr_csrows; index++) { | |
786 | u32 start; | |
787 | u32 end; | |
788 | ||
789 | csrow = &mci->csrows[index]; | |
790 | cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + | |
791 | (index * MPC85XX_MC_CS_BNDS_OFS)); | |
792 | start = (cs_bnds & 0xfff0000) << 4; | |
793 | end = ((cs_bnds & 0xfff) << 20); | |
794 | if (start) | |
795 | start |= 0xfffff; | |
796 | if (end) | |
797 | end |= 0xfffff; | |
798 | ||
799 | if (start == end) | |
800 | continue; /* not populated */ | |
801 | ||
802 | csrow->first_page = start >> PAGE_SHIFT; | |
803 | csrow->last_page = end >> PAGE_SHIFT; | |
804 | csrow->nr_pages = csrow->last_page + 1 - csrow->first_page; | |
805 | csrow->grain = 8; | |
806 | csrow->mtype = mtype; | |
807 | csrow->dtype = DEV_UNKNOWN; | |
808 | if (sdram_ctl & DSC_X32_EN) | |
809 | csrow->dtype = DEV_X32; | |
810 | csrow->edac_mode = EDAC_SECDED; | |
811 | } | |
812 | } | |
813 | ||
814 | static int __devinit mpc85xx_mc_err_probe(struct of_device *op, | |
815 | const struct of_device_id *match) | |
816 | { | |
817 | struct mem_ctl_info *mci; | |
818 | struct mpc85xx_mc_pdata *pdata; | |
819 | struct resource r; | |
820 | u32 sdram_ctl; | |
821 | int res; | |
822 | ||
823 | if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) | |
824 | return -ENOMEM; | |
825 | ||
826 | mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx); | |
827 | if (!mci) { | |
828 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); | |
829 | return -ENOMEM; | |
830 | } | |
831 | ||
832 | pdata = mci->pvt_info; | |
833 | pdata->name = "mpc85xx_mc_err"; | |
834 | pdata->irq = NO_IRQ; | |
835 | mci->dev = &op->dev; | |
836 | pdata->edac_idx = edac_mc_idx++; | |
837 | dev_set_drvdata(mci->dev, mci); | |
838 | mci->ctl_name = pdata->name; | |
839 | mci->dev_name = pdata->name; | |
840 | ||
841 | res = of_address_to_resource(op->node, 0, &r); | |
842 | if (res) { | |
843 | printk(KERN_ERR "%s: Unable to get resource for MC err regs\n", | |
844 | __func__); | |
845 | goto err; | |
846 | } | |
847 | ||
848 | if (!devm_request_mem_region(&op->dev, r.start, | |
849 | r.end - r.start + 1, pdata->name)) { | |
850 | printk(KERN_ERR "%s: Error while requesting mem region\n", | |
851 | __func__); | |
852 | res = -EBUSY; | |
853 | goto err; | |
854 | } | |
855 | ||
856 | pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); | |
857 | if (!pdata->mc_vbase) { | |
858 | printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); | |
859 | res = -ENOMEM; | |
860 | goto err; | |
861 | } | |
862 | ||
863 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); | |
864 | if (!(sdram_ctl & DSC_ECC_EN)) { | |
865 | /* no ECC */ | |
866 | printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); | |
867 | res = -ENODEV; | |
868 | goto err; | |
869 | } | |
870 | ||
871 | debugf3("%s(): init mci\n", __func__); | |
872 | mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | | |
873 | MEM_FLAG_DDR | MEM_FLAG_DDR2; | |
874 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
875 | mci->edac_cap = EDAC_FLAG_SECDED; | |
876 | mci->mod_name = EDAC_MOD_STR; | |
877 | mci->mod_ver = MPC85XX_REVISION; | |
878 | ||
879 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
880 | mci->edac_check = mpc85xx_mc_check; | |
881 | ||
882 | mci->ctl_page_to_phys = NULL; | |
883 | ||
884 | mci->scrub_mode = SCRUB_SW_SRC; | |
885 | ||
886 | mpc85xx_set_mc_sysfs_attributes(mci); | |
887 | ||
888 | mpc85xx_init_csrows(mci); | |
889 | ||
890 | #ifdef CONFIG_EDAC_DEBUG | |
891 | edac_mc_register_mcidev_debug((struct attribute **)debug_attr); | |
892 | #endif | |
893 | ||
894 | /* store the original error disable bits */ | |
895 | orig_ddr_err_disable = | |
896 | in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); | |
897 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); | |
898 | ||
899 | /* clear all error bits */ | |
900 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); | |
901 | ||
902 | if (edac_mc_add_mc(mci)) { | |
903 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); | |
904 | goto err; | |
905 | } | |
906 | ||
907 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
908 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, | |
909 | DDR_EIE_MBEE | DDR_EIE_SBEE); | |
910 | ||
911 | /* store the original error management threshold */ | |
912 | orig_ddr_err_sbe = in_be32(pdata->mc_vbase + | |
913 | MPC85XX_MC_ERR_SBE) & 0xff0000; | |
914 | ||
915 | /* set threshold to 1 error per interrupt */ | |
916 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); | |
917 | ||
918 | /* register interrupts */ | |
919 | pdata->irq = irq_of_parse_and_map(op->node, 0); | |
920 | res = devm_request_irq(&op->dev, pdata->irq, | |
60be7551 AK |
921 | mpc85xx_mc_isr, |
922 | IRQF_DISABLED | IRQF_SHARED, | |
a9a753d5 DJ |
923 | "[EDAC] MC err", mci); |
924 | if (res < 0) { | |
925 | printk(KERN_ERR "%s: Unable to request irq %d for " | |
926 | "MPC85xx DRAM ERR\n", __func__, pdata->irq); | |
927 | irq_dispose_mapping(pdata->irq); | |
928 | res = -ENODEV; | |
929 | goto err2; | |
930 | } | |
931 | ||
932 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n", | |
933 | pdata->irq); | |
934 | } | |
935 | ||
936 | devres_remove_group(&op->dev, mpc85xx_mc_err_probe); | |
937 | debugf3("%s(): success\n", __func__); | |
938 | printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); | |
939 | ||
940 | return 0; | |
941 | ||
942 | err2: | |
943 | edac_mc_del_mc(&op->dev); | |
944 | err: | |
945 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); | |
946 | edac_mc_free(mci); | |
947 | return res; | |
948 | } | |
949 | ||
950 | static int mpc85xx_mc_err_remove(struct of_device *op) | |
951 | { | |
952 | struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); | |
953 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
954 | ||
955 | debugf0("%s()\n", __func__); | |
956 | ||
957 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
958 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); | |
959 | irq_dispose_mapping(pdata->irq); | |
960 | } | |
961 | ||
962 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, | |
963 | orig_ddr_err_disable); | |
964 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); | |
965 | ||
966 | edac_mc_del_mc(&op->dev); | |
967 | edac_mc_free(mci); | |
968 | return 0; | |
969 | } | |
970 | ||
971 | static struct of_device_id mpc85xx_mc_err_of_match[] = { | |
29d6cf26 KG |
972 | /* deprecate the fsl,85.. forms in the future, 2.6.30? */ |
973 | { .compatible = "fsl,8540-memory-controller", }, | |
974 | { .compatible = "fsl,8541-memory-controller", }, | |
975 | { .compatible = "fsl,8544-memory-controller", }, | |
976 | { .compatible = "fsl,8548-memory-controller", }, | |
977 | { .compatible = "fsl,8555-memory-controller", }, | |
978 | { .compatible = "fsl,8568-memory-controller", }, | |
979 | { .compatible = "fsl,mpc8536-memory-controller", }, | |
980 | { .compatible = "fsl,mpc8540-memory-controller", }, | |
981 | { .compatible = "fsl,mpc8541-memory-controller", }, | |
982 | { .compatible = "fsl,mpc8544-memory-controller", }, | |
983 | { .compatible = "fsl,mpc8548-memory-controller", }, | |
984 | { .compatible = "fsl,mpc8555-memory-controller", }, | |
985 | { .compatible = "fsl,mpc8560-memory-controller", }, | |
986 | { .compatible = "fsl,mpc8568-memory-controller", }, | |
987 | { .compatible = "fsl,mpc8572-memory-controller", }, | |
a014554e | 988 | { .compatible = "fsl,p2020-memory-controller", }, |
a9a753d5 DJ |
989 | {}, |
990 | }; | |
991 | ||
992 | static struct of_platform_driver mpc85xx_mc_err_driver = { | |
993 | .owner = THIS_MODULE, | |
994 | .name = "mpc85xx_mc_err", | |
995 | .match_table = mpc85xx_mc_err_of_match, | |
996 | .probe = mpc85xx_mc_err_probe, | |
997 | .remove = mpc85xx_mc_err_remove, | |
998 | .driver = { | |
999 | .name = "mpc85xx_mc_err", | |
1000 | .owner = THIS_MODULE, | |
1001 | }, | |
1002 | }; | |
1003 | ||
60be7551 AK |
1004 | |
1005 | static void __init mpc85xx_mc_clear_rfxe(void *data) | |
1006 | { | |
1007 | orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); | |
1008 | mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000)); | |
1009 | } | |
1010 | ||
1011 | ||
a9a753d5 DJ |
1012 | static int __init mpc85xx_mc_init(void) |
1013 | { | |
1014 | int res = 0; | |
1015 | ||
1016 | printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " | |
1017 | "(C) 2006 Montavista Software\n"); | |
1018 | ||
1019 | /* make sure error reporting method is sane */ | |
1020 | switch (edac_op_state) { | |
1021 | case EDAC_OPSTATE_POLL: | |
1022 | case EDAC_OPSTATE_INT: | |
1023 | break; | |
1024 | default: | |
1025 | edac_op_state = EDAC_OPSTATE_INT; | |
1026 | break; | |
1027 | } | |
1028 | ||
1029 | res = of_register_platform_driver(&mpc85xx_mc_err_driver); | |
1030 | if (res) | |
1031 | printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n"); | |
1032 | ||
1033 | res = of_register_platform_driver(&mpc85xx_l2_err_driver); | |
1034 | if (res) | |
1035 | printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); | |
1036 | ||
1037 | #ifdef CONFIG_PCI | |
f87bd330 | 1038 | res = of_register_platform_driver(&mpc85xx_pci_err_driver); |
a9a753d5 DJ |
1039 | if (res) |
1040 | printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n"); | |
1041 | #endif | |
1042 | ||
1043 | /* | |
1044 | * need to clear HID1[RFXE] to disable machine check int | |
1045 | * so we can catch it | |
1046 | */ | |
60be7551 AK |
1047 | if (edac_op_state == EDAC_OPSTATE_INT) |
1048 | on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); | |
a9a753d5 DJ |
1049 | |
1050 | return 0; | |
1051 | } | |
1052 | ||
1053 | module_init(mpc85xx_mc_init); | |
1054 | ||
60be7551 AK |
1055 | static void __exit mpc85xx_mc_restore_hid1(void *data) |
1056 | { | |
1057 | mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]); | |
1058 | } | |
1059 | ||
a9a753d5 DJ |
1060 | static void __exit mpc85xx_mc_exit(void) |
1061 | { | |
60be7551 | 1062 | on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); |
a9a753d5 | 1063 | #ifdef CONFIG_PCI |
f87bd330 | 1064 | of_unregister_platform_driver(&mpc85xx_pci_err_driver); |
a9a753d5 DJ |
1065 | #endif |
1066 | of_unregister_platform_driver(&mpc85xx_l2_err_driver); | |
1067 | of_unregister_platform_driver(&mpc85xx_mc_err_driver); | |
1068 | } | |
1069 | ||
1070 | module_exit(mpc85xx_mc_exit); | |
1071 | ||
1072 | MODULE_LICENSE("GPL"); | |
1073 | MODULE_AUTHOR("Montavista Software, Inc."); | |
1074 | module_param(edac_op_state, int, 0444); | |
1075 | MODULE_PARM_DESC(edac_op_state, | |
1076 | "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); |