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a9a753d5 DJ |
1 | /* |
2 | * Freescale MPC85xx Memory Controller kenel module | |
3 | * | |
4 | * Author: Dave Jiang <djiang@mvista.com> | |
5 | * | |
6 | * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | * | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/ctype.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/mod_devicetable.h> | |
19 | #include <linux/edac.h> | |
60be7551 | 20 | #include <linux/smp.h> |
a9a753d5 DJ |
21 | |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/of_device.h> | |
a9a753d5 DJ |
24 | #include "edac_module.h" |
25 | #include "edac_core.h" | |
26 | #include "mpc85xx_edac.h" | |
27 | ||
28 | static int edac_dev_idx; | |
29 | static int edac_pci_idx; | |
30 | static int edac_mc_idx; | |
31 | ||
32 | static u32 orig_ddr_err_disable; | |
33 | static u32 orig_ddr_err_sbe; | |
34 | ||
35 | /* | |
36 | * PCI Err defines | |
37 | */ | |
38 | #ifdef CONFIG_PCI | |
39 | static u32 orig_pci_err_cap_dr; | |
40 | static u32 orig_pci_err_en; | |
41 | #endif | |
42 | ||
43 | static u32 orig_l2_err_disable; | |
b4846251 | 44 | #ifdef CONFIG_MPC85xx |
60be7551 | 45 | static u32 orig_hid1[2]; |
b4846251 | 46 | #endif |
a9a753d5 | 47 | |
a9a753d5 DJ |
48 | /************************ MC SYSFS parts ***********************************/ |
49 | ||
50 | static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci, | |
51 | char *data) | |
52 | { | |
53 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
54 | return sprintf(data, "0x%08x", | |
55 | in_be32(pdata->mc_vbase + | |
56 | MPC85XX_MC_DATA_ERR_INJECT_HI)); | |
57 | } | |
58 | ||
59 | static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci, | |
60 | char *data) | |
61 | { | |
62 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
63 | return sprintf(data, "0x%08x", | |
64 | in_be32(pdata->mc_vbase + | |
65 | MPC85XX_MC_DATA_ERR_INJECT_LO)); | |
66 | } | |
67 | ||
68 | static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data) | |
69 | { | |
70 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
71 | return sprintf(data, "0x%08x", | |
72 | in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); | |
73 | } | |
74 | ||
75 | static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci, | |
76 | const char *data, size_t count) | |
77 | { | |
78 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
79 | if (isdigit(*data)) { | |
80 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, | |
81 | simple_strtoul(data, NULL, 0)); | |
82 | return count; | |
83 | } | |
84 | return 0; | |
85 | } | |
86 | ||
87 | static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci, | |
88 | const char *data, size_t count) | |
89 | { | |
90 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
91 | if (isdigit(*data)) { | |
92 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, | |
93 | simple_strtoul(data, NULL, 0)); | |
94 | return count; | |
95 | } | |
96 | return 0; | |
97 | } | |
98 | ||
99 | static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci, | |
100 | const char *data, size_t count) | |
101 | { | |
102 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
103 | if (isdigit(*data)) { | |
104 | out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, | |
105 | simple_strtoul(data, NULL, 0)); | |
106 | return count; | |
107 | } | |
108 | return 0; | |
109 | } | |
110 | ||
111 | static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = { | |
112 | { | |
113 | .attr = { | |
114 | .name = "inject_data_hi", | |
115 | .mode = (S_IRUGO | S_IWUSR) | |
116 | }, | |
117 | .show = mpc85xx_mc_inject_data_hi_show, | |
118 | .store = mpc85xx_mc_inject_data_hi_store}, | |
119 | { | |
120 | .attr = { | |
121 | .name = "inject_data_lo", | |
122 | .mode = (S_IRUGO | S_IWUSR) | |
123 | }, | |
124 | .show = mpc85xx_mc_inject_data_lo_show, | |
125 | .store = mpc85xx_mc_inject_data_lo_store}, | |
126 | { | |
127 | .attr = { | |
128 | .name = "inject_ctrl", | |
129 | .mode = (S_IRUGO | S_IWUSR) | |
130 | }, | |
131 | .show = mpc85xx_mc_inject_ctrl_show, | |
132 | .store = mpc85xx_mc_inject_ctrl_store}, | |
133 | ||
134 | /* End of list */ | |
135 | { | |
136 | .attr = {.name = NULL} | |
137 | } | |
138 | }; | |
139 | ||
140 | static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci) | |
141 | { | |
142 | mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes; | |
143 | } | |
144 | ||
145 | /**************************** PCI Err device ***************************/ | |
146 | #ifdef CONFIG_PCI | |
147 | ||
148 | static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) | |
149 | { | |
150 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; | |
151 | u32 err_detect; | |
152 | ||
153 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); | |
154 | ||
155 | /* master aborts can happen during PCI config cycles */ | |
156 | if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { | |
157 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); | |
158 | return; | |
159 | } | |
160 | ||
161 | printk(KERN_ERR "PCI error(s) detected\n"); | |
162 | printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); | |
163 | ||
164 | printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", | |
165 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); | |
166 | printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", | |
167 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); | |
168 | printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", | |
169 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); | |
170 | printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", | |
171 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); | |
172 | printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", | |
173 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); | |
174 | ||
175 | /* clear error bits */ | |
176 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); | |
177 | ||
178 | if (err_detect & PCI_EDE_PERR_MASK) | |
179 | edac_pci_handle_pe(pci, pci->ctl_name); | |
180 | ||
181 | if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) | |
182 | edac_pci_handle_npe(pci, pci->ctl_name); | |
183 | } | |
184 | ||
185 | static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) | |
186 | { | |
187 | struct edac_pci_ctl_info *pci = dev_id; | |
188 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; | |
189 | u32 err_detect; | |
190 | ||
191 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); | |
192 | ||
193 | if (!err_detect) | |
194 | return IRQ_NONE; | |
195 | ||
196 | mpc85xx_pci_check(pci); | |
197 | ||
198 | return IRQ_HANDLED; | |
199 | } | |
200 | ||
f87bd330 DJ |
201 | static int __devinit mpc85xx_pci_err_probe(struct of_device *op, |
202 | const struct of_device_id *match) | |
a9a753d5 DJ |
203 | { |
204 | struct edac_pci_ctl_info *pci; | |
205 | struct mpc85xx_pci_pdata *pdata; | |
f87bd330 | 206 | struct resource r; |
a9a753d5 DJ |
207 | int res = 0; |
208 | ||
f87bd330 | 209 | if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) |
a9a753d5 DJ |
210 | return -ENOMEM; |
211 | ||
212 | pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); | |
213 | if (!pci) | |
214 | return -ENOMEM; | |
215 | ||
216 | pdata = pci->pvt_info; | |
217 | pdata->name = "mpc85xx_pci_err"; | |
218 | pdata->irq = NO_IRQ; | |
f87bd330 DJ |
219 | dev_set_drvdata(&op->dev, pci); |
220 | pci->dev = &op->dev; | |
a9a753d5 DJ |
221 | pci->mod_name = EDAC_MOD_STR; |
222 | pci->ctl_name = pdata->name; | |
031d5518 | 223 | pci->dev_name = dev_name(&op->dev); |
a9a753d5 DJ |
224 | |
225 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
226 | pci->edac_check = mpc85xx_pci_check; | |
227 | ||
228 | pdata->edac_idx = edac_pci_idx++; | |
229 | ||
f87bd330 DJ |
230 | res = of_address_to_resource(op->node, 0, &r); |
231 | if (res) { | |
a9a753d5 DJ |
232 | printk(KERN_ERR "%s: Unable to get resource for " |
233 | "PCI err regs\n", __func__); | |
234 | goto err; | |
235 | } | |
236 | ||
f87bd330 DJ |
237 | /* we only need the error registers */ |
238 | r.start += 0xe00; | |
239 | ||
240 | if (!devm_request_mem_region(&op->dev, r.start, | |
241 | r.end - r.start + 1, pdata->name)) { | |
a9a753d5 DJ |
242 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
243 | __func__); | |
244 | res = -EBUSY; | |
245 | goto err; | |
246 | } | |
247 | ||
f87bd330 DJ |
248 | pdata->pci_vbase = devm_ioremap(&op->dev, r.start, |
249 | r.end - r.start + 1); | |
a9a753d5 DJ |
250 | if (!pdata->pci_vbase) { |
251 | printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); | |
252 | res = -ENOMEM; | |
253 | goto err; | |
254 | } | |
255 | ||
256 | orig_pci_err_cap_dr = | |
257 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); | |
258 | ||
259 | /* PCI master abort is expected during config cycles */ | |
260 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); | |
261 | ||
262 | orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); | |
263 | ||
264 | /* disable master abort reporting */ | |
265 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); | |
266 | ||
267 | /* clear error bits */ | |
268 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); | |
269 | ||
270 | if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { | |
271 | debugf3("%s(): failed edac_pci_add_device()\n", __func__); | |
272 | goto err; | |
273 | } | |
274 | ||
275 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
f87bd330 DJ |
276 | pdata->irq = irq_of_parse_and_map(op->node, 0); |
277 | res = devm_request_irq(&op->dev, pdata->irq, | |
a9a753d5 DJ |
278 | mpc85xx_pci_isr, IRQF_DISABLED, |
279 | "[EDAC] PCI err", pci); | |
280 | if (res < 0) { | |
281 | printk(KERN_ERR | |
282 | "%s: Unable to requiest irq %d for " | |
283 | "MPC85xx PCI err\n", __func__, pdata->irq); | |
f87bd330 | 284 | irq_dispose_mapping(pdata->irq); |
a9a753d5 DJ |
285 | res = -ENODEV; |
286 | goto err2; | |
287 | } | |
288 | ||
289 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", | |
290 | pdata->irq); | |
291 | } | |
292 | ||
f87bd330 | 293 | devres_remove_group(&op->dev, mpc85xx_pci_err_probe); |
a9a753d5 DJ |
294 | debugf3("%s(): success\n", __func__); |
295 | printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); | |
296 | ||
297 | return 0; | |
298 | ||
299 | err2: | |
f87bd330 | 300 | edac_pci_del_device(&op->dev); |
a9a753d5 DJ |
301 | err: |
302 | edac_pci_free_ctl_info(pci); | |
f87bd330 | 303 | devres_release_group(&op->dev, mpc85xx_pci_err_probe); |
a9a753d5 DJ |
304 | return res; |
305 | } | |
306 | ||
f87bd330 | 307 | static int mpc85xx_pci_err_remove(struct of_device *op) |
a9a753d5 | 308 | { |
f87bd330 | 309 | struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev); |
a9a753d5 DJ |
310 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; |
311 | ||
312 | debugf0("%s()\n", __func__); | |
313 | ||
314 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, | |
315 | orig_pci_err_cap_dr); | |
316 | ||
317 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en); | |
318 | ||
319 | edac_pci_del_device(pci->dev); | |
320 | ||
321 | if (edac_op_state == EDAC_OPSTATE_INT) | |
322 | irq_dispose_mapping(pdata->irq); | |
323 | ||
324 | edac_pci_free_ctl_info(pci); | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
f87bd330 DJ |
329 | static struct of_device_id mpc85xx_pci_err_of_match[] = { |
330 | { | |
331 | .compatible = "fsl,mpc8540-pcix", | |
332 | }, | |
333 | { | |
334 | .compatible = "fsl,mpc8540-pci", | |
335 | }, | |
336 | {}, | |
337 | }; | |
338 | ||
339 | static struct of_platform_driver mpc85xx_pci_err_driver = { | |
340 | .owner = THIS_MODULE, | |
341 | .name = "mpc85xx_pci_err", | |
342 | .match_table = mpc85xx_pci_err_of_match, | |
a9a753d5 DJ |
343 | .probe = mpc85xx_pci_err_probe, |
344 | .remove = __devexit_p(mpc85xx_pci_err_remove), | |
345 | .driver = { | |
f87bd330 DJ |
346 | .name = "mpc85xx_pci_err", |
347 | .owner = THIS_MODULE, | |
348 | }, | |
a9a753d5 DJ |
349 | }; |
350 | ||
351 | #endif /* CONFIG_PCI */ | |
352 | ||
353 | /**************************** L2 Err device ***************************/ | |
354 | ||
355 | /************************ L2 SYSFS parts ***********************************/ | |
356 | ||
357 | static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info | |
358 | *edac_dev, char *data) | |
359 | { | |
360 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
361 | return sprintf(data, "0x%08x", | |
362 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); | |
363 | } | |
364 | ||
365 | static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info | |
366 | *edac_dev, char *data) | |
367 | { | |
368 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
369 | return sprintf(data, "0x%08x", | |
370 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); | |
371 | } | |
372 | ||
373 | static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info | |
374 | *edac_dev, char *data) | |
375 | { | |
376 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
377 | return sprintf(data, "0x%08x", | |
378 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); | |
379 | } | |
380 | ||
381 | static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info | |
382 | *edac_dev, const char *data, | |
383 | size_t count) | |
384 | { | |
385 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
386 | if (isdigit(*data)) { | |
387 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, | |
388 | simple_strtoul(data, NULL, 0)); | |
389 | return count; | |
390 | } | |
391 | return 0; | |
392 | } | |
393 | ||
394 | static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info | |
395 | *edac_dev, const char *data, | |
396 | size_t count) | |
397 | { | |
398 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
399 | if (isdigit(*data)) { | |
400 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, | |
401 | simple_strtoul(data, NULL, 0)); | |
402 | return count; | |
403 | } | |
404 | return 0; | |
405 | } | |
406 | ||
407 | static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info | |
408 | *edac_dev, const char *data, | |
409 | size_t count) | |
410 | { | |
411 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
412 | if (isdigit(*data)) { | |
413 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, | |
414 | simple_strtoul(data, NULL, 0)); | |
415 | return count; | |
416 | } | |
417 | return 0; | |
418 | } | |
419 | ||
420 | static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { | |
421 | { | |
422 | .attr = { | |
423 | .name = "inject_data_hi", | |
424 | .mode = (S_IRUGO | S_IWUSR) | |
425 | }, | |
426 | .show = mpc85xx_l2_inject_data_hi_show, | |
427 | .store = mpc85xx_l2_inject_data_hi_store}, | |
428 | { | |
429 | .attr = { | |
430 | .name = "inject_data_lo", | |
431 | .mode = (S_IRUGO | S_IWUSR) | |
432 | }, | |
433 | .show = mpc85xx_l2_inject_data_lo_show, | |
434 | .store = mpc85xx_l2_inject_data_lo_store}, | |
435 | { | |
436 | .attr = { | |
437 | .name = "inject_ctrl", | |
438 | .mode = (S_IRUGO | S_IWUSR) | |
439 | }, | |
440 | .show = mpc85xx_l2_inject_ctrl_show, | |
441 | .store = mpc85xx_l2_inject_ctrl_store}, | |
442 | ||
443 | /* End of list */ | |
444 | { | |
445 | .attr = {.name = NULL} | |
446 | } | |
447 | }; | |
448 | ||
449 | static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info | |
450 | *edac_dev) | |
451 | { | |
452 | edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; | |
453 | } | |
454 | ||
455 | /***************************** L2 ops ***********************************/ | |
456 | ||
457 | static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) | |
458 | { | |
459 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
460 | u32 err_detect; | |
461 | ||
462 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); | |
463 | ||
464 | if (!(err_detect & L2_EDE_MASK)) | |
465 | return; | |
466 | ||
467 | printk(KERN_ERR "ECC Error in CPU L2 cache\n"); | |
468 | printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); | |
469 | printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", | |
470 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); | |
471 | printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", | |
472 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); | |
473 | printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", | |
474 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); | |
475 | printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", | |
476 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); | |
477 | printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", | |
478 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); | |
479 | ||
480 | /* clear error detect register */ | |
481 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); | |
482 | ||
483 | if (err_detect & L2_EDE_CE_MASK) | |
484 | edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); | |
485 | ||
486 | if (err_detect & L2_EDE_UE_MASK) | |
487 | edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); | |
488 | } | |
489 | ||
490 | static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) | |
491 | { | |
492 | struct edac_device_ctl_info *edac_dev = dev_id; | |
493 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
494 | u32 err_detect; | |
495 | ||
496 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); | |
497 | ||
498 | if (!(err_detect & L2_EDE_MASK)) | |
499 | return IRQ_NONE; | |
500 | ||
501 | mpc85xx_l2_check(edac_dev); | |
502 | ||
503 | return IRQ_HANDLED; | |
504 | } | |
505 | ||
506 | static int __devinit mpc85xx_l2_err_probe(struct of_device *op, | |
507 | const struct of_device_id *match) | |
508 | { | |
509 | struct edac_device_ctl_info *edac_dev; | |
510 | struct mpc85xx_l2_pdata *pdata; | |
511 | struct resource r; | |
512 | int res; | |
513 | ||
514 | if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) | |
515 | return -ENOMEM; | |
516 | ||
517 | edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), | |
518 | "cpu", 1, "L", 1, 2, NULL, 0, | |
519 | edac_dev_idx); | |
520 | if (!edac_dev) { | |
521 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); | |
522 | return -ENOMEM; | |
523 | } | |
524 | ||
525 | pdata = edac_dev->pvt_info; | |
526 | pdata->name = "mpc85xx_l2_err"; | |
527 | pdata->irq = NO_IRQ; | |
528 | edac_dev->dev = &op->dev; | |
529 | dev_set_drvdata(edac_dev->dev, edac_dev); | |
530 | edac_dev->ctl_name = pdata->name; | |
531 | edac_dev->dev_name = pdata->name; | |
532 | ||
533 | res = of_address_to_resource(op->node, 0, &r); | |
534 | if (res) { | |
535 | printk(KERN_ERR "%s: Unable to get resource for " | |
536 | "L2 err regs\n", __func__); | |
537 | goto err; | |
538 | } | |
539 | ||
540 | /* we only need the error registers */ | |
541 | r.start += 0xe00; | |
542 | ||
543 | if (!devm_request_mem_region(&op->dev, r.start, | |
544 | r.end - r.start + 1, pdata->name)) { | |
545 | printk(KERN_ERR "%s: Error while requesting mem region\n", | |
546 | __func__); | |
547 | res = -EBUSY; | |
548 | goto err; | |
549 | } | |
550 | ||
551 | pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); | |
552 | if (!pdata->l2_vbase) { | |
553 | printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); | |
554 | res = -ENOMEM; | |
555 | goto err; | |
556 | } | |
557 | ||
558 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); | |
559 | ||
560 | orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); | |
561 | ||
562 | /* clear the err_dis */ | |
563 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); | |
564 | ||
565 | edac_dev->mod_name = EDAC_MOD_STR; | |
566 | ||
567 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
568 | edac_dev->edac_check = mpc85xx_l2_check; | |
569 | ||
570 | mpc85xx_set_l2_sysfs_attributes(edac_dev); | |
571 | ||
572 | pdata->edac_idx = edac_dev_idx++; | |
573 | ||
574 | if (edac_device_add_device(edac_dev) > 0) { | |
575 | debugf3("%s(): failed edac_device_add_device()\n", __func__); | |
576 | goto err; | |
577 | } | |
578 | ||
579 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
580 | pdata->irq = irq_of_parse_and_map(op->node, 0); | |
581 | res = devm_request_irq(&op->dev, pdata->irq, | |
582 | mpc85xx_l2_isr, IRQF_DISABLED, | |
583 | "[EDAC] L2 err", edac_dev); | |
584 | if (res < 0) { | |
585 | printk(KERN_ERR | |
586 | "%s: Unable to requiest irq %d for " | |
587 | "MPC85xx L2 err\n", __func__, pdata->irq); | |
588 | irq_dispose_mapping(pdata->irq); | |
589 | res = -ENODEV; | |
590 | goto err2; | |
591 | } | |
592 | ||
593 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", | |
594 | pdata->irq); | |
595 | ||
596 | edac_dev->op_state = OP_RUNNING_INTERRUPT; | |
597 | ||
598 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); | |
599 | } | |
600 | ||
601 | devres_remove_group(&op->dev, mpc85xx_l2_err_probe); | |
602 | ||
603 | debugf3("%s(): success\n", __func__); | |
604 | printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); | |
605 | ||
606 | return 0; | |
607 | ||
608 | err2: | |
609 | edac_device_del_device(&op->dev); | |
610 | err: | |
611 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); | |
612 | edac_device_free_ctl_info(edac_dev); | |
613 | return res; | |
614 | } | |
615 | ||
616 | static int mpc85xx_l2_err_remove(struct of_device *op) | |
617 | { | |
618 | struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); | |
619 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
620 | ||
621 | debugf0("%s()\n", __func__); | |
622 | ||
623 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
624 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); | |
625 | irq_dispose_mapping(pdata->irq); | |
626 | } | |
627 | ||
628 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); | |
629 | edac_device_del_device(&op->dev); | |
630 | edac_device_free_ctl_info(edac_dev); | |
631 | return 0; | |
632 | } | |
633 | ||
634 | static struct of_device_id mpc85xx_l2_err_of_match[] = { | |
29d6cf26 KG |
635 | /* deprecate the fsl,85.. forms in the future, 2.6.30? */ |
636 | { .compatible = "fsl,8540-l2-cache-controller", }, | |
637 | { .compatible = "fsl,8541-l2-cache-controller", }, | |
638 | { .compatible = "fsl,8544-l2-cache-controller", }, | |
639 | { .compatible = "fsl,8548-l2-cache-controller", }, | |
640 | { .compatible = "fsl,8555-l2-cache-controller", }, | |
641 | { .compatible = "fsl,8568-l2-cache-controller", }, | |
642 | { .compatible = "fsl,mpc8536-l2-cache-controller", }, | |
643 | { .compatible = "fsl,mpc8540-l2-cache-controller", }, | |
644 | { .compatible = "fsl,mpc8541-l2-cache-controller", }, | |
645 | { .compatible = "fsl,mpc8544-l2-cache-controller", }, | |
646 | { .compatible = "fsl,mpc8548-l2-cache-controller", }, | |
647 | { .compatible = "fsl,mpc8555-l2-cache-controller", }, | |
648 | { .compatible = "fsl,mpc8560-l2-cache-controller", }, | |
649 | { .compatible = "fsl,mpc8568-l2-cache-controller", }, | |
650 | { .compatible = "fsl,mpc8572-l2-cache-controller", }, | |
a014554e | 651 | { .compatible = "fsl,p2020-l2-cache-controller", }, |
a9a753d5 DJ |
652 | {}, |
653 | }; | |
654 | ||
655 | static struct of_platform_driver mpc85xx_l2_err_driver = { | |
656 | .owner = THIS_MODULE, | |
657 | .name = "mpc85xx_l2_err", | |
658 | .match_table = mpc85xx_l2_err_of_match, | |
659 | .probe = mpc85xx_l2_err_probe, | |
660 | .remove = mpc85xx_l2_err_remove, | |
661 | .driver = { | |
662 | .name = "mpc85xx_l2_err", | |
663 | .owner = THIS_MODULE, | |
664 | }, | |
665 | }; | |
666 | ||
667 | /**************************** MC Err device ***************************/ | |
668 | ||
669 | static void mpc85xx_mc_check(struct mem_ctl_info *mci) | |
670 | { | |
671 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
672 | struct csrow_info *csrow; | |
673 | u32 err_detect; | |
674 | u32 syndrome; | |
675 | u32 err_addr; | |
676 | u32 pfn; | |
677 | int row_index; | |
678 | ||
679 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); | |
55e5750b | 680 | if (!err_detect) |
a9a753d5 DJ |
681 | return; |
682 | ||
683 | mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", | |
684 | err_detect); | |
685 | ||
686 | /* no more processing if not ECC bit errors */ | |
687 | if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { | |
688 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); | |
689 | return; | |
690 | } | |
691 | ||
692 | syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); | |
693 | err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS); | |
694 | pfn = err_addr >> PAGE_SHIFT; | |
695 | ||
696 | for (row_index = 0; row_index < mci->nr_csrows; row_index++) { | |
697 | csrow = &mci->csrows[row_index]; | |
698 | if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) | |
699 | break; | |
700 | } | |
701 | ||
702 | mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data High: %#8.8x\n", | |
703 | in_be32(pdata->mc_vbase + | |
704 | MPC85XX_MC_CAPTURE_DATA_HI)); | |
705 | mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data Low: %#8.8x\n", | |
706 | in_be32(pdata->mc_vbase + | |
707 | MPC85XX_MC_CAPTURE_DATA_LO)); | |
708 | mpc85xx_mc_printk(mci, KERN_ERR, "syndrome: %#8.8x\n", syndrome); | |
709 | mpc85xx_mc_printk(mci, KERN_ERR, "err addr: %#8.8x\n", err_addr); | |
710 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); | |
711 | ||
712 | /* we are out of range */ | |
713 | if (row_index == mci->nr_csrows) | |
714 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); | |
715 | ||
716 | if (err_detect & DDR_EDE_SBE) | |
717 | edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK, | |
718 | syndrome, row_index, 0, mci->ctl_name); | |
719 | ||
720 | if (err_detect & DDR_EDE_MBE) | |
721 | edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK, | |
722 | row_index, mci->ctl_name); | |
723 | ||
724 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); | |
725 | } | |
726 | ||
727 | static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) | |
728 | { | |
729 | struct mem_ctl_info *mci = dev_id; | |
730 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
731 | u32 err_detect; | |
732 | ||
733 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); | |
734 | if (!err_detect) | |
735 | return IRQ_NONE; | |
736 | ||
737 | mpc85xx_mc_check(mci); | |
738 | ||
739 | return IRQ_HANDLED; | |
740 | } | |
741 | ||
742 | static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci) | |
743 | { | |
744 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
745 | struct csrow_info *csrow; | |
746 | u32 sdram_ctl; | |
747 | u32 sdtype; | |
748 | enum mem_type mtype; | |
749 | u32 cs_bnds; | |
750 | int index; | |
751 | ||
752 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); | |
753 | ||
754 | sdtype = sdram_ctl & DSC_SDTYPE_MASK; | |
755 | if (sdram_ctl & DSC_RD_EN) { | |
756 | switch (sdtype) { | |
757 | case DSC_SDTYPE_DDR: | |
758 | mtype = MEM_RDDR; | |
759 | break; | |
760 | case DSC_SDTYPE_DDR2: | |
761 | mtype = MEM_RDDR2; | |
762 | break; | |
b1cfebc9 YS |
763 | case DSC_SDTYPE_DDR3: |
764 | mtype = MEM_RDDR3; | |
765 | break; | |
a9a753d5 DJ |
766 | default: |
767 | mtype = MEM_UNKNOWN; | |
768 | break; | |
769 | } | |
770 | } else { | |
771 | switch (sdtype) { | |
772 | case DSC_SDTYPE_DDR: | |
773 | mtype = MEM_DDR; | |
774 | break; | |
775 | case DSC_SDTYPE_DDR2: | |
776 | mtype = MEM_DDR2; | |
777 | break; | |
b1cfebc9 YS |
778 | case DSC_SDTYPE_DDR3: |
779 | mtype = MEM_DDR3; | |
780 | break; | |
a9a753d5 DJ |
781 | default: |
782 | mtype = MEM_UNKNOWN; | |
783 | break; | |
784 | } | |
785 | } | |
786 | ||
787 | for (index = 0; index < mci->nr_csrows; index++) { | |
788 | u32 start; | |
789 | u32 end; | |
790 | ||
791 | csrow = &mci->csrows[index]; | |
792 | cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + | |
793 | (index * MPC85XX_MC_CS_BNDS_OFS)); | |
b4846251 IS |
794 | |
795 | start = (cs_bnds & 0xffff0000) >> 16; | |
796 | end = (cs_bnds & 0x0000ffff); | |
a9a753d5 DJ |
797 | |
798 | if (start == end) | |
799 | continue; /* not populated */ | |
800 | ||
b4846251 IS |
801 | start <<= (24 - PAGE_SHIFT); |
802 | end <<= (24 - PAGE_SHIFT); | |
803 | end |= (1 << (24 - PAGE_SHIFT)) - 1; | |
804 | ||
a9a753d5 DJ |
805 | csrow->first_page = start >> PAGE_SHIFT; |
806 | csrow->last_page = end >> PAGE_SHIFT; | |
b4846251 | 807 | csrow->nr_pages = end + 1 - start; |
a9a753d5 DJ |
808 | csrow->grain = 8; |
809 | csrow->mtype = mtype; | |
810 | csrow->dtype = DEV_UNKNOWN; | |
811 | if (sdram_ctl & DSC_X32_EN) | |
812 | csrow->dtype = DEV_X32; | |
813 | csrow->edac_mode = EDAC_SECDED; | |
814 | } | |
815 | } | |
816 | ||
817 | static int __devinit mpc85xx_mc_err_probe(struct of_device *op, | |
818 | const struct of_device_id *match) | |
819 | { | |
820 | struct mem_ctl_info *mci; | |
821 | struct mpc85xx_mc_pdata *pdata; | |
822 | struct resource r; | |
823 | u32 sdram_ctl; | |
824 | int res; | |
825 | ||
826 | if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) | |
827 | return -ENOMEM; | |
828 | ||
829 | mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx); | |
830 | if (!mci) { | |
831 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); | |
832 | return -ENOMEM; | |
833 | } | |
834 | ||
835 | pdata = mci->pvt_info; | |
836 | pdata->name = "mpc85xx_mc_err"; | |
837 | pdata->irq = NO_IRQ; | |
838 | mci->dev = &op->dev; | |
839 | pdata->edac_idx = edac_mc_idx++; | |
840 | dev_set_drvdata(mci->dev, mci); | |
841 | mci->ctl_name = pdata->name; | |
842 | mci->dev_name = pdata->name; | |
843 | ||
844 | res = of_address_to_resource(op->node, 0, &r); | |
845 | if (res) { | |
846 | printk(KERN_ERR "%s: Unable to get resource for MC err regs\n", | |
847 | __func__); | |
848 | goto err; | |
849 | } | |
850 | ||
851 | if (!devm_request_mem_region(&op->dev, r.start, | |
852 | r.end - r.start + 1, pdata->name)) { | |
853 | printk(KERN_ERR "%s: Error while requesting mem region\n", | |
854 | __func__); | |
855 | res = -EBUSY; | |
856 | goto err; | |
857 | } | |
858 | ||
859 | pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); | |
860 | if (!pdata->mc_vbase) { | |
861 | printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); | |
862 | res = -ENOMEM; | |
863 | goto err; | |
864 | } | |
865 | ||
866 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); | |
867 | if (!(sdram_ctl & DSC_ECC_EN)) { | |
868 | /* no ECC */ | |
869 | printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); | |
870 | res = -ENODEV; | |
871 | goto err; | |
872 | } | |
873 | ||
874 | debugf3("%s(): init mci\n", __func__); | |
875 | mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | | |
876 | MEM_FLAG_DDR | MEM_FLAG_DDR2; | |
877 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
878 | mci->edac_cap = EDAC_FLAG_SECDED; | |
879 | mci->mod_name = EDAC_MOD_STR; | |
880 | mci->mod_ver = MPC85XX_REVISION; | |
881 | ||
882 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
883 | mci->edac_check = mpc85xx_mc_check; | |
884 | ||
885 | mci->ctl_page_to_phys = NULL; | |
886 | ||
887 | mci->scrub_mode = SCRUB_SW_SRC; | |
888 | ||
889 | mpc85xx_set_mc_sysfs_attributes(mci); | |
890 | ||
891 | mpc85xx_init_csrows(mci); | |
892 | ||
893 | #ifdef CONFIG_EDAC_DEBUG | |
894 | edac_mc_register_mcidev_debug((struct attribute **)debug_attr); | |
895 | #endif | |
896 | ||
897 | /* store the original error disable bits */ | |
898 | orig_ddr_err_disable = | |
899 | in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); | |
900 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); | |
901 | ||
902 | /* clear all error bits */ | |
903 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); | |
904 | ||
905 | if (edac_mc_add_mc(mci)) { | |
906 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); | |
907 | goto err; | |
908 | } | |
909 | ||
910 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
911 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, | |
912 | DDR_EIE_MBEE | DDR_EIE_SBEE); | |
913 | ||
914 | /* store the original error management threshold */ | |
915 | orig_ddr_err_sbe = in_be32(pdata->mc_vbase + | |
916 | MPC85XX_MC_ERR_SBE) & 0xff0000; | |
917 | ||
918 | /* set threshold to 1 error per interrupt */ | |
919 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); | |
920 | ||
921 | /* register interrupts */ | |
922 | pdata->irq = irq_of_parse_and_map(op->node, 0); | |
923 | res = devm_request_irq(&op->dev, pdata->irq, | |
60be7551 AK |
924 | mpc85xx_mc_isr, |
925 | IRQF_DISABLED | IRQF_SHARED, | |
a9a753d5 DJ |
926 | "[EDAC] MC err", mci); |
927 | if (res < 0) { | |
928 | printk(KERN_ERR "%s: Unable to request irq %d for " | |
929 | "MPC85xx DRAM ERR\n", __func__, pdata->irq); | |
930 | irq_dispose_mapping(pdata->irq); | |
931 | res = -ENODEV; | |
932 | goto err2; | |
933 | } | |
934 | ||
935 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n", | |
936 | pdata->irq); | |
937 | } | |
938 | ||
939 | devres_remove_group(&op->dev, mpc85xx_mc_err_probe); | |
940 | debugf3("%s(): success\n", __func__); | |
941 | printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); | |
942 | ||
943 | return 0; | |
944 | ||
945 | err2: | |
946 | edac_mc_del_mc(&op->dev); | |
947 | err: | |
948 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); | |
949 | edac_mc_free(mci); | |
950 | return res; | |
951 | } | |
952 | ||
953 | static int mpc85xx_mc_err_remove(struct of_device *op) | |
954 | { | |
955 | struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); | |
956 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
957 | ||
958 | debugf0("%s()\n", __func__); | |
959 | ||
960 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
961 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); | |
962 | irq_dispose_mapping(pdata->irq); | |
963 | } | |
964 | ||
965 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, | |
966 | orig_ddr_err_disable); | |
967 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); | |
968 | ||
969 | edac_mc_del_mc(&op->dev); | |
970 | edac_mc_free(mci); | |
971 | return 0; | |
972 | } | |
973 | ||
974 | static struct of_device_id mpc85xx_mc_err_of_match[] = { | |
29d6cf26 KG |
975 | /* deprecate the fsl,85.. forms in the future, 2.6.30? */ |
976 | { .compatible = "fsl,8540-memory-controller", }, | |
977 | { .compatible = "fsl,8541-memory-controller", }, | |
978 | { .compatible = "fsl,8544-memory-controller", }, | |
979 | { .compatible = "fsl,8548-memory-controller", }, | |
980 | { .compatible = "fsl,8555-memory-controller", }, | |
981 | { .compatible = "fsl,8568-memory-controller", }, | |
982 | { .compatible = "fsl,mpc8536-memory-controller", }, | |
983 | { .compatible = "fsl,mpc8540-memory-controller", }, | |
984 | { .compatible = "fsl,mpc8541-memory-controller", }, | |
985 | { .compatible = "fsl,mpc8544-memory-controller", }, | |
986 | { .compatible = "fsl,mpc8548-memory-controller", }, | |
987 | { .compatible = "fsl,mpc8555-memory-controller", }, | |
988 | { .compatible = "fsl,mpc8560-memory-controller", }, | |
989 | { .compatible = "fsl,mpc8568-memory-controller", }, | |
990 | { .compatible = "fsl,mpc8572-memory-controller", }, | |
b4846251 | 991 | { .compatible = "fsl,mpc8349-memory-controller", }, |
a014554e | 992 | { .compatible = "fsl,p2020-memory-controller", }, |
a9a753d5 DJ |
993 | {}, |
994 | }; | |
995 | ||
996 | static struct of_platform_driver mpc85xx_mc_err_driver = { | |
997 | .owner = THIS_MODULE, | |
998 | .name = "mpc85xx_mc_err", | |
999 | .match_table = mpc85xx_mc_err_of_match, | |
1000 | .probe = mpc85xx_mc_err_probe, | |
1001 | .remove = mpc85xx_mc_err_remove, | |
1002 | .driver = { | |
1003 | .name = "mpc85xx_mc_err", | |
1004 | .owner = THIS_MODULE, | |
1005 | }, | |
1006 | }; | |
1007 | ||
b4846251 | 1008 | #ifdef CONFIG_MPC85xx |
60be7551 AK |
1009 | static void __init mpc85xx_mc_clear_rfxe(void *data) |
1010 | { | |
1011 | orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); | |
1012 | mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000)); | |
1013 | } | |
b4846251 | 1014 | #endif |
60be7551 | 1015 | |
a9a753d5 DJ |
1016 | static int __init mpc85xx_mc_init(void) |
1017 | { | |
1018 | int res = 0; | |
1019 | ||
1020 | printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " | |
1021 | "(C) 2006 Montavista Software\n"); | |
1022 | ||
1023 | /* make sure error reporting method is sane */ | |
1024 | switch (edac_op_state) { | |
1025 | case EDAC_OPSTATE_POLL: | |
1026 | case EDAC_OPSTATE_INT: | |
1027 | break; | |
1028 | default: | |
1029 | edac_op_state = EDAC_OPSTATE_INT; | |
1030 | break; | |
1031 | } | |
1032 | ||
1033 | res = of_register_platform_driver(&mpc85xx_mc_err_driver); | |
1034 | if (res) | |
1035 | printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n"); | |
1036 | ||
1037 | res = of_register_platform_driver(&mpc85xx_l2_err_driver); | |
1038 | if (res) | |
1039 | printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); | |
1040 | ||
1041 | #ifdef CONFIG_PCI | |
f87bd330 | 1042 | res = of_register_platform_driver(&mpc85xx_pci_err_driver); |
a9a753d5 DJ |
1043 | if (res) |
1044 | printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n"); | |
1045 | #endif | |
1046 | ||
b4846251 | 1047 | #ifdef CONFIG_MPC85xx |
a9a753d5 DJ |
1048 | /* |
1049 | * need to clear HID1[RFXE] to disable machine check int | |
1050 | * so we can catch it | |
1051 | */ | |
60be7551 AK |
1052 | if (edac_op_state == EDAC_OPSTATE_INT) |
1053 | on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); | |
b4846251 | 1054 | #endif |
a9a753d5 DJ |
1055 | |
1056 | return 0; | |
1057 | } | |
1058 | ||
1059 | module_init(mpc85xx_mc_init); | |
1060 | ||
b4846251 | 1061 | #ifdef CONFIG_MPC85xx |
60be7551 AK |
1062 | static void __exit mpc85xx_mc_restore_hid1(void *data) |
1063 | { | |
1064 | mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]); | |
1065 | } | |
b4846251 | 1066 | #endif |
60be7551 | 1067 | |
a9a753d5 DJ |
1068 | static void __exit mpc85xx_mc_exit(void) |
1069 | { | |
b4846251 | 1070 | #ifdef CONFIG_MPC85xx |
60be7551 | 1071 | on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); |
b4846251 | 1072 | #endif |
a9a753d5 | 1073 | #ifdef CONFIG_PCI |
f87bd330 | 1074 | of_unregister_platform_driver(&mpc85xx_pci_err_driver); |
a9a753d5 DJ |
1075 | #endif |
1076 | of_unregister_platform_driver(&mpc85xx_l2_err_driver); | |
1077 | of_unregister_platform_driver(&mpc85xx_mc_err_driver); | |
1078 | } | |
1079 | ||
1080 | module_exit(mpc85xx_mc_exit); | |
1081 | ||
1082 | MODULE_LICENSE("GPL"); | |
1083 | MODULE_AUTHOR("Montavista Software, Inc."); | |
1084 | module_param(edac_op_state, int, 0444); | |
1085 | MODULE_PARM_DESC(edac_op_state, | |
1086 | "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); |