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Merge branch 'topic/hda' into for-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / mpc85xx_edac.c
CommitLineData
a9a753d5
DJ		 1/*
2 * Freescale MPC85xx Memory Controller kenel module
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12#include <linux/module.h>
13#include <linux/init.h>
a9a753d5
DJ		 14#include <linux/interrupt.h>
15#include <linux/ctype.h>
16#include <linux/io.h>
17#include <linux/mod_devicetable.h>
18#include <linux/edac.h>
60be7551 19#include <linux/smp.h>
5a0e3ad6 20#include <linux/gfp.h>
a9a753d5
DJ		 21
22#include <linux/of_platform.h>
23#include <linux/of_device.h>
a9a753d5
DJ		 24#include "edac_module.h"
25#include "edac_core.h"
26#include "mpc85xx_edac.h"
27
28static int edac_dev_idx;
0616fb00 29#ifdef CONFIG_PCI
a9a753d5 30static int edac_pci_idx;
0616fb00 31#endif
a9a753d5
DJ		 32static int edac_mc_idx;
33
34static u32 orig_ddr_err_disable;
35static u32 orig_ddr_err_sbe;
36
37/*
38 * PCI Err defines
39 */
40#ifdef CONFIG_PCI
41static u32 orig_pci_err_cap_dr;
42static u32 orig_pci_err_en;
43#endif
44
45static u32 orig_l2_err_disable;
b4846251 46#ifdef CONFIG_MPC85xx
60be7551 47static u32 orig_hid1[2];
b4846251 48#endif
a9a753d5 49
a9a753d5
DJ		 50/************************ MC SYSFS parts ***********************************/
51
52static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci,
53 char *data)
54{
55 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
56 return sprintf(data, "0x%08x",
57 in_be32(pdata->mc_vbase +
58 MPC85XX_MC_DATA_ERR_INJECT_HI));
59}
60
61static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci,
62 char *data)
63{
64 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
65 return sprintf(data, "0x%08x",
66 in_be32(pdata->mc_vbase +
67 MPC85XX_MC_DATA_ERR_INJECT_LO));
68}
69
70static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data)
71{
72 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
73 return sprintf(data, "0x%08x",
74 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
75}
76
77static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci,
78 const char *data, size_t count)
79{
80 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
81 if (isdigit(*data)) {
82 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
83 simple_strtoul(data, NULL, 0));
84 return count;
85 }
86 return 0;
87}
88
89static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci,
90 const char *data, size_t count)
91{
92 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
93 if (isdigit(*data)) {
94 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
95 simple_strtoul(data, NULL, 0));
96 return count;
97 }
98 return 0;
99}
100
101static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci,
102 const char *data, size_t count)
103{
104 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
105 if (isdigit(*data)) {
106 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
107 simple_strtoul(data, NULL, 0));
108 return count;
109 }
110 return 0;
111}
112
113static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = {
114 {
115 .attr = {
116 .name = "inject_data_hi",
117 .mode = (S_IRUGO | S_IWUSR)
118 },
119 .show = mpc85xx_mc_inject_data_hi_show,
120 .store = mpc85xx_mc_inject_data_hi_store},
121 {
122 .attr = {
123 .name = "inject_data_lo",
124 .mode = (S_IRUGO | S_IWUSR)
125 },
126 .show = mpc85xx_mc_inject_data_lo_show,
127 .store = mpc85xx_mc_inject_data_lo_store},
128 {
129 .attr = {
130 .name = "inject_ctrl",
131 .mode = (S_IRUGO | S_IWUSR)
132 },
133 .show = mpc85xx_mc_inject_ctrl_show,
134 .store = mpc85xx_mc_inject_ctrl_store},
135
136 /* End of list */
137 {
138 .attr = {.name = NULL}
139 }
140};
141
142static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
143{
144 mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes;
145}
146
147/**************************** PCI Err device ***************************/
148#ifdef CONFIG_PCI
149
150static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
151{
152 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
153 u32 err_detect;
154
155 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
156
157 /* master aborts can happen during PCI config cycles */
158 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
159 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
160 return;
161 }
162
163 printk(KERN_ERR "PCI error(s) detected\n");
164 printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
165
166 printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
167 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
168 printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
169 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
170 printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
171 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
172 printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
173 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
174 printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
175 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
176
177 /* clear error bits */
178 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
179
180 if (err_detect & PCI_EDE_PERR_MASK)
181 edac_pci_handle_pe(pci, pci->ctl_name);
182
183 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
184 edac_pci_handle_npe(pci, pci->ctl_name);
185}
186
187static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
188{
189 struct edac_pci_ctl_info *pci = dev_id;
190 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
191 u32 err_detect;
192
193 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
194
195 if (!err_detect)
196 return IRQ_NONE;
197
198 mpc85xx_pci_check(pci);
199
200 return IRQ_HANDLED;
201}
202
f87bd330
DJ		 203static int __devinit mpc85xx_pci_err_probe(struct of_device *op,
204 const struct of_device_id *match)
a9a753d5
DJ		 205{
206 struct edac_pci_ctl_info *pci;
207 struct mpc85xx_pci_pdata *pdata;
f87bd330 208 struct resource r;
a9a753d5
DJ		 209 int res = 0;
210
f87bd330 211 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
a9a753d5
DJ		 212 return -ENOMEM;
213
214 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
215 if (!pci)
216 return -ENOMEM;
217
218 pdata = pci->pvt_info;
219 pdata->name = "mpc85xx_pci_err";
220 pdata->irq = NO_IRQ;
f87bd330
DJ		 221 dev_set_drvdata(&op->dev, pci);
222 pci->dev = &op->dev;
a9a753d5
DJ		 223 pci->mod_name = EDAC_MOD_STR;
224 pci->ctl_name = pdata->name;
031d5518 225 pci->dev_name = dev_name(&op->dev);
a9a753d5
DJ		 226
227 if (edac_op_state == EDAC_OPSTATE_POLL)
228 pci->edac_check = mpc85xx_pci_check;
229
230 pdata->edac_idx = edac_pci_idx++;
231
f87bd330
DJ		 232 res = of_address_to_resource(op->node, 0, &r);
233 if (res) {
a9a753d5
DJ		 234 printk(KERN_ERR "%s: Unable to get resource for "
235 "PCI err regs\n", __func__);
236 goto err;
237 }
238
f87bd330
DJ		 239 /* we only need the error registers */
240 r.start += 0xe00;
241
66ed3f75
HS		 242 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
243 pdata->name)) {
a9a753d5
DJ		 244 printk(KERN_ERR "%s: Error while requesting mem region\n",
245 __func__);
246 res = -EBUSY;
247 goto err;
248 }
249
66ed3f75 250 pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
a9a753d5
DJ		 251 if (!pdata->pci_vbase) {
252 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
253 res = -ENOMEM;
254 goto err;
255 }
256
257 orig_pci_err_cap_dr =
258 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
259
260 /* PCI master abort is expected during config cycles */
261 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
262
263 orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
264
265 /* disable master abort reporting */
266 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
267
268 /* clear error bits */
269 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
270
271 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
272 debugf3("%s(): failed edac_pci_add_device()\n", __func__);
273 goto err;
274 }
275
276 if (edac_op_state == EDAC_OPSTATE_INT) {
f87bd330
DJ		 277 pdata->irq = irq_of_parse_and_map(op->node, 0);
278 res = devm_request_irq(&op->dev, pdata->irq,
a9a753d5
DJ		 279 mpc85xx_pci_isr, IRQF_DISABLED,
280 "[EDAC] PCI err", pci);
281 if (res < 0) {
282 printk(KERN_ERR
283 "%s: Unable to requiest irq %d for "
284 "MPC85xx PCI err\n", __func__, pdata->irq);
f87bd330 285 irq_dispose_mapping(pdata->irq);
a9a753d5
DJ		 286 res = -ENODEV;
287 goto err2;
288 }
289
290 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
291 pdata->irq);
292 }
293
f87bd330 294 devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
a9a753d5
DJ		 295 debugf3("%s(): success\n", __func__);
296 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
297
298 return 0;
299
300err2:
f87bd330 301 edac_pci_del_device(&op->dev);
a9a753d5
DJ		 302err:
303 edac_pci_free_ctl_info(pci);
f87bd330 304 devres_release_group(&op->dev, mpc85xx_pci_err_probe);
a9a753d5
DJ		 305 return res;
306}
307
f87bd330 308static int mpc85xx_pci_err_remove(struct of_device *op)
a9a753d5 309{
f87bd330 310 struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
a9a753d5
DJ		 311 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
312
313 debugf0("%s()\n", __func__);
314
315 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
316 orig_pci_err_cap_dr);
317
318 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
319
320 edac_pci_del_device(pci->dev);
321
322 if (edac_op_state == EDAC_OPSTATE_INT)
323 irq_dispose_mapping(pdata->irq);
324
325 edac_pci_free_ctl_info(pci);
326
327 return 0;
328}
329
f87bd330
DJ		 330static struct of_device_id mpc85xx_pci_err_of_match[] = {
331 {
332 .compatible = "fsl,mpc8540-pcix",
333 },
334 {
335 .compatible = "fsl,mpc8540-pci",
336 },
337 {},
338};
339
340static struct of_platform_driver mpc85xx_pci_err_driver = {
341 .owner = THIS_MODULE,
342 .name = "mpc85xx_pci_err",
343 .match_table = mpc85xx_pci_err_of_match,
a9a753d5
DJ		 344 .probe = mpc85xx_pci_err_probe,
345 .remove = __devexit_p(mpc85xx_pci_err_remove),
346 .driver = {
f87bd330
DJ		 347 .name = "mpc85xx_pci_err",
348 .owner = THIS_MODULE,
349 },
a9a753d5
DJ		 350};
351
352#endif /* CONFIG_PCI */
353
354/**************************** L2 Err device ***************************/
355
356/************************ L2 SYSFS parts ***********************************/
357
358static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
359 *edac_dev, char *data)
360{
361 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
362 return sprintf(data, "0x%08x",
363 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
364}
365
366static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
367 *edac_dev, char *data)
368{
369 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
370 return sprintf(data, "0x%08x",
371 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
372}
373
374static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
375 *edac_dev, char *data)
376{
377 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
378 return sprintf(data, "0x%08x",
379 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
380}
381
382static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
383 *edac_dev, const char *data,
384 size_t count)
385{
386 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
387 if (isdigit(*data)) {
388 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
389 simple_strtoul(data, NULL, 0));
390 return count;
391 }
392 return 0;
393}
394
395static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
396 *edac_dev, const char *data,
397 size_t count)
398{
399 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
400 if (isdigit(*data)) {
401 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
402 simple_strtoul(data, NULL, 0));
403 return count;
404 }
405 return 0;
406}
407
408static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
409 *edac_dev, const char *data,
410 size_t count)
411{
412 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
413 if (isdigit(*data)) {
414 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
415 simple_strtoul(data, NULL, 0));
416 return count;
417 }
418 return 0;
419}
420
421static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
422 {
423 .attr = {
424 .name = "inject_data_hi",
425 .mode = (S_IRUGO | S_IWUSR)
426 },
427 .show = mpc85xx_l2_inject_data_hi_show,
428 .store = mpc85xx_l2_inject_data_hi_store},
429 {
430 .attr = {
431 .name = "inject_data_lo",
432 .mode = (S_IRUGO | S_IWUSR)
433 },
434 .show = mpc85xx_l2_inject_data_lo_show,
435 .store = mpc85xx_l2_inject_data_lo_store},
436 {
437 .attr = {
438 .name = "inject_ctrl",
439 .mode = (S_IRUGO | S_IWUSR)
440 },
441 .show = mpc85xx_l2_inject_ctrl_show,
442 .store = mpc85xx_l2_inject_ctrl_store},
443
444 /* End of list */
445 {
446 .attr = {.name = NULL}
447 }
448};
449
450static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
451 *edac_dev)
452{
453 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
454}
455
456/***************************** L2 ops ***********************************/
457
458static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
459{
460 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
461 u32 err_detect;
462
463 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
464
465 if (!(err_detect & L2_EDE_MASK))
466 return;
467
468 printk(KERN_ERR "ECC Error in CPU L2 cache\n");
469 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
470 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
471 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
472 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
473 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
474 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
475 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
476 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
477 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
478 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
479 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
480
481 /* clear error detect register */
482 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
483
484 if (err_detect & L2_EDE_CE_MASK)
485 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
486
487 if (err_detect & L2_EDE_UE_MASK)
488 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
489}
490
491static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
492{
493 struct edac_device_ctl_info *edac_dev = dev_id;
494 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
495 u32 err_detect;
496
497 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
498
499 if (!(err_detect & L2_EDE_MASK))
500 return IRQ_NONE;
501
502 mpc85xx_l2_check(edac_dev);
503
504 return IRQ_HANDLED;
505}
506
507static int __devinit mpc85xx_l2_err_probe(struct of_device *op,
508 const struct of_device_id *match)
509{
510 struct edac_device_ctl_info *edac_dev;
511 struct mpc85xx_l2_pdata *pdata;
512 struct resource r;
513 int res;
514
515 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
516 return -ENOMEM;
517
518 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
519 "cpu", 1, "L", 1, 2, NULL, 0,
520 edac_dev_idx);
521 if (!edac_dev) {
522 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
523 return -ENOMEM;
524 }
525
526 pdata = edac_dev->pvt_info;
527 pdata->name = "mpc85xx_l2_err";
528 pdata->irq = NO_IRQ;
529 edac_dev->dev = &op->dev;
530 dev_set_drvdata(edac_dev->dev, edac_dev);
531 edac_dev->ctl_name = pdata->name;
532 edac_dev->dev_name = pdata->name;
533
534 res = of_address_to_resource(op->node, 0, &r);
535 if (res) {
536 printk(KERN_ERR "%s: Unable to get resource for "
537 "L2 err regs\n", __func__);
538 goto err;
539 }
540
541 /* we only need the error registers */
542 r.start += 0xe00;
543
544 if (!devm_request_mem_region(&op->dev, r.start,
545 r.end - r.start + 1, pdata->name)) {
546 printk(KERN_ERR "%s: Error while requesting mem region\n",
547 __func__);
548 res = -EBUSY;
549 goto err;
550 }
551
552 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
553 if (!pdata->l2_vbase) {
554 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
555 res = -ENOMEM;
556 goto err;
557 }
558
559 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
560
561 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
562
563 /* clear the err_dis */
564 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
565
566 edac_dev->mod_name = EDAC_MOD_STR;
567
568 if (edac_op_state == EDAC_OPSTATE_POLL)
569 edac_dev->edac_check = mpc85xx_l2_check;
570
571 mpc85xx_set_l2_sysfs_attributes(edac_dev);
572
573 pdata->edac_idx = edac_dev_idx++;
574
575 if (edac_device_add_device(edac_dev) > 0) {
576 debugf3("%s(): failed edac_device_add_device()\n", __func__);
577 goto err;
578 }
579
580 if (edac_op_state == EDAC_OPSTATE_INT) {
581 pdata->irq = irq_of_parse_and_map(op->node, 0);
582 res = devm_request_irq(&op->dev, pdata->irq,
583 mpc85xx_l2_isr, IRQF_DISABLED,
584 "[EDAC] L2 err", edac_dev);
585 if (res < 0) {
586 printk(KERN_ERR
587 "%s: Unable to requiest irq %d for "
588 "MPC85xx L2 err\n", __func__, pdata->irq);
589 irq_dispose_mapping(pdata->irq);
590 res = -ENODEV;
591 goto err2;
592 }
593
594 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
595 pdata->irq);
596
597 edac_dev->op_state = OP_RUNNING_INTERRUPT;
598
599 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
600 }
601
602 devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
603
604 debugf3("%s(): success\n", __func__);
605 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
606
607 return 0;
608
609err2:
610 edac_device_del_device(&op->dev);
611err:
612 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
613 edac_device_free_ctl_info(edac_dev);
614 return res;
615}
616
617static int mpc85xx_l2_err_remove(struct of_device *op)
618{
619 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
620 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
621
622 debugf0("%s()\n", __func__);
623
624 if (edac_op_state == EDAC_OPSTATE_INT) {
625 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
626 irq_dispose_mapping(pdata->irq);
627 }
628
629 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
630 edac_device_del_device(&op->dev);
631 edac_device_free_ctl_info(edac_dev);
632 return 0;
633}
634
635static struct of_device_id mpc85xx_l2_err_of_match[] = {
29d6cf26
KG		 636/* deprecate the fsl,85.. forms in the future, 2.6.30? */
637 { .compatible = "fsl,8540-l2-cache-controller", },
638 { .compatible = "fsl,8541-l2-cache-controller", },
639 { .compatible = "fsl,8544-l2-cache-controller", },
640 { .compatible = "fsl,8548-l2-cache-controller", },
641 { .compatible = "fsl,8555-l2-cache-controller", },
642 { .compatible = "fsl,8568-l2-cache-controller", },
643 { .compatible = "fsl,mpc8536-l2-cache-controller", },
644 { .compatible = "fsl,mpc8540-l2-cache-controller", },
645 { .compatible = "fsl,mpc8541-l2-cache-controller", },
646 { .compatible = "fsl,mpc8544-l2-cache-controller", },
647 { .compatible = "fsl,mpc8548-l2-cache-controller", },
648 { .compatible = "fsl,mpc8555-l2-cache-controller", },
649 { .compatible = "fsl,mpc8560-l2-cache-controller", },
650 { .compatible = "fsl,mpc8568-l2-cache-controller", },
651 { .compatible = "fsl,mpc8572-l2-cache-controller", },
a014554e 652 { .compatible = "fsl,p2020-l2-cache-controller", },
a9a753d5
DJ		 653 {},
654};
655
656static struct of_platform_driver mpc85xx_l2_err_driver = {
657 .owner = THIS_MODULE,
658 .name = "mpc85xx_l2_err",
659 .match_table = mpc85xx_l2_err_of_match,
660 .probe = mpc85xx_l2_err_probe,
661 .remove = mpc85xx_l2_err_remove,
662 .driver = {
663 .name = "mpc85xx_l2_err",
664 .owner = THIS_MODULE,
665 },
666};
667
668/**************************** MC Err device ***************************/
669
dcca7c3d
PT		 670/*
671 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
672 * MPC8572 User's Manual. Each line represents a syndrome bit column as a
673 * 64-bit value, but split into an upper and lower 32-bit chunk. The labels
674 * below correspond to Freescale's manuals.
675 */
676static unsigned int ecc_table[16] = {
677 /* MSB LSB */
678 /* [0:31] [32:63] */
679 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
680 0x00ff00ff, 0x00fff0ff,
681 0x0f0f0f0f, 0x0f0fff00,
682 0x11113333, 0x7777000f,
683 0x22224444, 0x8888222f,
684 0x44448888, 0xffff4441,
685 0x8888ffff, 0x11118882,
686 0xffff1111, 0x22221114, /* Syndrome bit 0 */
687};
688
689/*
690 * Calculate the correct ECC value for a 64-bit value specified by high:low
691 */
692static u8 calculate_ecc(u32 high, u32 low)
693{
694 u32 mask_low;
695 u32 mask_high;
696 int bit_cnt;
697 u8 ecc = 0;
698 int i;
699 int j;
700
701 for (i = 0; i < 8; i++) {
702 mask_high = ecc_table[i * 2];
703 mask_low = ecc_table[i * 2 + 1];
704 bit_cnt = 0;
705
706 for (j = 0; j < 32; j++) {
707 if ((mask_high >> j) & 1)
708 bit_cnt ^= (high >> j) & 1;
709 if ((mask_low >> j) & 1)
710 bit_cnt ^= (low >> j) & 1;
711 }
712
713 ecc |= bit_cnt << i;
714 }
715
716 return ecc;
717}
718
719/*
720 * Create the syndrome code which is generated if the data line specified by
721 * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
722 * User's Manual and 9-61 in the MPC8572 User's Manual.
723 */
724static u8 syndrome_from_bit(unsigned int bit) {
725 int i;
726 u8 syndrome = 0;
727
728 /*
729 * Cycle through the upper or lower 32-bit portion of each value in
730 * ecc_table depending on if 'bit' is in the upper or lower half of
731 * 64-bit data.
732 */
733 for (i = bit < 32; i < 16; i += 2)
734 syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
735
736 return syndrome;
737}
738
739/*
740 * Decode data and ecc syndrome to determine what went wrong
741 * Note: This can only decode single-bit errors
742 */
743static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
744 int *bad_data_bit, int *bad_ecc_bit)
745{
746 int i;
747 u8 syndrome;
748
749 *bad_data_bit = -1;
750 *bad_ecc_bit = -1;
751
752 /*
753 * Calculate the ECC of the captured data and XOR it with the captured
754 * ECC to find an ECC syndrome value we can search for
755 */
756 syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
757
758 /* Check if a data line is stuck... */
759 for (i = 0; i < 64; i++) {
760 if (syndrome == syndrome_from_bit(i)) {
761 *bad_data_bit = i;
762 return;
763 }
764 }
765
766 /* If data is correct, check ECC bits for errors... */
767 for (i = 0; i < 8; i++) {
768 if ((syndrome >> i) & 0x1) {
769 *bad_ecc_bit = i;
770 return;
771 }
772 }
773}
774
a9a753d5
DJ		 775static void mpc85xx_mc_check(struct mem_ctl_info *mci)
776{
777 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
778 struct csrow_info *csrow;
21768639 779 u32 bus_width;
a9a753d5
DJ		 780 u32 err_detect;
781 u32 syndrome;
782 u32 err_addr;
783 u32 pfn;
784 int row_index;
dcca7c3d
PT		 785 u32 cap_high;
786 u32 cap_low;
787 int bad_data_bit;
788 int bad_ecc_bit;
a9a753d5
DJ		 789
790 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
55e5750b 791 if (!err_detect)
a9a753d5
DJ		 792 return;
793
794 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
795 err_detect);
796
797 /* no more processing if not ECC bit errors */
798 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
799 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
800 return;
801 }
802
803 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
21768639
PT		 804
805 /* Mask off appropriate bits of syndrome based on bus width */
806 bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) &
807 DSC_DBW_MASK) ? 32 : 64;
808 if (bus_width == 64)
809 syndrome &= 0xff;
810 else
811 syndrome &= 0xffff;
812
a9a753d5
DJ		 813 err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS);
814 pfn = err_addr >> PAGE_SHIFT;
815
816 for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
817 csrow = &mci->csrows[row_index];
818 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
819 break;
820 }
821
dcca7c3d
PT		 822 cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI);
823 cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO);
824
825 /*
826 * Analyze single-bit errors on 64-bit wide buses
827 * TODO: Add support for 32-bit wide buses
828 */
829 if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
830 sbe_ecc_decode(cap_high, cap_low, syndrome,
831 &bad_data_bit, &bad_ecc_bit);
832
833 if (bad_data_bit != -1)
834 mpc85xx_mc_printk(mci, KERN_ERR,
835 "Faulty Data bit: %d\n", bad_data_bit);
836 if (bad_ecc_bit != -1)
837 mpc85xx_mc_printk(mci, KERN_ERR,
838 "Faulty ECC bit: %d\n", bad_ecc_bit);
839
840 mpc85xx_mc_printk(mci, KERN_ERR,
841 "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
842 cap_high ^ (1 << (bad_data_bit - 32)),
843 cap_low ^ (1 << bad_data_bit),
844 syndrome ^ (1 << bad_ecc_bit));
845 }
846
847 mpc85xx_mc_printk(mci, KERN_ERR,
848 "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
849 cap_high, cap_low, syndrome);
850 mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x\n", err_addr);
a9a753d5
DJ		 851 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
852
853 /* we are out of range */
854 if (row_index == mci->nr_csrows)
855 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
856
857 if (err_detect & DDR_EDE_SBE)
858 edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK,
859 syndrome, row_index, 0, mci->ctl_name);
860
861 if (err_detect & DDR_EDE_MBE)
862 edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK,
863 row_index, mci->ctl_name);
864
865 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
866}
867
868static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
869{
870 struct mem_ctl_info *mci = dev_id;
871 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
872 u32 err_detect;
873
874 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
875 if (!err_detect)
876 return IRQ_NONE;
877
878 mpc85xx_mc_check(mci);
879
880 return IRQ_HANDLED;
881}
882
883static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
884{
885 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
886 struct csrow_info *csrow;
887 u32 sdram_ctl;
888 u32 sdtype;
889 enum mem_type mtype;
890 u32 cs_bnds;
891 int index;
892
893 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
894
895 sdtype = sdram_ctl & DSC_SDTYPE_MASK;
896 if (sdram_ctl & DSC_RD_EN) {
897 switch (sdtype) {
898 case DSC_SDTYPE_DDR:
899 mtype = MEM_RDDR;
900 break;
901 case DSC_SDTYPE_DDR2:
902 mtype = MEM_RDDR2;
903 break;
b1cfebc9
YS		 904 case DSC_SDTYPE_DDR3:
905 mtype = MEM_RDDR3;
906 break;
a9a753d5
DJ		 907 default:
908 mtype = MEM_UNKNOWN;
909 break;
910 }
911 } else {
912 switch (sdtype) {
913 case DSC_SDTYPE_DDR:
914 mtype = MEM_DDR;
915 break;
916 case DSC_SDTYPE_DDR2:
917 mtype = MEM_DDR2;
918 break;
b1cfebc9
YS		 919 case DSC_SDTYPE_DDR3:
920 mtype = MEM_DDR3;
921 break;
a9a753d5
DJ		 922 default:
923 mtype = MEM_UNKNOWN;
924 break;
925 }
926 }
927
928 for (index = 0; index < mci->nr_csrows; index++) {
929 u32 start;
930 u32 end;
931
932 csrow = &mci->csrows[index];
933 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
934 (index * MPC85XX_MC_CS_BNDS_OFS));
b4846251
IS		 935
936 start = (cs_bnds & 0xffff0000) >> 16;
937 end = (cs_bnds & 0x0000ffff);
a9a753d5
DJ		 938
939 if (start == end)
940 continue; /* not populated */
941
b4846251
IS		 942 start <<= (24 - PAGE_SHIFT);
943 end <<= (24 - PAGE_SHIFT);
944 end |= (1 << (24 - PAGE_SHIFT)) - 1;
945
cff9279e
PT		 946 csrow->first_page = start;
947 csrow->last_page = end;
b4846251 948 csrow->nr_pages = end + 1 - start;
a9a753d5
DJ		 949 csrow->grain = 8;
950 csrow->mtype = mtype;
951 csrow->dtype = DEV_UNKNOWN;
952 if (sdram_ctl & DSC_X32_EN)
953 csrow->dtype = DEV_X32;
954 csrow->edac_mode = EDAC_SECDED;
955 }
956}
957
958static int __devinit mpc85xx_mc_err_probe(struct of_device *op,
959 const struct of_device_id *match)
960{
961 struct mem_ctl_info *mci;
962 struct mpc85xx_mc_pdata *pdata;
963 struct resource r;
964 u32 sdram_ctl;
965 int res;
966
967 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
968 return -ENOMEM;
969
970 mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx);
971 if (!mci) {
972 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
973 return -ENOMEM;
974 }
975
976 pdata = mci->pvt_info;
977 pdata->name = "mpc85xx_mc_err";
978 pdata->irq = NO_IRQ;
979 mci->dev = &op->dev;
980 pdata->edac_idx = edac_mc_idx++;
981 dev_set_drvdata(mci->dev, mci);
982 mci->ctl_name = pdata->name;
983 mci->dev_name = pdata->name;
984
985 res = of_address_to_resource(op->node, 0, &r);
986 if (res) {
987 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
988 __func__);
989 goto err;
990 }
991
992 if (!devm_request_mem_region(&op->dev, r.start,
993 r.end - r.start + 1, pdata->name)) {
994 printk(KERN_ERR "%s: Error while requesting mem region\n",
995 __func__);
996 res = -EBUSY;
997 goto err;
998 }
999
1000 pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
1001 if (!pdata->mc_vbase) {
1002 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
1003 res = -ENOMEM;
1004 goto err;
1005 }
1006
1007 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
1008 if (!(sdram_ctl & DSC_ECC_EN)) {
1009 /* no ECC */
1010 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
1011 res = -ENODEV;
1012 goto err;
1013 }
1014
1015 debugf3("%s(): init mci\n", __func__);
1016 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
1017 MEM_FLAG_DDR | MEM_FLAG_DDR2;
1018 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
1019 mci->edac_cap = EDAC_FLAG_SECDED;
1020 mci->mod_name = EDAC_MOD_STR;
1021 mci->mod_ver = MPC85XX_REVISION;
1022
1023 if (edac_op_state == EDAC_OPSTATE_POLL)
1024 mci->edac_check = mpc85xx_mc_check;
1025
1026 mci->ctl_page_to_phys = NULL;
1027
1028 mci->scrub_mode = SCRUB_SW_SRC;
1029
1030 mpc85xx_set_mc_sysfs_attributes(mci);
1031
1032 mpc85xx_init_csrows(mci);
1033
a9a753d5
DJ		 1034 /* store the original error disable bits */
1035 orig_ddr_err_disable =
1036 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
1037 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
1038
1039 /* clear all error bits */
1040 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
1041
1042 if (edac_mc_add_mc(mci)) {
1043 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
1044 goto err;
1045 }
1046
1047 if (edac_op_state == EDAC_OPSTATE_INT) {
1048 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
1049 DDR_EIE_MBEE | DDR_EIE_SBEE);
1050
1051 /* store the original error management threshold */
1052 orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
1053 MPC85XX_MC_ERR_SBE) & 0xff0000;
1054
1055 /* set threshold to 1 error per interrupt */
1056 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
1057
1058 /* register interrupts */
1059 pdata->irq = irq_of_parse_and_map(op->node, 0);
1060 res = devm_request_irq(&op->dev, pdata->irq,
60be7551
AK		 1061 mpc85xx_mc_isr,
1062 IRQF_DISABLED | IRQF_SHARED,
a9a753d5
DJ		 1063 "[EDAC] MC err", mci);
1064 if (res < 0) {
1065 printk(KERN_ERR "%s: Unable to request irq %d for "
1066 "MPC85xx DRAM ERR\n", __func__, pdata->irq);
1067 irq_dispose_mapping(pdata->irq);
1068 res = -ENODEV;
1069 goto err2;
1070 }
1071
1072 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
1073 pdata->irq);
1074 }
1075
1076 devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
1077 debugf3("%s(): success\n", __func__);
1078 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
1079
1080 return 0;
1081
1082err2:
1083 edac_mc_del_mc(&op->dev);
1084err:
1085 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
1086 edac_mc_free(mci);
1087 return res;
1088}
1089
1090static int mpc85xx_mc_err_remove(struct of_device *op)
1091{
1092 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1093 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
1094
1095 debugf0("%s()\n", __func__);
1096
1097 if (edac_op_state == EDAC_OPSTATE_INT) {
1098 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
1099 irq_dispose_mapping(pdata->irq);
1100 }
1101
1102 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
1103 orig_ddr_err_disable);
1104 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
1105
1106 edac_mc_del_mc(&op->dev);
1107 edac_mc_free(mci);
1108 return 0;
1109}
1110
1111static struct of_device_id mpc85xx_mc_err_of_match[] = {
29d6cf26
KG		 1112/* deprecate the fsl,85.. forms in the future, 2.6.30? */
1113 { .compatible = "fsl,8540-memory-controller", },
1114 { .compatible = "fsl,8541-memory-controller", },
1115 { .compatible = "fsl,8544-memory-controller", },
1116 { .compatible = "fsl,8548-memory-controller", },
1117 { .compatible = "fsl,8555-memory-controller", },
1118 { .compatible = "fsl,8568-memory-controller", },
1119 { .compatible = "fsl,mpc8536-memory-controller", },
1120 { .compatible = "fsl,mpc8540-memory-controller", },
1121 { .compatible = "fsl,mpc8541-memory-controller", },
1122 { .compatible = "fsl,mpc8544-memory-controller", },
1123 { .compatible = "fsl,mpc8548-memory-controller", },
1124 { .compatible = "fsl,mpc8555-memory-controller", },
1125 { .compatible = "fsl,mpc8560-memory-controller", },
1126 { .compatible = "fsl,mpc8568-memory-controller", },
1127 { .compatible = "fsl,mpc8572-memory-controller", },
b4846251 1128 { .compatible = "fsl,mpc8349-memory-controller", },
a014554e 1129 { .compatible = "fsl,p2020-memory-controller", },
a9a753d5
DJ		 1130 {},
1131};
1132
1133static struct of_platform_driver mpc85xx_mc_err_driver = {
1134 .owner = THIS_MODULE,
1135 .name = "mpc85xx_mc_err",
1136 .match_table = mpc85xx_mc_err_of_match,
1137 .probe = mpc85xx_mc_err_probe,
1138 .remove = mpc85xx_mc_err_remove,
1139 .driver = {
1140 .name = "mpc85xx_mc_err",
1141 .owner = THIS_MODULE,
1142 },
1143};
1144
b4846251 1145#ifdef CONFIG_MPC85xx
60be7551
AK		 1146static void __init mpc85xx_mc_clear_rfxe(void *data)
1147{
1148 orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
1149 mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
1150}
b4846251 1151#endif
60be7551 1152
a9a753d5
DJ		 1153static int __init mpc85xx_mc_init(void)
1154{
1155 int res = 0;
1156
1157 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
1158 "(C) 2006 Montavista Software\n");
1159
1160 /* make sure error reporting method is sane */
1161 switch (edac_op_state) {
1162 case EDAC_OPSTATE_POLL:
1163 case EDAC_OPSTATE_INT:
1164 break;
1165 default:
1166 edac_op_state = EDAC_OPSTATE_INT;
1167 break;
1168 }
1169
1170 res = of_register_platform_driver(&mpc85xx_mc_err_driver);
1171 if (res)
1172 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
1173
1174 res = of_register_platform_driver(&mpc85xx_l2_err_driver);
1175 if (res)
1176 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
1177
1178#ifdef CONFIG_PCI
f87bd330 1179 res = of_register_platform_driver(&mpc85xx_pci_err_driver);
a9a753d5
DJ		 1180 if (res)
1181 printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
1182#endif
1183
b4846251 1184#ifdef CONFIG_MPC85xx
a9a753d5
DJ		 1185 /*
1186 * need to clear HID1[RFXE] to disable machine check int
1187 * so we can catch it
1188 */
60be7551
AK		 1189 if (edac_op_state == EDAC_OPSTATE_INT)
1190 on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
b4846251 1191#endif
a9a753d5
DJ		 1192
1193 return 0;
1194}
1195
1196module_init(mpc85xx_mc_init);
1197
b4846251 1198#ifdef CONFIG_MPC85xx
60be7551
AK		 1199static void __exit mpc85xx_mc_restore_hid1(void *data)
1200{
1201 mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
1202}
b4846251 1203#endif
60be7551 1204
a9a753d5
DJ		 1205static void __exit mpc85xx_mc_exit(void)
1206{
b4846251 1207#ifdef CONFIG_MPC85xx
60be7551 1208 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
b4846251 1209#endif
a9a753d5 1210#ifdef CONFIG_PCI
f87bd330 1211 of_unregister_platform_driver(&mpc85xx_pci_err_driver);
a9a753d5
DJ		 1212#endif
1213 of_unregister_platform_driver(&mpc85xx_l2_err_driver);
1214 of_unregister_platform_driver(&mpc85xx_mc_err_driver);
1215}
1216
1217module_exit(mpc85xx_mc_exit);
1218
1219MODULE_LICENSE("GPL");
1220MODULE_AUTHOR("Montavista Software, Inc.");
1221module_param(edac_op_state, int, 0444);
1222MODULE_PARM_DESC(edac_op_state,
1223 "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
kernel source for telekom puls (alcatel/mediatek)