[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / i82860_edac.c

/*
 * Intel 82860 Memory Controller kernel module
 * (C) 2005 Red Hat (http://www.redhat.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Ben Woodard <woodard@redhat.com>
 * shamelessly copied from and based upon the edac_i82875 driver
 * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
 */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include "edac_mc.h"

#define  I82860_REVISION " Ver: 2.0.0 " __DATE__

#define i82860_printk(level, fmt, arg...) \
	edac_printk(level, "i82860", fmt, ##arg)

#define i82860_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)

#ifndef PCI_DEVICE_ID_INTEL_82860_0
#define PCI_DEVICE_ID_INTEL_82860_0	0x2531
#endif				/* PCI_DEVICE_ID_INTEL_82860_0 */

#define I82860_MCHCFG 0x50
#define I82860_GBA 0x60
#define I82860_GBA_MASK 0x7FF
#define I82860_GBA_SHIFT 24
#define I82860_ERRSTS 0xC8
#define I82860_EAP 0xE4
#define I82860_DERRCTL_STS 0xE2

enum i82860_chips {
	I82860 = 0,
};

struct i82860_dev_info {
	const char *ctl_name;
};

struct i82860_error_info {
	u16 errsts;
	u32 eap;
	u16 derrsyn;
	u16 errsts2;
};

static const struct i82860_dev_info i82860_devs[] = {
	[I82860] = {
		.ctl_name = "i82860"
	},
};

static struct pci_dev *mci_pdev = NULL;	/* init dev: in case that AGP code
					 * has already registered driver
					 */

static void i82860_get_error_info(struct mem_ctl_info *mci,
		struct i82860_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->dev);

	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);

	pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);

	/*
	 * If the error is the same for both reads then the first set of reads
	 * is valid.  If there is a change then there is a CE no info and the
	 * second set of reads is valid and should be UE info.
	 */
	if (!(info->errsts2 & 0x0003))
		return;

	if ((info->errsts ^ info->errsts2) & 0x0003) {
		pci_read_config_dword(pdev, I82860_EAP, &info->eap);
		pci_read_config_word(pdev, I82860_DERRCTL_STS,
				&info->derrsyn);
	}
}

static int i82860_process_error_info(struct mem_ctl_info *mci,
		struct i82860_error_info *info, int handle_errors)
{
	int row;

	if (!(info->errsts2 & 0x0003))
		return 0;

	if (!handle_errors)
		return 1;

	if ((info->errsts ^ info->errsts2) & 0x0003) {
		edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
		info->errsts = info->errsts2;
	}

	info->eap >>= PAGE_SHIFT;
	row = edac_mc_find_csrow_by_page(mci, info->eap);

	if (info->errsts & 0x0002)
		edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
	else
		edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, 0,
				"i82860 UE");

	return 1;
}

static void i82860_check(struct mem_ctl_info *mci)
{
	struct i82860_error_info info;

	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
	i82860_get_error_info(mci, &info);
	i82860_process_error_info(mci, &info, 1);
}

static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc = -ENODEV;
	int index;
	struct mem_ctl_info *mci = NULL;
	unsigned long last_cumul_size;
	struct i82860_error_info discard;

	u16 mchcfg_ddim;	/* DRAM Data Integrity Mode 0=none,2=edac */

	/* RDRAM has channels but these don't map onto the abstractions that
	   edac uses.
	   The device groups from the GRA registers seem to map reasonably
	   well onto the notion of a chip select row.
	   There are 16 GRA registers and since the name is associated with
	   the channel and the GRA registers map to physical devices so we are
	   going to make 1 channel for group.
	 */
	mci = edac_mc_alloc(0, 16, 1);

	if (!mci)
		return -ENOMEM;

	debugf3("%s(): init mci\n", __func__);
	mci->dev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR;

	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	/* I"m not sure about this but I think that all RDRAM is SECDED */
	mci->edac_cap = EDAC_FLAG_SECDED;
	/* adjust FLAGS */

	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = I82860_REVISION;
	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
	mci->edac_check = i82860_check;
	mci->ctl_page_to_phys = NULL;

	pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
	mchcfg_ddim = mchcfg_ddim & 0x180;

	/*
	 * The group row boundary (GRA) reg values are boundary address
	 * for each DRAM row with a granularity of 16MB.  GRA regs are
	 * cumulative; therefore GRA15 will contain the total memory contained
	 * in all eight rows.
	 */
	for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
		u16 value;
		u32 cumul_size;
		struct csrow_info *csrow = &mci->csrows[index];

		pci_read_config_word(pdev, I82860_GBA + index * 2,
				&value);

		cumul_size = (value & I82860_GBA_MASK) <<
		    (I82860_GBA_SHIFT - PAGE_SHIFT);
		debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
			cumul_size);

		if (cumul_size == last_cumul_size)
			continue;	/* not populated */

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		csrow->nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;
		csrow->grain = 1 << 12;  /* I82860_EAP has 4KiB reolution */
		csrow->mtype = MEM_RMBS;
		csrow->dtype = DEV_UNKNOWN;
		csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
	}

	i82860_get_error_info(mci, &discard);  /* clear counters */

	/* Here we assume that we will never see multiple instances of this
	 * type of memory controller.  The ID is therefore hardcoded to 0.
	 */
	if (edac_mc_add_mc(mci,0)) {
		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
		edac_mc_free(mci);
	} else {
		/* get this far and it's successful */
		debugf3("%s(): success\n", __func__);
		rc = 0;
	}

	return rc;
}

/* returns count (>= 0), or negative on error */
static int __devinit i82860_init_one(struct pci_dev *pdev,
		const struct pci_device_id *ent)
{
	int rc;

	debugf0("%s()\n", __func__);
	i82860_printk(KERN_INFO, "i82860 init one\n");

	if (pci_enable_device(pdev) < 0)
		return -EIO;

	rc = i82860_probe1(pdev, ent->driver_data);

	if (rc == 0)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void __devexit i82860_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	debugf0("%s()\n", __func__);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id i82860_pci_tbl[] __devinitdata = {
	{
		PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
		I82860
	},
	{
		0,
	}	/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);

static struct pci_driver i82860_driver = {
	.name = EDAC_MOD_STR,
	.probe = i82860_init_one,
	.remove = __devexit_p(i82860_remove_one),
	.id_table = i82860_pci_tbl,
};

static int __init i82860_init(void)
{
	int pci_rc;

	debugf3("%s()\n", __func__);

	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
		goto fail0;

	if (!mci_pdev) {
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
					PCI_DEVICE_ID_INTEL_82860_0, NULL);

		if (mci_pdev == NULL) {
			debugf0("860 pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);

		if (pci_rc < 0) {
			debugf0("860 init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i82860_driver);

fail0:
	if (mci_pdev != NULL)
		pci_dev_put(mci_pdev);

	return pci_rc;
}

static void __exit i82860_exit(void)
{
	debugf3("%s()\n", __func__);

	pci_unregister_driver(&i82860_driver);

	if (mci_pdev != NULL)
		pci_dev_put(mci_pdev);
}

module_init(i82860_init);
module_exit(i82860_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
	"Ben Woodard <woodard@redhat.com>");
MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
Commit	Line	Data
0d88a10e AC	1	/*
	2	* Intel 82860 Memory Controller kernel module
	3	* (C) 2005 Red Hat (http://www.redhat.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Ben Woodard <woodard@redhat.com>
	8	* shamelessly copied from and based upon the edac_i82875 driver
	9	* by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
	10	*/
	11
0d88a10e AC	12	#include <linux/config.h>
	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/pci.h>
	16	#include <linux/pci_ids.h>
	17	#include <linux/slab.h>
	18	#include "edac_mc.h"
	19
37f04581 DT	20	#define I82860_REVISION " Ver: 2.0.0 " __DATE__
37f04581 DT	21
537fba28	22	#define i82860_printk(level, fmt, arg...) \
e7ecd891	23	edac_printk(level, "i82860", fmt, ##arg)
537fba28 DP	24
537fba28 DP	25	#define i82860_mc_printk(mci, level, fmt, arg...) \
e7ecd891	26	edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
537fba28	27
0d88a10e AC	28	#ifndef PCI_DEVICE_ID_INTEL_82860_0
	29	#define PCI_DEVICE_ID_INTEL_82860_0 0x2531
	30	#endif /* PCI_DEVICE_ID_INTEL_82860_0 */
	31
	32	#define I82860_MCHCFG 0x50
	33	#define I82860_GBA 0x60
	34	#define I82860_GBA_MASK 0x7FF
	35	#define I82860_GBA_SHIFT 24
	36	#define I82860_ERRSTS 0xC8
	37	#define I82860_EAP 0xE4
	38	#define I82860_DERRCTL_STS 0xE2
	39
	40	enum i82860_chips {
	41	I82860 = 0,
	42	};
	43
	44	struct i82860_dev_info {
	45	const char *ctl_name;
	46	};
	47
	48	struct i82860_error_info {
	49	u16 errsts;
	50	u32 eap;
	51	u16 derrsyn;
	52	u16 errsts2;
	53	};
	54
	55	static const struct i82860_dev_info i82860_devs[] = {
	56	[I82860] = {
e7ecd891 DP	57	.ctl_name = "i82860"
e7ecd891 DP	58	},
0d88a10e AC	59	};
	60
	61	static struct pci_dev mci_pdev = NULL; / init dev: in case that AGP code
e7ecd891 DP	62	* has already registered driver
e7ecd891 DP	63	*/
0d88a10e	64
e7ecd891	65	static void i82860_get_error_info(struct mem_ctl_info *mci,
0d88a10e AC	66	struct i82860_error_info *info)
0d88a10e AC	67	{
37f04581 DT	68	struct pci_dev *pdev;
	69
	70	pdev = to_pci_dev(mci->dev);
	71
0d88a10e AC	72	/*
	73	* This is a mess because there is no atomic way to read all the
	74	* registers at once and the registers can transition from CE being
	75	* overwritten by UE.
	76	*/
37f04581 DT	77	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
	78	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
	79	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
	80	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
0d88a10e	81
37f04581	82	pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
0d88a10e AC	83
	84	/*
	85	* If the error is the same for both reads then the first set of reads
	86	* is valid. If there is a change then there is a CE no info and the
	87	* second set of reads is valid and should be UE info.
	88	*/
	89	if (!(info->errsts2 & 0x0003))
	90	return;
e7ecd891	91
0d88a10e	92	if ((info->errsts ^ info->errsts2) & 0x0003) {
37f04581 DT	93	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
37f04581 DT	94	pci_read_config_word(pdev, I82860_DERRCTL_STS,
e7ecd891	95	&info->derrsyn);
0d88a10e AC	96	}
	97	}
	98
e7ecd891	99	static int i82860_process_error_info(struct mem_ctl_info *mci,
0d88a10e AC	100	struct i82860_error_info *info, int handle_errors)
	101	{
	102	int row;
	103
	104	if (!(info->errsts2 & 0x0003))
	105	return 0;
	106
	107	if (!handle_errors)
	108	return 1;
	109
	110	if ((info->errsts ^ info->errsts2) & 0x0003) {
	111	edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
	112	info->errsts = info->errsts2;
	113	}
	114
	115	info->eap >>= PAGE_SHIFT;
	116	row = edac_mc_find_csrow_by_page(mci, info->eap);
	117
	118	if (info->errsts & 0x0002)
	119	edac_mc_handle_ue(mci, info->eap, 0, row, "i82860 UE");
	120	else
e7ecd891 DP	121	edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, 0,
e7ecd891 DP	122	"i82860 UE");
0d88a10e AC	123
	124	return 1;
	125	}
	126
	127	static void i82860_check(struct mem_ctl_info *mci)
	128	{
	129	struct i82860_error_info info;
	130
537fba28	131	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
0d88a10e AC	132	i82860_get_error_info(mci, &info);
	133	i82860_process_error_info(mci, &info, 1);
	134	}
	135
	136	static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
	137	{
	138	int rc = -ENODEV;
	139	int index;
	140	struct mem_ctl_info *mci = NULL;
	141	unsigned long last_cumul_size;
749ede57	142	struct i82860_error_info discard;
0d88a10e AC	143
	144	u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
	145
	146	/* RDRAM has channels but these don't map onto the abstractions that
	147	edac uses.
	148	The device groups from the GRA registers seem to map reasonably
	149	well onto the notion of a chip select row.
	150	There are 16 GRA registers and since the name is associated with
	151	the channel and the GRA registers map to physical devices so we are
	152	going to make 1 channel for group.
	153	*/
	154	mci = edac_mc_alloc(0, 16, 1);
e7ecd891	155
0d88a10e AC	156	if (!mci)
	157	return -ENOMEM;
	158
537fba28	159	debugf3("%s(): init mci\n", __func__);
37f04581	160	mci->dev = &pdev->dev;
0d88a10e AC	161	mci->mtype_cap = MEM_FLAG_DDR;
0d88a10e AC	162
0d88a10e AC	163	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	164	/* I"m not sure about this but I think that all RDRAM is SECDED */
	165	mci->edac_cap = EDAC_FLAG_SECDED;
	166	/* adjust FLAGS */
	167
680cbbbb	168	mci->mod_name = EDAC_MOD_STR;
37f04581	169	mci->mod_ver = I82860_REVISION;
0d88a10e AC	170	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
	171	mci->edac_check = i82860_check;
	172	mci->ctl_page_to_phys = NULL;
	173
37f04581	174	pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
0d88a10e AC	175	mchcfg_ddim = mchcfg_ddim & 0x180;
	176
	177	/*
	178	* The group row boundary (GRA) reg values are boundary address
	179	* for each DRAM row with a granularity of 16MB. GRA regs are
	180	* cumulative; therefore GRA15 will contain the total memory contained
	181	* in all eight rows.
	182	*/
	183	for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
	184	u16 value;
	185	u32 cumul_size;
	186	struct csrow_info *csrow = &mci->csrows[index];
	187
37f04581	188	pci_read_config_word(pdev, I82860_GBA + index * 2,
e7ecd891	189	&value);
0d88a10e AC	190
	191	cumul_size = (value & I82860_GBA_MASK) <<
	192	(I82860_GBA_SHIFT - PAGE_SHIFT);
537fba28 DP	193	debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
537fba28 DP	194	cumul_size);
e7ecd891	195
0d88a10e AC	196	if (cumul_size == last_cumul_size)
	197	continue; /* not populated */
	198
	199	csrow->first_page = last_cumul_size;
	200	csrow->last_page = cumul_size - 1;
	201	csrow->nr_pages = cumul_size - last_cumul_size;
	202	last_cumul_size = cumul_size;
e7ecd891	203	csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
0d88a10e AC	204	csrow->mtype = MEM_RMBS;
	205	csrow->dtype = DEV_UNKNOWN;
	206	csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
	207	}
	208
749ede57	209	i82860_get_error_info(mci, &discard); /* clear counters */
0d88a10e	210
2d7bbb91 DT	211	/* Here we assume that we will never see multiple instances of this
	212	* type of memory controller. The ID is therefore hardcoded to 0.
	213	*/
	214	if (edac_mc_add_mc(mci,0)) {
537fba28	215	debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
0d88a10e AC	216	edac_mc_free(mci);
	217	} else {
	218	/* get this far and it's successful */
537fba28	219	debugf3("%s(): success\n", __func__);
0d88a10e AC	220	rc = 0;
0d88a10e AC	221	}
e7ecd891	222
0d88a10e AC	223	return rc;
	224	}
	225
	226	/* returns count (>= 0), or negative on error */
	227	static int __devinit i82860_init_one(struct pci_dev *pdev,
e7ecd891	228	const struct pci_device_id *ent)
0d88a10e AC	229	{
	230	int rc;
	231
537fba28	232	debugf0("%s()\n", __func__);
537fba28	233	i82860_printk(KERN_INFO, "i82860 init one\n");
e7ecd891 DP	234
e7ecd891 DP	235	if (pci_enable_device(pdev) < 0)
0d88a10e	236	return -EIO;
e7ecd891	237
0d88a10e	238	rc = i82860_probe1(pdev, ent->driver_data);
e7ecd891 DP	239
e7ecd891 DP	240	if (rc == 0)
0d88a10e	241	mci_pdev = pci_dev_get(pdev);
e7ecd891	242
0d88a10e AC	243	return rc;
	244	}
	245
	246	static void __devexit i82860_remove_one(struct pci_dev *pdev)
	247	{
	248	struct mem_ctl_info *mci;
	249
537fba28	250	debugf0("%s()\n", __func__);
0d88a10e	251
37f04581	252	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
18dbc337 DP	253	return;
	254
	255	edac_mc_free(mci);
0d88a10e AC	256	}
	257
	258	static const struct pci_device_id i82860_pci_tbl[] __devinitdata = {
e7ecd891 DP	259	{
	260	PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	261	I82860
	262	},
	263	{
	264	0,
	265	} /* 0 terminated list. */
0d88a10e AC	266	};
	267
	268	MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
	269
	270	static struct pci_driver i82860_driver = {
680cbbbb	271	.name = EDAC_MOD_STR,
0d88a10e AC	272	.probe = i82860_init_one,
	273	.remove = __devexit_p(i82860_remove_one),
	274	.id_table = i82860_pci_tbl,
	275	};
	276
da9bb1d2	277	static int __init i82860_init(void)
0d88a10e AC	278	{
	279	int pci_rc;
	280
537fba28	281	debugf3("%s()\n", __func__);
e7ecd891	282
0d88a10e	283	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
e8a491b4	284	goto fail0;
0d88a10e AC	285
0d88a10e AC	286	if (!mci_pdev) {
0d88a10e	287	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
e7ecd891 DP	288	PCI_DEVICE_ID_INTEL_82860_0, NULL);
e7ecd891 DP	289
0d88a10e AC	290	if (mci_pdev == NULL) {
0d88a10e AC	291	debugf0("860 pci_get_device fail\n");
e8a491b4 DP	292	pci_rc = -ENODEV;
e8a491b4 DP	293	goto fail1;
0d88a10e	294	}
e7ecd891	295
0d88a10e	296	pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
e7ecd891	297
0d88a10e AC	298	if (pci_rc < 0) {
0d88a10e AC	299	debugf0("860 init fail\n");
e8a491b4 DP	300	pci_rc = -ENODEV;
e8a491b4 DP	301	goto fail1;
0d88a10e AC	302	}
0d88a10e AC	303	}
e7ecd891	304
0d88a10e	305	return 0;
e8a491b4 DP	306
	307	fail1:
	308	pci_unregister_driver(&i82860_driver);
	309
	310	fail0:
	311	if (mci_pdev != NULL)
	312	pci_dev_put(mci_pdev);
	313
	314	return pci_rc;
0d88a10e AC	315	}
	316
	317	static void __exit i82860_exit(void)
	318	{
537fba28	319	debugf3("%s()\n", __func__);
0d88a10e AC	320
0d88a10e AC	321	pci_unregister_driver(&i82860_driver);
e8a491b4 DP	322
e8a491b4 DP	323	if (mci_pdev != NULL)
0d88a10e	324	pci_dev_put(mci_pdev);
0d88a10e AC	325	}
	326
	327	module_init(i82860_init);
	328	module_exit(i82860_exit);
	329
	330	MODULE_LICENSE("GPL");
e7ecd891 DP	331	MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
e7ecd891 DP	332	"Ben Woodard <woodard@redhat.com>");
0d88a10e	333	MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");