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i7300_edac: Detect if the device is on single mode
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / i7300_edac.c
CommitLineData
fcaf780b
MCC		 1/*
2 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License version 2 only.
6 *
7 * Copyright (c) 2010 by:
8 * Mauro Carvalho Chehab <mchehab@redhat.com>
9 *
10 * Red Hat Inc. http://www.redhat.com
11 *
12 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://www.intel.com/Assets/PDF/datasheet/318082.pdf
14 *
15 * TODO: The chipset allow checking for PCI Express errors also. Currently,
16 * the driver covers only memory error errors
17 *
18 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
19 */
20
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/pci.h>
24#include <linux/pci_ids.h>
25#include <linux/slab.h>
26#include <linux/edac.h>
27#include <linux/mmzone.h>
28
29#include "edac_core.h"
30
31/*
32 * Alter this version for the I7300 module when modifications are made
33 */
34#define I7300_REVISION " Ver: 1.0.0 " __DATE__
35
36#define EDAC_MOD_STR "i7300_edac"
37
38#define i7300_printk(level, fmt, arg...) \
39 edac_printk(level, "i7300", fmt, ##arg)
40
41#define i7300_mc_printk(mci, level, fmt, arg...) \
42 edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
43
44/*
45 * Memory topology is organized as:
46 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
47 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
48 * Each channel can have to 8 DIMM sets (called as SLOTS)
49 * Slots should generally be filled in pairs
50 * Except on Single Channel mode of operation
51 * just slot 0/channel0 filled on this mode
52 * On normal operation mode, the two channels on a branch should be
c3af2eaf 53 * filled together for the same SLOT#
fcaf780b
MCC		 54 * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
55 * channels on both branches should be filled
56 */
57
58/* Limits for i7300 */
59#define MAX_SLOTS 8
60#define MAX_BRANCHES 2
61#define MAX_CH_PER_BRANCH 2
62#define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES)
63#define MAX_MIR 3
64
65#define to_channel(ch, branch) ((((branch)) << 1) | (ch))
66
67#define to_csrow(slot, ch, branch) \
68 (to_channel(ch, branch) | ((slot) << 2))
69
c3af2eaf
MCC		 70/*
71 * I7300 devices
fcaf780b
MCC		 72 * All 3 functions of Device 16 (0,1,2) share the SAME DID and
73 * uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2),
74 * PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
75 * for device 21 (0,1).
c3af2eaf
MCC		 76 */
77
78/****************************************************
79 * i7300 Register definitions for memory enumberation
80 ****************************************************/
81
82/*
83 * Device 16,
84 * Function 0: System Address (not documented)
85 * Function 1: Memory Branch Map, Control, Errors Register
fcaf780b
MCC		 86 */
87
88 /* OFFSETS for Function 0 */
af3d8831
MCC		 89#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
90#define MAXCH 0x56 /* Max Channel Number */
91#define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
fcaf780b
MCC		 92
93 /* OFFSETS for Function 1 */
af3d8831 94#define MC_SETTINGS 0x40
bb81a216
MCC		 95 #define IS_MIRRORED(mc) ((mc) & (1 << 16))
96 #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5))
97 #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31))
98 #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8))
fcaf780b 99
bb81a216
MCC		 100#define MC_SETTINGS_A 0x58
101 #define IS_SINGLE_MODE(mca) ((mca) & (1 << 14))
d7de2bdb 102
af3d8831
MCC		 103#define TOLM 0x6C
104#define REDMEMB 0x7C
105
106#define MIR0 0x80
107#define MIR1 0x84
108#define MIR2 0x88
fcaf780b 109
fcaf780b
MCC		 110/*
111 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
112 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
113 * seems that we cannot use this information directly for the same usage.
114 * Each memory slot may have up to 2 AMB interfaces, one for income and another
115 * for outcome interface to the next slot.
116 * For now, the driver just stores the AMB present registers, but rely only at
117 * the MTR info to detect memory.
118 * Datasheet is also not clear about how to map each AMBPRESENT registers to
119 * one of the 4 available channels.
120 */
121#define AMBPRESENT_0 0x64
122#define AMBPRESENT_1 0x66
123
124const static u16 mtr_regs [MAX_SLOTS] = {
125 0x80, 0x84, 0x88, 0x8c,
126 0x82, 0x86, 0x8a, 0x8e
127};
128
129/* Defines to extract the vaious fields from the
130 * MTRx - Memory Technology Registers
131 */
132#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8))
133#define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7))
134#define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
135#define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4)
136#define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0)
137#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
138#define MTR_DRAM_BANKS_ADDR_BITS 2
139#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
140#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
141#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
142
fcaf780b
MCC		 143#ifdef CONFIG_EDAC_DEBUG
144/* MTR NUMROW */
145static const char *numrow_toString[] = {
146 "8,192 - 13 rows",
147 "16,384 - 14 rows",
148 "32,768 - 15 rows",
149 "65,536 - 16 rows"
150};
151
152/* MTR NUMCOL */
153static const char *numcol_toString[] = {
154 "1,024 - 10 columns",
155 "2,048 - 11 columns",
156 "4,096 - 12 columns",
157 "reserved"
158};
159#endif
160
c3af2eaf
MCC		 161/************************************************
162 * i7300 Register definitions for error detection
163 ************************************************/
164/*
165 * Device 16.2: Global Error Registers
166 */
167
5de6e07e
MCC		 168#define FERR_GLOBAL_HI 0x48
169static const char *ferr_global_hi_name[] = {
170 [3] = "FSB 3 Fatal Error",
171 [2] = "FSB 2 Fatal Error",
172 [1] = "FSB 1 Fatal Error",
173 [0] = "FSB 0 Fatal Error",
174};
175#define ferr_global_hi_is_fatal(errno) 1
176
c3af2eaf 177#define FERR_GLOBAL_LO 0x40
5de6e07e 178static const char *ferr_global_lo_name[] = {
c3af2eaf
MCC		 179 [31] = "Internal MCH Fatal Error",
180 [30] = "Intel QuickData Technology Device Fatal Error",
181 [29] = "FSB1 Fatal Error",
182 [28] = "FSB0 Fatal Error",
183 [27] = "FBD Channel 3 Fatal Error",
184 [26] = "FBD Channel 2 Fatal Error",
185 [25] = "FBD Channel 1 Fatal Error",
186 [24] = "FBD Channel 0 Fatal Error",
187 [23] = "PCI Express Device 7Fatal Error",
188 [22] = "PCI Express Device 6 Fatal Error",
189 [21] = "PCI Express Device 5 Fatal Error",
190 [20] = "PCI Express Device 4 Fatal Error",
191 [19] = "PCI Express Device 3 Fatal Error",
192 [18] = "PCI Express Device 2 Fatal Error",
193 [17] = "PCI Express Device 1 Fatal Error",
194 [16] = "ESI Fatal Error",
195 [15] = "Internal MCH Non-Fatal Error",
196 [14] = "Intel QuickData Technology Device Non Fatal Error",
197 [13] = "FSB1 Non-Fatal Error",
198 [12] = "FSB 0 Non-Fatal Error",
199 [11] = "FBD Channel 3 Non-Fatal Error",
200 [10] = "FBD Channel 2 Non-Fatal Error",
201 [9] = "FBD Channel 1 Non-Fatal Error",
202 [8] = "FBD Channel 0 Non-Fatal Error",
203 [7] = "PCI Express Device 7 Non-Fatal Error",
204 [6] = "PCI Express Device 6 Non-Fatal Error",
205 [5] = "PCI Express Device 5 Non-Fatal Error",
206 [4] = "PCI Express Device 4 Non-Fatal Error",
207 [3] = "PCI Express Device 3 Non-Fatal Error",
208 [2] = "PCI Express Device 2 Non-Fatal Error",
209 [1] = "PCI Express Device 1 Non-Fatal Error",
210 [0] = "ESI Non-Fatal Error",
211};
5de6e07e 212#define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1)
fcaf780b
MCC		 213
214/* Device name and register DID (Device ID) */
215struct i7300_dev_info {
216 const char *ctl_name; /* name for this device */
217 u16 fsb_mapping_errors; /* DID for the branchmap,control */
218};
219
220/* Table of devices attributes supported by this driver */
221static const struct i7300_dev_info i7300_devs[] = {
222 {
223 .ctl_name = "I7300",
224 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
225 },
226};
227
228struct i7300_dimm_info {
229 int megabytes; /* size, 0 means not present */
230};
231
232/* driver private data structure */
233struct i7300_pvt {
3e57eef6
MCC		 234 struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */
235 struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */
236 struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */
237 struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */
fcaf780b
MCC		 238
239 u16 tolm; /* top of low memory */
240 u64 ambase; /* AMB BAR */
241
bb81a216
MCC		 242 u32 mc_settings; /* Report several settings */
243 u32 mc_settings_a;
244
245 u16 mir[MAX_MIR]; /* Memory Interleave Reg*/
fcaf780b
MCC		 246
247 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */
248 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */
249
250 /* DIMM information matrix, allocating architecture maximums */
251 struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];
252};
253
fcaf780b
MCC		 254/* FIXME: Why do we need to have this static? */
255static struct edac_pci_ctl_info *i7300_pci;
256
5de6e07e
MCC		 257/********************************************
258 * i7300 Functions related to error detection
259 ********************************************/
fcaf780b 260
5de6e07e
MCC		 261struct i7300_error_info {
262 int dummy; /* FIXME */
263};
264
265const char *get_err_from_table(const char *table[], int size, int pos)
fcaf780b 266{
5de6e07e
MCC		 267 if (pos >= size)
268 return "Reserved";
269
270 return table[pos];
fcaf780b
MCC		 271}
272
5de6e07e
MCC		 273#define GET_ERR_FROM_TABLE(table, pos) \
274 get_err_from_table(table, ARRAY_SIZE(table), pos)
275
fcaf780b
MCC		 276/*
277 * i7300_get_error_info Retrieve the hardware error information from
278 * the hardware and cache it in the 'info'
279 * structure
280 */
281static void i7300_get_error_info(struct mem_ctl_info *mci,
282 struct i7300_error_info *info)
283{
fcaf780b
MCC		 284}
285
286/*
5de6e07e
MCC		 287 * i7300_process_error_global Retrieve the hardware error information from
288 * the hardware and cache it in the 'info'
289 * structure
fcaf780b 290 */
5de6e07e
MCC		 291static void i7300_process_error_global(struct mem_ctl_info *mci,
292 struct i7300_error_info *info)
fcaf780b 293{
5de6e07e
MCC		 294 struct i7300_pvt *pvt;
295 u32 errnum, value;
296 unsigned long errors;
297 const char *specific;
298 bool is_fatal;
fcaf780b 299
5de6e07e 300 pvt = mci->pvt_info;
fcaf780b 301
5de6e07e
MCC		 302 /* read in the 1st FATAL error register */
303 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
304 FERR_GLOBAL_HI, &value);
305 if (unlikely(value)) {
306 errors = value;
307 errnum = find_first_bit(&errors,
308 ARRAY_SIZE(ferr_global_hi_name));
309 specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum);
310 is_fatal = ferr_global_hi_is_fatal(errnum);
86002324
MCC		 311
312 /* Clear the error bit */
313 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
314 FERR_GLOBAL_HI, value);
315
5de6e07e 316 goto error_global;
fcaf780b
MCC		 317 }
318
5de6e07e
MCC		 319 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
320 FERR_GLOBAL_LO, &value);
321 if (unlikely(value)) {
322 errors = value;
323 errnum = find_first_bit(&errors,
324 ARRAY_SIZE(ferr_global_lo_name));
325 specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum);
326 is_fatal = ferr_global_lo_is_fatal(errnum);
86002324
MCC		 327
328 /* Clear the error bit */
329 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
330 FERR_GLOBAL_LO, value);
331
5de6e07e
MCC		 332 goto error_global;
333 }
334 return;
fcaf780b 335
5de6e07e
MCC		 336error_global:
337 i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n",
338 is_fatal ? "Fatal" : "NOT fatal", specific);
fcaf780b
MCC		 339}
340
341/*
5de6e07e
MCC		 342 * i7300_process_error_info Retrieve the hardware error information from
343 * the hardware and cache it in the 'info'
344 * structure
fcaf780b
MCC		 345 */
346static void i7300_process_error_info(struct mem_ctl_info *mci,
5de6e07e
MCC		 347 struct i7300_error_info *info)
348{
349 i7300_process_error_global(mci, info);
350};
fcaf780b
MCC		 351
352/*
353 * i7300_clear_error Retrieve any error from the hardware
354 * but do NOT process that error.
355 * Used for 'clearing' out of previous errors
356 * Called by the Core module.
357 */
358static void i7300_clear_error(struct mem_ctl_info *mci)
359{
360 struct i7300_error_info info;
361
362 i7300_get_error_info(mci, &info);
363}
364
365/*
366 * i7300_check_error Retrieve and process errors reported by the
367 * hardware. Called by the Core module.
368 */
369static void i7300_check_error(struct mem_ctl_info *mci)
370{
371 struct i7300_error_info info;
372 debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
5de6e07e 373
fcaf780b
MCC		 374 i7300_get_error_info(mci, &info);
375 i7300_process_error_info(mci, &info);
376}
377
378/*
379 * i7300_enable_error_reporting
380 * Turn on the memory reporting features of the hardware
381 */
382static void i7300_enable_error_reporting(struct mem_ctl_info *mci)
383{
fcaf780b 384}
5de6e07e
MCC		 385
386/************************************************
387 * i7300 Functions related to memory enumberation
388 ************************************************/
fcaf780b
MCC		 389
390/*
391 * determine_mtr(pvt, csrow, channel)
392 *
393 * return the proper MTR register as determine by the csrow and desired channel
394 */
395static int decode_mtr(struct i7300_pvt *pvt,
396 int slot, int ch, int branch,
397 struct i7300_dimm_info *dinfo,
398 struct csrow_info *p_csrow)
399{
400 int mtr, ans, addrBits, channel;
401
402 channel = to_channel(ch, branch);
403
404 mtr = pvt->mtr[slot][branch];
405 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
406
407 debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n",
408 slot, channel,
409 ans ? "Present" : "NOT Present");
410
411 /* Determine if there is a DIMM present in this DIMM slot */
412
413#if 0
414 if (!amb_present || !ans)
415 return 0;
416#else
417 if (!ans)
418 return 0;
419#endif
420
421 /* Start with the number of bits for a Bank
422 * on the DRAM */
423 addrBits = MTR_DRAM_BANKS_ADDR_BITS;
424 /* Add thenumber of ROW bits */
425 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
426 /* add the number of COLUMN bits */
427 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
428 /* add the number of RANK bits */
429 addrBits += MTR_DIMM_RANKS(mtr);
430
431 addrBits += 6; /* add 64 bits per DIMM */
432 addrBits -= 20; /* divide by 2^^20 */
433 addrBits -= 3; /* 8 bits per bytes */
434
435 dinfo->megabytes = 1 << addrBits;
436
437 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
438
439 debugf2("\t\tELECTRICAL THROTTLING is %s\n",
440 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
441
442 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
443 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single");
444 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
445 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
446 debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
447
448 p_csrow->grain = 8;
449 p_csrow->nr_pages = dinfo->megabytes << 8;
450 p_csrow->mtype = MEM_FB_DDR2;
116389ed
MCC		 451
452 /*
453 * FIXME: the type of error detection actually depends of the
454 * mode of operation. When it is just one single memory chip, at
455 * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
456 * In normal or mirrored mode, it uses Single Device Data correction,
457 * with the possibility of using an extended algorithm for x8 memories
458 * See datasheet Sections 7.3.6 to 7.3.8
459 */
fcaf780b
MCC		 460 p_csrow->edac_mode = EDAC_S8ECD8ED;
461
462 /* ask what device type on this row */
d7de2bdb
MCC		 463 if (MTR_DRAM_WIDTH(mtr)) {
464 debugf0("Scrub algorithm for x8 is on %s mode\n",
465 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
466 "enhanced" : "normal");
467
fcaf780b 468 p_csrow->dtype = DEV_X8;
d7de2bdb 469 } else
fcaf780b
MCC		 470 p_csrow->dtype = DEV_X4;
471
472 return mtr;
473}
474
475/*
476 * print_dimm_size
477 *
478 * also will output a DIMM matrix map, if debug is enabled, for viewing
479 * how the DIMMs are populated
480 */
481static void print_dimm_size(struct i7300_pvt *pvt)
482{
483 struct i7300_dimm_info *dinfo;
484 char *p, *mem_buffer;
485 int space, n;
486 int channel, slot;
487
488 space = PAGE_SIZE;
489 mem_buffer = p = kmalloc(space, GFP_KERNEL);
490 if (p == NULL) {
491 i7300_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
492 __FILE__, __func__);
493 return;
494 }
495
496 n = snprintf(p, space, " ");
497 p += n;
498 space -= n;
499 for (channel = 0; channel < MAX_CHANNELS; channel++) {
500 n = snprintf(p, space, "channel %d | ", channel);
501 p += n;
502 space -= n;
503 }
504 debugf2("%s\n", mem_buffer);
505 p = mem_buffer;
506 space = PAGE_SIZE;
507 n = snprintf(p, space, "-------------------------------"
508 "------------------------------");
509 p += n;
510 space -= n;
511 debugf2("%s\n", mem_buffer);
512 p = mem_buffer;
513 space = PAGE_SIZE;
514
515 for (slot = 0; slot < MAX_SLOTS; slot++) {
516 n = snprintf(p, space, "csrow/SLOT %d ", slot);
517 p += n;
518 space -= n;
519
520 for (channel = 0; channel < MAX_CHANNELS; channel++) {
521 dinfo = &pvt->dimm_info[slot][channel];
522 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
523 p += n;
524 space -= n;
525 }
526
527 debugf2("%s\n", mem_buffer);
528 p = mem_buffer;
529 space = PAGE_SIZE;
530 }
531
532 n = snprintf(p, space, "-------------------------------"
533 "------------------------------");
534 p += n;
535 space -= n;
536 debugf2("%s\n", mem_buffer);
537 p = mem_buffer;
538 space = PAGE_SIZE;
539
540 kfree(mem_buffer);
541}
542
543/*
544 * i7300_init_csrows Initialize the 'csrows' table within
545 * the mci control structure with the
546 * addressing of memory.
547 *
548 * return:
549 * 0 success
550 * 1 no actual memory found on this MC
551 */
552static int i7300_init_csrows(struct mem_ctl_info *mci)
553{
554 struct i7300_pvt *pvt;
555 struct i7300_dimm_info *dinfo;
556 struct csrow_info *p_csrow;
557 int empty;
558 int mtr;
559 int ch, branch, slot, channel;
560
561 pvt = mci->pvt_info;
562
563 empty = 1; /* Assume NO memory */
564
565 debugf2("Memory Technology Registers:\n");
566
567 /* Get the AMB present registers for the four channels */
568 for (branch = 0; branch < MAX_BRANCHES; branch++) {
569 /* Read and dump branch 0's MTRs */
570 channel = to_channel(0, branch);
3e57eef6 571 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_0,
fcaf780b
MCC		 572 &pvt->ambpresent[channel]);
573 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
574 channel, pvt->ambpresent[channel]);
575
576 channel = to_channel(1, branch);
3e57eef6 577 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_1,
fcaf780b
MCC		 578 &pvt->ambpresent[channel]);
579 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
580 channel, pvt->ambpresent[channel]);
581 }
582
583 /* Get the set of MTR[0-7] regs by each branch */
584 for (slot = 0; slot < MAX_SLOTS; slot++) {
585 int where = mtr_regs[slot];
586 for (branch = 0; branch < MAX_BRANCHES; branch++) {
3e57eef6 587 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
fcaf780b
MCC		 588 where,
589 &pvt->mtr[slot][branch]);
590 for (ch = 0; ch < MAX_BRANCHES; ch++) {
591 int channel = to_channel(ch, branch);
592
593 dinfo = &pvt->dimm_info[slot][channel];
594 p_csrow = &mci->csrows[slot];
595
596 mtr = decode_mtr(pvt, slot, ch, branch,
597 dinfo, p_csrow);
598 /* if no DIMMS on this row, continue */
599 if (!MTR_DIMMS_PRESENT(mtr))
600 continue;
601
602 p_csrow->csrow_idx = slot;
603
604 /* FAKE OUT VALUES, FIXME */
605 p_csrow->first_page = 0 + slot * 20;
606 p_csrow->last_page = 9 + slot * 20;
607 p_csrow->page_mask = 0xfff;
608
609 empty = 0;
610 }
611 }
612 }
613
614 return empty;
615}
616
617static void decode_mir(int mir_no, u16 mir[MAX_MIR])
618{
619 if (mir[mir_no] & 3)
620 debugf2("MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n",
621 mir_no,
622 (mir[mir_no] >> 4) & 0xfff,
623 (mir[mir_no] & 1) ? "B0" : "",
624 (mir[mir_no] & 2) ? "B1": "");
625}
626
627/*
628 * i7300_get_mc_regs read in the necessary registers and
629 * cache locally
630 *
631 * Fills in the private data members
632 */
633static int i7300_get_mc_regs(struct mem_ctl_info *mci)
634{
635 struct i7300_pvt *pvt;
636 u32 actual_tolm;
637 int i, rc;
638
639 pvt = mci->pvt_info;
640
3e57eef6 641 pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE,
fcaf780b
MCC		 642 (u32 *) &pvt->ambase);
643
644 debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
645
646 /* Get the Branch Map regs */
3e57eef6 647 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm);
fcaf780b
MCC		 648 pvt->tolm >>= 12;
649 debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
650 pvt->tolm);
651
652 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
653 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
654 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
655
af3d8831 656 /* Get memory controller settings */
3e57eef6 657 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS,
af3d8831 658 &pvt->mc_settings);
bb81a216
MCC		 659 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A,
660 &pvt->mc_settings_a);
d7de2bdb 661
bb81a216
MCC		 662 if (IS_SINGLE_MODE(pvt->mc_settings_a))
663 debugf0("Memory controller operating on single mode\n");
664 else
665 debugf0("Memory controller operating on %s mode\n",
d7de2bdb 666 IS_MIRRORED(pvt->mc_settings) ? "mirrored" : "non-mirrored");
bb81a216 667
af3d8831 668 debugf0("Error detection is %s\n",
d7de2bdb
MCC		 669 IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
670 debugf0("Retry is %s\n",
671 IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
af3d8831
MCC		 672
673 /* Get Memory Interleave Range registers */
3e57eef6
MCC		 674 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, &pvt->mir[0]);
675 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1, &pvt->mir[1]);
676 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2, &pvt->mir[2]);
fcaf780b
MCC		 677
678 /* Decode the MIR regs */
679 for (i = 0; i < MAX_MIR; i++)
680 decode_mir(i, pvt->mir);
681
682 rc = i7300_init_csrows(mci);
683 if (rc < 0)
684 return rc;
685
686 /* Go and determine the size of each DIMM and place in an
687 * orderly matrix */
688 print_dimm_size(pvt);
689
690 return 0;
691}
692
5de6e07e
MCC		 693/*************************************************
694 * i7300 Functions related to device probe/release
695 *************************************************/
696
fcaf780b
MCC		 697/*
698 * i7300_put_devices 'put' all the devices that we have
699 * reserved via 'get'
700 */
701static void i7300_put_devices(struct mem_ctl_info *mci)
702{
703 struct i7300_pvt *pvt;
704 int branch;
705
706 pvt = mci->pvt_info;
707
708 /* Decrement usage count for devices */
709 for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++)
3e57eef6
MCC		 710 pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]);
711 pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs);
712 pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map);
fcaf780b
MCC		 713}
714
715/*
716 * i7300_get_devices Find and perform 'get' operation on the MCH's
717 * device/functions we want to reference for this driver
718 *
719 * Need to 'get' device 16 func 1 and func 2
720 */
721static int i7300_get_devices(struct mem_ctl_info *mci, int dev_idx)
722{
723 struct i7300_pvt *pvt;
724 struct pci_dev *pdev;
725
726 pvt = mci->pvt_info;
727
728 /* Attempt to 'get' the MCH register we want */
729 pdev = NULL;
3e57eef6 730 while (!pvt->pci_dev_16_1_fsb_addr_map || !pvt->pci_dev_16_2_fsb_err_regs) {
fcaf780b
MCC		 731 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
732 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev);
733 if (!pdev) {
734 /* End of list, leave */
735 i7300_printk(KERN_ERR,
736 "'system address,Process Bus' "
737 "device not found:"
738 "vendor 0x%x device 0x%x ERR funcs "
739 "(broken BIOS?)\n",
740 PCI_VENDOR_ID_INTEL,
741 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR);
742 goto error;
743 }
744
745 /* Store device 16 funcs 1 and 2 */
746 switch (PCI_FUNC(pdev->devfn)) {
747 case 1:
3e57eef6 748 pvt->pci_dev_16_1_fsb_addr_map = pdev;
fcaf780b
MCC		 749 break;
750 case 2:
3e57eef6 751 pvt->pci_dev_16_2_fsb_err_regs = pdev;
fcaf780b
MCC		 752 break;
753 }
754 }
755
756 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
3e57eef6
MCC		 757 pci_name(pvt->pci_dev_16_0_fsb_ctlr),
758 pvt->pci_dev_16_0_fsb_ctlr->vendor, pvt->pci_dev_16_0_fsb_ctlr->device);
fcaf780b 759 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
3e57eef6
MCC		 760 pci_name(pvt->pci_dev_16_1_fsb_addr_map),
761 pvt->pci_dev_16_1_fsb_addr_map->vendor, pvt->pci_dev_16_1_fsb_addr_map->device);
fcaf780b 762 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
3e57eef6
MCC		 763 pci_name(pvt->pci_dev_16_2_fsb_err_regs),
764 pvt->pci_dev_16_2_fsb_err_regs->vendor, pvt->pci_dev_16_2_fsb_err_regs->device);
fcaf780b 765
3e57eef6 766 pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
fcaf780b
MCC		 767 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
768 NULL);
3e57eef6 769 if (!pvt->pci_dev_2x_0_fbd_branch[0]) {
fcaf780b
MCC		 770 i7300_printk(KERN_ERR,
771 "MC: 'BRANCH 0' device not found:"
772 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
773 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0);
774 goto error;
775 }
776
3e57eef6 777 pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
fcaf780b
MCC		 778 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1,
779 NULL);
3e57eef6 780 if (!pvt->pci_dev_2x_0_fbd_branch[1]) {
fcaf780b
MCC		 781 i7300_printk(KERN_ERR,
782 "MC: 'BRANCH 1' device not found:"
783 "vendor 0x%x device 0x%x Func 0 "
784 "(broken BIOS?)\n",
785 PCI_VENDOR_ID_INTEL,
786 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1);
787 goto error;
788 }
789
790 return 0;
791
792error:
793 i7300_put_devices(mci);
794 return -ENODEV;
795}
796
797/*
798 * i7300_probe1 Probe for ONE instance of device to see if it is
799 * present.
800 * return:
801 * 0 for FOUND a device
802 * < 0 for error code
803 */
804static int i7300_probe1(struct pci_dev *pdev, int dev_idx)
805{
806 struct mem_ctl_info *mci;
807 struct i7300_pvt *pvt;
808 int num_channels;
809 int num_dimms_per_channel;
810 int num_csrows;
811
812 if (dev_idx >= ARRAY_SIZE(i7300_devs))
813 return -EINVAL;
814
815 debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
816 __func__,
817 pdev->bus->number,
818 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
819
820 /* We only are looking for func 0 of the set */
821 if (PCI_FUNC(pdev->devfn) != 0)
822 return -ENODEV;
823
824 /* As we don't have a motherboard identification routine to determine
825 * actual number of slots/dimms per channel, we thus utilize the
826 * resource as specified by the chipset. Thus, we might have
827 * have more DIMMs per channel than actually on the mobo, but this
828 * allows the driver to support upto the chipset max, without
829 * some fancy mobo determination.
830 */
831 num_dimms_per_channel = MAX_SLOTS;
832 num_channels = MAX_CHANNELS;
833 num_csrows = MAX_SLOTS * MAX_CHANNELS;
834
835 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
836 __func__, num_channels, num_dimms_per_channel, num_csrows);
837
838 /* allocate a new MC control structure */
839 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
840
841 if (mci == NULL)
842 return -ENOMEM;
843
844 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
845
846 mci->dev = &pdev->dev; /* record ptr to the generic device */
847
848 pvt = mci->pvt_info;
3e57eef6 849 pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */
fcaf780b
MCC		 850
851 /* 'get' the pci devices we want to reserve for our use */
852 if (i7300_get_devices(mci, dev_idx))
853 goto fail0;
854
855 mci->mc_idx = 0;
856 mci->mtype_cap = MEM_FLAG_FB_DDR2;
857 mci->edac_ctl_cap = EDAC_FLAG_NONE;
858 mci->edac_cap = EDAC_FLAG_NONE;
859 mci->mod_name = "i7300_edac.c";
860 mci->mod_ver = I7300_REVISION;
861 mci->ctl_name = i7300_devs[dev_idx].ctl_name;
862 mci->dev_name = pci_name(pdev);
863 mci->ctl_page_to_phys = NULL;
864
fcaf780b
MCC		 865 /* Set the function pointer to an actual operation function */
866 mci->edac_check = i7300_check_error;
fcaf780b
MCC		 867
868 /* initialize the MC control structure 'csrows' table
869 * with the mapping and control information */
870 if (i7300_get_mc_regs(mci)) {
871 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
872 " because i7300_init_csrows() returned nonzero "
873 "value\n");
874 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
875 } else {
fcaf780b
MCC		 876 debugf1("MC: Enable error reporting now\n");
877 i7300_enable_error_reporting(mci);
fcaf780b
MCC		 878 }
879
880 /* add this new MC control structure to EDAC's list of MCs */
881 if (edac_mc_add_mc(mci)) {
882 debugf0("MC: " __FILE__
883 ": %s(): failed edac_mc_add_mc()\n", __func__);
884 /* FIXME: perhaps some code should go here that disables error
885 * reporting if we just enabled it
886 */
887 goto fail1;
888 }
889
fcaf780b 890 i7300_clear_error(mci);
fcaf780b
MCC		 891
892 /* allocating generic PCI control info */
893 i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
894 if (!i7300_pci) {
895 printk(KERN_WARNING
896 "%s(): Unable to create PCI control\n",
897 __func__);
898 printk(KERN_WARNING
899 "%s(): PCI error report via EDAC not setup\n",
900 __func__);
901 }
902
903 return 0;
904
905 /* Error exit unwinding stack */
906fail1:
907
908 i7300_put_devices(mci);
909
910fail0:
911 edac_mc_free(mci);
912 return -ENODEV;
913}
914
915/*
916 * i7300_init_one constructor for one instance of device
917 *
918 * returns:
919 * negative on error
920 * count (>= 0)
921 */
922static int __devinit i7300_init_one(struct pci_dev *pdev,
923 const struct pci_device_id *id)
924{
925 int rc;
926
927 debugf0("MC: " __FILE__ ": %s()\n", __func__);
928
929 /* wake up device */
930 rc = pci_enable_device(pdev);
931 if (rc == -EIO)
932 return rc;
933
934 /* now probe and enable the device */
935 return i7300_probe1(pdev, id->driver_data);
936}
937
938/*
939 * i7300_remove_one destructor for one instance of device
940 *
941 */
942static void __devexit i7300_remove_one(struct pci_dev *pdev)
943{
944 struct mem_ctl_info *mci;
945
946 debugf0(__FILE__ ": %s()\n", __func__);
947
948 if (i7300_pci)
949 edac_pci_release_generic_ctl(i7300_pci);
950
951 mci = edac_mc_del_mc(&pdev->dev);
952 if (!mci)
953 return;
954
955 /* retrieve references to resources, and free those resources */
956 i7300_put_devices(mci);
957
958 edac_mc_free(mci);
959}
960
961/*
962 * pci_device_id table for which devices we are looking for
963 *
964 * The "E500P" device is the first device supported.
965 */
966static const struct pci_device_id i7300_pci_tbl[] __devinitdata = {
967 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
968 {0,} /* 0 terminated list. */
969};
970
971MODULE_DEVICE_TABLE(pci, i7300_pci_tbl);
972
973/*
974 * i7300_driver pci_driver structure for this module
975 *
976 */
977static struct pci_driver i7300_driver = {
978 .name = "i7300_edac",
979 .probe = i7300_init_one,
980 .remove = __devexit_p(i7300_remove_one),
981 .id_table = i7300_pci_tbl,
982};
983
984/*
985 * i7300_init Module entry function
986 * Try to initialize this module for its devices
987 */
988static int __init i7300_init(void)
989{
990 int pci_rc;
991
992 debugf2("MC: " __FILE__ ": %s()\n", __func__);
993
994 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
995 opstate_init();
996
997 pci_rc = pci_register_driver(&i7300_driver);
998
999 return (pci_rc < 0) ? pci_rc : 0;
1000}
1001
1002/*
1003 * i7300_exit() Module exit function
1004 * Unregister the driver
1005 */
1006static void __exit i7300_exit(void)
1007{
1008 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1009 pci_unregister_driver(&i7300_driver);
1010}
1011
1012module_init(i7300_init);
1013module_exit(i7300_exit);
1014
1015MODULE_LICENSE("GPL");
1016MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1017MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1018MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
1019 I7300_REVISION);
1020
1021module_param(edac_op_state, int, 0444);
1022MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
kernel source for telekom puls (alcatel/mediatek)