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8f421c59 AJ |
1 | /* |
2 | * Intel 5100 Memory Controllers kernel module | |
3 | * | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * This module is based on the following document: | |
8 | * | |
9 | * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet | |
10 | * http://download.intel.com/design/chipsets/datashts/318378.pdf | |
11 | * | |
bbead210 NC |
12 | * The intel 5100 has two independent channels. EDAC core currently |
13 | * can not reflect this configuration so instead the chip-select | |
14 | * rows for each respective channel are layed out one after another, | |
15 | * the first half belonging to channel 0, the second half belonging | |
16 | * to channel 1. | |
8f421c59 AJ |
17 | */ |
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/pci_ids.h> | |
8f421c59 AJ |
22 | #include <linux/edac.h> |
23 | #include <linux/delay.h> | |
24 | #include <linux/mmzone.h> | |
25 | ||
26 | #include "edac_core.h" | |
27 | ||
b238e577 | 28 | /* register addresses */ |
8f421c59 AJ |
29 | |
30 | /* device 16, func 1 */ | |
43920a59 | 31 | #define I5100_MC 0x40 /* Memory Control Register */ |
295439f2 NC |
32 | #define I5100_MC_SCRBEN_MASK (1 << 7) |
33 | #define I5100_MC_SCRBDONE_MASK (1 << 4) | |
8f421c59 AJ |
34 | #define I5100_MS 0x44 /* Memory Status Register */ |
35 | #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */ | |
8f421c59 | 36 | #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */ |
8f421c59 | 37 | #define I5100_TOLM 0x6c /* Top of Low Memory */ |
8f421c59 AJ |
38 | #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */ |
39 | #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */ | |
40 | #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */ | |
41 | #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */ | |
8f421c59 | 42 | #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */ |
8f421c59 AJ |
43 | #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16) |
44 | #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15) | |
45 | #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14) | |
f7952ffc AJ |
46 | #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12) |
47 | #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11) | |
48 | #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10) | |
49 | #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6) | |
50 | #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5) | |
51 | #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4) | |
52 | #define I5100_FERR_NF_MEM_M1ERR_MASK 1 | |
8f421c59 AJ |
53 | #define I5100_FERR_NF_MEM_ANY_MASK \ |
54 | (I5100_FERR_NF_MEM_M16ERR_MASK | \ | |
55 | I5100_FERR_NF_MEM_M15ERR_MASK | \ | |
f7952ffc AJ |
56 | I5100_FERR_NF_MEM_M14ERR_MASK | \ |
57 | I5100_FERR_NF_MEM_M12ERR_MASK | \ | |
58 | I5100_FERR_NF_MEM_M11ERR_MASK | \ | |
59 | I5100_FERR_NF_MEM_M10ERR_MASK | \ | |
60 | I5100_FERR_NF_MEM_M6ERR_MASK | \ | |
61 | I5100_FERR_NF_MEM_M5ERR_MASK | \ | |
62 | I5100_FERR_NF_MEM_M4ERR_MASK | \ | |
63 | I5100_FERR_NF_MEM_M1ERR_MASK) | |
8f421c59 | 64 | #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */ |
178d5a74 | 65 | #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */ |
8f421c59 AJ |
66 | |
67 | /* device 21 and 22, func 0 */ | |
68 | #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */ | |
69 | #define I5100_DMIR 0x15c /* DIMM Interleave Range */ | |
8f421c59 | 70 | #define I5100_VALIDLOG 0x18c /* Valid Log Markers */ |
8f421c59 | 71 | #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */ |
8f421c59 | 72 | #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */ |
8f421c59 | 73 | #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */ |
8f421c59 | 74 | #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */ |
8f421c59 | 75 | #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */ |
8f421c59 | 76 | #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */ |
b238e577 AJ |
77 | #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */ |
78 | ||
79 | /* bit field accessors */ | |
80 | ||
295439f2 NC |
81 | static inline u32 i5100_mc_scrben(u32 mc) |
82 | { | |
83 | return mc >> 7 & 1; | |
84 | } | |
85 | ||
b238e577 AJ |
86 | static inline u32 i5100_mc_errdeten(u32 mc) |
87 | { | |
88 | return mc >> 5 & 1; | |
89 | } | |
90 | ||
295439f2 NC |
91 | static inline u32 i5100_mc_scrbdone(u32 mc) |
92 | { | |
93 | return mc >> 4 & 1; | |
94 | } | |
95 | ||
b238e577 AJ |
96 | static inline u16 i5100_spddata_rdo(u16 a) |
97 | { | |
98 | return a >> 15 & 1; | |
99 | } | |
100 | ||
101 | static inline u16 i5100_spddata_sbe(u16 a) | |
102 | { | |
103 | return a >> 13 & 1; | |
104 | } | |
105 | ||
106 | static inline u16 i5100_spddata_busy(u16 a) | |
107 | { | |
108 | return a >> 12 & 1; | |
109 | } | |
110 | ||
111 | static inline u16 i5100_spddata_data(u16 a) | |
112 | { | |
113 | return a & ((1 << 8) - 1); | |
114 | } | |
115 | ||
116 | static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba, | |
117 | u32 data, u32 cmd) | |
118 | { | |
119 | return ((dti & ((1 << 4) - 1)) << 28) | | |
120 | ((ckovrd & 1) << 27) | | |
121 | ((sa & ((1 << 3) - 1)) << 24) | | |
122 | ((ba & ((1 << 8) - 1)) << 16) | | |
123 | ((data & ((1 << 8) - 1)) << 8) | | |
124 | (cmd & 1); | |
125 | } | |
126 | ||
127 | static inline u16 i5100_tolm_tolm(u16 a) | |
128 | { | |
129 | return a >> 12 & ((1 << 4) - 1); | |
130 | } | |
131 | ||
132 | static inline u16 i5100_mir_limit(u16 a) | |
133 | { | |
134 | return a >> 4 & ((1 << 12) - 1); | |
135 | } | |
136 | ||
137 | static inline u16 i5100_mir_way1(u16 a) | |
138 | { | |
139 | return a >> 1 & 1; | |
140 | } | |
141 | ||
142 | static inline u16 i5100_mir_way0(u16 a) | |
143 | { | |
144 | return a & 1; | |
145 | } | |
146 | ||
147 | static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a) | |
148 | { | |
149 | return a >> 28 & 1; | |
150 | } | |
151 | ||
152 | static inline u32 i5100_ferr_nf_mem_any(u32 a) | |
153 | { | |
154 | return a & I5100_FERR_NF_MEM_ANY_MASK; | |
155 | } | |
156 | ||
157 | static inline u32 i5100_nerr_nf_mem_any(u32 a) | |
158 | { | |
159 | return i5100_ferr_nf_mem_any(a); | |
160 | } | |
161 | ||
162 | static inline u32 i5100_dmir_limit(u32 a) | |
163 | { | |
164 | return a >> 16 & ((1 << 11) - 1); | |
165 | } | |
166 | ||
167 | static inline u32 i5100_dmir_rank(u32 a, u32 i) | |
168 | { | |
169 | return a >> (4 * i) & ((1 << 2) - 1); | |
170 | } | |
171 | ||
172 | static inline u16 i5100_mtr_present(u16 a) | |
173 | { | |
174 | return a >> 10 & 1; | |
175 | } | |
176 | ||
177 | static inline u16 i5100_mtr_ethrottle(u16 a) | |
178 | { | |
179 | return a >> 9 & 1; | |
180 | } | |
181 | ||
182 | static inline u16 i5100_mtr_width(u16 a) | |
183 | { | |
184 | return a >> 8 & 1; | |
185 | } | |
186 | ||
187 | static inline u16 i5100_mtr_numbank(u16 a) | |
188 | { | |
189 | return a >> 6 & 1; | |
190 | } | |
191 | ||
192 | static inline u16 i5100_mtr_numrow(u16 a) | |
193 | { | |
194 | return a >> 2 & ((1 << 2) - 1); | |
195 | } | |
196 | ||
197 | static inline u16 i5100_mtr_numcol(u16 a) | |
198 | { | |
199 | return a & ((1 << 2) - 1); | |
200 | } | |
201 | ||
202 | ||
203 | static inline u32 i5100_validlog_redmemvalid(u32 a) | |
204 | { | |
205 | return a >> 2 & 1; | |
206 | } | |
207 | ||
208 | static inline u32 i5100_validlog_recmemvalid(u32 a) | |
209 | { | |
210 | return a >> 1 & 1; | |
211 | } | |
212 | ||
213 | static inline u32 i5100_validlog_nrecmemvalid(u32 a) | |
214 | { | |
215 | return a & 1; | |
216 | } | |
217 | ||
218 | static inline u32 i5100_nrecmema_merr(u32 a) | |
219 | { | |
220 | return a >> 15 & ((1 << 5) - 1); | |
221 | } | |
222 | ||
223 | static inline u32 i5100_nrecmema_bank(u32 a) | |
224 | { | |
225 | return a >> 12 & ((1 << 3) - 1); | |
226 | } | |
227 | ||
228 | static inline u32 i5100_nrecmema_rank(u32 a) | |
229 | { | |
230 | return a >> 8 & ((1 << 3) - 1); | |
231 | } | |
232 | ||
233 | static inline u32 i5100_nrecmema_dm_buf_id(u32 a) | |
234 | { | |
235 | return a & ((1 << 8) - 1); | |
236 | } | |
237 | ||
238 | static inline u32 i5100_nrecmemb_cas(u32 a) | |
239 | { | |
240 | return a >> 16 & ((1 << 13) - 1); | |
241 | } | |
242 | ||
243 | static inline u32 i5100_nrecmemb_ras(u32 a) | |
244 | { | |
245 | return a & ((1 << 16) - 1); | |
246 | } | |
247 | ||
248 | static inline u32 i5100_redmemb_ecc_locator(u32 a) | |
249 | { | |
250 | return a & ((1 << 18) - 1); | |
251 | } | |
252 | ||
253 | static inline u32 i5100_recmema_merr(u32 a) | |
254 | { | |
255 | return i5100_nrecmema_merr(a); | |
256 | } | |
257 | ||
258 | static inline u32 i5100_recmema_bank(u32 a) | |
259 | { | |
260 | return i5100_nrecmema_bank(a); | |
261 | } | |
262 | ||
263 | static inline u32 i5100_recmema_rank(u32 a) | |
264 | { | |
265 | return i5100_nrecmema_rank(a); | |
266 | } | |
267 | ||
268 | static inline u32 i5100_recmema_dm_buf_id(u32 a) | |
269 | { | |
270 | return i5100_nrecmema_dm_buf_id(a); | |
271 | } | |
272 | ||
273 | static inline u32 i5100_recmemb_cas(u32 a) | |
274 | { | |
275 | return i5100_nrecmemb_cas(a); | |
276 | } | |
277 | ||
278 | static inline u32 i5100_recmemb_ras(u32 a) | |
279 | { | |
280 | return i5100_nrecmemb_ras(a); | |
281 | } | |
8f421c59 AJ |
282 | |
283 | /* some generic limits */ | |
b18dfd05 NC |
284 | #define I5100_MAX_RANKS_PER_CHAN 6 |
285 | #define I5100_CHANNELS 2 | |
8f421c59 AJ |
286 | #define I5100_MAX_RANKS_PER_DIMM 4 |
287 | #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */ | |
b18dfd05 | 288 | #define I5100_MAX_DIMM_SLOTS_PER_CHAN 4 |
8f421c59 AJ |
289 | #define I5100_MAX_RANK_INTERLEAVE 4 |
290 | #define I5100_MAX_DMIRS 5 | |
295439f2 | 291 | #define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ) |
8f421c59 AJ |
292 | |
293 | struct i5100_priv { | |
294 | /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */ | |
b18dfd05 | 295 | int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN]; |
8f421c59 AJ |
296 | |
297 | /* | |
298 | * mainboard chip select map -- maps i5100 chip selects to | |
299 | * DIMM slot chip selects. In the case of only 4 ranks per | |
b18dfd05 NC |
300 | * channel, the mapping is fairly obvious but not unique. |
301 | * we map -1 -> NC and assume both channels use the same | |
8f421c59 AJ |
302 | * map... |
303 | * | |
304 | */ | |
b18dfd05 | 305 | int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM]; |
8f421c59 AJ |
306 | |
307 | /* memory interleave range */ | |
308 | struct { | |
309 | u64 limit; | |
310 | unsigned way[2]; | |
b18dfd05 | 311 | } mir[I5100_CHANNELS]; |
8f421c59 AJ |
312 | |
313 | /* adjusted memory interleave range register */ | |
b18dfd05 | 314 | unsigned amir[I5100_CHANNELS]; |
8f421c59 AJ |
315 | |
316 | /* dimm interleave range */ | |
317 | struct { | |
318 | unsigned rank[I5100_MAX_RANK_INTERLEAVE]; | |
319 | u64 limit; | |
b18dfd05 | 320 | } dmir[I5100_CHANNELS][I5100_MAX_DMIRS]; |
8f421c59 AJ |
321 | |
322 | /* memory technology registers... */ | |
323 | struct { | |
324 | unsigned present; /* 0 or 1 */ | |
325 | unsigned ethrottle; /* 0 or 1 */ | |
326 | unsigned width; /* 4 or 8 bits */ | |
327 | unsigned numbank; /* 2 or 3 lines */ | |
328 | unsigned numrow; /* 13 .. 16 lines */ | |
329 | unsigned numcol; /* 11 .. 12 lines */ | |
b18dfd05 | 330 | } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; |
8f421c59 AJ |
331 | |
332 | u64 tolm; /* top of low memory in bytes */ | |
b18dfd05 | 333 | unsigned ranksperchan; /* number of ranks per channel */ |
8f421c59 AJ |
334 | |
335 | struct pci_dev *mc; /* device 16 func 1 */ | |
336 | struct pci_dev *ch0mm; /* device 21 func 0 */ | |
337 | struct pci_dev *ch1mm; /* device 22 func 0 */ | |
295439f2 NC |
338 | |
339 | struct delayed_work i5100_scrubbing; | |
340 | int scrub_enable; | |
8f421c59 AJ |
341 | }; |
342 | ||
b18dfd05 | 343 | /* map a rank/chan to a slot number on the mainboard */ |
8f421c59 | 344 | static int i5100_rank_to_slot(const struct mem_ctl_info *mci, |
b18dfd05 | 345 | int chan, int rank) |
8f421c59 AJ |
346 | { |
347 | const struct i5100_priv *priv = mci->pvt_info; | |
348 | int i; | |
349 | ||
b18dfd05 | 350 | for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { |
8f421c59 | 351 | int j; |
b18dfd05 | 352 | const int numrank = priv->dimm_numrank[chan][i]; |
8f421c59 AJ |
353 | |
354 | for (j = 0; j < numrank; j++) | |
355 | if (priv->dimm_csmap[i][j] == rank) | |
b18dfd05 | 356 | return i * 2 + chan; |
8f421c59 AJ |
357 | } |
358 | ||
359 | return -1; | |
360 | } | |
361 | ||
8f421c59 AJ |
362 | static const char *i5100_err_msg(unsigned err) |
363 | { | |
b238e577 | 364 | static const char *merrs[] = { |
8f421c59 AJ |
365 | "unknown", /* 0 */ |
366 | "uncorrectable data ECC on replay", /* 1 */ | |
367 | "unknown", /* 2 */ | |
368 | "unknown", /* 3 */ | |
369 | "aliased uncorrectable demand data ECC", /* 4 */ | |
370 | "aliased uncorrectable spare-copy data ECC", /* 5 */ | |
371 | "aliased uncorrectable patrol data ECC", /* 6 */ | |
372 | "unknown", /* 7 */ | |
373 | "unknown", /* 8 */ | |
374 | "unknown", /* 9 */ | |
375 | "non-aliased uncorrectable demand data ECC", /* 10 */ | |
376 | "non-aliased uncorrectable spare-copy data ECC", /* 11 */ | |
377 | "non-aliased uncorrectable patrol data ECC", /* 12 */ | |
378 | "unknown", /* 13 */ | |
379 | "correctable demand data ECC", /* 14 */ | |
380 | "correctable spare-copy data ECC", /* 15 */ | |
381 | "correctable patrol data ECC", /* 16 */ | |
382 | "unknown", /* 17 */ | |
383 | "SPD protocol error", /* 18 */ | |
384 | "unknown", /* 19 */ | |
385 | "spare copy initiated", /* 20 */ | |
386 | "spare copy completed", /* 21 */ | |
387 | }; | |
388 | unsigned i; | |
389 | ||
390 | for (i = 0; i < ARRAY_SIZE(merrs); i++) | |
391 | if (1 << i & err) | |
392 | return merrs[i]; | |
393 | ||
394 | return "none"; | |
395 | } | |
396 | ||
b18dfd05 | 397 | /* convert csrow index into a rank (per channel -- 0..5) */ |
8f421c59 AJ |
398 | static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow) |
399 | { | |
400 | const struct i5100_priv *priv = mci->pvt_info; | |
401 | ||
b18dfd05 | 402 | return csrow % priv->ranksperchan; |
8f421c59 AJ |
403 | } |
404 | ||
b18dfd05 NC |
405 | /* convert csrow index into a channel (0..1) */ |
406 | static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow) | |
8f421c59 AJ |
407 | { |
408 | const struct i5100_priv *priv = mci->pvt_info; | |
409 | ||
b18dfd05 | 410 | return csrow / priv->ranksperchan; |
8f421c59 AJ |
411 | } |
412 | ||
413 | static unsigned i5100_rank_to_csrow(const struct mem_ctl_info *mci, | |
b18dfd05 | 414 | int chan, int rank) |
8f421c59 AJ |
415 | { |
416 | const struct i5100_priv *priv = mci->pvt_info; | |
417 | ||
b18dfd05 | 418 | return chan * priv->ranksperchan + rank; |
8f421c59 AJ |
419 | } |
420 | ||
421 | static void i5100_handle_ce(struct mem_ctl_info *mci, | |
b18dfd05 | 422 | int chan, |
8f421c59 AJ |
423 | unsigned bank, |
424 | unsigned rank, | |
425 | unsigned long syndrome, | |
426 | unsigned cas, | |
427 | unsigned ras, | |
428 | const char *msg) | |
429 | { | |
b18dfd05 | 430 | const int csrow = i5100_rank_to_csrow(mci, chan, rank); |
8f421c59 AJ |
431 | |
432 | printk(KERN_ERR | |
b18dfd05 | 433 | "CE chan %d, bank %u, rank %u, syndrome 0x%lx, " |
8f421c59 | 434 | "cas %u, ras %u, csrow %u, label \"%s\": %s\n", |
b18dfd05 | 435 | chan, bank, rank, syndrome, cas, ras, |
8f421c59 AJ |
436 | csrow, mci->csrows[csrow].channels[0].label, msg); |
437 | ||
438 | mci->ce_count++; | |
439 | mci->csrows[csrow].ce_count++; | |
440 | mci->csrows[csrow].channels[0].ce_count++; | |
441 | } | |
442 | ||
443 | static void i5100_handle_ue(struct mem_ctl_info *mci, | |
b18dfd05 | 444 | int chan, |
8f421c59 AJ |
445 | unsigned bank, |
446 | unsigned rank, | |
447 | unsigned long syndrome, | |
448 | unsigned cas, | |
449 | unsigned ras, | |
450 | const char *msg) | |
451 | { | |
b18dfd05 | 452 | const int csrow = i5100_rank_to_csrow(mci, chan, rank); |
8f421c59 AJ |
453 | |
454 | printk(KERN_ERR | |
b18dfd05 | 455 | "UE chan %d, bank %u, rank %u, syndrome 0x%lx, " |
8f421c59 | 456 | "cas %u, ras %u, csrow %u, label \"%s\": %s\n", |
b18dfd05 | 457 | chan, bank, rank, syndrome, cas, ras, |
8f421c59 AJ |
458 | csrow, mci->csrows[csrow].channels[0].label, msg); |
459 | ||
460 | mci->ue_count++; | |
461 | mci->csrows[csrow].ue_count++; | |
462 | } | |
463 | ||
b18dfd05 | 464 | static void i5100_read_log(struct mem_ctl_info *mci, int chan, |
8f421c59 AJ |
465 | u32 ferr, u32 nerr) |
466 | { | |
467 | struct i5100_priv *priv = mci->pvt_info; | |
b18dfd05 | 468 | struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm; |
8f421c59 AJ |
469 | u32 dw; |
470 | u32 dw2; | |
471 | unsigned syndrome = 0; | |
472 | unsigned ecc_loc = 0; | |
473 | unsigned merr; | |
474 | unsigned bank; | |
475 | unsigned rank; | |
476 | unsigned cas; | |
477 | unsigned ras; | |
478 | ||
479 | pci_read_config_dword(pdev, I5100_VALIDLOG, &dw); | |
480 | ||
b238e577 | 481 | if (i5100_validlog_redmemvalid(dw)) { |
8f421c59 | 482 | pci_read_config_dword(pdev, I5100_REDMEMA, &dw2); |
b238e577 | 483 | syndrome = dw2; |
8f421c59 | 484 | pci_read_config_dword(pdev, I5100_REDMEMB, &dw2); |
b238e577 | 485 | ecc_loc = i5100_redmemb_ecc_locator(dw2); |
8f421c59 AJ |
486 | } |
487 | ||
b238e577 | 488 | if (i5100_validlog_recmemvalid(dw)) { |
8f421c59 AJ |
489 | const char *msg; |
490 | ||
491 | pci_read_config_dword(pdev, I5100_RECMEMA, &dw2); | |
b238e577 AJ |
492 | merr = i5100_recmema_merr(dw2); |
493 | bank = i5100_recmema_bank(dw2); | |
494 | rank = i5100_recmema_rank(dw2); | |
8f421c59 AJ |
495 | |
496 | pci_read_config_dword(pdev, I5100_RECMEMB, &dw2); | |
b238e577 AJ |
497 | cas = i5100_recmemb_cas(dw2); |
498 | ras = i5100_recmemb_ras(dw2); | |
8f421c59 AJ |
499 | |
500 | /* FIXME: not really sure if this is what merr is... | |
501 | */ | |
502 | if (!merr) | |
503 | msg = i5100_err_msg(ferr); | |
504 | else | |
505 | msg = i5100_err_msg(nerr); | |
506 | ||
b18dfd05 | 507 | i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); |
8f421c59 AJ |
508 | } |
509 | ||
b238e577 | 510 | if (i5100_validlog_nrecmemvalid(dw)) { |
8f421c59 AJ |
511 | const char *msg; |
512 | ||
513 | pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2); | |
b238e577 AJ |
514 | merr = i5100_nrecmema_merr(dw2); |
515 | bank = i5100_nrecmema_bank(dw2); | |
516 | rank = i5100_nrecmema_rank(dw2); | |
8f421c59 AJ |
517 | |
518 | pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2); | |
b238e577 AJ |
519 | cas = i5100_nrecmemb_cas(dw2); |
520 | ras = i5100_nrecmemb_ras(dw2); | |
8f421c59 AJ |
521 | |
522 | /* FIXME: not really sure if this is what merr is... | |
523 | */ | |
524 | if (!merr) | |
525 | msg = i5100_err_msg(ferr); | |
526 | else | |
527 | msg = i5100_err_msg(nerr); | |
528 | ||
b18dfd05 | 529 | i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); |
8f421c59 AJ |
530 | } |
531 | ||
532 | pci_write_config_dword(pdev, I5100_VALIDLOG, dw); | |
533 | } | |
534 | ||
535 | static void i5100_check_error(struct mem_ctl_info *mci) | |
536 | { | |
537 | struct i5100_priv *priv = mci->pvt_info; | |
538 | u32 dw; | |
539 | ||
540 | ||
541 | pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw); | |
b238e577 | 542 | if (i5100_ferr_nf_mem_any(dw)) { |
8f421c59 AJ |
543 | u32 dw2; |
544 | ||
545 | pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2); | |
546 | if (dw2) | |
547 | pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, | |
548 | dw2); | |
549 | pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); | |
550 | ||
b238e577 AJ |
551 | i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw), |
552 | i5100_ferr_nf_mem_any(dw), | |
553 | i5100_nerr_nf_mem_any(dw2)); | |
8f421c59 AJ |
554 | } |
555 | } | |
556 | ||
295439f2 NC |
557 | /* The i5100 chipset will scrub the entire memory once, then |
558 | * set a done bit. Continuous scrubbing is achieved by enqueing | |
559 | * delayed work to a workqueue, checking every few minutes if | |
560 | * the scrubbing has completed and if so reinitiating it. | |
561 | */ | |
562 | ||
563 | static void i5100_refresh_scrubbing(struct work_struct *work) | |
564 | { | |
565 | struct delayed_work *i5100_scrubbing = container_of(work, | |
566 | struct delayed_work, | |
567 | work); | |
568 | struct i5100_priv *priv = container_of(i5100_scrubbing, | |
569 | struct i5100_priv, | |
570 | i5100_scrubbing); | |
571 | u32 dw; | |
572 | ||
573 | pci_read_config_dword(priv->mc, I5100_MC, &dw); | |
574 | ||
575 | if (priv->scrub_enable) { | |
576 | ||
577 | pci_read_config_dword(priv->mc, I5100_MC, &dw); | |
578 | ||
579 | if (i5100_mc_scrbdone(dw)) { | |
580 | dw |= I5100_MC_SCRBEN_MASK; | |
581 | pci_write_config_dword(priv->mc, I5100_MC, dw); | |
582 | pci_read_config_dword(priv->mc, I5100_MC, &dw); | |
583 | } | |
584 | ||
585 | schedule_delayed_work(&(priv->i5100_scrubbing), | |
586 | I5100_SCRUB_REFRESH_RATE); | |
587 | } | |
588 | } | |
589 | /* | |
590 | * The bandwidth is based on experimentation, feel free to refine it. | |
591 | */ | |
592 | static int i5100_set_scrub_rate(struct mem_ctl_info *mci, | |
593 | u32 *bandwidth) | |
594 | { | |
595 | struct i5100_priv *priv = mci->pvt_info; | |
596 | u32 dw; | |
597 | ||
598 | pci_read_config_dword(priv->mc, I5100_MC, &dw); | |
599 | if (*bandwidth) { | |
600 | priv->scrub_enable = 1; | |
601 | dw |= I5100_MC_SCRBEN_MASK; | |
602 | schedule_delayed_work(&(priv->i5100_scrubbing), | |
603 | I5100_SCRUB_REFRESH_RATE); | |
604 | } else { | |
605 | priv->scrub_enable = 0; | |
606 | dw &= ~I5100_MC_SCRBEN_MASK; | |
607 | cancel_delayed_work(&(priv->i5100_scrubbing)); | |
608 | } | |
609 | pci_write_config_dword(priv->mc, I5100_MC, dw); | |
610 | ||
611 | pci_read_config_dword(priv->mc, I5100_MC, &dw); | |
612 | ||
613 | *bandwidth = 5900000 * i5100_mc_scrben(dw); | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | static int i5100_get_scrub_rate(struct mem_ctl_info *mci, | |
619 | u32 *bandwidth) | |
620 | { | |
621 | struct i5100_priv *priv = mci->pvt_info; | |
622 | u32 dw; | |
623 | ||
624 | pci_read_config_dword(priv->mc, I5100_MC, &dw); | |
625 | ||
626 | *bandwidth = 5900000 * i5100_mc_scrben(dw); | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
8f421c59 AJ |
631 | static struct pci_dev *pci_get_device_func(unsigned vendor, |
632 | unsigned device, | |
633 | unsigned func) | |
634 | { | |
635 | struct pci_dev *ret = NULL; | |
636 | ||
637 | while (1) { | |
638 | ret = pci_get_device(vendor, device, ret); | |
639 | ||
640 | if (!ret) | |
641 | break; | |
642 | ||
643 | if (PCI_FUNC(ret->devfn) == func) | |
644 | break; | |
645 | } | |
646 | ||
647 | return ret; | |
648 | } | |
649 | ||
650 | static unsigned long __devinit i5100_npages(struct mem_ctl_info *mci, | |
651 | int csrow) | |
652 | { | |
653 | struct i5100_priv *priv = mci->pvt_info; | |
b18dfd05 NC |
654 | const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow); |
655 | const unsigned chan = i5100_csrow_to_chan(mci, csrow); | |
8f421c59 AJ |
656 | unsigned addr_lines; |
657 | ||
658 | /* dimm present? */ | |
b18dfd05 | 659 | if (!priv->mtr[chan][chan_rank].present) |
8f421c59 AJ |
660 | return 0ULL; |
661 | ||
662 | addr_lines = | |
663 | I5100_DIMM_ADDR_LINES + | |
b18dfd05 NC |
664 | priv->mtr[chan][chan_rank].numcol + |
665 | priv->mtr[chan][chan_rank].numrow + | |
666 | priv->mtr[chan][chan_rank].numbank; | |
8f421c59 AJ |
667 | |
668 | return (unsigned long) | |
669 | ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE); | |
670 | } | |
671 | ||
672 | static void __devinit i5100_init_mtr(struct mem_ctl_info *mci) | |
673 | { | |
674 | struct i5100_priv *priv = mci->pvt_info; | |
675 | struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; | |
676 | int i; | |
677 | ||
b18dfd05 | 678 | for (i = 0; i < I5100_CHANNELS; i++) { |
8f421c59 AJ |
679 | int j; |
680 | struct pci_dev *pdev = mms[i]; | |
681 | ||
b18dfd05 | 682 | for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) { |
8f421c59 AJ |
683 | const unsigned addr = |
684 | (j < 4) ? I5100_MTR_0 + j * 2 : | |
685 | I5100_MTR_4 + (j - 4) * 2; | |
686 | u16 w; | |
687 | ||
688 | pci_read_config_word(pdev, addr, &w); | |
689 | ||
b238e577 AJ |
690 | priv->mtr[i][j].present = i5100_mtr_present(w); |
691 | priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); | |
692 | priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); | |
693 | priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w); | |
694 | priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); | |
695 | priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w); | |
8f421c59 AJ |
696 | } |
697 | } | |
698 | } | |
699 | ||
700 | /* | |
701 | * FIXME: make this into a real i2c adapter (so that dimm-decode | |
702 | * will work)? | |
703 | */ | |
704 | static int i5100_read_spd_byte(const struct mem_ctl_info *mci, | |
705 | u8 ch, u8 slot, u8 addr, u8 *byte) | |
706 | { | |
707 | struct i5100_priv *priv = mci->pvt_info; | |
708 | u16 w; | |
8f421c59 AJ |
709 | unsigned long et; |
710 | ||
711 | pci_read_config_word(priv->mc, I5100_SPDDATA, &w); | |
b238e577 | 712 | if (i5100_spddata_busy(w)) |
8f421c59 AJ |
713 | return -1; |
714 | ||
b238e577 AJ |
715 | pci_write_config_dword(priv->mc, I5100_SPDCMD, |
716 | i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr, | |
717 | 0, 0)); | |
8f421c59 AJ |
718 | |
719 | /* wait up to 100ms */ | |
720 | et = jiffies + HZ / 10; | |
721 | udelay(100); | |
722 | while (1) { | |
723 | pci_read_config_word(priv->mc, I5100_SPDDATA, &w); | |
b238e577 | 724 | if (!i5100_spddata_busy(w)) |
8f421c59 AJ |
725 | break; |
726 | udelay(100); | |
727 | } | |
728 | ||
b238e577 | 729 | if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w)) |
8f421c59 AJ |
730 | return -1; |
731 | ||
b238e577 | 732 | *byte = i5100_spddata_data(w); |
8f421c59 AJ |
733 | |
734 | return 0; | |
735 | } | |
736 | ||
737 | /* | |
738 | * fill dimm chip select map | |
739 | * | |
740 | * FIXME: | |
8f421c59 AJ |
741 | * o not the only way to may chip selects to dimm slots |
742 | * o investigate if there is some way to obtain this map from the bios | |
743 | */ | |
744 | static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci) | |
745 | { | |
746 | struct i5100_priv *priv = mci->pvt_info; | |
747 | int i; | |
748 | ||
b18dfd05 | 749 | for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { |
8f421c59 AJ |
750 | int j; |
751 | ||
752 | for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++) | |
753 | priv->dimm_csmap[i][j] = -1; /* default NC */ | |
754 | } | |
755 | ||
756 | /* only 2 chip selects per slot... */ | |
bbead210 NC |
757 | if (priv->ranksperchan == 4) { |
758 | priv->dimm_csmap[0][0] = 0; | |
759 | priv->dimm_csmap[0][1] = 3; | |
760 | priv->dimm_csmap[1][0] = 1; | |
761 | priv->dimm_csmap[1][1] = 2; | |
762 | priv->dimm_csmap[2][0] = 2; | |
763 | priv->dimm_csmap[3][0] = 3; | |
764 | } else { | |
765 | priv->dimm_csmap[0][0] = 0; | |
766 | priv->dimm_csmap[0][1] = 1; | |
767 | priv->dimm_csmap[1][0] = 2; | |
768 | priv->dimm_csmap[1][1] = 3; | |
769 | priv->dimm_csmap[2][0] = 4; | |
770 | priv->dimm_csmap[2][1] = 5; | |
771 | } | |
8f421c59 AJ |
772 | } |
773 | ||
774 | static void __devinit i5100_init_dimm_layout(struct pci_dev *pdev, | |
775 | struct mem_ctl_info *mci) | |
776 | { | |
777 | struct i5100_priv *priv = mci->pvt_info; | |
778 | int i; | |
779 | ||
b18dfd05 | 780 | for (i = 0; i < I5100_CHANNELS; i++) { |
8f421c59 AJ |
781 | int j; |
782 | ||
b18dfd05 | 783 | for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) { |
8f421c59 AJ |
784 | u8 rank; |
785 | ||
786 | if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0) | |
787 | priv->dimm_numrank[i][j] = 0; | |
788 | else | |
789 | priv->dimm_numrank[i][j] = (rank & 3) + 1; | |
790 | } | |
791 | } | |
792 | ||
793 | i5100_init_dimm_csmap(mci); | |
794 | } | |
795 | ||
796 | static void __devinit i5100_init_interleaving(struct pci_dev *pdev, | |
797 | struct mem_ctl_info *mci) | |
798 | { | |
799 | u16 w; | |
800 | u32 dw; | |
801 | struct i5100_priv *priv = mci->pvt_info; | |
802 | struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; | |
803 | int i; | |
804 | ||
805 | pci_read_config_word(pdev, I5100_TOLM, &w); | |
b238e577 | 806 | priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024; |
8f421c59 AJ |
807 | |
808 | pci_read_config_word(pdev, I5100_MIR0, &w); | |
b238e577 AJ |
809 | priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28; |
810 | priv->mir[0].way[1] = i5100_mir_way1(w); | |
811 | priv->mir[0].way[0] = i5100_mir_way0(w); | |
8f421c59 AJ |
812 | |
813 | pci_read_config_word(pdev, I5100_MIR1, &w); | |
b238e577 AJ |
814 | priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28; |
815 | priv->mir[1].way[1] = i5100_mir_way1(w); | |
816 | priv->mir[1].way[0] = i5100_mir_way0(w); | |
8f421c59 AJ |
817 | |
818 | pci_read_config_word(pdev, I5100_AMIR_0, &w); | |
819 | priv->amir[0] = w; | |
820 | pci_read_config_word(pdev, I5100_AMIR_1, &w); | |
821 | priv->amir[1] = w; | |
822 | ||
b18dfd05 | 823 | for (i = 0; i < I5100_CHANNELS; i++) { |
8f421c59 AJ |
824 | int j; |
825 | ||
826 | for (j = 0; j < 5; j++) { | |
827 | int k; | |
828 | ||
829 | pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw); | |
830 | ||
831 | priv->dmir[i][j].limit = | |
b238e577 | 832 | (u64) i5100_dmir_limit(dw) << 28; |
8f421c59 AJ |
833 | for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++) |
834 | priv->dmir[i][j].rank[k] = | |
b238e577 | 835 | i5100_dmir_rank(dw, k); |
8f421c59 AJ |
836 | } |
837 | } | |
838 | ||
839 | i5100_init_mtr(mci); | |
840 | } | |
841 | ||
842 | static void __devinit i5100_init_csrows(struct mem_ctl_info *mci) | |
843 | { | |
844 | int i; | |
845 | unsigned long total_pages = 0UL; | |
846 | struct i5100_priv *priv = mci->pvt_info; | |
847 | ||
848 | for (i = 0; i < mci->nr_csrows; i++) { | |
849 | const unsigned long npages = i5100_npages(mci, i); | |
b18dfd05 | 850 | const unsigned chan = i5100_csrow_to_chan(mci, i); |
8f421c59 AJ |
851 | const unsigned rank = i5100_csrow_to_rank(mci, i); |
852 | ||
853 | if (!npages) | |
854 | continue; | |
855 | ||
856 | /* | |
857 | * FIXME: these two are totally bogus -- I don't see how to | |
858 | * map them correctly to this structure... | |
859 | */ | |
860 | mci->csrows[i].first_page = total_pages; | |
861 | mci->csrows[i].last_page = total_pages + npages - 1; | |
862 | mci->csrows[i].page_mask = 0UL; | |
863 | ||
864 | mci->csrows[i].nr_pages = npages; | |
865 | mci->csrows[i].grain = 32; | |
866 | mci->csrows[i].csrow_idx = i; | |
867 | mci->csrows[i].dtype = | |
b18dfd05 | 868 | (priv->mtr[chan][rank].width == 4) ? DEV_X4 : DEV_X8; |
8f421c59 AJ |
869 | mci->csrows[i].ue_count = 0; |
870 | mci->csrows[i].ce_count = 0; | |
871 | mci->csrows[i].mtype = MEM_RDDR2; | |
872 | mci->csrows[i].edac_mode = EDAC_SECDED; | |
873 | mci->csrows[i].mci = mci; | |
874 | mci->csrows[i].nr_channels = 1; | |
875 | mci->csrows[i].channels[0].chan_idx = 0; | |
876 | mci->csrows[i].channels[0].ce_count = 0; | |
877 | mci->csrows[i].channels[0].csrow = mci->csrows + i; | |
878 | snprintf(mci->csrows[i].channels[0].label, | |
879 | sizeof(mci->csrows[i].channels[0].label), | |
b18dfd05 | 880 | "DIMM%u", i5100_rank_to_slot(mci, chan, rank)); |
8f421c59 AJ |
881 | |
882 | total_pages += npages; | |
883 | } | |
884 | } | |
885 | ||
886 | static int __devinit i5100_init_one(struct pci_dev *pdev, | |
887 | const struct pci_device_id *id) | |
888 | { | |
889 | int rc; | |
890 | struct mem_ctl_info *mci; | |
891 | struct i5100_priv *priv; | |
892 | struct pci_dev *ch0mm, *ch1mm; | |
893 | int ret = 0; | |
894 | u32 dw; | |
895 | int ranksperch; | |
896 | ||
897 | if (PCI_FUNC(pdev->devfn) != 1) | |
898 | return -ENODEV; | |
899 | ||
900 | rc = pci_enable_device(pdev); | |
901 | if (rc < 0) { | |
902 | ret = rc; | |
903 | goto bail; | |
904 | } | |
905 | ||
43920a59 AJ |
906 | /* ECC enabled? */ |
907 | pci_read_config_dword(pdev, I5100_MC, &dw); | |
b238e577 | 908 | if (!i5100_mc_errdeten(dw)) { |
43920a59 AJ |
909 | printk(KERN_INFO "i5100_edac: ECC not enabled.\n"); |
910 | ret = -ENODEV; | |
b238e577 | 911 | goto bail_pdev; |
43920a59 AJ |
912 | } |
913 | ||
8f421c59 AJ |
914 | /* figure out how many ranks, from strapped state of 48GB_Mode input */ |
915 | pci_read_config_dword(pdev, I5100_MS, &dw); | |
916 | ranksperch = !!(dw & (1 << 8)) * 2 + 4; | |
917 | ||
178d5a74 AJ |
918 | /* enable error reporting... */ |
919 | pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw); | |
920 | dw &= ~I5100_FERR_NF_MEM_ANY_MASK; | |
921 | pci_write_config_dword(pdev, I5100_EMASK_MEM, dw); | |
922 | ||
8f421c59 AJ |
923 | /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */ |
924 | ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, | |
925 | PCI_DEVICE_ID_INTEL_5100_21, 0); | |
b238e577 AJ |
926 | if (!ch0mm) { |
927 | ret = -ENODEV; | |
928 | goto bail_pdev; | |
929 | } | |
8f421c59 AJ |
930 | |
931 | rc = pci_enable_device(ch0mm); | |
932 | if (rc < 0) { | |
933 | ret = rc; | |
934 | goto bail_ch0; | |
935 | } | |
936 | ||
937 | /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */ | |
938 | ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, | |
939 | PCI_DEVICE_ID_INTEL_5100_22, 0); | |
940 | if (!ch1mm) { | |
941 | ret = -ENODEV; | |
b238e577 | 942 | goto bail_disable_ch0; |
8f421c59 AJ |
943 | } |
944 | ||
945 | rc = pci_enable_device(ch1mm); | |
946 | if (rc < 0) { | |
947 | ret = rc; | |
948 | goto bail_ch1; | |
949 | } | |
950 | ||
951 | mci = edac_mc_alloc(sizeof(*priv), ranksperch * 2, 1, 0); | |
952 | if (!mci) { | |
953 | ret = -ENOMEM; | |
b238e577 | 954 | goto bail_disable_ch1; |
8f421c59 AJ |
955 | } |
956 | ||
957 | mci->dev = &pdev->dev; | |
958 | ||
959 | priv = mci->pvt_info; | |
b18dfd05 | 960 | priv->ranksperchan = ranksperch; |
8f421c59 AJ |
961 | priv->mc = pdev; |
962 | priv->ch0mm = ch0mm; | |
963 | priv->ch1mm = ch1mm; | |
964 | ||
295439f2 NC |
965 | INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing); |
966 | ||
967 | /* If scrubbing was already enabled by the bios, start maintaining it */ | |
968 | pci_read_config_dword(pdev, I5100_MC, &dw); | |
969 | if (i5100_mc_scrben(dw)) { | |
970 | priv->scrub_enable = 1; | |
971 | schedule_delayed_work(&(priv->i5100_scrubbing), | |
972 | I5100_SCRUB_REFRESH_RATE); | |
973 | } | |
974 | ||
8f421c59 AJ |
975 | i5100_init_dimm_layout(pdev, mci); |
976 | i5100_init_interleaving(pdev, mci); | |
977 | ||
978 | mci->mtype_cap = MEM_FLAG_FB_DDR2; | |
979 | mci->edac_ctl_cap = EDAC_FLAG_SECDED; | |
980 | mci->edac_cap = EDAC_FLAG_SECDED; | |
981 | mci->mod_name = "i5100_edac.c"; | |
982 | mci->mod_ver = "not versioned"; | |
983 | mci->ctl_name = "i5100"; | |
984 | mci->dev_name = pci_name(pdev); | |
b238e577 | 985 | mci->ctl_page_to_phys = NULL; |
8f421c59 AJ |
986 | |
987 | mci->edac_check = i5100_check_error; | |
295439f2 NC |
988 | mci->set_sdram_scrub_rate = i5100_set_scrub_rate; |
989 | mci->get_sdram_scrub_rate = i5100_get_scrub_rate; | |
8f421c59 AJ |
990 | |
991 | i5100_init_csrows(mci); | |
992 | ||
993 | /* this strange construction seems to be in every driver, dunno why */ | |
994 | switch (edac_op_state) { | |
995 | case EDAC_OPSTATE_POLL: | |
996 | case EDAC_OPSTATE_NMI: | |
997 | break; | |
998 | default: | |
999 | edac_op_state = EDAC_OPSTATE_POLL; | |
1000 | break; | |
1001 | } | |
1002 | ||
1003 | if (edac_mc_add_mc(mci)) { | |
1004 | ret = -ENODEV; | |
295439f2 | 1005 | goto bail_scrub; |
8f421c59 AJ |
1006 | } |
1007 | ||
b238e577 | 1008 | return ret; |
8f421c59 | 1009 | |
295439f2 NC |
1010 | bail_scrub: |
1011 | priv->scrub_enable = 0; | |
1012 | cancel_delayed_work_sync(&(priv->i5100_scrubbing)); | |
8f421c59 AJ |
1013 | edac_mc_free(mci); |
1014 | ||
b238e577 AJ |
1015 | bail_disable_ch1: |
1016 | pci_disable_device(ch1mm); | |
1017 | ||
8f421c59 AJ |
1018 | bail_ch1: |
1019 | pci_dev_put(ch1mm); | |
1020 | ||
b238e577 AJ |
1021 | bail_disable_ch0: |
1022 | pci_disable_device(ch0mm); | |
1023 | ||
8f421c59 AJ |
1024 | bail_ch0: |
1025 | pci_dev_put(ch0mm); | |
1026 | ||
b238e577 AJ |
1027 | bail_pdev: |
1028 | pci_disable_device(pdev); | |
1029 | ||
8f421c59 AJ |
1030 | bail: |
1031 | return ret; | |
1032 | } | |
1033 | ||
1034 | static void __devexit i5100_remove_one(struct pci_dev *pdev) | |
1035 | { | |
1036 | struct mem_ctl_info *mci; | |
1037 | struct i5100_priv *priv; | |
1038 | ||
1039 | mci = edac_mc_del_mc(&pdev->dev); | |
1040 | ||
1041 | if (!mci) | |
1042 | return; | |
1043 | ||
1044 | priv = mci->pvt_info; | |
295439f2 NC |
1045 | |
1046 | priv->scrub_enable = 0; | |
1047 | cancel_delayed_work_sync(&(priv->i5100_scrubbing)); | |
1048 | ||
b238e577 AJ |
1049 | pci_disable_device(pdev); |
1050 | pci_disable_device(priv->ch0mm); | |
1051 | pci_disable_device(priv->ch1mm); | |
8f421c59 AJ |
1052 | pci_dev_put(priv->ch0mm); |
1053 | pci_dev_put(priv->ch1mm); | |
1054 | ||
1055 | edac_mc_free(mci); | |
1056 | } | |
1057 | ||
1058 | static const struct pci_device_id i5100_pci_tbl[] __devinitdata = { | |
1059 | /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */ | |
1060 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) }, | |
1061 | { 0, } | |
1062 | }; | |
1063 | MODULE_DEVICE_TABLE(pci, i5100_pci_tbl); | |
1064 | ||
1065 | static struct pci_driver i5100_driver = { | |
1066 | .name = KBUILD_BASENAME, | |
1067 | .probe = i5100_init_one, | |
1068 | .remove = __devexit_p(i5100_remove_one), | |
1069 | .id_table = i5100_pci_tbl, | |
1070 | }; | |
1071 | ||
1072 | static int __init i5100_init(void) | |
1073 | { | |
1074 | int pci_rc; | |
1075 | ||
1076 | pci_rc = pci_register_driver(&i5100_driver); | |
1077 | ||
1078 | return (pci_rc < 0) ? pci_rc : 0; | |
1079 | } | |
1080 | ||
1081 | static void __exit i5100_exit(void) | |
1082 | { | |
1083 | pci_unregister_driver(&i5100_driver); | |
1084 | } | |
1085 | ||
1086 | module_init(i5100_init); | |
1087 | module_exit(i5100_exit); | |
1088 | ||
1089 | MODULE_LICENSE("GPL"); | |
1090 | MODULE_AUTHOR | |
1091 | ("Arthur Jones <ajones@riverbed.com>"); | |
1092 | MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers"); |