Merge branches 'fixes' and 'mmci' into for-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / edac_mc_sysfs.c
CommitLineData
7c9281d7
DT
1/*
2 * edac_mc kernel module
42a8e397
DT
3 * (C) 2005-2007 Linux Networx (http://lnxi.com)
4 *
7c9281d7
DT
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
42a8e397 8 * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
7c9281d7 9 *
7a623c03
MCC
10 * (c) 2012 - Mauro Carvalho Chehab <mchehab@redhat.com>
11 * The entire API were re-written, and ported to use struct device
12 *
7c9281d7
DT
13 */
14
7c9281d7 15#include <linux/ctype.h>
5a0e3ad6 16#include <linux/slab.h>
30e1f7a8 17#include <linux/edac.h>
8096cfaf 18#include <linux/bug.h>
7a623c03 19#include <linux/pm_runtime.h>
452a6bf9 20#include <linux/uaccess.h>
7c9281d7 21
20bcb7a8 22#include "edac_core.h"
7c9281d7
DT
23#include "edac_module.h"
24
25/* MC EDAC Controls, setable by module parameter, and sysfs */
4de78c68
DJ
26static int edac_mc_log_ue = 1;
27static int edac_mc_log_ce = 1;
f044091c 28static int edac_mc_panic_on_ue;
4de78c68 29static int edac_mc_poll_msec = 1000;
7c9281d7
DT
30
31/* Getter functions for above */
4de78c68 32int edac_mc_get_log_ue(void)
7c9281d7 33{
4de78c68 34 return edac_mc_log_ue;
7c9281d7
DT
35}
36
4de78c68 37int edac_mc_get_log_ce(void)
7c9281d7 38{
4de78c68 39 return edac_mc_log_ce;
7c9281d7
DT
40}
41
4de78c68 42int edac_mc_get_panic_on_ue(void)
7c9281d7 43{
4de78c68 44 return edac_mc_panic_on_ue;
7c9281d7
DT
45}
46
81d87cb1
DJ
47/* this is temporary */
48int edac_mc_get_poll_msec(void)
49{
4de78c68 50 return edac_mc_poll_msec;
7c9281d7
DT
51}
52
096846e2
AJ
53static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
54{
55 long l;
56 int ret;
57
58 if (!val)
59 return -EINVAL;
60
61 ret = strict_strtol(val, 0, &l);
62 if (ret == -EINVAL || ((int)l != l))
63 return -EINVAL;
64 *((int *)kp->arg) = l;
65
66 /* notify edac_mc engine to reset the poll period */
67 edac_mc_reset_delay_period(l);
68
69 return 0;
70}
71
7c9281d7 72/* Parameter declarations for above */
4de78c68
DJ
73module_param(edac_mc_panic_on_ue, int, 0644);
74MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
75module_param(edac_mc_log_ue, int, 0644);
76MODULE_PARM_DESC(edac_mc_log_ue,
079708b9 77 "Log uncorrectable error to console: 0=off 1=on");
4de78c68
DJ
78module_param(edac_mc_log_ce, int, 0644);
79MODULE_PARM_DESC(edac_mc_log_ce,
079708b9 80 "Log correctable error to console: 0=off 1=on");
096846e2
AJ
81module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
82 &edac_mc_poll_msec, 0644);
4de78c68 83MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
7c9281d7 84
de3910eb 85static struct device *mci_pdev;
7a623c03 86
7c9281d7
DT
87/*
88 * various constants for Memory Controllers
89 */
90static const char *mem_types[] = {
91 [MEM_EMPTY] = "Empty",
92 [MEM_RESERVED] = "Reserved",
93 [MEM_UNKNOWN] = "Unknown",
94 [MEM_FPM] = "FPM",
95 [MEM_EDO] = "EDO",
96 [MEM_BEDO] = "BEDO",
97 [MEM_SDR] = "Unbuffered-SDR",
98 [MEM_RDR] = "Registered-SDR",
99 [MEM_DDR] = "Unbuffered-DDR",
100 [MEM_RDDR] = "Registered-DDR",
1a9b85e6
DJ
101 [MEM_RMBS] = "RMBS",
102 [MEM_DDR2] = "Unbuffered-DDR2",
103 [MEM_FB_DDR2] = "FullyBuffered-DDR2",
1d5f726c 104 [MEM_RDDR2] = "Registered-DDR2",
b1cfebc9
YS
105 [MEM_XDR] = "XDR",
106 [MEM_DDR3] = "Unbuffered-DDR3",
107 [MEM_RDDR3] = "Registered-DDR3"
7c9281d7
DT
108};
109
110static const char *dev_types[] = {
111 [DEV_UNKNOWN] = "Unknown",
112 [DEV_X1] = "x1",
113 [DEV_X2] = "x2",
114 [DEV_X4] = "x4",
115 [DEV_X8] = "x8",
116 [DEV_X16] = "x16",
117 [DEV_X32] = "x32",
118 [DEV_X64] = "x64"
119};
120
121static const char *edac_caps[] = {
122 [EDAC_UNKNOWN] = "Unknown",
123 [EDAC_NONE] = "None",
124 [EDAC_RESERVED] = "Reserved",
125 [EDAC_PARITY] = "PARITY",
126 [EDAC_EC] = "EC",
127 [EDAC_SECDED] = "SECDED",
128 [EDAC_S2ECD2ED] = "S2ECD2ED",
129 [EDAC_S4ECD4ED] = "S4ECD4ED",
130 [EDAC_S8ECD8ED] = "S8ECD8ED",
131 [EDAC_S16ECD16ED] = "S16ECD16ED"
132};
133
19974710 134#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
135/*
136 * EDAC sysfs CSROW data structures and methods
137 */
138
139#define to_csrow(k) container_of(k, struct csrow_info, dev)
140
141/*
142 * We need it to avoid namespace conflicts between the legacy API
143 * and the per-dimm/per-rank one
7c9281d7 144 */
7a623c03
MCC
145#define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
146 struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
147
148struct dev_ch_attribute {
149 struct device_attribute attr;
150 int channel;
151};
152
153#define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
154 struct dev_ch_attribute dev_attr_legacy_##_name = \
155 { __ATTR(_name, _mode, _show, _store), (_var) }
156
157#define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
7c9281d7
DT
158
159/* Set of more default csrow<id> attribute show/store functions */
7a623c03
MCC
160static ssize_t csrow_ue_count_show(struct device *dev,
161 struct device_attribute *mattr, char *data)
7c9281d7 162{
7a623c03
MCC
163 struct csrow_info *csrow = to_csrow(dev);
164
079708b9 165 return sprintf(data, "%u\n", csrow->ue_count);
7c9281d7
DT
166}
167
7a623c03
MCC
168static ssize_t csrow_ce_count_show(struct device *dev,
169 struct device_attribute *mattr, char *data)
7c9281d7 170{
7a623c03
MCC
171 struct csrow_info *csrow = to_csrow(dev);
172
079708b9 173 return sprintf(data, "%u\n", csrow->ce_count);
7c9281d7
DT
174}
175
7a623c03
MCC
176static ssize_t csrow_size_show(struct device *dev,
177 struct device_attribute *mattr, char *data)
7c9281d7 178{
7a623c03 179 struct csrow_info *csrow = to_csrow(dev);
a895bf8b
MCC
180 int i;
181 u32 nr_pages = 0;
182
16a528ee
BP
183 if (csrow->mci->csbased)
184 return sprintf(data, "%u\n", PAGES_TO_MiB(csrow->nr_pages));
185
a895bf8b 186 for (i = 0; i < csrow->nr_channels; i++)
de3910eb 187 nr_pages += csrow->channels[i]->dimm->nr_pages;
a895bf8b 188 return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
7c9281d7
DT
189}
190
7a623c03
MCC
191static ssize_t csrow_mem_type_show(struct device *dev,
192 struct device_attribute *mattr, char *data)
7c9281d7 193{
7a623c03
MCC
194 struct csrow_info *csrow = to_csrow(dev);
195
de3910eb 196 return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
7c9281d7
DT
197}
198
7a623c03
MCC
199static ssize_t csrow_dev_type_show(struct device *dev,
200 struct device_attribute *mattr, char *data)
7c9281d7 201{
7a623c03
MCC
202 struct csrow_info *csrow = to_csrow(dev);
203
de3910eb 204 return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
7c9281d7
DT
205}
206
7a623c03
MCC
207static ssize_t csrow_edac_mode_show(struct device *dev,
208 struct device_attribute *mattr,
209 char *data)
7c9281d7 210{
7a623c03
MCC
211 struct csrow_info *csrow = to_csrow(dev);
212
de3910eb 213 return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
7c9281d7
DT
214}
215
216/* show/store functions for DIMM Label attributes */
7a623c03
MCC
217static ssize_t channel_dimm_label_show(struct device *dev,
218 struct device_attribute *mattr,
219 char *data)
7c9281d7 220{
7a623c03
MCC
221 struct csrow_info *csrow = to_csrow(dev);
222 unsigned chan = to_channel(mattr);
de3910eb 223 struct rank_info *rank = csrow->channels[chan];
7a623c03 224
124682c7 225 /* if field has not been initialized, there is nothing to send */
7a623c03 226 if (!rank->dimm->label[0])
124682c7
AJ
227 return 0;
228
229 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
7a623c03 230 rank->dimm->label);
7c9281d7
DT
231}
232
7a623c03
MCC
233static ssize_t channel_dimm_label_store(struct device *dev,
234 struct device_attribute *mattr,
235 const char *data, size_t count)
7c9281d7 236{
7a623c03
MCC
237 struct csrow_info *csrow = to_csrow(dev);
238 unsigned chan = to_channel(mattr);
de3910eb 239 struct rank_info *rank = csrow->channels[chan];
7a623c03 240
7c9281d7
DT
241 ssize_t max_size = 0;
242
079708b9 243 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
7a623c03
MCC
244 strncpy(rank->dimm->label, data, max_size);
245 rank->dimm->label[max_size] = '\0';
7c9281d7
DT
246
247 return max_size;
248}
249
250/* show function for dynamic chX_ce_count attribute */
7a623c03
MCC
251static ssize_t channel_ce_count_show(struct device *dev,
252 struct device_attribute *mattr, char *data)
7c9281d7 253{
7a623c03
MCC
254 struct csrow_info *csrow = to_csrow(dev);
255 unsigned chan = to_channel(mattr);
de3910eb 256 struct rank_info *rank = csrow->channels[chan];
7a623c03
MCC
257
258 return sprintf(data, "%u\n", rank->ce_count);
7c9281d7
DT
259}
260
7a623c03
MCC
261/* cwrow<id>/attribute files */
262DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
263DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
264DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
265DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
266DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
267DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
7c9281d7 268
7a623c03
MCC
269/* default attributes of the CSROW<id> object */
270static struct attribute *csrow_attrs[] = {
271 &dev_attr_legacy_dev_type.attr,
272 &dev_attr_legacy_mem_type.attr,
273 &dev_attr_legacy_edac_mode.attr,
274 &dev_attr_legacy_size_mb.attr,
275 &dev_attr_legacy_ue_count.attr,
276 &dev_attr_legacy_ce_count.attr,
277 NULL,
278};
7c9281d7 279
7a623c03
MCC
280static struct attribute_group csrow_attr_grp = {
281 .attrs = csrow_attrs,
282};
7c9281d7 283
7a623c03
MCC
284static const struct attribute_group *csrow_attr_groups[] = {
285 &csrow_attr_grp,
286 NULL
287};
7c9281d7 288
de3910eb 289static void csrow_attr_release(struct device *dev)
7c9281d7 290{
de3910eb
MCC
291 struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
292
956b9ba1 293 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
de3910eb 294 kfree(csrow);
7c9281d7
DT
295}
296
7a623c03
MCC
297static struct device_type csrow_attr_type = {
298 .groups = csrow_attr_groups,
299 .release = csrow_attr_release,
7c9281d7
DT
300};
301
7a623c03
MCC
302/*
303 * possible dynamic channel DIMM Label attribute files
304 *
305 */
7c9281d7 306
7a623c03 307#define EDAC_NR_CHANNELS 6
7c9281d7 308
7a623c03 309DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 310 channel_dimm_label_show, channel_dimm_label_store, 0);
7a623c03 311DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 312 channel_dimm_label_show, channel_dimm_label_store, 1);
7a623c03 313DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 314 channel_dimm_label_show, channel_dimm_label_store, 2);
7a623c03 315DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 316 channel_dimm_label_show, channel_dimm_label_store, 3);
7a623c03 317DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 318 channel_dimm_label_show, channel_dimm_label_store, 4);
7a623c03 319DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 320 channel_dimm_label_show, channel_dimm_label_store, 5);
7c9281d7
DT
321
322/* Total possible dynamic DIMM Label attribute file table */
7a623c03
MCC
323static struct device_attribute *dynamic_csrow_dimm_attr[] = {
324 &dev_attr_legacy_ch0_dimm_label.attr,
325 &dev_attr_legacy_ch1_dimm_label.attr,
326 &dev_attr_legacy_ch2_dimm_label.attr,
327 &dev_attr_legacy_ch3_dimm_label.attr,
328 &dev_attr_legacy_ch4_dimm_label.attr,
329 &dev_attr_legacy_ch5_dimm_label.attr
7c9281d7
DT
330};
331
332/* possible dynamic channel ce_count attribute files */
7a623c03
MCC
333DEVICE_CHANNEL(ch0_ce_count, S_IRUGO | S_IWUSR,
334 channel_ce_count_show, NULL, 0);
335DEVICE_CHANNEL(ch1_ce_count, S_IRUGO | S_IWUSR,
336 channel_ce_count_show, NULL, 1);
337DEVICE_CHANNEL(ch2_ce_count, S_IRUGO | S_IWUSR,
338 channel_ce_count_show, NULL, 2);
339DEVICE_CHANNEL(ch3_ce_count, S_IRUGO | S_IWUSR,
340 channel_ce_count_show, NULL, 3);
341DEVICE_CHANNEL(ch4_ce_count, S_IRUGO | S_IWUSR,
342 channel_ce_count_show, NULL, 4);
343DEVICE_CHANNEL(ch5_ce_count, S_IRUGO | S_IWUSR,
344 channel_ce_count_show, NULL, 5);
7c9281d7
DT
345
346/* Total possible dynamic ce_count attribute file table */
7a623c03
MCC
347static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
348 &dev_attr_legacy_ch0_ce_count.attr,
349 &dev_attr_legacy_ch1_ce_count.attr,
350 &dev_attr_legacy_ch2_ce_count.attr,
351 &dev_attr_legacy_ch3_ce_count.attr,
352 &dev_attr_legacy_ch4_ce_count.attr,
353 &dev_attr_legacy_ch5_ce_count.attr
7c9281d7
DT
354};
355
e39f4ea9
MCC
356static inline int nr_pages_per_csrow(struct csrow_info *csrow)
357{
358 int chan, nr_pages = 0;
359
360 for (chan = 0; chan < csrow->nr_channels; chan++)
de3910eb 361 nr_pages += csrow->channels[chan]->dimm->nr_pages;
e39f4ea9
MCC
362
363 return nr_pages;
364}
365
7a623c03
MCC
366/* Create a CSROW object under specifed edac_mc_device */
367static int edac_create_csrow_object(struct mem_ctl_info *mci,
368 struct csrow_info *csrow, int index)
7c9281d7 369{
7a623c03 370 int err, chan;
7c9281d7 371
7a623c03
MCC
372 if (csrow->nr_channels >= EDAC_NR_CHANNELS)
373 return -ENODEV;
7c9281d7 374
7a623c03
MCC
375 csrow->dev.type = &csrow_attr_type;
376 csrow->dev.bus = &mci->bus;
377 device_initialize(&csrow->dev);
378 csrow->dev.parent = &mci->dev;
921a6899 379 csrow->mci = mci;
7a623c03
MCC
380 dev_set_name(&csrow->dev, "csrow%d", index);
381 dev_set_drvdata(&csrow->dev, csrow);
7c9281d7 382
956b9ba1
JP
383 edac_dbg(0, "creating (virtual) csrow node %s\n",
384 dev_name(&csrow->dev));
7c9281d7 385
7a623c03
MCC
386 err = device_add(&csrow->dev);
387 if (err < 0)
388 return err;
7c9281d7 389
7a623c03 390 for (chan = 0; chan < csrow->nr_channels; chan++) {
e39f4ea9 391 /* Only expose populated DIMMs */
de3910eb 392 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 393 continue;
7a623c03
MCC
394 err = device_create_file(&csrow->dev,
395 dynamic_csrow_dimm_attr[chan]);
396 if (err < 0)
397 goto error;
398 err = device_create_file(&csrow->dev,
399 dynamic_csrow_ce_count_attr[chan]);
400 if (err < 0) {
401 device_remove_file(&csrow->dev,
402 dynamic_csrow_dimm_attr[chan]);
403 goto error;
404 }
405 }
8096cfaf 406
7a623c03 407 return 0;
8096cfaf 408
7a623c03
MCC
409error:
410 for (--chan; chan >= 0; chan--) {
411 device_remove_file(&csrow->dev,
412 dynamic_csrow_dimm_attr[chan]);
413 device_remove_file(&csrow->dev,
414 dynamic_csrow_ce_count_attr[chan]);
415 }
416 put_device(&csrow->dev);
7c9281d7 417
7a623c03
MCC
418 return err;
419}
7c9281d7
DT
420
421/* Create a CSROW object under specifed edac_mc_device */
7a623c03 422static int edac_create_csrow_objects(struct mem_ctl_info *mci)
7c9281d7 423{
7a623c03
MCC
424 int err, i, chan;
425 struct csrow_info *csrow;
7c9281d7 426
7a623c03 427 for (i = 0; i < mci->nr_csrows; i++) {
de3910eb 428 csrow = mci->csrows[i];
e39f4ea9
MCC
429 if (!nr_pages_per_csrow(csrow))
430 continue;
de3910eb 431 err = edac_create_csrow_object(mci, mci->csrows[i], i);
7a623c03
MCC
432 if (err < 0)
433 goto error;
434 }
435 return 0;
8096cfaf 436
7a623c03
MCC
437error:
438 for (--i; i >= 0; i--) {
de3910eb 439 csrow = mci->csrows[i];
e39f4ea9
MCC
440 if (!nr_pages_per_csrow(csrow))
441 continue;
7a623c03 442 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
de3910eb 443 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 444 continue;
7a623c03
MCC
445 device_remove_file(&csrow->dev,
446 dynamic_csrow_dimm_attr[chan]);
447 device_remove_file(&csrow->dev,
448 dynamic_csrow_ce_count_attr[chan]);
449 }
de3910eb 450 put_device(&mci->csrows[i]->dev);
8096cfaf 451 }
7c9281d7 452
7a623c03
MCC
453 return err;
454}
8096cfaf 455
7a623c03
MCC
456static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
457{
458 int i, chan;
459 struct csrow_info *csrow;
8096cfaf 460
7a623c03 461 for (i = mci->nr_csrows - 1; i >= 0; i--) {
de3910eb 462 csrow = mci->csrows[i];
e39f4ea9
MCC
463 if (!nr_pages_per_csrow(csrow))
464 continue;
7a623c03 465 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
de3910eb 466 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 467 continue;
956b9ba1
JP
468 edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
469 i, chan);
7a623c03
MCC
470 device_remove_file(&csrow->dev,
471 dynamic_csrow_dimm_attr[chan]);
472 device_remove_file(&csrow->dev,
473 dynamic_csrow_ce_count_attr[chan]);
7c9281d7 474 }
44d22e24 475 device_unregister(&mci->csrows[i]->dev);
7c9281d7 476 }
7c9281d7 477}
19974710
MCC
478#endif
479
480/*
481 * Per-dimm (or per-rank) devices
482 */
483
484#define to_dimm(k) container_of(k, struct dimm_info, dev)
485
486/* show/store functions for DIMM Label attributes */
487static ssize_t dimmdev_location_show(struct device *dev,
488 struct device_attribute *mattr, char *data)
489{
490 struct dimm_info *dimm = to_dimm(dev);
19974710 491
6e84d359 492 return edac_dimm_info_location(dimm, data, PAGE_SIZE);
19974710
MCC
493}
494
495static ssize_t dimmdev_label_show(struct device *dev,
496 struct device_attribute *mattr, char *data)
497{
498 struct dimm_info *dimm = to_dimm(dev);
499
500 /* if field has not been initialized, there is nothing to send */
501 if (!dimm->label[0])
502 return 0;
503
504 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
505}
506
507static ssize_t dimmdev_label_store(struct device *dev,
508 struct device_attribute *mattr,
509 const char *data,
510 size_t count)
511{
512 struct dimm_info *dimm = to_dimm(dev);
513
514 ssize_t max_size = 0;
515
516 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
517 strncpy(dimm->label, data, max_size);
518 dimm->label[max_size] = '\0';
519
520 return max_size;
521}
522
523static ssize_t dimmdev_size_show(struct device *dev,
524 struct device_attribute *mattr, char *data)
525{
526 struct dimm_info *dimm = to_dimm(dev);
527
528 return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
529}
530
531static ssize_t dimmdev_mem_type_show(struct device *dev,
532 struct device_attribute *mattr, char *data)
533{
534 struct dimm_info *dimm = to_dimm(dev);
535
536 return sprintf(data, "%s\n", mem_types[dimm->mtype]);
537}
538
539static ssize_t dimmdev_dev_type_show(struct device *dev,
540 struct device_attribute *mattr, char *data)
541{
542 struct dimm_info *dimm = to_dimm(dev);
543
544 return sprintf(data, "%s\n", dev_types[dimm->dtype]);
545}
546
547static ssize_t dimmdev_edac_mode_show(struct device *dev,
548 struct device_attribute *mattr,
549 char *data)
550{
551 struct dimm_info *dimm = to_dimm(dev);
552
553 return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
554}
555
556/* dimm/rank attribute files */
557static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
558 dimmdev_label_show, dimmdev_label_store);
559static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
560static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
561static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
562static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
563static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
564
565/* attributes of the dimm<id>/rank<id> object */
566static struct attribute *dimm_attrs[] = {
567 &dev_attr_dimm_label.attr,
568 &dev_attr_dimm_location.attr,
569 &dev_attr_size.attr,
570 &dev_attr_dimm_mem_type.attr,
571 &dev_attr_dimm_dev_type.attr,
572 &dev_attr_dimm_edac_mode.attr,
573 NULL,
574};
575
576static struct attribute_group dimm_attr_grp = {
577 .attrs = dimm_attrs,
578};
579
580static const struct attribute_group *dimm_attr_groups[] = {
581 &dimm_attr_grp,
582 NULL
583};
584
de3910eb 585static void dimm_attr_release(struct device *dev)
19974710 586{
de3910eb
MCC
587 struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
588
956b9ba1 589 edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
de3910eb 590 kfree(dimm);
19974710
MCC
591}
592
593static struct device_type dimm_attr_type = {
594 .groups = dimm_attr_groups,
595 .release = dimm_attr_release,
596};
597
598/* Create a DIMM object under specifed memory controller device */
599static int edac_create_dimm_object(struct mem_ctl_info *mci,
600 struct dimm_info *dimm,
601 int index)
602{
603 int err;
604 dimm->mci = mci;
605
606 dimm->dev.type = &dimm_attr_type;
607 dimm->dev.bus = &mci->bus;
608 device_initialize(&dimm->dev);
609
610 dimm->dev.parent = &mci->dev;
611 if (mci->mem_is_per_rank)
612 dev_set_name(&dimm->dev, "rank%d", index);
613 else
614 dev_set_name(&dimm->dev, "dimm%d", index);
615 dev_set_drvdata(&dimm->dev, dimm);
616 pm_runtime_forbid(&mci->dev);
617
618 err = device_add(&dimm->dev);
619
956b9ba1 620 edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
19974710
MCC
621
622 return err;
623}
7c9281d7 624
7a623c03
MCC
625/*
626 * Memory controller device
627 */
628
629#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
7c9281d7 630
7a623c03
MCC
631static ssize_t mci_reset_counters_store(struct device *dev,
632 struct device_attribute *mattr,
079708b9 633 const char *data, size_t count)
7c9281d7 634{
7a623c03
MCC
635 struct mem_ctl_info *mci = to_mci(dev);
636 int cnt, row, chan, i;
5926ff50
MCC
637 mci->ue_mc = 0;
638 mci->ce_mc = 0;
7a623c03
MCC
639 mci->ue_noinfo_count = 0;
640 mci->ce_noinfo_count = 0;
7c9281d7
DT
641
642 for (row = 0; row < mci->nr_csrows; row++) {
de3910eb 643 struct csrow_info *ri = mci->csrows[row];
7c9281d7
DT
644
645 ri->ue_count = 0;
646 ri->ce_count = 0;
647
648 for (chan = 0; chan < ri->nr_channels; chan++)
de3910eb 649 ri->channels[chan]->ce_count = 0;
7c9281d7
DT
650 }
651
7a623c03
MCC
652 cnt = 1;
653 for (i = 0; i < mci->n_layers; i++) {
654 cnt *= mci->layers[i].size;
655 memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
656 memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
657 }
658
7c9281d7
DT
659 mci->start_time = jiffies;
660 return count;
661}
662
39094443
BP
663/* Memory scrubbing interface:
664 *
665 * A MC driver can limit the scrubbing bandwidth based on the CPU type.
666 * Therefore, ->set_sdram_scrub_rate should be made to return the actual
667 * bandwidth that is accepted or 0 when scrubbing is to be disabled.
668 *
669 * Negative value still means that an error has occurred while setting
670 * the scrub rate.
671 */
7a623c03
MCC
672static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
673 struct device_attribute *mattr,
eba042a8 674 const char *data, size_t count)
7c9281d7 675{
7a623c03 676 struct mem_ctl_info *mci = to_mci(dev);
eba042a8 677 unsigned long bandwidth = 0;
39094443 678 int new_bw = 0;
7c9281d7 679
39094443 680 if (!mci->set_sdram_scrub_rate)
5e8e19bf 681 return -ENODEV;
7c9281d7 682
eba042a8
BP
683 if (strict_strtoul(data, 10, &bandwidth) < 0)
684 return -EINVAL;
7c9281d7 685
39094443 686 new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
4949603a
MT
687 if (new_bw < 0) {
688 edac_printk(KERN_WARNING, EDAC_MC,
689 "Error setting scrub rate to: %lu\n", bandwidth);
690 return -EINVAL;
7c9281d7 691 }
39094443 692
4949603a 693 return count;
7c9281d7
DT
694}
695
39094443
BP
696/*
697 * ->get_sdram_scrub_rate() return value semantics same as above.
698 */
7a623c03
MCC
699static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
700 struct device_attribute *mattr,
701 char *data)
7c9281d7 702{
7a623c03 703 struct mem_ctl_info *mci = to_mci(dev);
39094443 704 int bandwidth = 0;
eba042a8 705
39094443 706 if (!mci->get_sdram_scrub_rate)
5e8e19bf 707 return -ENODEV;
eba042a8 708
39094443
BP
709 bandwidth = mci->get_sdram_scrub_rate(mci);
710 if (bandwidth < 0) {
eba042a8 711 edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
39094443 712 return bandwidth;
7c9281d7 713 }
39094443 714
39094443 715 return sprintf(data, "%d\n", bandwidth);
7c9281d7
DT
716}
717
718/* default attribute files for the MCI object */
7a623c03
MCC
719static ssize_t mci_ue_count_show(struct device *dev,
720 struct device_attribute *mattr,
721 char *data)
7c9281d7 722{
7a623c03
MCC
723 struct mem_ctl_info *mci = to_mci(dev);
724
5926ff50 725 return sprintf(data, "%d\n", mci->ue_mc);
7c9281d7
DT
726}
727
7a623c03
MCC
728static ssize_t mci_ce_count_show(struct device *dev,
729 struct device_attribute *mattr,
730 char *data)
7c9281d7 731{
7a623c03
MCC
732 struct mem_ctl_info *mci = to_mci(dev);
733
5926ff50 734 return sprintf(data, "%d\n", mci->ce_mc);
7c9281d7
DT
735}
736
7a623c03
MCC
737static ssize_t mci_ce_noinfo_show(struct device *dev,
738 struct device_attribute *mattr,
739 char *data)
7c9281d7 740{
7a623c03
MCC
741 struct mem_ctl_info *mci = to_mci(dev);
742
079708b9 743 return sprintf(data, "%d\n", mci->ce_noinfo_count);
7c9281d7
DT
744}
745
7a623c03
MCC
746static ssize_t mci_ue_noinfo_show(struct device *dev,
747 struct device_attribute *mattr,
748 char *data)
7c9281d7 749{
7a623c03
MCC
750 struct mem_ctl_info *mci = to_mci(dev);
751
079708b9 752 return sprintf(data, "%d\n", mci->ue_noinfo_count);
7c9281d7
DT
753}
754
7a623c03
MCC
755static ssize_t mci_seconds_show(struct device *dev,
756 struct device_attribute *mattr,
757 char *data)
7c9281d7 758{
7a623c03
MCC
759 struct mem_ctl_info *mci = to_mci(dev);
760
079708b9 761 return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
7c9281d7
DT
762}
763
7a623c03
MCC
764static ssize_t mci_ctl_name_show(struct device *dev,
765 struct device_attribute *mattr,
766 char *data)
7c9281d7 767{
7a623c03
MCC
768 struct mem_ctl_info *mci = to_mci(dev);
769
079708b9 770 return sprintf(data, "%s\n", mci->ctl_name);
7c9281d7
DT
771}
772
7a623c03
MCC
773static ssize_t mci_size_mb_show(struct device *dev,
774 struct device_attribute *mattr,
775 char *data)
7c9281d7 776{
7a623c03 777 struct mem_ctl_info *mci = to_mci(dev);
a895bf8b 778 int total_pages = 0, csrow_idx, j;
7c9281d7 779
a895bf8b 780 for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
de3910eb 781 struct csrow_info *csrow = mci->csrows[csrow_idx];
7c9281d7 782
3c062276
JH
783 if (csrow->mci->csbased) {
784 total_pages += csrow->nr_pages;
785 } else {
786 for (j = 0; j < csrow->nr_channels; j++) {
787 struct dimm_info *dimm = csrow->channels[j]->dimm;
788
789 total_pages += dimm->nr_pages;
790 }
a895bf8b 791 }
7c9281d7
DT
792 }
793
079708b9 794 return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
7c9281d7
DT
795}
796
8ad6c78a
MCC
797static ssize_t mci_max_location_show(struct device *dev,
798 struct device_attribute *mattr,
799 char *data)
800{
801 struct mem_ctl_info *mci = to_mci(dev);
802 int i;
803 char *p = data;
804
805 for (i = 0; i < mci->n_layers; i++) {
806 p += sprintf(p, "%s %d ",
807 edac_layer_name[mci->layers[i].type],
808 mci->layers[i].size - 1);
809 }
810
811 return p - data;
812}
813
452a6bf9
MCC
814#ifdef CONFIG_EDAC_DEBUG
815static ssize_t edac_fake_inject_write(struct file *file,
816 const char __user *data,
817 size_t count, loff_t *ppos)
818{
819 struct device *dev = file->private_data;
820 struct mem_ctl_info *mci = to_mci(dev);
821 static enum hw_event_mc_err_type type;
38ced28b
MCC
822 u16 errcount = mci->fake_inject_count;
823
824 if (!errcount)
825 errcount = 1;
452a6bf9
MCC
826
827 type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
828 : HW_EVENT_ERR_CORRECTED;
829
830 printk(KERN_DEBUG
38ced28b
MCC
831 "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
832 errcount,
452a6bf9 833 (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
38ced28b 834 errcount > 1 ? "s" : "",
452a6bf9
MCC
835 mci->fake_inject_layer[0],
836 mci->fake_inject_layer[1],
837 mci->fake_inject_layer[2]
838 );
38ced28b 839 edac_mc_handle_error(type, mci, errcount, 0, 0, 0,
452a6bf9
MCC
840 mci->fake_inject_layer[0],
841 mci->fake_inject_layer[1],
842 mci->fake_inject_layer[2],
03f7eae8 843 "FAKE ERROR", "for EDAC testing only");
452a6bf9
MCC
844
845 return count;
846}
847
452a6bf9 848static const struct file_operations debug_fake_inject_fops = {
db7312a2 849 .open = simple_open,
452a6bf9
MCC
850 .write = edac_fake_inject_write,
851 .llseek = generic_file_llseek,
852};
853#endif
854
7c9281d7 855/* default Control file */
7a623c03 856DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
7c9281d7
DT
857
858/* default Attribute files */
7a623c03
MCC
859DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
860DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
861DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
862DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
863DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
864DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
865DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
8ad6c78a 866DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
7c9281d7
DT
867
868/* memory scrubber attribute file */
7a623c03 869DEVICE_ATTR(sdram_scrub_rate, S_IRUGO | S_IWUSR, mci_sdram_scrub_rate_show,
052dfb45 870 mci_sdram_scrub_rate_store);
7c9281d7 871
7a623c03
MCC
872static struct attribute *mci_attrs[] = {
873 &dev_attr_reset_counters.attr,
874 &dev_attr_mc_name.attr,
875 &dev_attr_size_mb.attr,
876 &dev_attr_seconds_since_reset.attr,
877 &dev_attr_ue_noinfo_count.attr,
878 &dev_attr_ce_noinfo_count.attr,
879 &dev_attr_ue_count.attr,
880 &dev_attr_ce_count.attr,
881 &dev_attr_sdram_scrub_rate.attr,
8ad6c78a 882 &dev_attr_max_location.attr,
7c9281d7
DT
883 NULL
884};
885
7a623c03
MCC
886static struct attribute_group mci_attr_grp = {
887 .attrs = mci_attrs,
cc301b3a
MCC
888};
889
7a623c03
MCC
890static const struct attribute_group *mci_attr_groups[] = {
891 &mci_attr_grp,
892 NULL
cc301b3a
MCC
893};
894
de3910eb 895static void mci_attr_release(struct device *dev)
42a8e397 896{
de3910eb
MCC
897 struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
898
956b9ba1 899 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
de3910eb 900 kfree(mci);
42a8e397
DT
901}
902
7a623c03
MCC
903static struct device_type mci_attr_type = {
904 .groups = mci_attr_groups,
905 .release = mci_attr_release,
906};
8096cfaf 907
452a6bf9 908#ifdef CONFIG_EDAC_DEBUG
e7930ba4
RH
909static struct dentry *edac_debugfs;
910
911int __init edac_debugfs_init(void)
912{
913 edac_debugfs = debugfs_create_dir("edac", NULL);
914 if (IS_ERR(edac_debugfs)) {
915 edac_debugfs = NULL;
916 return -ENOMEM;
917 }
918 return 0;
919}
920
921void __exit edac_debugfs_exit(void)
922{
923 debugfs_remove(edac_debugfs);
924}
925
452a6bf9
MCC
926int edac_create_debug_nodes(struct mem_ctl_info *mci)
927{
928 struct dentry *d, *parent;
929 char name[80];
930 int i;
931
e7930ba4
RH
932 if (!edac_debugfs)
933 return -ENODEV;
934
935 d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs);
452a6bf9
MCC
936 if (!d)
937 return -ENOMEM;
938 parent = d;
939
940 for (i = 0; i < mci->n_layers; i++) {
941 sprintf(name, "fake_inject_%s",
942 edac_layer_name[mci->layers[i].type]);
943 d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
944 &mci->fake_inject_layer[i]);
945 if (!d)
946 goto nomem;
947 }
948
949 d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
950 &mci->fake_inject_ue);
951 if (!d)
952 goto nomem;
953
38ced28b
MCC
954 d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent,
955 &mci->fake_inject_count);
956 if (!d)
957 goto nomem;
958
452a6bf9
MCC
959 d = debugfs_create_file("fake_inject", S_IWUSR, parent,
960 &mci->dev,
961 &debug_fake_inject_fops);
962 if (!d)
963 goto nomem;
964
e7930ba4 965 mci->debugfs = parent;
452a6bf9
MCC
966 return 0;
967nomem:
968 debugfs_remove(mci->debugfs);
969 return -ENOMEM;
970}
971#endif
972
7c9281d7
DT
973/*
974 * Create a new Memory Controller kobject instance,
975 * mc<id> under the 'mc' directory
976 *
977 * Return:
978 * 0 Success
979 * !0 Failure
980 */
981int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
982{
7a623c03 983 int i, err;
7c9281d7 984
de3910eb
MCC
985 /*
986 * The memory controller needs its own bus, in order to avoid
987 * namespace conflicts at /sys/bus/edac.
988 */
989 mci->bus.name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
990 if (!mci->bus.name)
991 return -ENOMEM;
956b9ba1 992 edac_dbg(0, "creating bus %s\n", mci->bus.name);
de3910eb
MCC
993 err = bus_register(&mci->bus);
994 if (err < 0)
995 return err;
7c9281d7 996
7a623c03 997 /* get the /sys/devices/system/edac subsys reference */
7a623c03
MCC
998 mci->dev.type = &mci_attr_type;
999 device_initialize(&mci->dev);
7c9281d7 1000
de3910eb 1001 mci->dev.parent = mci_pdev;
7a623c03
MCC
1002 mci->dev.bus = &mci->bus;
1003 dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
1004 dev_set_drvdata(&mci->dev, mci);
1005 pm_runtime_forbid(&mci->dev);
1006
956b9ba1 1007 edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
7a623c03
MCC
1008 err = device_add(&mci->dev);
1009 if (err < 0) {
1010 bus_unregister(&mci->bus);
1011 kfree(mci->bus.name);
1012 return err;
42a8e397
DT
1013 }
1014
7a623c03
MCC
1015 /*
1016 * Create the dimm/rank devices
7c9281d7 1017 */
7a623c03 1018 for (i = 0; i < mci->tot_dimms; i++) {
de3910eb 1019 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1020 /* Only expose populated DIMMs */
1021 if (dimm->nr_pages == 0)
1022 continue;
1023#ifdef CONFIG_EDAC_DEBUG
956b9ba1 1024 edac_dbg(1, "creating dimm%d, located at ", i);
7a623c03
MCC
1025 if (edac_debug_level >= 1) {
1026 int lay;
1027 for (lay = 0; lay < mci->n_layers; lay++)
1028 printk(KERN_CONT "%s %d ",
1029 edac_layer_name[mci->layers[lay].type],
1030 dimm->location[lay]);
1031 printk(KERN_CONT "\n");
7c9281d7 1032 }
7a623c03 1033#endif
19974710
MCC
1034 err = edac_create_dimm_object(mci, dimm, i);
1035 if (err) {
956b9ba1 1036 edac_dbg(1, "failure: create dimm %d obj\n", i);
19974710
MCC
1037 goto fail;
1038 }
7c9281d7
DT
1039 }
1040
19974710 1041#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
1042 err = edac_create_csrow_objects(mci);
1043 if (err < 0)
1044 goto fail;
19974710 1045#endif
7a623c03 1046
452a6bf9
MCC
1047#ifdef CONFIG_EDAC_DEBUG
1048 edac_create_debug_nodes(mci);
1049#endif
7c9281d7
DT
1050 return 0;
1051
7a623c03 1052fail:
079708b9 1053 for (i--; i >= 0; i--) {
de3910eb 1054 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1055 if (dimm->nr_pages == 0)
1056 continue;
44d22e24 1057 device_unregister(&dimm->dev);
7c9281d7 1058 }
44d22e24 1059 device_unregister(&mci->dev);
7a623c03
MCC
1060 bus_unregister(&mci->bus);
1061 kfree(mci->bus.name);
7c9281d7
DT
1062 return err;
1063}
1064
1065/*
1066 * remove a Memory Controller instance
1067 */
1068void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
1069{
7a623c03 1070 int i;
7c9281d7 1071
956b9ba1 1072 edac_dbg(0, "\n");
7c9281d7 1073
452a6bf9
MCC
1074#ifdef CONFIG_EDAC_DEBUG
1075 debugfs_remove(mci->debugfs);
1076#endif
19974710 1077#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03 1078 edac_delete_csrow_objects(mci);
19974710 1079#endif
7c9281d7 1080
7a623c03 1081 for (i = 0; i < mci->tot_dimms; i++) {
de3910eb 1082 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1083 if (dimm->nr_pages == 0)
1084 continue;
956b9ba1 1085 edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
44d22e24 1086 device_unregister(&dimm->dev);
6fe1108f 1087 }
7c9281d7 1088}
8096cfaf 1089
7a623c03
MCC
1090void edac_unregister_sysfs(struct mem_ctl_info *mci)
1091{
956b9ba1 1092 edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
44d22e24 1093 device_unregister(&mci->dev);
7a623c03
MCC
1094 bus_unregister(&mci->bus);
1095 kfree(mci->bus.name);
1096}
8096cfaf 1097
de3910eb 1098static void mc_attr_release(struct device *dev)
7a623c03 1099{
de3910eb
MCC
1100 /*
1101 * There's no container structure here, as this is just the mci
1102 * parent device, used to create the /sys/devices/mc sysfs node.
1103 * So, there are no attributes on it.
1104 */
956b9ba1 1105 edac_dbg(1, "Releasing device %s\n", dev_name(dev));
de3910eb 1106 kfree(dev);
7a623c03 1107}
8096cfaf 1108
7a623c03
MCC
1109static struct device_type mc_attr_type = {
1110 .release = mc_attr_release,
1111};
8096cfaf 1112/*
7a623c03 1113 * Init/exit code for the module. Basically, creates/removes /sys/class/rc
8096cfaf 1114 */
7a623c03 1115int __init edac_mc_sysfs_init(void)
8096cfaf 1116{
fe5ff8b8 1117 struct bus_type *edac_subsys;
7a623c03 1118 int err;
8096cfaf 1119
fe5ff8b8
KS
1120 /* get the /sys/devices/system/edac subsys reference */
1121 edac_subsys = edac_get_sysfs_subsys();
1122 if (edac_subsys == NULL) {
956b9ba1 1123 edac_dbg(1, "no edac_subsys\n");
2d56b109
DK
1124 err = -EINVAL;
1125 goto out;
8096cfaf
DT
1126 }
1127
de3910eb 1128 mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
2d56b109
DK
1129 if (!mci_pdev) {
1130 err = -ENOMEM;
1131 goto out_put_sysfs;
1132 }
de3910eb
MCC
1133
1134 mci_pdev->bus = edac_subsys;
1135 mci_pdev->type = &mc_attr_type;
1136 device_initialize(mci_pdev);
1137 dev_set_name(mci_pdev, "mc");
8096cfaf 1138
de3910eb 1139 err = device_add(mci_pdev);
7a623c03 1140 if (err < 0)
2d56b109 1141 goto out_dev_free;
8096cfaf 1142
956b9ba1 1143 edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
de3910eb 1144
8096cfaf 1145 return 0;
2d56b109
DK
1146
1147 out_dev_free:
1148 kfree(mci_pdev);
1149 out_put_sysfs:
1150 edac_put_sysfs_subsys();
1151 out:
1152 return err;
8096cfaf
DT
1153}
1154
7a623c03 1155void __exit edac_mc_sysfs_exit(void)
8096cfaf 1156{
44d22e24 1157 device_unregister(mci_pdev);
fe5ff8b8 1158 edac_put_sysfs_subsys();
8096cfaf 1159}