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7c9281d7 DT |
1 | /* |
2 | * Defines, structures, APIs for edac_core module | |
3 | * | |
4 | * (C) 2007 Linux Networx (http://lnxi.com) | |
5 | * This file may be distributed under the terms of the | |
6 | * GNU General Public License. | |
7 | * | |
8 | * Written by Thayne Harbaugh | |
9 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
10 | * http://www.anime.net/~goemon/linux-ecc/ | |
11 | * | |
12 | * NMI handling support added by | |
13 | * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com> | |
14 | * | |
15 | * Refactored for multi-source files: | |
16 | * Doug Thompson <norsk5@xmission.com> | |
17 | * | |
18 | */ | |
19 | ||
20 | #ifndef _EDAC_CORE_H_ | |
21 | #define _EDAC_CORE_H_ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/smp.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/nmi.h> | |
31 | #include <linux/rcupdate.h> | |
32 | #include <linux/completion.h> | |
33 | #include <linux/kobject.h> | |
34 | #include <linux/platform_device.h> | |
e27e3dac DT |
35 | #include <linux/sysdev.h> |
36 | #include <linux/workqueue.h> | |
37 | #include <linux/version.h> | |
7c9281d7 DT |
38 | |
39 | #define EDAC_MC_LABEL_LEN 31 | |
e27e3dac DT |
40 | #define EDAC_DEVICE_NAME_LEN 31 |
41 | #define EDAC_ATTRIB_VALUE_LEN 15 | |
42 | #define MC_PROC_NAME_MAX_LEN 7 | |
7c9281d7 DT |
43 | |
44 | #if PAGE_SHIFT < 20 | |
45 | #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) ) | |
46 | #else /* PAGE_SHIFT > 20 */ | |
47 | #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) ) | |
48 | #endif | |
49 | ||
50 | #define edac_printk(level, prefix, fmt, arg...) \ | |
51 | printk(level "EDAC " prefix ": " fmt, ##arg) | |
52 | ||
53 | #define edac_mc_printk(mci, level, fmt, arg...) \ | |
54 | printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg) | |
55 | ||
56 | #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \ | |
57 | printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg) | |
58 | ||
e27e3dac DT |
59 | /* edac_device printk */ |
60 | #define edac_device_printk(ctl, level, fmt, arg...) \ | |
61 | printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg) | |
62 | ||
7c9281d7 DT |
63 | /* prefixes for edac_printk() and edac_mc_printk() */ |
64 | #define EDAC_MC "MC" | |
65 | #define EDAC_PCI "PCI" | |
66 | #define EDAC_DEBUG "DEBUG" | |
67 | ||
68 | #ifdef CONFIG_EDAC_DEBUG | |
69 | extern int edac_debug_level; | |
70 | ||
71 | #define edac_debug_printk(level, fmt, arg...) \ | |
72 | do { \ | |
73 | if (level <= edac_debug_level) \ | |
e27e3dac | 74 | edac_printk(KERN_EMERG, EDAC_DEBUG, fmt, ##arg); \ |
7c9281d7 DT |
75 | } while(0) |
76 | ||
77 | #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ ) | |
78 | #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ ) | |
79 | #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ ) | |
80 | #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ ) | |
81 | #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ ) | |
82 | ||
83 | #else /* !CONFIG_EDAC_DEBUG */ | |
84 | ||
85 | #define debugf0( ... ) | |
86 | #define debugf1( ... ) | |
87 | #define debugf2( ... ) | |
88 | #define debugf3( ... ) | |
89 | #define debugf4( ... ) | |
90 | ||
91 | #endif /* !CONFIG_EDAC_DEBUG */ | |
92 | ||
93 | #define BIT(x) (1 << (x)) | |
94 | ||
95 | #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \ | |
96 | PCI_DEVICE_ID_ ## vend ## _ ## dev | |
97 | ||
98 | #if defined(CONFIG_X86) && defined(CONFIG_PCI) | |
99 | #define dev_name(dev) pci_name(to_pci_dev(dev)) | |
100 | #else | |
101 | #define dev_name(dev) to_platform_device(dev)->name | |
102 | #endif | |
103 | ||
104 | /* memory devices */ | |
105 | enum dev_type { | |
106 | DEV_UNKNOWN = 0, | |
107 | DEV_X1, | |
108 | DEV_X2, | |
109 | DEV_X4, | |
110 | DEV_X8, | |
111 | DEV_X16, | |
112 | DEV_X32, /* Do these parts exist? */ | |
113 | DEV_X64 /* Do these parts exist? */ | |
114 | }; | |
115 | ||
116 | #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) | |
117 | #define DEV_FLAG_X1 BIT(DEV_X1) | |
118 | #define DEV_FLAG_X2 BIT(DEV_X2) | |
119 | #define DEV_FLAG_X4 BIT(DEV_X4) | |
120 | #define DEV_FLAG_X8 BIT(DEV_X8) | |
121 | #define DEV_FLAG_X16 BIT(DEV_X16) | |
122 | #define DEV_FLAG_X32 BIT(DEV_X32) | |
123 | #define DEV_FLAG_X64 BIT(DEV_X64) | |
124 | ||
125 | /* memory types */ | |
126 | enum mem_type { | |
127 | MEM_EMPTY = 0, /* Empty csrow */ | |
128 | MEM_RESERVED, /* Reserved csrow type */ | |
129 | MEM_UNKNOWN, /* Unknown csrow type */ | |
130 | MEM_FPM, /* Fast page mode */ | |
131 | MEM_EDO, /* Extended data out */ | |
132 | MEM_BEDO, /* Burst Extended data out */ | |
133 | MEM_SDR, /* Single data rate SDRAM */ | |
134 | MEM_RDR, /* Registered single data rate SDRAM */ | |
135 | MEM_DDR, /* Double data rate SDRAM */ | |
136 | MEM_RDDR, /* Registered Double data rate SDRAM */ | |
137 | MEM_RMBS, /* Rambus DRAM */ | |
138 | MEM_DDR2, /* DDR2 RAM */ | |
139 | MEM_FB_DDR2, /* fully buffered DDR2 */ | |
140 | MEM_RDDR2, /* Registered DDR2 RAM */ | |
141 | }; | |
142 | ||
143 | #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) | |
144 | #define MEM_FLAG_RESERVED BIT(MEM_RESERVED) | |
145 | #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) | |
146 | #define MEM_FLAG_FPM BIT(MEM_FPM) | |
147 | #define MEM_FLAG_EDO BIT(MEM_EDO) | |
148 | #define MEM_FLAG_BEDO BIT(MEM_BEDO) | |
149 | #define MEM_FLAG_SDR BIT(MEM_SDR) | |
150 | #define MEM_FLAG_RDR BIT(MEM_RDR) | |
151 | #define MEM_FLAG_DDR BIT(MEM_DDR) | |
152 | #define MEM_FLAG_RDDR BIT(MEM_RDDR) | |
153 | #define MEM_FLAG_RMBS BIT(MEM_RMBS) | |
154 | #define MEM_FLAG_DDR2 BIT(MEM_DDR2) | |
155 | #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) | |
156 | #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) | |
157 | ||
158 | /* chipset Error Detection and Correction capabilities and mode */ | |
159 | enum edac_type { | |
160 | EDAC_UNKNOWN = 0, /* Unknown if ECC is available */ | |
161 | EDAC_NONE, /* Doesnt support ECC */ | |
162 | EDAC_RESERVED, /* Reserved ECC type */ | |
163 | EDAC_PARITY, /* Detects parity errors */ | |
164 | EDAC_EC, /* Error Checking - no correction */ | |
165 | EDAC_SECDED, /* Single bit error correction, Double detection */ | |
166 | EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */ | |
167 | EDAC_S4ECD4ED, /* Chipkill x4 devices */ | |
168 | EDAC_S8ECD8ED, /* Chipkill x8 devices */ | |
169 | EDAC_S16ECD16ED, /* Chipkill x16 devices */ | |
170 | }; | |
171 | ||
172 | #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) | |
173 | #define EDAC_FLAG_NONE BIT(EDAC_NONE) | |
174 | #define EDAC_FLAG_PARITY BIT(EDAC_PARITY) | |
175 | #define EDAC_FLAG_EC BIT(EDAC_EC) | |
176 | #define EDAC_FLAG_SECDED BIT(EDAC_SECDED) | |
177 | #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) | |
178 | #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) | |
179 | #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) | |
180 | #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) | |
181 | ||
182 | /* scrubbing capabilities */ | |
183 | enum scrub_type { | |
184 | SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */ | |
185 | SCRUB_NONE, /* No scrubber */ | |
186 | SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */ | |
187 | SCRUB_SW_SRC, /* Software scrub only errors */ | |
188 | SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */ | |
189 | SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */ | |
190 | SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */ | |
191 | SCRUB_HW_SRC, /* Hardware scrub only errors */ | |
192 | SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */ | |
193 | SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */ | |
194 | }; | |
195 | ||
196 | #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) | |
522a94bd DT |
197 | #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC) |
198 | #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC) | |
7c9281d7 DT |
199 | #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) |
200 | #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) | |
522a94bd DT |
201 | #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC) |
202 | #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC) | |
7c9281d7 DT |
203 | #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) |
204 | ||
205 | /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */ | |
206 | ||
e27e3dac DT |
207 | extern char * edac_align_ptr(void *ptr, unsigned size); |
208 | ||
7c9281d7 DT |
209 | /* |
210 | * There are several things to be aware of that aren't at all obvious: | |
211 | * | |
212 | * | |
213 | * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. | |
214 | * | |
215 | * These are some of the many terms that are thrown about that don't always | |
216 | * mean what people think they mean (Inconceivable!). In the interest of | |
217 | * creating a common ground for discussion, terms and their definitions | |
218 | * will be established. | |
219 | * | |
220 | * Memory devices: The individual chip on a memory stick. These devices | |
221 | * commonly output 4 and 8 bits each. Grouping several | |
222 | * of these in parallel provides 64 bits which is common | |
223 | * for a memory stick. | |
224 | * | |
225 | * Memory Stick: A printed circuit board that agregates multiple | |
226 | * memory devices in parallel. This is the atomic | |
227 | * memory component that is purchaseable by Joe consumer | |
228 | * and loaded into a memory socket. | |
229 | * | |
230 | * Socket: A physical connector on the motherboard that accepts | |
231 | * a single memory stick. | |
232 | * | |
233 | * Channel: Set of memory devices on a memory stick that must be | |
234 | * grouped in parallel with one or more additional | |
235 | * channels from other memory sticks. This parallel | |
236 | * grouping of the output from multiple channels are | |
237 | * necessary for the smallest granularity of memory access. | |
238 | * Some memory controllers are capable of single channel - | |
239 | * which means that memory sticks can be loaded | |
240 | * individually. Other memory controllers are only | |
241 | * capable of dual channel - which means that memory | |
242 | * sticks must be loaded as pairs (see "socket set"). | |
243 | * | |
244 | * Chip-select row: All of the memory devices that are selected together. | |
245 | * for a single, minimum grain of memory access. | |
246 | * This selects all of the parallel memory devices across | |
247 | * all of the parallel channels. Common chip-select rows | |
248 | * for single channel are 64 bits, for dual channel 128 | |
249 | * bits. | |
250 | * | |
251 | * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory. | |
252 | * Motherboards commonly drive two chip-select pins to | |
253 | * a memory stick. A single-ranked stick, will occupy | |
254 | * only one of those rows. The other will be unused. | |
255 | * | |
256 | * Double-Ranked stick: A double-ranked stick has two chip-select rows which | |
257 | * access different sets of memory devices. The two | |
258 | * rows cannot be accessed concurrently. | |
259 | * | |
260 | * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick. | |
261 | * A double-sided stick has two chip-select rows which | |
262 | * access different sets of memory devices. The two | |
263 | * rows cannot be accessed concurrently. "Double-sided" | |
264 | * is irrespective of the memory devices being mounted | |
265 | * on both sides of the memory stick. | |
266 | * | |
267 | * Socket set: All of the memory sticks that are required for for | |
268 | * a single memory access or all of the memory sticks | |
269 | * spanned by a chip-select row. A single socket set | |
270 | * has two chip-select rows and if double-sided sticks | |
271 | * are used these will occupy those chip-select rows. | |
272 | * | |
273 | * Bank: This term is avoided because it is unclear when | |
274 | * needing to distinguish between chip-select rows and | |
275 | * socket sets. | |
276 | * | |
277 | * Controller pages: | |
278 | * | |
279 | * Physical pages: | |
280 | * | |
281 | * Virtual pages: | |
282 | * | |
283 | * | |
284 | * STRUCTURE ORGANIZATION AND CHOICES | |
285 | * | |
286 | * | |
287 | * | |
288 | * PS - I enjoyed writing all that about as much as you enjoyed reading it. | |
289 | */ | |
290 | ||
291 | struct channel_info { | |
292 | int chan_idx; /* channel index */ | |
293 | u32 ce_count; /* Correctable Errors for this CHANNEL */ | |
294 | char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ | |
295 | struct csrow_info *csrow; /* the parent */ | |
296 | }; | |
297 | ||
298 | struct csrow_info { | |
299 | unsigned long first_page; /* first page number in dimm */ | |
300 | unsigned long last_page; /* last page number in dimm */ | |
301 | unsigned long page_mask; /* used for interleaving - | |
302 | * 0UL for non intlv | |
303 | */ | |
304 | u32 nr_pages; /* number of pages in csrow */ | |
305 | u32 grain; /* granularity of reported error in bytes */ | |
306 | int csrow_idx; /* the chip-select row */ | |
307 | enum dev_type dtype; /* memory device type */ | |
308 | u32 ue_count; /* Uncorrectable Errors for this csrow */ | |
309 | u32 ce_count; /* Correctable Errors for this csrow */ | |
310 | enum mem_type mtype; /* memory csrow type */ | |
311 | enum edac_type edac_mode; /* EDAC mode for this csrow */ | |
312 | struct mem_ctl_info *mci; /* the parent */ | |
313 | ||
314 | struct kobject kobj; /* sysfs kobject for this csrow */ | |
315 | struct completion kobj_complete; | |
316 | ||
317 | /* FIXME the number of CHANNELs might need to become dynamic */ | |
318 | u32 nr_channels; | |
319 | struct channel_info *channels; | |
320 | }; | |
321 | ||
322 | struct mem_ctl_info { | |
323 | struct list_head link; /* for global list of mem_ctl_info structs */ | |
324 | unsigned long mtype_cap; /* memory types supported by mc */ | |
325 | unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */ | |
326 | unsigned long edac_cap; /* configuration capabilities - this is | |
327 | * closely related to edac_ctl_cap. The | |
328 | * difference is that the controller may be | |
329 | * capable of s4ecd4ed which would be listed | |
330 | * in edac_ctl_cap, but if channels aren't | |
331 | * capable of s4ecd4ed then the edac_cap would | |
332 | * not have that capability. | |
333 | */ | |
334 | unsigned long scrub_cap; /* chipset scrub capabilities */ | |
335 | enum scrub_type scrub_mode; /* current scrub mode */ | |
336 | ||
337 | /* Translates sdram memory scrub rate given in bytes/sec to the | |
338 | internal representation and configures whatever else needs | |
339 | to be configured. | |
340 | */ | |
341 | int (*set_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw); | |
342 | ||
343 | /* Get the current sdram memory scrub rate from the internal | |
344 | representation and converts it to the closest matching | |
345 | bandwith in bytes/sec. | |
346 | */ | |
347 | int (*get_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw); | |
348 | ||
349 | /* pointer to edac checking routine */ | |
350 | void (*edac_check) (struct mem_ctl_info * mci); | |
351 | ||
352 | /* | |
353 | * Remaps memory pages: controller pages to physical pages. | |
354 | * For most MC's, this will be NULL. | |
355 | */ | |
356 | /* FIXME - why not send the phys page to begin with? */ | |
357 | unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci, | |
358 | unsigned long page); | |
359 | int mc_idx; | |
360 | int nr_csrows; | |
361 | struct csrow_info *csrows; | |
362 | /* | |
363 | * FIXME - what about controllers on other busses? - IDs must be | |
364 | * unique. dev pointer should be sufficiently unique, but | |
365 | * BUS:SLOT.FUNC numbers may not be unique. | |
366 | */ | |
367 | struct device *dev; | |
368 | const char *mod_name; | |
369 | const char *mod_ver; | |
370 | const char *ctl_name; | |
371 | char proc_name[MC_PROC_NAME_MAX_LEN + 1]; | |
372 | void *pvt_info; | |
373 | u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */ | |
374 | u32 ce_noinfo_count; /* Correctable Errors w/o info */ | |
375 | u32 ue_count; /* Total Uncorrectable Errors for this MC */ | |
376 | u32 ce_count; /* Total Correctable Errors for this MC */ | |
377 | unsigned long start_time; /* mci load start time (in jiffies) */ | |
378 | ||
379 | /* this stuff is for safe removal of mc devices from global list while | |
380 | * NMI handlers may be traversing list | |
381 | */ | |
382 | struct rcu_head rcu; | |
383 | struct completion complete; | |
384 | ||
385 | /* edac sysfs device control */ | |
386 | struct kobject edac_mci_kobj; | |
387 | struct completion kobj_complete; | |
388 | }; | |
389 | ||
e27e3dac DT |
390 | /* |
391 | * The following are the structures to provide for a generice | |
392 | * or abstract 'edac_device'. This set of structures and the | |
393 | * code that implements the APIs for the same, provide for | |
394 | * registering EDAC type devices which are NOT standard memory. | |
395 | * | |
396 | * CPU caches (L1 and L2) | |
397 | * DMA engines | |
398 | * Core CPU swithces | |
399 | * Fabric switch units | |
400 | * PCIe interface controllers | |
401 | * other EDAC/ECC type devices that can be monitored for | |
402 | * errors, etc. | |
403 | * | |
404 | * It allows for a 2 level set of hiearchry. For example: | |
405 | * | |
406 | * cache could be composed of L1, L2 and L3 levels of cache. | |
407 | * Each CPU core would have its own L1 cache, while sharing | |
408 | * L2 and maybe L3 caches. | |
409 | * | |
410 | * View them arranged, via the sysfs presentation: | |
411 | * /sys/devices/system/edac/.. | |
412 | * | |
413 | * mc/ <existing memory device directory> | |
414 | * cpu/cpu0/.. <L1 and L2 block directory> | |
415 | * /L1-cache/ce_count | |
416 | * /ue_count | |
417 | * /L2-cache/ce_count | |
418 | * /ue_count | |
419 | * cpu/cpu1/.. <L1 and L2 block directory> | |
420 | * /L1-cache/ce_count | |
421 | * /ue_count | |
422 | * /L2-cache/ce_count | |
423 | * /ue_count | |
424 | * ... | |
425 | * | |
426 | * the L1 and L2 directories would be "edac_device_block's" | |
427 | */ | |
428 | ||
429 | struct edac_device_counter { | |
430 | u32 ue_count; | |
431 | u32 ce_count; | |
432 | }; | |
433 | ||
434 | #define INC_COUNTER(cnt) (cnt++) | |
435 | ||
436 | /* | |
437 | * An array of these is passed to the alloc() function | |
438 | * to specify attributes of the edac_block | |
439 | */ | |
440 | struct edac_attrib_spec { | |
441 | char name[EDAC_DEVICE_NAME_LEN + 1]; | |
442 | ||
443 | int type; | |
444 | #define EDAC_ATTR_INT 0x01 | |
445 | #define EDAC_ATTR_CHAR 0x02 | |
446 | }; | |
447 | ||
448 | ||
449 | /* Attribute control structure | |
450 | * In this structure is a pointer to the driver's edac_attrib_spec | |
451 | * The life of this pointer is inclusive in the life of the driver's | |
452 | * life cycle. | |
453 | */ | |
454 | struct edac_attrib { | |
455 | struct edac_device_block *block; /* Up Pointer */ | |
456 | ||
457 | struct edac_attrib_spec *spec; /* ptr to module spec entry */ | |
458 | ||
459 | union { /* actual value */ | |
460 | int edac_attrib_int_value; | |
461 | char edac_attrib_char_value[EDAC_ATTRIB_VALUE_LEN + 1]; | |
462 | } edac_attrib_value; | |
463 | }; | |
464 | ||
465 | /* device block control structure */ | |
466 | struct edac_device_block { | |
467 | struct edac_device_instance *instance; /* Up Pointer */ | |
468 | char name[EDAC_DEVICE_NAME_LEN + 1]; | |
469 | ||
470 | struct edac_device_counter counters; /* basic UE and CE counters */ | |
471 | ||
472 | int nr_attribs; /* how many attributes */ | |
473 | struct edac_attrib *attribs; /* this block's attributes */ | |
474 | ||
475 | /* edac sysfs device control */ | |
476 | struct kobject kobj; | |
477 | struct completion kobj_complete; | |
478 | }; | |
479 | ||
480 | /* device instance control structure */ | |
481 | struct edac_device_instance { | |
482 | struct edac_device_ctl_info *ctl; /* Up pointer */ | |
483 | char name[EDAC_DEVICE_NAME_LEN + 4]; | |
484 | ||
485 | struct edac_device_counter counters; /* instance counters */ | |
486 | ||
487 | u32 nr_blocks; /* how many blocks */ | |
488 | struct edac_device_block *blocks; /* block array */ | |
489 | ||
490 | /* edac sysfs device control */ | |
491 | struct kobject kobj; | |
492 | struct completion kobj_complete; | |
493 | }; | |
494 | ||
495 | ||
496 | /* | |
497 | * Abstract edac_device control info structure | |
498 | * | |
499 | */ | |
500 | struct edac_device_ctl_info { | |
501 | /* for global list of edac_device_ctl_info structs */ | |
502 | struct list_head link; | |
503 | ||
504 | int dev_idx; | |
505 | ||
506 | /* Per instance controls for this edac_device */ | |
507 | int log_ue; /* boolean for logging UEs */ | |
508 | int log_ce; /* boolean for logging CEs */ | |
509 | int panic_on_ue; /* boolean for panic'ing on an UE */ | |
510 | unsigned poll_msec; /* number of milliseconds to poll interval */ | |
511 | unsigned long delay; /* number of jiffies for poll_msec */ | |
512 | ||
513 | struct sysdev_class *edac_class; /* pointer to class */ | |
514 | ||
515 | /* the internal state of this controller instance */ | |
516 | int op_state; | |
517 | #define OP_ALLOC 0x100 | |
518 | #define OP_RUNNING_POLL 0x201 | |
519 | #define OP_RUNNING_INTERRUPT 0x202 | |
520 | #define OP_RUNNING_POLL_INTR 0x203 | |
521 | #define OP_OFFLINE 0x300 | |
522 | ||
523 | /* work struct for this instance */ | |
524 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) | |
525 | struct delayed_work work; | |
526 | #else | |
527 | struct work_struct work; | |
528 | #endif | |
529 | ||
530 | /* pointer to edac polling checking routine: | |
531 | * If NOT NULL: points to polling check routine | |
532 | * If NULL: Then assumes INTERRUPT operation, where | |
533 | * MC driver will receive events | |
534 | */ | |
535 | void (*edac_check) (struct edac_device_ctl_info * edac_dev); | |
536 | ||
537 | struct device *dev; /* pointer to device structure */ | |
538 | ||
539 | const char *mod_name; /* module name */ | |
540 | const char *ctl_name; /* edac controller name */ | |
541 | ||
542 | void *pvt_info; /* pointer to 'private driver' info */ | |
543 | ||
544 | unsigned long start_time;/* edac_device load start time (jiffies)*/ | |
545 | ||
546 | /* these are for safe removal of mc devices from global list while | |
547 | * NMI handlers may be traversing list | |
548 | */ | |
549 | struct rcu_head rcu; | |
550 | struct completion complete; | |
551 | ||
552 | /* sysfs top name under 'edac' directory | |
553 | * and instance name: | |
554 | * cpu/cpu0/... | |
555 | * cpu/cpu1/... | |
556 | * cpu/cpu2/... | |
557 | * ... | |
558 | */ | |
559 | char name[EDAC_DEVICE_NAME_LEN + 1]; | |
560 | ||
561 | /* Number of instances supported on this control structure | |
562 | * and the array of those instances | |
563 | */ | |
564 | u32 nr_instances; | |
565 | struct edac_device_instance *instances; | |
566 | ||
567 | /* Event counters for the this whole EDAC Device */ | |
568 | struct edac_device_counter counters; | |
569 | ||
570 | /* edac sysfs device control for the 'name' | |
571 | * device this structure controls | |
572 | */ | |
573 | struct kobject kobj; | |
574 | struct completion kobj_complete; | |
575 | }; | |
576 | ||
577 | /* To get from the instance's wq to the beginning of the ctl structure */ | |
578 | #define to_edac_device_ctl_work(w) \ | |
579 | container_of(w,struct edac_device_ctl_info,work) | |
580 | ||
581 | /* Function to calc the number of delay jiffies from poll_msec */ | |
582 | static inline void edac_device_calc_delay( | |
583 | struct edac_device_ctl_info *edac_dev) | |
584 | { | |
585 | /* convert from msec to jiffies */ | |
586 | edac_dev->delay = edac_dev->poll_msec * HZ / 1000; | |
587 | } | |
588 | ||
589 | /* | |
590 | * The alloc() and free() functions for the 'edac_device' control info | |
591 | * structure. A MC driver will allocate one of these for each edac_device | |
592 | * it is going to control/register with the EDAC CORE. | |
593 | */ | |
594 | extern struct edac_device_ctl_info *edac_device_alloc_ctl_info( | |
595 | unsigned sizeof_private, | |
596 | char *edac_device_name, | |
597 | unsigned nr_instances, | |
598 | char *edac_block_name, | |
599 | unsigned nr_blocks, | |
600 | unsigned offset_value, | |
601 | struct edac_attrib_spec *attrib_spec, | |
602 | unsigned nr_attribs | |
603 | ); | |
604 | ||
605 | /* The offset value can be: | |
606 | * -1 indicating no offset value | |
607 | * 0 for zero-based block numbers | |
608 | * 1 for 1-based block number | |
609 | * other for other-based block number | |
610 | */ | |
611 | #define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1) | |
612 | ||
613 | extern void edac_device_free_ctl_info( struct edac_device_ctl_info *ctl_info); | |
614 | ||
7c9281d7 DT |
615 | #ifdef CONFIG_PCI |
616 | ||
617 | /* write all or some bits in a byte-register*/ | |
618 | static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value, | |
619 | u8 mask) | |
620 | { | |
621 | if (mask != 0xff) { | |
622 | u8 buf; | |
623 | ||
624 | pci_read_config_byte(pdev, offset, &buf); | |
625 | value &= mask; | |
626 | buf &= ~mask; | |
627 | value |= buf; | |
628 | } | |
629 | ||
630 | pci_write_config_byte(pdev, offset, value); | |
631 | } | |
632 | ||
633 | /* write all or some bits in a word-register*/ | |
634 | static inline void pci_write_bits16(struct pci_dev *pdev, int offset, | |
635 | u16 value, u16 mask) | |
636 | { | |
637 | if (mask != 0xffff) { | |
638 | u16 buf; | |
639 | ||
640 | pci_read_config_word(pdev, offset, &buf); | |
641 | value &= mask; | |
642 | buf &= ~mask; | |
643 | value |= buf; | |
644 | } | |
645 | ||
646 | pci_write_config_word(pdev, offset, value); | |
647 | } | |
648 | ||
649 | /* write all or some bits in a dword-register*/ | |
650 | static inline void pci_write_bits32(struct pci_dev *pdev, int offset, | |
651 | u32 value, u32 mask) | |
652 | { | |
653 | if (mask != 0xffff) { | |
654 | u32 buf; | |
655 | ||
656 | pci_read_config_dword(pdev, offset, &buf); | |
657 | value &= mask; | |
658 | buf &= ~mask; | |
659 | value |= buf; | |
660 | } | |
661 | ||
662 | pci_write_config_dword(pdev, offset, value); | |
663 | } | |
664 | ||
665 | #endif /* CONFIG_PCI */ | |
666 | ||
667 | extern struct mem_ctl_info * edac_mc_find(int idx); | |
668 | extern int edac_mc_add_mc(struct mem_ctl_info *mci,int mc_idx); | |
669 | extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev); | |
670 | extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, | |
671 | unsigned long page); | |
672 | ||
673 | /* | |
674 | * The no info errors are used when error overflows are reported. | |
675 | * There are a limited number of error logging registers that can | |
676 | * be exausted. When all registers are exhausted and an additional | |
677 | * error occurs then an error overflow register records that an | |
678 | * error occured and the type of error, but doesn't have any | |
679 | * further information. The ce/ue versions make for cleaner | |
680 | * reporting logic and function interface - reduces conditional | |
681 | * statement clutter and extra function arguments. | |
682 | */ | |
683 | extern void edac_mc_handle_ce(struct mem_ctl_info *mci, | |
684 | unsigned long page_frame_number, unsigned long offset_in_page, | |
685 | unsigned long syndrome, int row, int channel, | |
686 | const char *msg); | |
687 | extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci, | |
688 | const char *msg); | |
689 | extern void edac_mc_handle_ue(struct mem_ctl_info *mci, | |
690 | unsigned long page_frame_number, unsigned long offset_in_page, | |
691 | int row, const char *msg); | |
692 | extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci, | |
693 | const char *msg); | |
694 | extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, | |
695 | unsigned int csrow, | |
696 | unsigned int channel0, | |
697 | unsigned int channel1, | |
698 | char *msg); | |
699 | extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, | |
700 | unsigned int csrow, | |
701 | unsigned int channel, | |
702 | char *msg); | |
703 | ||
704 | /* | |
e27e3dac | 705 | * edac_device APIs |
7c9281d7 DT |
706 | */ |
707 | extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows, | |
708 | unsigned nr_chans); | |
7c9281d7 | 709 | extern void edac_mc_free(struct mem_ctl_info *mci); |
e27e3dac DT |
710 | extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev, int edac_idx); |
711 | extern struct edac_device_ctl_info * edac_device_del_device(struct device *dev); | |
712 | extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev, | |
713 | int inst_nr, int block_nr, const char *msg); | |
714 | extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev, | |
715 | int inst_nr, int block_nr, const char *msg); | |
716 | ||
7c9281d7 DT |
717 | |
718 | #endif /* _EDAC_CORE_H_ */ |