[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / edac / edac_core.h

/*
 * Defines, structures, APIs for edac_core module
 *
 * (C) 2007 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Thayne Harbaugh
 * Based on work by Dan Hollis <goemon at anime dot net> and others.
 *	http://www.anime.net/~goemon/linux-ecc/
 *
 * NMI handling support added by
 *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
 *
 * Refactored for multi-source files:
 *	Doug Thompson <norsk5@xmission.com>
 *
 */

#ifndef _EDAC_CORE_H_
#define _EDAC_CORE_H_

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/pci.h>
#include <linux/time.h>
#include <linux/nmi.h>
#include <linux/rcupdate.h>
#include <linux/completion.h>
#include <linux/kobject.h>
#include <linux/platform_device.h>
#include <linux/workqueue.h>
#include <linux/edac.h>

#define EDAC_DEVICE_NAME_LEN	31
#define EDAC_ATTRIB_VALUE_LEN	15

#if PAGE_SHIFT < 20
#define PAGES_TO_MiB(pages)	((pages) >> (20 - PAGE_SHIFT))
#define MiB_TO_PAGES(mb)	((mb) << (20 - PAGE_SHIFT))
#else				/* PAGE_SHIFT > 20 */
#define PAGES_TO_MiB(pages)	((pages) << (PAGE_SHIFT - 20))
#define MiB_TO_PAGES(mb)	((mb) >> (PAGE_SHIFT - 20))
#endif

#define edac_printk(level, prefix, fmt, arg...) \
	printk(level "EDAC " prefix ": " fmt, ##arg)

#define edac_mc_printk(mci, level, fmt, arg...) \
	printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)

#define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
	printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)

#define edac_device_printk(ctl, level, fmt, arg...) \
	printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)

#define edac_pci_printk(ctl, level, fmt, arg...) \
	printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)

/* prefixes for edac_printk() and edac_mc_printk() */
#define EDAC_MC "MC"
#define EDAC_PCI "PCI"
#define EDAC_DEBUG "DEBUG"

extern const char *edac_mem_types[];

#ifdef CONFIG_EDAC_DEBUG
extern int edac_debug_level;

#define edac_debug_printk(level, fmt, arg...)                           \
	do {                                                            \
		if (level <= edac_debug_level)                          \
			edac_printk(KERN_DEBUG, EDAC_DEBUG,		\
				    "%s: " fmt, __func__, ##arg);	\
	} while (0)

#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
#define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
#define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
#define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )

#else				/* !CONFIG_EDAC_DEBUG */

#define debugf0( ... )
#define debugf1( ... )
#define debugf2( ... )
#define debugf3( ... )
#define debugf4( ... )

#endif				/* !CONFIG_EDAC_DEBUG */

#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
	PCI_DEVICE_ID_ ## vend ## _ ## dev

#define edac_dev_name(dev) (dev)->dev_name

/*
 * The following are the structures to provide for a generic
 * or abstract 'edac_device'. This set of structures and the
 * code that implements the APIs for the same, provide for
 * registering EDAC type devices which are NOT standard memory.
 *
 * CPU caches (L1 and L2)
 * DMA engines
 * Core CPU swithces
 * Fabric switch units
 * PCIe interface controllers
 * other EDAC/ECC type devices that can be monitored for
 * errors, etc.
 *
 * It allows for a 2 level set of hiearchry. For example:
 *
 * cache could be composed of L1, L2 and L3 levels of cache.
 * Each CPU core would have its own L1 cache, while sharing
 * L2 and maybe L3 caches.
 *
 * View them arranged, via the sysfs presentation:
 * /sys/devices/system/edac/..
 *
 *	mc/		<existing memory device directory>
 *	cpu/cpu0/..	<L1 and L2 block directory>
 *		/L1-cache/ce_count
 *			 /ue_count
 *		/L2-cache/ce_count
 *			 /ue_count
 *	cpu/cpu1/..	<L1 and L2 block directory>
 *		/L1-cache/ce_count
 *			 /ue_count
 *		/L2-cache/ce_count
 *			 /ue_count
 *	...
 *
 *	the L1 and L2 directories would be "edac_device_block's"
 */

struct edac_device_counter {
	u32 ue_count;
	u32 ce_count;
};

/* forward reference */
struct edac_device_ctl_info;
struct edac_device_block;

/* edac_dev_sysfs_attribute structure
 *	used for driver sysfs attributes in mem_ctl_info
 *	for extra controls and attributes:
 *		like high level error Injection controls
 */
struct edac_dev_sysfs_attribute {
	struct attribute attr;
	ssize_t (*show)(struct edac_device_ctl_info *, char *);
	ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
};

/* edac_dev_sysfs_block_attribute structure
 *
 *	used in leaf 'block' nodes for adding controls/attributes
 *
 *	each block in each instance of the containing control structure
 *	can have an array of the following. The show and store functions
 *	will be filled in with the show/store function in the
 *	low level driver.
 *
 *	The 'value' field will be the actual value field used for
 *	counting
 */
struct edac_dev_sysfs_block_attribute {
	struct attribute attr;
	ssize_t (*show)(struct kobject *, struct attribute *, char *);
	ssize_t (*store)(struct kobject *, struct attribute *,
			const char *, size_t);
	struct edac_device_block *block;

	unsigned int value;
};

/* device block control structure */
struct edac_device_block {
	struct edac_device_instance *instance;	/* Up Pointer */
	char name[EDAC_DEVICE_NAME_LEN + 1];

	struct edac_device_counter counters;	/* basic UE and CE counters */

	int nr_attribs;		/* how many attributes */

	/* this block's attributes, could be NULL */
	struct edac_dev_sysfs_block_attribute *block_attributes;

	/* edac sysfs device control */
	struct kobject kobj;
};

/* device instance control structure */
struct edac_device_instance {
	struct edac_device_ctl_info *ctl;	/* Up pointer */
	char name[EDAC_DEVICE_NAME_LEN + 4];

	struct edac_device_counter counters;	/* instance counters */

	u32 nr_blocks;		/* how many blocks */
	struct edac_device_block *blocks;	/* block array */

	/* edac sysfs device control */
	struct kobject kobj;
};


/*
 * Abstract edac_device control info structure
 *
 */
struct edac_device_ctl_info {
	/* for global list of edac_device_ctl_info structs */
	struct list_head link;

	struct module *owner;	/* Module owner of this control struct */

	int dev_idx;

	/* Per instance controls for this edac_device */
	int log_ue;		/* boolean for logging UEs */
	int log_ce;		/* boolean for logging CEs */
	int panic_on_ue;	/* boolean for panic'ing on an UE */
	unsigned poll_msec;	/* number of milliseconds to poll interval */
	unsigned long delay;	/* number of jiffies for poll_msec */

	/* Additional top controller level attributes, but specified
	 * by the low level driver.
	 *
	 * Set by the low level driver to provide attributes at the
	 * controller level, same level as 'ue_count' and 'ce_count' above.
	 * An array of structures, NULL terminated
	 *
	 * If attributes are desired, then set to array of attributes
	 * If no attributes are desired, leave NULL
	 */
	struct edac_dev_sysfs_attribute *sysfs_attributes;

	/* pointer to main 'edac' subsys in sysfs */
	struct bus_type *edac_subsys;

	/* the internal state of this controller instance */
	int op_state;
	/* work struct for this instance */
	struct delayed_work work;

	/* pointer to edac polling checking routine:
	 *      If NOT NULL: points to polling check routine
	 *      If NULL: Then assumes INTERRUPT operation, where
	 *              MC driver will receive events
	 */
	void (*edac_check) (struct edac_device_ctl_info * edac_dev);

	struct device *dev;	/* pointer to device structure */

	const char *mod_name;	/* module name */
	const char *ctl_name;	/* edac controller  name */
	const char *dev_name;	/* pci/platform/etc... name */

	void *pvt_info;		/* pointer to 'private driver' info */

	unsigned long start_time;	/* edac_device load start time (jiffies) */

	struct completion removal_complete;

	/* sysfs top name under 'edac' directory
	 * and instance name:
	 *      cpu/cpu0/...
	 *      cpu/cpu1/...
	 *      cpu/cpu2/...
	 *      ...
	 */
	char name[EDAC_DEVICE_NAME_LEN + 1];

	/* Number of instances supported on this control structure
	 * and the array of those instances
	 */
	u32 nr_instances;
	struct edac_device_instance *instances;

	/* Event counters for the this whole EDAC Device */
	struct edac_device_counter counters;

	/* edac sysfs device control for the 'name'
	 * device this structure controls
	 */
	struct kobject kobj;
};

/* To get from the instance's wq to the beginning of the ctl structure */
#define to_edac_mem_ctl_work(w) \
		container_of(w, struct mem_ctl_info, work)

#define to_edac_device_ctl_work(w) \
		container_of(w,struct edac_device_ctl_info,work)

/*
 * The alloc() and free() functions for the 'edac_device' control info
 * structure. A MC driver will allocate one of these for each edac_device
 * it is going to control/register with the EDAC CORE.
 */
extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
		unsigned sizeof_private,
		char *edac_device_name, unsigned nr_instances,
		char *edac_block_name, unsigned nr_blocks,
		unsigned offset_value,
		struct edac_dev_sysfs_block_attribute *block_attributes,
		unsigned nr_attribs,
		int device_index);

/* The offset value can be:
 *	-1 indicating no offset value
 *	0 for zero-based block numbers
 *	1 for 1-based block number
 *	other for other-based block number
 */
#define	BLOCK_OFFSET_VALUE_OFF	((unsigned) -1)

extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);

#ifdef CONFIG_PCI

struct edac_pci_counter {
	atomic_t pe_count;
	atomic_t npe_count;
};

/*
 * Abstract edac_pci control info structure
 *
 */
struct edac_pci_ctl_info {
	/* for global list of edac_pci_ctl_info structs */
	struct list_head link;

	int pci_idx;

	struct bus_type *edac_subsys;	/* pointer to subsystem */

	/* the internal state of this controller instance */
	int op_state;
	/* work struct for this instance */
	struct delayed_work work;

	/* pointer to edac polling checking routine:
	 *      If NOT NULL: points to polling check routine
	 *      If NULL: Then assumes INTERRUPT operation, where
	 *              MC driver will receive events
	 */
	void (*edac_check) (struct edac_pci_ctl_info * edac_dev);

	struct device *dev;	/* pointer to device structure */

	const char *mod_name;	/* module name */
	const char *ctl_name;	/* edac controller  name */
	const char *dev_name;	/* pci/platform/etc... name */

	void *pvt_info;		/* pointer to 'private driver' info */

	unsigned long start_time;	/* edac_pci load start time (jiffies) */

	struct completion complete;

	/* sysfs top name under 'edac' directory
	 * and instance name:
	 *      cpu/cpu0/...
	 *      cpu/cpu1/...
	 *      cpu/cpu2/...
	 *      ...
	 */
	char name[EDAC_DEVICE_NAME_LEN + 1];

	/* Event counters for the this whole EDAC Device */
	struct edac_pci_counter counters;

	/* edac sysfs device control for the 'name'
	 * device this structure controls
	 */
	struct kobject kobj;
	struct completion kobj_complete;
};

#define to_edac_pci_ctl_work(w) \
		container_of(w, struct edac_pci_ctl_info,work)

/* write all or some bits in a byte-register*/
static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
				   u8 mask)
{
	if (mask != 0xff) {
		u8 buf;

		pci_read_config_byte(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_byte(pdev, offset, value);
}

/* write all or some bits in a word-register*/
static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
				    u16 value, u16 mask)
{
	if (mask != 0xffff) {
		u16 buf;

		pci_read_config_word(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_word(pdev, offset, value);
}

/*
 * pci_write_bits32
 *
 * edac local routine to do pci_write_config_dword, but adds
 * a mask parameter. If mask is all ones, ignore the mask.
 * Otherwise utilize the mask to isolate specified bits
 *
 * write all or some bits in a dword-register
 */
static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
				    u32 value, u32 mask)
{
	if (mask != 0xffffffff) {
		u32 buf;

		pci_read_config_dword(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_dword(pdev, offset, value);
}

#endif				/* CONFIG_PCI */

extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
					  unsigned nr_chans, int edac_index);
extern int edac_mc_add_mc(struct mem_ctl_info *mci);
extern void edac_mc_free(struct mem_ctl_info *mci);
extern struct mem_ctl_info *edac_mc_find(int idx);
extern struct mem_ctl_info *find_mci_by_dev(struct device *dev);
extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
				      unsigned long page);

/*
 * The no info errors are used when error overflows are reported.
 * There are a limited number of error logging registers that can
 * be exausted.  When all registers are exhausted and an additional
 * error occurs then an error overflow register records that an
 * error occurred and the type of error, but doesn't have any
 * further information.  The ce/ue versions make for cleaner
 * reporting logic and function interface - reduces conditional
 * statement clutter and extra function arguments.
 */
extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
			      unsigned long page_frame_number,
			      unsigned long offset_in_page,
			      unsigned long syndrome, int row, int channel,
			      const char *msg);
extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
				      const char *msg);
extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
			      unsigned long page_frame_number,
			      unsigned long offset_in_page, int row,
			      const char *msg);
extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
				      const char *msg);
extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
				  unsigned int channel0, unsigned int channel1,
				  char *msg);
extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
				  unsigned int channel, char *msg);

/*
 * edac_device APIs
 */
extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
				int inst_nr, int block_nr, const char *msg);
extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
				int inst_nr, int block_nr, const char *msg);
extern int edac_device_alloc_index(void);

/*
 * edac_pci APIs
 */
extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
				const char *edac_pci_name);

extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);

extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
				unsigned long value);

extern int edac_pci_alloc_index(void);
extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);

extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
				struct device *dev,
				const char *mod_name);

extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);

/*
 * edac misc APIs
 */
extern char *edac_op_state_to_string(int op_state);

#endif				/* _EDAC_CORE_H_ */
Commit	Line	Data
7c9281d7 DT	1	/*
	2	* Defines, structures, APIs for edac_core module
	3	*
	4	* (C) 2007 Linux Networx (http://lnxi.com)
	5	* This file may be distributed under the terms of the
	6	* GNU General Public License.
	7	*
	8	* Written by Thayne Harbaugh
	9	* Based on work by Dan Hollis <goemon at anime dot net> and others.
	10	* http://www.anime.net/~goemon/linux-ecc/
	11	*
	12	* NMI handling support added by
	13	* Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
	14	*
	15	* Refactored for multi-source files:
	16	* Doug Thompson <norsk5@xmission.com>
	17	*
	18	*/
	19
	20	#ifndef _EDAC_CORE_H_
	21	#define _EDAC_CORE_H_
	22
	23	#include <linux/kernel.h>
	24	#include <linux/types.h>
	25	#include <linux/module.h>
	26	#include <linux/spinlock.h>
	27	#include <linux/smp.h>
	28	#include <linux/pci.h>
	29	#include <linux/time.h>
	30	#include <linux/nmi.h>
	31	#include <linux/rcupdate.h>
	32	#include <linux/completion.h>
	33	#include <linux/kobject.h>
	34	#include <linux/platform_device.h>
e27e3dac	35	#include <linux/workqueue.h>
ddeb3547	36	#include <linux/edac.h>
7c9281d7	37
e27e3dac DT	38	#define EDAC_DEVICE_NAME_LEN 31
e27e3dac DT	39	#define EDAC_ATTRIB_VALUE_LEN 15
7c9281d7 DT	40
7c9281d7 DT	41	#if PAGE_SHIFT < 20
76f04f25 AK	42	#define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT))
76f04f25 AK	43	#define MiB_TO_PAGES(mb) ((mb) << (20 - PAGE_SHIFT))
7c9281d7	44	#else /* PAGE_SHIFT > 20 */
76f04f25	45	#define PAGES_TO_MiB(pages) ((pages) << (PAGE_SHIFT - 20))
e9144601	46	#define MiB_TO_PAGES(mb) ((mb) >> (PAGE_SHIFT - 20))
7c9281d7 DT	47	#endif
	48
	49	#define edac_printk(level, prefix, fmt, arg...) \
	50	printk(level "EDAC " prefix ": " fmt, ##arg)
	51
	52	#define edac_mc_printk(mci, level, fmt, arg...) \
	53	printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
	54
	55	#define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
	56	printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
	57
e27e3dac DT	58	#define edac_device_printk(ctl, level, fmt, arg...) \
	59	printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
	60
91b99041 DJ	61	#define edac_pci_printk(ctl, level, fmt, arg...) \
	62	printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
	63
7c9281d7 DT	64	/* prefixes for edac_printk() and edac_mc_printk() */
	65	#define EDAC_MC "MC"
	66	#define EDAC_PCI "PCI"
	67	#define EDAC_DEBUG "DEBUG"
	68
24f9a7fe BP	69	extern const char *edac_mem_types[];
24f9a7fe BP	70
7c9281d7 DT	71	#ifdef CONFIG_EDAC_DEBUG
	72	extern int edac_debug_level;
	73
d357cbb4 BP	74	#define edac_debug_printk(level, fmt, arg...) \
	75	do { \
	76	if (level <= edac_debug_level) \
	77	edac_printk(KERN_DEBUG, EDAC_DEBUG, \
	78	"%s: " fmt, __func__, ##arg); \
cc18e3cd	79	} while (0)
7c9281d7 DT	80
	81	#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
	82	#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
	83	#define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
	84	#define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
	85	#define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
	86
079708b9	87	#else /* !CONFIG_EDAC_DEBUG */
7c9281d7 DT	88
	89	#define debugf0( ... )
	90	#define debugf1( ... )
	91	#define debugf2( ... )
	92	#define debugf3( ... )
	93	#define debugf4( ... )
	94
079708b9	95	#endif /* !CONFIG_EDAC_DEBUG */
7c9281d7	96
7c9281d7 DT	97	#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
	98	PCI_DEVICE_ID_ ## vend ## _ ## dev
	99
17aa7e03	100	#define edac_dev_name(dev) (dev)->dev_name
7c9281d7	101
e27e3dac	102	/*
42a8e397	103	* The following are the structures to provide for a generic
e27e3dac DT	104	* or abstract 'edac_device'. This set of structures and the
	105	* code that implements the APIs for the same, provide for
	106	* registering EDAC type devices which are NOT standard memory.
	107	*
	108	* CPU caches (L1 and L2)
	109	* DMA engines
	110	* Core CPU swithces
	111	* Fabric switch units
	112	* PCIe interface controllers
	113	* other EDAC/ECC type devices that can be monitored for
	114	* errors, etc.
	115	*
	116	* It allows for a 2 level set of hiearchry. For example:
	117	*
	118	* cache could be composed of L1, L2 and L3 levels of cache.
	119	* Each CPU core would have its own L1 cache, while sharing
	120	* L2 and maybe L3 caches.
	121	*
	122	* View them arranged, via the sysfs presentation:
	123	* /sys/devices/system/edac/..
	124	*
	125	* mc/ <existing memory device directory>
	126	* cpu/cpu0/.. <L1 and L2 block directory>
	127	* /L1-cache/ce_count
	128	* /ue_count
	129	* /L2-cache/ce_count
	130	* /ue_count
	131	* cpu/cpu1/.. <L1 and L2 block directory>
	132	* /L1-cache/ce_count
	133	* /ue_count
	134	* /L2-cache/ce_count
	135	* /ue_count
	136	* ...
	137	*
	138	* the L1 and L2 directories would be "edac_device_block's"
	139	*/
	140
	141	struct edac_device_counter {
079708b9 DT	142	u32 ue_count;
079708b9 DT	143	u32 ce_count;
e27e3dac DT	144	};
e27e3dac DT	145
fd309a9d DT	146	/* forward reference */
	147	struct edac_device_ctl_info;
	148	struct edac_device_block;
e27e3dac	149
fd309a9d DT	150	/* edac_dev_sysfs_attribute structure
	151	* used for driver sysfs attributes in mem_ctl_info
	152	* for extra controls and attributes:
	153	* like high level error Injection controls
	154	*/
	155	struct edac_dev_sysfs_attribute {
	156	struct attribute attr;
	157	ssize_t (show)(struct edac_device_ctl_info , char *);
	158	ssize_t (store)(struct edac_device_ctl_info , const char *, size_t);
e27e3dac DT	159	};
e27e3dac DT	160
fd309a9d	161	/* edac_dev_sysfs_block_attribute structure
b2a4ac0c	162	*
fd309a9d	163	* used in leaf 'block' nodes for adding controls/attributes
b2a4ac0c DT	164	*
	165	* each block in each instance of the containing control structure
	166	* can have an array of the following. The show and store functions
	167	* will be filled in with the show/store function in the
	168	* low level driver.
	169	*
	170	* The 'value' field will be the actual value field used for
	171	* counting
e27e3dac	172	*/
fd309a9d DT	173	struct edac_dev_sysfs_block_attribute {
	174	struct attribute attr;
	175	ssize_t (show)(struct kobject , struct attribute , char );
	176	ssize_t (store)(struct kobject , struct attribute *,
	177	const char *, size_t);
	178	struct edac_device_block *block;
	179
fd309a9d	180	unsigned int value;
e27e3dac DT	181	};
	182
	183	/* device block control structure */
	184	struct edac_device_block {
	185	struct edac_device_instance instance; / Up Pointer */
079708b9	186	char name[EDAC_DEVICE_NAME_LEN + 1];
e27e3dac DT	187
	188	struct edac_device_counter counters; /* basic UE and CE counters */
	189
079708b9	190	int nr_attribs; /* how many attributes */
fd309a9d DT	191
	192	/* this block's attributes, could be NULL */
	193	struct edac_dev_sysfs_block_attribute *block_attributes;
e27e3dac DT	194
	195	/* edac sysfs device control */
	196	struct kobject kobj;
e27e3dac DT	197	};
	198
	199	/* device instance control structure */
	200	struct edac_device_instance {
	201	struct edac_device_ctl_info ctl; / Up pointer */
	202	char name[EDAC_DEVICE_NAME_LEN + 4];
	203
	204	struct edac_device_counter counters; /* instance counters */
	205
079708b9	206	u32 nr_blocks; /* how many blocks */
e27e3dac DT	207	struct edac_device_block blocks; / block array */
	208
	209	/* edac sysfs device control */
	210	struct kobject kobj;
e27e3dac DT	211	};
e27e3dac DT	212
42a8e397	213
e27e3dac DT	214	/*
	215	* Abstract edac_device control info structure
	216	*
	217	*/
	218	struct edac_device_ctl_info {
	219	/* for global list of edac_device_ctl_info structs */
	220	struct list_head link;
	221
1c3631ff DT	222	struct module owner; / Module owner of this control struct */
1c3631ff DT	223
e27e3dac DT	224	int dev_idx;
	225
	226	/* Per instance controls for this edac_device */
	227	int log_ue; /* boolean for logging UEs */
	228	int log_ce; /* boolean for logging CEs */
	229	int panic_on_ue; /* boolean for panic'ing on an UE */
	230	unsigned poll_msec; /* number of milliseconds to poll interval */
	231	unsigned long delay; /* number of jiffies for poll_msec */
	232
42a8e397 DT	233	/* Additional top controller level attributes, but specified
	234	* by the low level driver.
	235	*
	236	* Set by the low level driver to provide attributes at the
	237	* controller level, same level as 'ue_count' and 'ce_count' above.
	238	* An array of structures, NULL terminated
	239	*
	240	* If attributes are desired, then set to array of attributes
	241	* If no attributes are desired, leave NULL
	242	*/
	243	struct edac_dev_sysfs_attribute *sysfs_attributes;
	244
fe5ff8b8 KS	245	/* pointer to main 'edac' subsys in sysfs */
fe5ff8b8 KS	246	struct bus_type *edac_subsys;
e27e3dac DT	247
	248	/* the internal state of this controller instance */
	249	int op_state;
e27e3dac	250	/* work struct for this instance */
e27e3dac	251	struct delayed_work work;
e27e3dac DT	252
e27e3dac DT	253	/* pointer to edac polling checking routine:
079708b9 DT	254	* If NOT NULL: points to polling check routine
	255	* If NULL: Then assumes INTERRUPT operation, where
	256	* MC driver will receive events
e27e3dac DT	257	*/
	258	void (edac_check) (struct edac_device_ctl_info edac_dev);
	259
	260	struct device dev; / pointer to device structure */
	261
	262	const char mod_name; / module name */
	263	const char ctl_name; / edac controller name */
c4192705	264	const char dev_name; / pci/platform/etc... name */
e27e3dac DT	265
	266	void pvt_info; / pointer to 'private driver' info */
	267
079708b9	268	unsigned long start_time; /* edac_device load start time (jiffies) */
e27e3dac	269
1c3631ff	270	struct completion removal_complete;
e27e3dac DT	271
	272	/* sysfs top name under 'edac' directory
	273	* and instance name:
079708b9 DT	274	* cpu/cpu0/...
	275	* cpu/cpu1/...
	276	* cpu/cpu2/...
	277	* ...
e27e3dac DT	278	*/
	279	char name[EDAC_DEVICE_NAME_LEN + 1];
	280
	281	/* Number of instances supported on this control structure
	282	* and the array of those instances
	283	*/
	284	u32 nr_instances;
	285	struct edac_device_instance *instances;
	286
	287	/* Event counters for the this whole EDAC Device */
	288	struct edac_device_counter counters;
	289
	290	/* edac sysfs device control for the 'name'
	291	* device this structure controls
	292	*/
	293	struct kobject kobj;
e27e3dac DT	294	};
	295
	296	/* To get from the instance's wq to the beginning of the ctl structure */
81d87cb1 DJ	297	#define to_edac_mem_ctl_work(w) \
	298	container_of(w, struct mem_ctl_info, work)
	299
e27e3dac DT	300	#define to_edac_device_ctl_work(w) \
	301	container_of(w,struct edac_device_ctl_info,work)
	302
e27e3dac DT	303	/*
	304	* The alloc() and free() functions for the 'edac_device' control info
	305	* structure. A MC driver will allocate one of these for each edac_device
	306	* it is going to control/register with the EDAC CORE.
	307	*/
	308	extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
079708b9	309	unsigned sizeof_private,
fd309a9d DT	310	char *edac_device_name, unsigned nr_instances,
fd309a9d DT	311	char *edac_block_name, unsigned nr_blocks,
079708b9	312	unsigned offset_value,
fd309a9d	313	struct edac_dev_sysfs_block_attribute *block_attributes,
d45e7823 DT	314	unsigned nr_attribs,
d45e7823 DT	315	int device_index);
e27e3dac DT	316
	317	/* The offset value can be:
	318	* -1 indicating no offset value
	319	* 0 for zero-based block numbers
	320	* 1 for 1-based block number
	321	* other for other-based block number
	322	*/
	323	#define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
	324
079708b9	325	extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
e27e3dac	326
7c9281d7 DT	327	#ifdef CONFIG_PCI
7c9281d7 DT	328
91b99041	329	struct edac_pci_counter {
079708b9 DT	330	atomic_t pe_count;
079708b9 DT	331	atomic_t npe_count;
91b99041 DJ	332	};
	333
	334	/*
	335	* Abstract edac_pci control info structure
	336	*
	337	*/
	338	struct edac_pci_ctl_info {
	339	/* for global list of edac_pci_ctl_info structs */
	340	struct list_head link;
	341
	342	int pci_idx;
	343
fe5ff8b8	344	struct bus_type edac_subsys; / pointer to subsystem */
91b99041 DJ	345
	346	/* the internal state of this controller instance */
	347	int op_state;
	348	/* work struct for this instance */
91b99041	349	struct delayed_work work;
91b99041 DJ	350
91b99041 DJ	351	/* pointer to edac polling checking routine:
079708b9 DT	352	* If NOT NULL: points to polling check routine
	353	* If NULL: Then assumes INTERRUPT operation, where
	354	* MC driver will receive events
91b99041 DJ	355	*/
	356	void (edac_check) (struct edac_pci_ctl_info edac_dev);
	357
	358	struct device dev; / pointer to device structure */
	359
	360	const char mod_name; / module name */
	361	const char ctl_name; / edac controller name */
	362	const char dev_name; / pci/platform/etc... name */
	363
	364	void pvt_info; / pointer to 'private driver' info */
	365
079708b9	366	unsigned long start_time; /* edac_pci load start time (jiffies) */
91b99041	367
91b99041 DJ	368	struct completion complete;
	369
	370	/* sysfs top name under 'edac' directory
	371	* and instance name:
079708b9 DT	372	* cpu/cpu0/...
	373	* cpu/cpu1/...
	374	* cpu/cpu2/...
	375	* ...
91b99041 DJ	376	*/
	377	char name[EDAC_DEVICE_NAME_LEN + 1];
	378
	379	/* Event counters for the this whole EDAC Device */
	380	struct edac_pci_counter counters;
	381
	382	/* edac sysfs device control for the 'name'
	383	* device this structure controls
	384	*/
	385	struct kobject kobj;
	386	struct completion kobj_complete;
	387	};
	388
	389	#define to_edac_pci_ctl_work(w) \
	390	container_of(w, struct edac_pci_ctl_info,work)
	391
7c9281d7 DT	392	/* write all or some bits in a byte-register*/
7c9281d7 DT	393	static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
079708b9	394	u8 mask)
7c9281d7 DT	395	{
	396	if (mask != 0xff) {
	397	u8 buf;
	398
	399	pci_read_config_byte(pdev, offset, &buf);
	400	value &= mask;
	401	buf &= ~mask;
	402	value \|= buf;
	403	}
	404
	405	pci_write_config_byte(pdev, offset, value);
	406	}
	407
	408	/* write all or some bits in a word-register*/
	409	static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
079708b9	410	u16 value, u16 mask)
7c9281d7 DT	411	{
	412	if (mask != 0xffff) {
	413	u16 buf;
	414
	415	pci_read_config_word(pdev, offset, &buf);
	416	value &= mask;
	417	buf &= ~mask;
	418	value \|= buf;
	419	}
	420
	421	pci_write_config_word(pdev, offset, value);
	422	}
	423
e6da46b2 JH	424	/*
	425	* pci_write_bits32
	426	*
	427	* edac local routine to do pci_write_config_dword, but adds
	428	* a mask parameter. If mask is all ones, ignore the mask.
	429	* Otherwise utilize the mask to isolate specified bits
	430	*
	431	* write all or some bits in a dword-register
	432	*/
7c9281d7	433	static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
079708b9	434	u32 value, u32 mask)
7c9281d7	435	{
e6da46b2	436	if (mask != 0xffffffff) {
7c9281d7 DT	437	u32 buf;
	438
	439	pci_read_config_dword(pdev, offset, &buf);
	440	value &= mask;
	441	buf &= ~mask;
	442	value \|= buf;
	443	}
	444
	445	pci_write_config_dword(pdev, offset, value);
	446	}
	447
079708b9	448	#endif /* CONFIG_PCI */
7c9281d7	449
b8f6f975 DT	450	extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
	451	unsigned nr_chans, int edac_index);
	452	extern int edac_mc_add_mc(struct mem_ctl_info *mci);
	453	extern void edac_mc_free(struct mem_ctl_info *mci);
079708b9	454	extern struct mem_ctl_info *edac_mc_find(int idx);
939747bd	455	extern struct mem_ctl_info find_mci_by_dev(struct device dev);
079708b9	456	extern struct mem_ctl_info edac_mc_del_mc(struct device dev);
7c9281d7	457	extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
079708b9	458	unsigned long page);
7c9281d7 DT	459
	460	/*
	461	* The no info errors are used when error overflows are reported.
	462	* There are a limited number of error logging registers that can
	463	* be exausted. When all registers are exhausted and an additional
	464	* error occurs then an error overflow register records that an
25985edc	465	* error occurred and the type of error, but doesn't have any
7c9281d7 DT	466	* further information. The ce/ue versions make for cleaner
	467	* reporting logic and function interface - reduces conditional
	468	* statement clutter and extra function arguments.
	469	*/
	470	extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
079708b9 DT	471	unsigned long page_frame_number,
	472	unsigned long offset_in_page,
	473	unsigned long syndrome, int row, int channel,
	474	const char *msg);
7c9281d7	475	extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
079708b9	476	const char *msg);
7c9281d7	477	extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
079708b9 DT	478	unsigned long page_frame_number,
	479	unsigned long offset_in_page, int row,
	480	const char *msg);
7c9281d7	481	extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
079708b9 DT	482	const char *msg);
	483	extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
	484	unsigned int channel0, unsigned int channel1,
	485	char *msg);
	486	extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
	487	unsigned int channel, char *msg);
7c9281d7 DT	488
7c9281d7 DT	489	/*
e27e3dac	490	* edac_device APIs
7c9281d7	491	*/
d45e7823	492	extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
079708b9	493	extern struct edac_device_ctl_info edac_device_del_device(struct device dev);
e27e3dac	494	extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
b8f6f975	495	int inst_nr, int block_nr, const char *msg);
e27e3dac	496	extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
b8f6f975	497	int inst_nr, int block_nr, const char *msg);
1dc9b70d	498	extern int edac_device_alloc_index(void);
e27e3dac	499
91b99041 DJ	500	/*
	501	* edac_pci APIs
	502	*/
b8f6f975 DT	503	extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
b8f6f975 DT	504	const char *edac_pci_name);
91b99041 DJ	505
	506	extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
	507
b8f6f975 DT	508	extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
b8f6f975 DT	509	unsigned long value);
91b99041	510
8641a384	511	extern int edac_pci_alloc_index(void);
91b99041	512	extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
079708b9	513	extern struct edac_pci_ctl_info edac_pci_del_device(struct device dev);
91b99041	514
b8f6f975 DT	515	extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
	516	struct device *dev,
	517	const char *mod_name);
91b99041 DJ	518
	519	extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
	520	extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
	521	extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
	522
	523	/*
	524	* edac misc APIs
	525	*/
494d0d55	526	extern char *edac_op_state_to_string(int op_state);
7c9281d7 DT	527
7c9281d7 DT	528	#endif /* _EDAC_CORE_H_ */