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806c35f5 AC |
1 | /* |
2 | * Intel e752x Memory Controller kernel module | |
3 | * (C) 2004 Linux Networx (http://lnxi.com) | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * See "enum e752x_chips" below for supported chipsets | |
8 | * | |
9 | * Written by Tom Zimmerman | |
10 | * | |
11 | * Contributors: | |
12 | * Thayne Harbaugh at realmsys.com (?) | |
13 | * Wang Zhenyu at intel.com | |
14 | * Dave Jiang at mvista.com | |
15 | * | |
da9bb1d2 | 16 | * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $ |
806c35f5 AC |
17 | * |
18 | */ | |
19 | ||
20 | ||
21 | #include <linux/config.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/init.h> | |
24 | ||
25 | #include <linux/pci.h> | |
26 | #include <linux/pci_ids.h> | |
27 | ||
28 | #include <linux/slab.h> | |
29 | ||
30 | #include "edac_mc.h" | |
31 | ||
32 | ||
33 | #ifndef PCI_DEVICE_ID_INTEL_7520_0 | |
34 | #define PCI_DEVICE_ID_INTEL_7520_0 0x3590 | |
35 | #endif /* PCI_DEVICE_ID_INTEL_7520_0 */ | |
36 | ||
37 | #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR | |
38 | #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591 | |
39 | #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */ | |
40 | ||
41 | #ifndef PCI_DEVICE_ID_INTEL_7525_0 | |
42 | #define PCI_DEVICE_ID_INTEL_7525_0 0x359E | |
43 | #endif /* PCI_DEVICE_ID_INTEL_7525_0 */ | |
44 | ||
45 | #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR | |
46 | #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593 | |
47 | #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */ | |
48 | ||
49 | #ifndef PCI_DEVICE_ID_INTEL_7320_0 | |
50 | #define PCI_DEVICE_ID_INTEL_7320_0 0x3592 | |
51 | #endif /* PCI_DEVICE_ID_INTEL_7320_0 */ | |
52 | ||
53 | #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR | |
54 | #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593 | |
55 | #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */ | |
56 | ||
57 | #define E752X_NR_CSROWS 8 /* number of csrows */ | |
58 | ||
59 | ||
60 | /* E752X register addresses - device 0 function 0 */ | |
61 | #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */ | |
62 | #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */ | |
63 | /* | |
64 | * 31:30 Device width row 7 | |
65 | * 01=x8 10=x4 11=x8 DDR2 | |
66 | * 27:26 Device width row 6 | |
67 | * 23:22 Device width row 5 | |
68 | * 19:20 Device width row 4 | |
69 | * 15:14 Device width row 3 | |
70 | * 11:10 Device width row 2 | |
71 | * 7:6 Device width row 1 | |
72 | * 3:2 Device width row 0 | |
73 | */ | |
74 | #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */ | |
75 | /* FIXME:IS THIS RIGHT? */ | |
76 | /* | |
77 | * 22 Number channels 0=1,1=2 | |
78 | * 19:18 DRB Granularity 32/64MB | |
79 | */ | |
80 | #define E752X_DRM 0x80 /* Dimm mapping register */ | |
81 | #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */ | |
82 | /* | |
83 | * 14:12 1 single A, 2 single B, 3 dual | |
84 | */ | |
85 | #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ | |
86 | #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ | |
87 | #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ | |
88 | #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */ | |
89 | ||
90 | /* E752X register addresses - device 0 function 1 */ | |
91 | #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */ | |
92 | #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */ | |
93 | #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */ | |
94 | #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */ | |
95 | #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */ | |
96 | #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */ | |
97 | #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */ | |
98 | #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */ | |
99 | #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */ | |
100 | #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */ | |
101 | #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */ | |
102 | #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */ | |
103 | #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */ | |
104 | #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */ | |
105 | #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */ | |
106 | #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */ | |
107 | #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */ | |
108 | #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */ | |
109 | #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */ | |
110 | #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */ | |
111 | /* error address register (32b) */ | |
112 | /* | |
113 | * 31 Reserved | |
114 | * 30:2 CE address (64 byte block 34:6) | |
115 | * 1 Reserved | |
116 | * 0 HiLoCS | |
117 | */ | |
118 | #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */ | |
119 | /* error address register (32b) */ | |
120 | /* | |
121 | * 31 Reserved | |
122 | * 30:2 CE address (64 byte block 34:6) | |
123 | * 1 Reserved | |
124 | * 0 HiLoCS | |
125 | */ | |
126 | #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */ | |
127 | /* error address register (32b) */ | |
128 | /* | |
129 | * 31 Reserved | |
130 | * 30:2 CE address (64 byte block 34:6) | |
131 | * 1 Reserved | |
132 | * 0 HiLoCS | |
133 | */ | |
134 | #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */ | |
135 | /* error address register (32b) */ | |
136 | /* | |
137 | * 31 Reserved | |
138 | * 30:2 CE address (64 byte block 34:6) | |
139 | * 1 Reserved | |
140 | * 0 HiLoCS | |
141 | */ | |
142 | #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */ | |
143 | /* error syndrome register (16b) */ | |
144 | #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */ | |
145 | /* error syndrome register (16b) */ | |
146 | #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */ | |
147 | ||
148 | /* ICH5R register addresses - device 30 function 0 */ | |
149 | #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */ | |
150 | #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */ | |
151 | #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */ | |
152 | ||
153 | enum e752x_chips { | |
154 | E7520 = 0, | |
155 | E7525 = 1, | |
156 | E7320 = 2 | |
157 | }; | |
158 | ||
159 | ||
160 | struct e752x_pvt { | |
161 | struct pci_dev *bridge_ck; | |
162 | struct pci_dev *dev_d0f0; | |
163 | struct pci_dev *dev_d0f1; | |
164 | u32 tolm; | |
165 | u32 remapbase; | |
166 | u32 remaplimit; | |
167 | int mc_symmetric; | |
168 | u8 map[8]; | |
169 | int map_type; | |
170 | const struct e752x_dev_info *dev_info; | |
171 | }; | |
172 | ||
173 | ||
174 | struct e752x_dev_info { | |
175 | u16 err_dev; | |
176 | const char *ctl_name; | |
177 | }; | |
178 | ||
179 | struct e752x_error_info { | |
180 | u32 ferr_global; | |
181 | u32 nerr_global; | |
182 | u8 hi_ferr; | |
183 | u8 hi_nerr; | |
184 | u16 sysbus_ferr; | |
185 | u16 sysbus_nerr; | |
186 | u8 buf_ferr; | |
187 | u8 buf_nerr; | |
188 | u16 dram_ferr; | |
189 | u16 dram_nerr; | |
190 | u32 dram_sec1_add; | |
191 | u32 dram_sec2_add; | |
192 | u16 dram_sec1_syndrome; | |
193 | u16 dram_sec2_syndrome; | |
194 | u32 dram_ded_add; | |
195 | u32 dram_scrb_add; | |
196 | u32 dram_retr_add; | |
197 | }; | |
198 | ||
199 | static const struct e752x_dev_info e752x_devs[] = { | |
200 | [E7520] = { | |
201 | .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR, | |
202 | .ctl_name = "E7520"}, | |
203 | [E7525] = { | |
204 | .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR, | |
205 | .ctl_name = "E7525"}, | |
206 | [E7320] = { | |
207 | .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR, | |
208 | .ctl_name = "E7320"}, | |
209 | }; | |
210 | ||
211 | ||
212 | static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, | |
213 | unsigned long page) | |
214 | { | |
215 | u32 remap; | |
216 | struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; | |
217 | ||
218 | debugf3("MC: " __FILE__ ": %s()\n", __func__); | |
219 | ||
220 | if (page < pvt->tolm) | |
221 | return page; | |
222 | if ((page >= 0x100000) && (page < pvt->remapbase)) | |
223 | return page; | |
224 | remap = (page - pvt->tolm) + pvt->remapbase; | |
225 | if (remap < pvt->remaplimit) | |
226 | return remap; | |
227 | printk(KERN_ERR "Invalid page %lx - out of range\n", page); | |
228 | return pvt->tolm - 1; | |
229 | } | |
230 | ||
231 | static void do_process_ce(struct mem_ctl_info *mci, u16 error_one, | |
232 | u32 sec1_add, u16 sec1_syndrome) | |
233 | { | |
234 | u32 page; | |
235 | int row; | |
236 | int channel; | |
237 | int i; | |
238 | struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; | |
239 | ||
240 | debugf3("MC: " __FILE__ ": %s()\n", __func__); | |
241 | ||
242 | /* convert the addr to 4k page */ | |
243 | page = sec1_add >> (PAGE_SHIFT - 4); | |
244 | ||
245 | /* FIXME - check for -1 */ | |
246 | if (pvt->mc_symmetric) { | |
247 | /* chip select are bits 14 & 13 */ | |
248 | row = ((page >> 1) & 3); | |
249 | printk(KERN_WARNING | |
250 | "Test row %d Table %d %d %d %d %d %d %d %d\n", | |
251 | row, pvt->map[0], pvt->map[1], pvt->map[2], | |
252 | pvt->map[3], pvt->map[4], pvt->map[5], | |
253 | pvt->map[6], pvt->map[7]); | |
254 | ||
255 | /* test for channel remapping */ | |
256 | for (i = 0; i < 8; i++) { | |
257 | if (pvt->map[i] == row) | |
258 | break; | |
259 | } | |
260 | printk(KERN_WARNING "Test computed row %d\n", i); | |
261 | if (i < 8) | |
262 | row = i; | |
263 | else | |
264 | printk(KERN_WARNING | |
265 | "MC%d: row %d not found in remap table\n", | |
266 | mci->mc_idx, row); | |
267 | } else | |
268 | row = edac_mc_find_csrow_by_page(mci, page); | |
269 | /* 0 = channel A, 1 = channel B */ | |
270 | channel = !(error_one & 1); | |
271 | ||
272 | if (!pvt->map_type) | |
273 | row = 7 - row; | |
274 | edac_mc_handle_ce(mci, page, 0, sec1_syndrome, row, channel, | |
275 | "e752x CE"); | |
276 | } | |
277 | ||
278 | ||
279 | static inline void process_ce(struct mem_ctl_info *mci, u16 error_one, | |
280 | u32 sec1_add, u16 sec1_syndrome, int *error_found, | |
281 | int handle_error) | |
282 | { | |
283 | *error_found = 1; | |
284 | ||
285 | if (handle_error) | |
286 | do_process_ce(mci, error_one, sec1_add, sec1_syndrome); | |
287 | } | |
288 | ||
289 | static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, u32 ded_add, | |
290 | u32 scrb_add) | |
291 | { | |
292 | u32 error_2b, block_page; | |
293 | int row; | |
294 | struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; | |
295 | ||
296 | debugf3("MC: " __FILE__ ": %s()\n", __func__); | |
297 | ||
298 | if (error_one & 0x0202) { | |
299 | error_2b = ded_add; | |
300 | /* convert to 4k address */ | |
301 | block_page = error_2b >> (PAGE_SHIFT - 4); | |
302 | row = pvt->mc_symmetric ? | |
303 | /* chip select are bits 14 & 13 */ | |
304 | ((block_page >> 1) & 3) : | |
305 | edac_mc_find_csrow_by_page(mci, block_page); | |
306 | edac_mc_handle_ue(mci, block_page, 0, row, | |
307 | "e752x UE from Read"); | |
308 | } | |
309 | if (error_one & 0x0404) { | |
310 | error_2b = scrb_add; | |
311 | /* convert to 4k address */ | |
312 | block_page = error_2b >> (PAGE_SHIFT - 4); | |
313 | row = pvt->mc_symmetric ? | |
314 | /* chip select are bits 14 & 13 */ | |
315 | ((block_page >> 1) & 3) : | |
316 | edac_mc_find_csrow_by_page(mci, block_page); | |
317 | edac_mc_handle_ue(mci, block_page, 0, row, | |
318 | "e752x UE from Scruber"); | |
319 | } | |
320 | } | |
321 | ||
322 | static inline void process_ue(struct mem_ctl_info *mci, u16 error_one, | |
323 | u32 ded_add, u32 scrb_add, int *error_found, int handle_error) | |
324 | { | |
325 | *error_found = 1; | |
326 | ||
327 | if (handle_error) | |
328 | do_process_ue(mci, error_one, ded_add, scrb_add); | |
329 | } | |
330 | ||
331 | static inline void process_ue_no_info_wr(struct mem_ctl_info *mci, | |
332 | int *error_found, int handle_error) | |
333 | { | |
334 | *error_found = 1; | |
335 | ||
336 | if (!handle_error) | |
337 | return; | |
338 | ||
339 | debugf3("MC: " __FILE__ ": %s()\n", __func__); | |
340 | edac_mc_handle_ue_no_info(mci, "e752x UE log memory write"); | |
341 | } | |
342 | ||
343 | static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error, | |
344 | u32 retry_add) | |
345 | { | |
346 | u32 error_1b, page; | |
347 | int row; | |
348 | struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; | |
349 | ||
350 | error_1b = retry_add; | |
351 | page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */ | |
352 | row = pvt->mc_symmetric ? | |
353 | ((page >> 1) & 3) : /* chip select are bits 14 & 13 */ | |
354 | edac_mc_find_csrow_by_page(mci, page); | |
355 | printk(KERN_WARNING | |
356 | "MC%d: CE page 0x%lx, row %d : Memory read retry\n", | |
357 | mci->mc_idx, (long unsigned int) page, row); | |
358 | } | |
359 | ||
360 | static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error, | |
361 | u32 retry_add, int *error_found, int handle_error) | |
362 | { | |
363 | *error_found = 1; | |
364 | ||
365 | if (handle_error) | |
366 | do_process_ded_retry(mci, error, retry_add); | |
367 | } | |
368 | ||
369 | static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error, | |
370 | int *error_found, int handle_error) | |
371 | { | |
372 | *error_found = 1; | |
373 | ||
374 | if (handle_error) | |
375 | printk(KERN_WARNING "MC%d: Memory threshold CE\n", | |
376 | mci->mc_idx); | |
377 | } | |
378 | ||
da9bb1d2 | 379 | static char *global_message[11] = { |
806c35f5 AC |
380 | "PCI Express C1", "PCI Express C", "PCI Express B1", |
381 | "PCI Express B", "PCI Express A1", "PCI Express A", | |
382 | "DMA Controler", "HUB Interface", "System Bus", | |
383 | "DRAM Controler", "Internal Buffer" | |
384 | }; | |
385 | ||
da9bb1d2 | 386 | static char *fatal_message[2] = { "Non-Fatal ", "Fatal " }; |
806c35f5 AC |
387 | |
388 | static void do_global_error(int fatal, u32 errors) | |
389 | { | |
390 | int i; | |
391 | ||
392 | for (i = 0; i < 11; i++) { | |
393 | if (errors & (1 << i)) | |
394 | printk(KERN_WARNING "%sError %s\n", | |
395 | fatal_message[fatal], global_message[i]); | |
396 | } | |
397 | } | |
398 | ||
399 | static inline void global_error(int fatal, u32 errors, int *error_found, | |
400 | int handle_error) | |
401 | { | |
402 | *error_found = 1; | |
403 | ||
404 | if (handle_error) | |
405 | do_global_error(fatal, errors); | |
406 | } | |
407 | ||
da9bb1d2 | 408 | static char *hub_message[7] = { |
806c35f5 AC |
409 | "HI Address or Command Parity", "HI Illegal Access", |
410 | "HI Internal Parity", "Out of Range Access", | |
411 | "HI Data Parity", "Enhanced Config Access", | |
412 | "Hub Interface Target Abort" | |
413 | }; | |
414 | ||
415 | static void do_hub_error(int fatal, u8 errors) | |
416 | { | |
417 | int i; | |
418 | ||
419 | for (i = 0; i < 7; i++) { | |
420 | if (errors & (1 << i)) | |
421 | printk(KERN_WARNING "%sError %s\n", | |
422 | fatal_message[fatal], hub_message[i]); | |
423 | } | |
424 | } | |
425 | ||
426 | static inline void hub_error(int fatal, u8 errors, int *error_found, | |
427 | int handle_error) | |
428 | { | |
429 | *error_found = 1; | |
430 | ||
431 | if (handle_error) | |
432 | do_hub_error(fatal, errors); | |
433 | } | |
434 | ||
da9bb1d2 | 435 | static char *membuf_message[4] = { |
806c35f5 AC |
436 | "Internal PMWB to DRAM parity", |
437 | "Internal PMWB to System Bus Parity", | |
438 | "Internal System Bus or IO to PMWB Parity", | |
439 | "Internal DRAM to PMWB Parity" | |
440 | }; | |
441 | ||
442 | static void do_membuf_error(u8 errors) | |
443 | { | |
444 | int i; | |
445 | ||
446 | for (i = 0; i < 4; i++) { | |
447 | if (errors & (1 << i)) | |
448 | printk(KERN_WARNING "Non-Fatal Error %s\n", | |
449 | membuf_message[i]); | |
450 | } | |
451 | } | |
452 | ||
453 | static inline void membuf_error(u8 errors, int *error_found, int handle_error) | |
454 | { | |
455 | *error_found = 1; | |
456 | ||
457 | if (handle_error) | |
458 | do_membuf_error(errors); | |
459 | } | |
460 | ||
da9bb1d2 | 461 | #if 0 |
806c35f5 AC |
462 | char *sysbus_message[10] = { |
463 | "Addr or Request Parity", | |
464 | "Data Strobe Glitch", | |
465 | "Addr Strobe Glitch", | |
466 | "Data Parity", | |
467 | "Addr Above TOM", | |
468 | "Non DRAM Lock Error", | |
469 | "MCERR", "BINIT", | |
470 | "Memory Parity", | |
471 | "IO Subsystem Parity" | |
472 | }; | |
da9bb1d2 | 473 | #endif /* 0 */ |
806c35f5 AC |
474 | |
475 | static void do_sysbus_error(int fatal, u32 errors) | |
476 | { | |
477 | int i; | |
478 | ||
479 | for (i = 0; i < 10; i++) { | |
480 | if (errors & (1 << i)) | |
481 | printk(KERN_WARNING "%sError System Bus %s\n", | |
482 | fatal_message[fatal], global_message[i]); | |
483 | } | |
484 | } | |
485 | ||
486 | static inline void sysbus_error(int fatal, u32 errors, int *error_found, | |
487 | int handle_error) | |
488 | { | |
489 | *error_found = 1; | |
490 | ||
491 | if (handle_error) | |
492 | do_sysbus_error(fatal, errors); | |
493 | } | |
494 | ||
495 | static void e752x_check_hub_interface (struct e752x_error_info *info, | |
496 | int *error_found, int handle_error) | |
497 | { | |
498 | u8 stat8; | |
499 | ||
500 | //pci_read_config_byte(dev,E752X_HI_FERR,&stat8); | |
501 | stat8 = info->hi_ferr; | |
502 | if(stat8 & 0x7f) { /* Error, so process */ | |
503 | stat8 &= 0x7f; | |
504 | if(stat8 & 0x2b) | |
505 | hub_error(1, stat8 & 0x2b, error_found, handle_error); | |
506 | if(stat8 & 0x54) | |
507 | hub_error(0, stat8 & 0x54, error_found, handle_error); | |
508 | } | |
509 | //pci_read_config_byte(dev,E752X_HI_NERR,&stat8); | |
510 | stat8 = info->hi_nerr; | |
511 | if(stat8 & 0x7f) { /* Error, so process */ | |
512 | stat8 &= 0x7f; | |
513 | if (stat8 & 0x2b) | |
514 | hub_error(1, stat8 & 0x2b, error_found, handle_error); | |
515 | if(stat8 & 0x54) | |
516 | hub_error(0, stat8 & 0x54, error_found, handle_error); | |
517 | } | |
518 | } | |
519 | ||
520 | static void e752x_check_sysbus (struct e752x_error_info *info, int *error_found, | |
521 | int handle_error) | |
522 | { | |
523 | u32 stat32, error32; | |
524 | ||
525 | //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32); | |
526 | stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16); | |
527 | ||
528 | if (stat32 == 0) | |
529 | return; /* no errors */ | |
530 | ||
531 | error32 = (stat32 >> 16) & 0x3ff; | |
532 | stat32 = stat32 & 0x3ff; | |
533 | if(stat32 & 0x083) | |
534 | sysbus_error(1, stat32 & 0x083, error_found, handle_error); | |
535 | if(stat32 & 0x37c) | |
536 | sysbus_error(0, stat32 & 0x37c, error_found, handle_error); | |
537 | if(error32 & 0x083) | |
538 | sysbus_error(1, error32 & 0x083, error_found, handle_error); | |
539 | if(error32 & 0x37c) | |
540 | sysbus_error(0, error32 & 0x37c, error_found, handle_error); | |
541 | } | |
542 | ||
543 | static void e752x_check_membuf (struct e752x_error_info *info, int *error_found, | |
544 | int handle_error) | |
545 | { | |
546 | u8 stat8; | |
547 | ||
548 | stat8 = info->buf_ferr; | |
549 | if (stat8 & 0x0f) { /* Error, so process */ | |
550 | stat8 &= 0x0f; | |
551 | membuf_error(stat8, error_found, handle_error); | |
552 | } | |
553 | stat8 = info->buf_nerr; | |
554 | if (stat8 & 0x0f) { /* Error, so process */ | |
555 | stat8 &= 0x0f; | |
556 | membuf_error(stat8, error_found, handle_error); | |
557 | } | |
558 | } | |
559 | ||
560 | static void e752x_check_dram (struct mem_ctl_info *mci, | |
561 | struct e752x_error_info *info, int *error_found, int handle_error) | |
562 | { | |
563 | u16 error_one, error_next; | |
564 | ||
565 | error_one = info->dram_ferr; | |
566 | error_next = info->dram_nerr; | |
567 | ||
568 | /* decode and report errors */ | |
569 | if(error_one & 0x0101) /* check first error correctable */ | |
570 | process_ce(mci, error_one, info->dram_sec1_add, | |
571 | info->dram_sec1_syndrome, error_found, | |
572 | handle_error); | |
573 | ||
574 | if(error_next & 0x0101) /* check next error correctable */ | |
575 | process_ce(mci, error_next, info->dram_sec2_add, | |
576 | info->dram_sec2_syndrome, error_found, | |
577 | handle_error); | |
578 | ||
579 | if(error_one & 0x4040) | |
580 | process_ue_no_info_wr(mci, error_found, handle_error); | |
581 | ||
582 | if(error_next & 0x4040) | |
583 | process_ue_no_info_wr(mci, error_found, handle_error); | |
584 | ||
585 | if(error_one & 0x2020) | |
586 | process_ded_retry(mci, error_one, info->dram_retr_add, | |
587 | error_found, handle_error); | |
588 | ||
589 | if(error_next & 0x2020) | |
590 | process_ded_retry(mci, error_next, info->dram_retr_add, | |
591 | error_found, handle_error); | |
592 | ||
593 | if(error_one & 0x0808) | |
594 | process_threshold_ce(mci, error_one, error_found, | |
595 | handle_error); | |
596 | ||
597 | if(error_next & 0x0808) | |
598 | process_threshold_ce(mci, error_next, error_found, | |
599 | handle_error); | |
600 | ||
601 | if(error_one & 0x0606) | |
602 | process_ue(mci, error_one, info->dram_ded_add, | |
603 | info->dram_scrb_add, error_found, handle_error); | |
604 | ||
605 | if(error_next & 0x0606) | |
606 | process_ue(mci, error_next, info->dram_ded_add, | |
607 | info->dram_scrb_add, error_found, handle_error); | |
608 | } | |
609 | ||
610 | static void e752x_get_error_info (struct mem_ctl_info *mci, | |
611 | struct e752x_error_info *info) | |
612 | { | |
613 | struct pci_dev *dev; | |
614 | struct e752x_pvt *pvt; | |
615 | ||
616 | memset(info, 0, sizeof(*info)); | |
617 | pvt = (struct e752x_pvt *) mci->pvt_info; | |
618 | dev = pvt->dev_d0f1; | |
619 | ||
620 | pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global); | |
621 | ||
622 | if (info->ferr_global) { | |
623 | pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr); | |
624 | pci_read_config_word(dev, E752X_SYSBUS_FERR, | |
625 | &info->sysbus_ferr); | |
626 | pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr); | |
627 | pci_read_config_word(dev, E752X_DRAM_FERR, | |
628 | &info->dram_ferr); | |
629 | pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD, | |
630 | &info->dram_sec1_add); | |
631 | pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME, | |
632 | &info->dram_sec1_syndrome); | |
633 | pci_read_config_dword(dev, E752X_DRAM_DED_ADD, | |
634 | &info->dram_ded_add); | |
635 | pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD, | |
636 | &info->dram_scrb_add); | |
637 | pci_read_config_dword(dev, E752X_DRAM_RETR_ADD, | |
638 | &info->dram_retr_add); | |
639 | ||
640 | if (info->hi_ferr & 0x7f) | |
641 | pci_write_config_byte(dev, E752X_HI_FERR, | |
642 | info->hi_ferr); | |
643 | ||
644 | if (info->sysbus_ferr) | |
645 | pci_write_config_word(dev, E752X_SYSBUS_FERR, | |
646 | info->sysbus_ferr); | |
647 | ||
648 | if (info->buf_ferr & 0x0f) | |
649 | pci_write_config_byte(dev, E752X_BUF_FERR, | |
650 | info->buf_ferr); | |
651 | ||
652 | if (info->dram_ferr) | |
653 | pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR, | |
654 | info->dram_ferr, info->dram_ferr); | |
655 | ||
656 | pci_write_config_dword(dev, E752X_FERR_GLOBAL, | |
657 | info->ferr_global); | |
658 | } | |
659 | ||
660 | pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global); | |
661 | ||
662 | if (info->nerr_global) { | |
663 | pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr); | |
664 | pci_read_config_word(dev, E752X_SYSBUS_NERR, | |
665 | &info->sysbus_nerr); | |
666 | pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr); | |
667 | pci_read_config_word(dev, E752X_DRAM_NERR, | |
668 | &info->dram_nerr); | |
669 | pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD, | |
670 | &info->dram_sec2_add); | |
671 | pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME, | |
672 | &info->dram_sec2_syndrome); | |
673 | ||
674 | if (info->hi_nerr & 0x7f) | |
675 | pci_write_config_byte(dev, E752X_HI_NERR, | |
676 | info->hi_nerr); | |
677 | ||
678 | if (info->sysbus_nerr) | |
679 | pci_write_config_word(dev, E752X_SYSBUS_NERR, | |
680 | info->sysbus_nerr); | |
681 | ||
682 | if (info->buf_nerr & 0x0f) | |
683 | pci_write_config_byte(dev, E752X_BUF_NERR, | |
684 | info->buf_nerr); | |
685 | ||
686 | if (info->dram_nerr) | |
687 | pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR, | |
688 | info->dram_nerr, info->dram_nerr); | |
689 | ||
690 | pci_write_config_dword(dev, E752X_NERR_GLOBAL, | |
691 | info->nerr_global); | |
692 | } | |
693 | } | |
694 | ||
695 | static int e752x_process_error_info (struct mem_ctl_info *mci, | |
696 | struct e752x_error_info *info, int handle_errors) | |
697 | { | |
698 | u32 error32, stat32; | |
699 | int error_found; | |
700 | ||
701 | error_found = 0; | |
702 | error32 = (info->ferr_global >> 18) & 0x3ff; | |
703 | stat32 = (info->ferr_global >> 4) & 0x7ff; | |
704 | ||
705 | if (error32) | |
706 | global_error(1, error32, &error_found, handle_errors); | |
707 | ||
708 | if (stat32) | |
709 | global_error(0, stat32, &error_found, handle_errors); | |
710 | ||
711 | error32 = (info->nerr_global >> 18) & 0x3ff; | |
712 | stat32 = (info->nerr_global >> 4) & 0x7ff; | |
713 | ||
714 | if (error32) | |
715 | global_error(1, error32, &error_found, handle_errors); | |
716 | ||
717 | if (stat32) | |
718 | global_error(0, stat32, &error_found, handle_errors); | |
719 | ||
720 | e752x_check_hub_interface(info, &error_found, handle_errors); | |
721 | e752x_check_sysbus(info, &error_found, handle_errors); | |
722 | e752x_check_membuf(info, &error_found, handle_errors); | |
723 | e752x_check_dram(mci, info, &error_found, handle_errors); | |
724 | return error_found; | |
725 | } | |
726 | ||
727 | static void e752x_check(struct mem_ctl_info *mci) | |
728 | { | |
729 | struct e752x_error_info info; | |
730 | debugf3("MC: " __FILE__ ": %s()\n", __func__); | |
731 | e752x_get_error_info(mci, &info); | |
732 | e752x_process_error_info(mci, &info, 1); | |
733 | } | |
734 | ||
735 | static int e752x_probe1(struct pci_dev *pdev, int dev_idx) | |
736 | { | |
737 | int rc = -ENODEV; | |
738 | int index; | |
739 | u16 pci_data, stat; | |
740 | u32 stat32; | |
741 | u16 stat16; | |
742 | u8 stat8; | |
743 | struct mem_ctl_info *mci = NULL; | |
744 | struct e752x_pvt *pvt = NULL; | |
745 | u16 ddrcsr; | |
746 | u32 drc; | |
747 | int drc_chan; /* Number of channels 0=1chan,1=2chan */ | |
748 | int drc_drbg; /* DRB granularity 0=64mb,1=128mb */ | |
749 | int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */ | |
750 | u32 dra; | |
751 | unsigned long last_cumul_size; | |
752 | struct pci_dev *pres_dev; | |
753 | struct pci_dev *dev = NULL; | |
754 | ||
755 | debugf0("MC: " __FILE__ ": %s(): mci\n", __func__); | |
756 | debugf0("Starting Probe1\n"); | |
757 | ||
758 | /* enable device 0 function 1 */ | |
759 | pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8); | |
760 | stat8 |= (1 << 5); | |
761 | pci_write_config_byte(pdev, E752X_DEVPRES1, stat8); | |
762 | ||
763 | /* need to find out the number of channels */ | |
764 | pci_read_config_dword(pdev, E752X_DRC, &drc); | |
765 | pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr); | |
766 | /* FIXME: should check >>12 or 0xf, true for all? */ | |
767 | /* Dual channel = 1, Single channel = 0 */ | |
768 | drc_chan = (((ddrcsr >> 12) & 3) == 3); | |
769 | drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */ | |
770 | drc_ddim = (drc >> 20) & 0x3; | |
771 | ||
772 | mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1); | |
773 | ||
774 | if (mci == NULL) { | |
775 | rc = -ENOMEM; | |
776 | goto fail; | |
777 | } | |
778 | ||
779 | debugf3("MC: " __FILE__ ": %s(): init mci\n", __func__); | |
780 | ||
781 | mci->mtype_cap = MEM_FLAG_RDDR; | |
782 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | | |
783 | EDAC_FLAG_S4ECD4ED; | |
784 | /* FIXME - what if different memory types are in different csrows? */ | |
785 | mci->mod_name = BS_MOD_STR; | |
786 | mci->mod_ver = "$Revision: 1.5.2.11 $"; | |
787 | mci->pdev = pdev; | |
788 | ||
789 | debugf3("MC: " __FILE__ ": %s(): init pvt\n", __func__); | |
790 | pvt = (struct e752x_pvt *) mci->pvt_info; | |
791 | pvt->dev_info = &e752x_devs[dev_idx]; | |
792 | pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, | |
793 | pvt->dev_info->err_dev, | |
794 | pvt->bridge_ck); | |
795 | if (pvt->bridge_ck == NULL) | |
796 | pvt->bridge_ck = pci_scan_single_device(pdev->bus, | |
797 | PCI_DEVFN(0, 1)); | |
798 | if (pvt->bridge_ck == NULL) { | |
799 | printk(KERN_ERR "MC: error reporting device not found:" | |
800 | "vendor %x device 0x%x (broken BIOS?)\n", | |
801 | PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev); | |
802 | goto fail; | |
803 | } | |
804 | pvt->mc_symmetric = ((ddrcsr & 0x10) != 0); | |
805 | ||
806 | debugf3("MC: " __FILE__ ": %s(): more mci init\n", __func__); | |
807 | mci->ctl_name = pvt->dev_info->ctl_name; | |
808 | mci->edac_check = e752x_check; | |
809 | mci->ctl_page_to_phys = ctl_page_to_phys; | |
810 | ||
811 | /* find out the device types */ | |
812 | pci_read_config_dword(pdev, E752X_DRA, &dra); | |
813 | ||
814 | /* | |
815 | * The dram row boundary (DRB) reg values are boundary address for | |
816 | * each DRAM row with a granularity of 64 or 128MB (single/dual | |
817 | * channel operation). DRB regs are cumulative; therefore DRB7 will | |
818 | * contain the total memory contained in all eight rows. | |
819 | */ | |
820 | for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) { | |
821 | u8 value; | |
822 | u32 cumul_size; | |
823 | /* mem_dev 0=x8, 1=x4 */ | |
824 | int mem_dev = (dra >> (index * 4 + 2)) & 0x3; | |
825 | struct csrow_info *csrow = &mci->csrows[index]; | |
826 | ||
827 | mem_dev = (mem_dev == 2); | |
828 | pci_read_config_byte(mci->pdev, E752X_DRB + index, &value); | |
829 | /* convert a 128 or 64 MiB DRB to a page size. */ | |
830 | cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); | |
831 | debugf3("MC: " __FILE__ ": %s(): (%d) cumul_size 0x%x\n", | |
832 | __func__, index, cumul_size); | |
833 | if (cumul_size == last_cumul_size) | |
834 | continue; /* not populated */ | |
835 | ||
836 | csrow->first_page = last_cumul_size; | |
837 | csrow->last_page = cumul_size - 1; | |
838 | csrow->nr_pages = cumul_size - last_cumul_size; | |
839 | last_cumul_size = cumul_size; | |
840 | csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ | |
841 | csrow->mtype = MEM_RDDR; /* only one type supported */ | |
842 | csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; | |
843 | ||
844 | /* | |
845 | * if single channel or x8 devices then SECDED | |
846 | * if dual channel and x4 then S4ECD4ED | |
847 | */ | |
848 | if (drc_ddim) { | |
849 | if (drc_chan && mem_dev) { | |
850 | csrow->edac_mode = EDAC_S4ECD4ED; | |
851 | mci->edac_cap |= EDAC_FLAG_S4ECD4ED; | |
852 | } else { | |
853 | csrow->edac_mode = EDAC_SECDED; | |
854 | mci->edac_cap |= EDAC_FLAG_SECDED; | |
855 | } | |
856 | } else | |
857 | csrow->edac_mode = EDAC_NONE; | |
858 | } | |
859 | ||
860 | /* Fill in the memory map table */ | |
861 | { | |
862 | u8 value; | |
863 | u8 last = 0; | |
864 | u8 row = 0; | |
865 | for (index = 0; index < 8; index += 2) { | |
866 | ||
867 | pci_read_config_byte(mci->pdev, E752X_DRB + index, | |
868 | &value); | |
869 | /* test if there is a dimm in this slot */ | |
870 | if (value == last) { | |
871 | /* no dimm in the slot, so flag it as empty */ | |
872 | pvt->map[index] = 0xff; | |
873 | pvt->map[index + 1] = 0xff; | |
874 | } else { /* there is a dimm in the slot */ | |
875 | pvt->map[index] = row; | |
876 | row++; | |
877 | last = value; | |
878 | /* test the next value to see if the dimm is | |
879 | double sided */ | |
880 | pci_read_config_byte(mci->pdev, | |
881 | E752X_DRB + index + 1, | |
882 | &value); | |
883 | pvt->map[index + 1] = (value == last) ? | |
884 | 0xff : /* the dimm is single sided, | |
885 | so flag as empty */ | |
886 | row; /* this is a double sided dimm | |
887 | to save the next row # */ | |
888 | row++; | |
889 | last = value; | |
890 | } | |
891 | } | |
892 | } | |
893 | ||
894 | /* set the map type. 1 = normal, 0 = reversed */ | |
895 | pci_read_config_byte(mci->pdev, E752X_DRM, &stat8); | |
896 | pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f)); | |
897 | ||
898 | mci->edac_cap |= EDAC_FLAG_NONE; | |
899 | ||
900 | debugf3("MC: " __FILE__ ": %s(): tolm, remapbase, remaplimit\n", | |
901 | __func__); | |
902 | /* load the top of low memory, remap base, and remap limit vars */ | |
903 | pci_read_config_word(mci->pdev, E752X_TOLM, &pci_data); | |
904 | pvt->tolm = ((u32) pci_data) << 4; | |
905 | pci_read_config_word(mci->pdev, E752X_REMAPBASE, &pci_data); | |
906 | pvt->remapbase = ((u32) pci_data) << 14; | |
907 | pci_read_config_word(mci->pdev, E752X_REMAPLIMIT, &pci_data); | |
908 | pvt->remaplimit = ((u32) pci_data) << 14; | |
909 | printk("tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm, | |
910 | pvt->remapbase, pvt->remaplimit); | |
911 | ||
912 | if (edac_mc_add_mc(mci)) { | |
913 | debugf3("MC: " __FILE__ | |
914 | ": %s(): failed edac_mc_add_mc()\n", | |
915 | __func__); | |
916 | goto fail; | |
917 | } | |
918 | ||
919 | /* Walk through the PCI table and clear errors */ | |
920 | switch (dev_idx) { | |
921 | case E7520: | |
922 | dev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
923 | PCI_DEVICE_ID_INTEL_7520_0, NULL); | |
924 | break; | |
925 | case E7525: | |
926 | dev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
927 | PCI_DEVICE_ID_INTEL_7525_0, NULL); | |
928 | break; | |
929 | case E7320: | |
930 | dev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
931 | PCI_DEVICE_ID_INTEL_7320_0, NULL); | |
932 | break; | |
933 | } | |
934 | ||
935 | ||
936 | pvt->dev_d0f0 = dev; | |
937 | for (pres_dev = dev; | |
938 | ((struct pci_dev *) pres_dev->global_list.next != dev); | |
939 | pres_dev = (struct pci_dev *) pres_dev->global_list.next) { | |
940 | pci_read_config_dword(pres_dev, PCI_COMMAND, &stat32); | |
941 | stat = (u16) (stat32 >> 16); | |
942 | /* clear any error bits */ | |
943 | if (stat32 & ((1 << 6) + (1 << 8))) | |
944 | pci_write_config_word(pres_dev, PCI_STATUS, stat); | |
945 | } | |
946 | /* find the error reporting device and clear errors */ | |
947 | dev = pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck); | |
948 | /* Turn off error disable & SMI in case the BIOS turned it on */ | |
949 | pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00); | |
950 | pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00); | |
951 | pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00); | |
952 | pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00); | |
953 | pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00); | |
954 | pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00); | |
955 | pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00); | |
956 | pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00); | |
957 | /* clear other MCH errors */ | |
958 | pci_read_config_dword(dev, E752X_FERR_GLOBAL, &stat32); | |
959 | pci_write_config_dword(dev, E752X_FERR_GLOBAL, stat32); | |
960 | pci_read_config_dword(dev, E752X_NERR_GLOBAL, &stat32); | |
961 | pci_write_config_dword(dev, E752X_NERR_GLOBAL, stat32); | |
962 | pci_read_config_byte(dev, E752X_HI_FERR, &stat8); | |
963 | pci_write_config_byte(dev, E752X_HI_FERR, stat8); | |
964 | pci_read_config_byte(dev, E752X_HI_NERR, &stat8); | |
965 | pci_write_config_byte(dev, E752X_HI_NERR, stat8); | |
966 | pci_read_config_dword(dev, E752X_SYSBUS_FERR, &stat32); | |
967 | pci_write_config_dword(dev, E752X_SYSBUS_FERR, stat32); | |
968 | pci_read_config_byte(dev, E752X_BUF_FERR, &stat8); | |
969 | pci_write_config_byte(dev, E752X_BUF_FERR, stat8); | |
970 | pci_read_config_byte(dev, E752X_BUF_NERR, &stat8); | |
971 | pci_write_config_byte(dev, E752X_BUF_NERR, stat8); | |
972 | pci_read_config_word(dev, E752X_DRAM_FERR, &stat16); | |
973 | pci_write_config_word(dev, E752X_DRAM_FERR, stat16); | |
974 | pci_read_config_word(dev, E752X_DRAM_NERR, &stat16); | |
975 | pci_write_config_word(dev, E752X_DRAM_NERR, stat16); | |
976 | ||
977 | /* get this far and it's successful */ | |
978 | debugf3("MC: " __FILE__ ": %s(): success\n", __func__); | |
979 | return 0; | |
980 | ||
981 | fail: | |
982 | if (mci) { | |
983 | if (pvt->dev_d0f0) | |
984 | pci_dev_put(pvt->dev_d0f0); | |
985 | if (pvt->dev_d0f1) | |
986 | pci_dev_put(pvt->dev_d0f1); | |
987 | if (pvt->bridge_ck) | |
988 | pci_dev_put(pvt->bridge_ck); | |
989 | edac_mc_free(mci); | |
990 | } | |
991 | return rc; | |
992 | } | |
993 | ||
994 | /* returns count (>= 0), or negative on error */ | |
995 | static int __devinit e752x_init_one(struct pci_dev *pdev, | |
996 | const struct pci_device_id *ent) | |
997 | { | |
998 | debugf0("MC: " __FILE__ ": %s()\n", __func__); | |
999 | ||
1000 | /* wake up and enable device */ | |
1001 | if(pci_enable_device(pdev) < 0) | |
1002 | return -EIO; | |
1003 | return e752x_probe1(pdev, ent->driver_data); | |
1004 | } | |
1005 | ||
1006 | ||
1007 | static void __devexit e752x_remove_one(struct pci_dev *pdev) | |
1008 | { | |
1009 | struct mem_ctl_info *mci; | |
1010 | struct e752x_pvt *pvt; | |
1011 | ||
1012 | debugf0(__FILE__ ": %s()\n", __func__); | |
1013 | ||
1014 | if ((mci = edac_mc_find_mci_by_pdev(pdev)) == NULL) | |
1015 | return; | |
1016 | ||
1017 | if (edac_mc_del_mc(mci)) | |
1018 | return; | |
1019 | ||
1020 | pvt = (struct e752x_pvt *) mci->pvt_info; | |
1021 | pci_dev_put(pvt->dev_d0f0); | |
1022 | pci_dev_put(pvt->dev_d0f1); | |
1023 | pci_dev_put(pvt->bridge_ck); | |
1024 | edac_mc_free(mci); | |
1025 | } | |
1026 | ||
1027 | ||
1028 | static const struct pci_device_id e752x_pci_tbl[] __devinitdata = { | |
1029 | {PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1030 | E7520}, | |
1031 | {PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1032 | E7525}, | |
1033 | {PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1034 | E7320}, | |
1035 | {0,} /* 0 terminated list. */ | |
1036 | }; | |
1037 | ||
1038 | MODULE_DEVICE_TABLE(pci, e752x_pci_tbl); | |
1039 | ||
1040 | ||
1041 | static struct pci_driver e752x_driver = { | |
1042 | name: BS_MOD_STR, | |
1043 | probe: e752x_init_one, | |
1044 | remove: __devexit_p(e752x_remove_one), | |
1045 | id_table: e752x_pci_tbl, | |
1046 | }; | |
1047 | ||
1048 | ||
da9bb1d2 | 1049 | static int __init e752x_init(void) |
806c35f5 AC |
1050 | { |
1051 | int pci_rc; | |
1052 | ||
1053 | debugf3("MC: " __FILE__ ": %s()\n", __func__); | |
1054 | pci_rc = pci_register_driver(&e752x_driver); | |
1055 | return (pci_rc < 0) ? pci_rc : 0; | |
1056 | } | |
1057 | ||
1058 | ||
1059 | static void __exit e752x_exit(void) | |
1060 | { | |
1061 | debugf3("MC: " __FILE__ ": %s()\n", __func__); | |
1062 | pci_unregister_driver(&e752x_driver); | |
1063 | } | |
1064 | ||
1065 | ||
1066 | module_init(e752x_init); | |
1067 | module_exit(e752x_exit); | |
1068 | ||
1069 | MODULE_LICENSE("GPL"); | |
1070 | MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n"); | |
1071 | MODULE_DESCRIPTION("MC support for Intel e752x memory controllers"); |