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[PATCH] IRQ: warning message cleanup
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / e752x_edac.c
CommitLineData
806c35f5
AC		 1/*
2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e752x_chips" below for supported chipsets
8 *
9 * Written by Tom Zimmerman
10 *
11 * Contributors:
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
15 *
da9bb1d2 16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
806c35f5
AC		 17 *
18 */
19
806c35f5
AC		 20#include <linux/module.h>
21#include <linux/init.h>
806c35f5
AC		 22#include <linux/pci.h>
23#include <linux/pci_ids.h>
806c35f5 24#include <linux/slab.h>
806c35f5
AC		 25#include "edac_mc.h"
26
37f04581
DT		 27#define E752X_REVISION " Ver: 2.0.0 " __DATE__
28
96941026 29static int force_function_unhide;
30
537fba28 31#define e752x_printk(level, fmt, arg...) \
e7ecd891 32 edac_printk(level, "e752x", fmt, ##arg)
537fba28
DP		 33
34#define e752x_mc_printk(mci, level, fmt, arg...) \
e7ecd891 35 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
537fba28 36
806c35f5
AC		 37#ifndef PCI_DEVICE_ID_INTEL_7520_0
38#define PCI_DEVICE_ID_INTEL_7520_0 0x3590
39#endif /* PCI_DEVICE_ID_INTEL_7520_0 */
40
41#ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
42#define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
43#endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
44
45#ifndef PCI_DEVICE_ID_INTEL_7525_0
46#define PCI_DEVICE_ID_INTEL_7525_0 0x359E
47#endif /* PCI_DEVICE_ID_INTEL_7525_0 */
48
49#ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
50#define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
51#endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
52
53#ifndef PCI_DEVICE_ID_INTEL_7320_0
54#define PCI_DEVICE_ID_INTEL_7320_0 0x3592
55#endif /* PCI_DEVICE_ID_INTEL_7320_0 */
56
57#ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
58#define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
59#endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
60
61#define E752X_NR_CSROWS 8 /* number of csrows */
62
806c35f5
AC		 63/* E752X register addresses - device 0 function 0 */
64#define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
65#define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
66 /*
67 * 31:30 Device width row 7
68 * 01=x8 10=x4 11=x8 DDR2
69 * 27:26 Device width row 6
70 * 23:22 Device width row 5
71 * 19:20 Device width row 4
72 * 15:14 Device width row 3
73 * 11:10 Device width row 2
74 * 7:6 Device width row 1
75 * 3:2 Device width row 0
76 */
77#define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
78 /* FIXME:IS THIS RIGHT? */
79 /*
80 * 22 Number channels 0=1,1=2
81 * 19:18 DRB Granularity 32/64MB
82 */
83#define E752X_DRM 0x80 /* Dimm mapping register */
84#define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
85 /*
86 * 14:12 1 single A, 2 single B, 3 dual
87 */
88#define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
89#define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
90#define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
91#define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
92
93/* E752X register addresses - device 0 function 1 */
94#define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
95#define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
96#define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
97#define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
98#define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
99#define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
100#define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
101#define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
102#define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
103#define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
104#define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
105#define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
106#define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
107#define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
108#define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
109#define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
110#define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
111#define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
112#define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
113#define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
114 /* error address register (32b) */
115 /*
116 * 31 Reserved
117 * 30:2 CE address (64 byte block 34:6)
118 * 1 Reserved
119 * 0 HiLoCS
120 */
121#define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
122 /* error address register (32b) */
123 /*
124 * 31 Reserved
125 * 30:2 CE address (64 byte block 34:6)
126 * 1 Reserved
127 * 0 HiLoCS
128 */
129#define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
130 /* error address register (32b) */
131 /*
132 * 31 Reserved
133 * 30:2 CE address (64 byte block 34:6)
134 * 1 Reserved
135 * 0 HiLoCS
136 */
137#define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
138 /* error address register (32b) */
139 /*
140 * 31 Reserved
141 * 30:2 CE address (64 byte block 34:6)
142 * 1 Reserved
143 * 0 HiLoCS
144 */
145#define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
146 /* error syndrome register (16b) */
147#define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
148 /* error syndrome register (16b) */
149#define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
150
151/* ICH5R register addresses - device 30 function 0 */
152#define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
153#define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
154#define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
155
156enum e752x_chips {
157 E7520 = 0,
158 E7525 = 1,
159 E7320 = 2
160};
161
806c35f5
AC		 162struct e752x_pvt {
163 struct pci_dev *bridge_ck;
164 struct pci_dev *dev_d0f0;
165 struct pci_dev *dev_d0f1;
166 u32 tolm;
167 u32 remapbase;
168 u32 remaplimit;
169 int mc_symmetric;
170 u8 map[8];
171 int map_type;
172 const struct e752x_dev_info *dev_info;
173};
174
806c35f5
AC		 175struct e752x_dev_info {
176 u16 err_dev;
3847bccc 177 u16 ctl_dev;
806c35f5
AC		 178 const char *ctl_name;
179};
180
181struct e752x_error_info {
182 u32 ferr_global;
183 u32 nerr_global;
184 u8 hi_ferr;
185 u8 hi_nerr;
186 u16 sysbus_ferr;
187 u16 sysbus_nerr;
188 u8 buf_ferr;
189 u8 buf_nerr;
190 u16 dram_ferr;
191 u16 dram_nerr;
192 u32 dram_sec1_add;
193 u32 dram_sec2_add;
194 u16 dram_sec1_syndrome;
195 u16 dram_sec2_syndrome;
196 u32 dram_ded_add;
197 u32 dram_scrb_add;
198 u32 dram_retr_add;
199};
200
201static const struct e752x_dev_info e752x_devs[] = {
202 [E7520] = {
e7ecd891
DP		 203 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
204 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
205 .ctl_name = "E7520"
206 },
806c35f5 207 [E7525] = {
e7ecd891
DP		 208 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
209 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
210 .ctl_name = "E7525"
211 },
806c35f5 212 [E7320] = {
e7ecd891
DP		 213 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
214 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
215 .ctl_name = "E7320"
216 },
806c35f5
AC		 217};
218
806c35f5 219static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
e7ecd891 220 unsigned long page)
806c35f5
AC		 221{
222 u32 remap;
223 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
224
537fba28 225 debugf3("%s()\n", __func__);
806c35f5
AC		 226
227 if (page < pvt->tolm)
228 return page;
e7ecd891 229
806c35f5
AC		 230 if ((page >= 0x100000) && (page < pvt->remapbase))
231 return page;
e7ecd891 232
806c35f5 233 remap = (page - pvt->tolm) + pvt->remapbase;
e7ecd891 234
806c35f5
AC		 235 if (remap < pvt->remaplimit)
236 return remap;
e7ecd891 237
537fba28 238 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
806c35f5
AC		 239 return pvt->tolm - 1;
240}
241
242static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
e7ecd891 243 u32 sec1_add, u16 sec1_syndrome)
806c35f5
AC		 244{
245 u32 page;
246 int row;
247 int channel;
248 int i;
249 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
250
537fba28 251 debugf3("%s()\n", __func__);
806c35f5
AC		 252
253 /* convert the addr to 4k page */
254 page = sec1_add >> (PAGE_SHIFT - 4);
255
256 /* FIXME - check for -1 */
257 if (pvt->mc_symmetric) {
258 /* chip select are bits 14 & 13 */
259 row = ((page >> 1) & 3);
537fba28 260 e752x_printk(KERN_WARNING,
e7ecd891
DP		 261 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
262 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
263 pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]);
806c35f5
AC		 264
265 /* test for channel remapping */
266 for (i = 0; i < 8; i++) {
267 if (pvt->map[i] == row)
268 break;
269 }
e7ecd891 270
537fba28 271 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
e7ecd891 272
806c35f5
AC		 273 if (i < 8)
274 row = i;
275 else
537fba28 276 e752x_mc_printk(mci, KERN_WARNING,
e7ecd891 277 "row %d not found in remap table\n", row);
806c35f5
AC		 278 } else
279 row = edac_mc_find_csrow_by_page(mci, page);
e7ecd891 280
806c35f5
AC		 281 /* 0 = channel A, 1 = channel B */
282 channel = !(error_one & 1);
283
284 if (!pvt->map_type)
285 row = 7 - row;
e7ecd891 286
806c35f5 287 edac_mc_handle_ce(mci, page, 0, sec1_syndrome, row, channel,
e7ecd891 288 "e752x CE");
806c35f5
AC		 289}
290
806c35f5
AC		 291static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
292 u32 sec1_add, u16 sec1_syndrome, int *error_found,
293 int handle_error)
294{
295 *error_found = 1;
296
297 if (handle_error)
298 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
299}
300
e7ecd891
DP		 301static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
302 u32 ded_add, u32 scrb_add)
806c35f5
AC		 303{
304 u32 error_2b, block_page;
305 int row;
306 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
307
537fba28 308 debugf3("%s()\n", __func__);
806c35f5
AC		 309
310 if (error_one & 0x0202) {
311 error_2b = ded_add;
e7ecd891 312
806c35f5
AC		 313 /* convert to 4k address */
314 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 315
806c35f5 316 row = pvt->mc_symmetric ?
e7ecd891
DP		 317 /* chip select are bits 14 & 13 */
318 ((block_page >> 1) & 3) :
319 edac_mc_find_csrow_by_page(mci, block_page);
320
806c35f5 321 edac_mc_handle_ue(mci, block_page, 0, row,
e7ecd891 322 "e752x UE from Read");
806c35f5
AC		 323 }
324 if (error_one & 0x0404) {
325 error_2b = scrb_add;
e7ecd891 326
806c35f5
AC		 327 /* convert to 4k address */
328 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 329
806c35f5 330 row = pvt->mc_symmetric ?
e7ecd891
DP		 331 /* chip select are bits 14 & 13 */
332 ((block_page >> 1) & 3) :
333 edac_mc_find_csrow_by_page(mci, block_page);
334
806c35f5 335 edac_mc_handle_ue(mci, block_page, 0, row,
e7ecd891 336 "e752x UE from Scruber");
806c35f5
AC		 337 }
338}
339
340static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
341 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
342{
343 *error_found = 1;
344
345 if (handle_error)
346 do_process_ue(mci, error_one, ded_add, scrb_add);
347}
348
349static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
350 int *error_found, int handle_error)
351{
352 *error_found = 1;
353
354 if (!handle_error)
355 return;
356
537fba28 357 debugf3("%s()\n", __func__);
806c35f5
AC		 358 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
359}
360
361static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
362 u32 retry_add)
363{
364 u32 error_1b, page;
365 int row;
366 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
367
368 error_1b = retry_add;
e7ecd891 369 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
806c35f5 370 row = pvt->mc_symmetric ?
e7ecd891
DP		 371 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
372 edac_mc_find_csrow_by_page(mci, page);
537fba28 373 e752x_mc_printk(mci, KERN_WARNING,
e7ecd891
DP		 374 "CE page 0x%lx, row %d : Memory read retry\n",
375 (long unsigned int) page, row);
806c35f5
AC		 376}
377
378static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
379 u32 retry_add, int *error_found, int handle_error)
380{
381 *error_found = 1;
382
383 if (handle_error)
384 do_process_ded_retry(mci, error, retry_add);
385}
386
387static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
388 int *error_found, int handle_error)
389{
390 *error_found = 1;
391
392 if (handle_error)
537fba28 393 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
806c35f5
AC		 394}
395
da9bb1d2 396static char *global_message[11] = {
806c35f5
AC		 397 "PCI Express C1", "PCI Express C", "PCI Express B1",
398 "PCI Express B", "PCI Express A1", "PCI Express A",
399 "DMA Controler", "HUB Interface", "System Bus",
400 "DRAM Controler", "Internal Buffer"
401};
402
da9bb1d2 403static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
806c35f5
AC		 404
405static void do_global_error(int fatal, u32 errors)
406{
407 int i;
408
409 for (i = 0; i < 11; i++) {
410 if (errors & (1 << i))
537fba28 411 e752x_printk(KERN_WARNING, "%sError %s\n",
e7ecd891 412 fatal_message[fatal], global_message[i]);
806c35f5
AC		 413 }
414}
415
416static inline void global_error(int fatal, u32 errors, int *error_found,
417 int handle_error)
418{
419 *error_found = 1;
420
421 if (handle_error)
422 do_global_error(fatal, errors);
423}
424
da9bb1d2 425static char *hub_message[7] = {
806c35f5
AC		 426 "HI Address or Command Parity", "HI Illegal Access",
427 "HI Internal Parity", "Out of Range Access",
428 "HI Data Parity", "Enhanced Config Access",
429 "Hub Interface Target Abort"
430};
431
432static void do_hub_error(int fatal, u8 errors)
433{
434 int i;
435
436 for (i = 0; i < 7; i++) {
437 if (errors & (1 << i))
537fba28 438 e752x_printk(KERN_WARNING, "%sError %s\n",
e7ecd891 439 fatal_message[fatal], hub_message[i]);
806c35f5
AC		 440 }
441}
442
443static inline void hub_error(int fatal, u8 errors, int *error_found,
444 int handle_error)
445{
446 *error_found = 1;
447
448 if (handle_error)
449 do_hub_error(fatal, errors);
450}
451
da9bb1d2 452static char *membuf_message[4] = {
806c35f5
AC		 453 "Internal PMWB to DRAM parity",
454 "Internal PMWB to System Bus Parity",
455 "Internal System Bus or IO to PMWB Parity",
456 "Internal DRAM to PMWB Parity"
457};
458
459static void do_membuf_error(u8 errors)
460{
461 int i;
462
463 for (i = 0; i < 4; i++) {
464 if (errors & (1 << i))
537fba28 465 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
e7ecd891 466 membuf_message[i]);
806c35f5
AC		 467 }
468}
469
470static inline void membuf_error(u8 errors, int *error_found, int handle_error)
471{
472 *error_found = 1;
473
474 if (handle_error)
475 do_membuf_error(errors);
476}
477
e009356f 478static char *sysbus_message[10] = {
806c35f5
AC		 479 "Addr or Request Parity",
480 "Data Strobe Glitch",
481 "Addr Strobe Glitch",
482 "Data Parity",
483 "Addr Above TOM",
484 "Non DRAM Lock Error",
485 "MCERR", "BINIT",
486 "Memory Parity",
487 "IO Subsystem Parity"
488};
489
490static void do_sysbus_error(int fatal, u32 errors)
491{
492 int i;
493
494 for (i = 0; i < 10; i++) {
495 if (errors & (1 << i))
537fba28 496 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
e009356f 497 fatal_message[fatal], sysbus_message[i]);
806c35f5
AC		 498 }
499}
500
501static inline void sysbus_error(int fatal, u32 errors, int *error_found,
502 int handle_error)
503{
504 *error_found = 1;
505
506 if (handle_error)
507 do_sysbus_error(fatal, errors);
508}
509
e7ecd891 510static void e752x_check_hub_interface(struct e752x_error_info *info,
806c35f5
AC		 511 int *error_found, int handle_error)
512{
513 u8 stat8;
514
515 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
e7ecd891 516
806c35f5 517 stat8 = info->hi_ferr;
e7ecd891 518
806c35f5
AC		 519 if(stat8 & 0x7f) { /* Error, so process */
520 stat8 &= 0x7f;
e7ecd891 521
806c35f5
AC		 522 if(stat8 & 0x2b)
523 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 524
806c35f5
AC		 525 if(stat8 & 0x54)
526 hub_error(0, stat8 & 0x54, error_found, handle_error);
527 }
e7ecd891 528
806c35f5 529 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
e7ecd891 530
806c35f5 531 stat8 = info->hi_nerr;
e7ecd891 532
806c35f5
AC		 533 if(stat8 & 0x7f) { /* Error, so process */
534 stat8 &= 0x7f;
e7ecd891 535
806c35f5
AC		 536 if (stat8 & 0x2b)
537 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 538
806c35f5
AC		 539 if(stat8 & 0x54)
540 hub_error(0, stat8 & 0x54, error_found, handle_error);
541 }
542}
543
e7ecd891
DP		 544static void e752x_check_sysbus(struct e752x_error_info *info,
545 int *error_found, int handle_error)
806c35f5
AC		 546{
547 u32 stat32, error32;
548
549 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
550 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
551
552 if (stat32 == 0)
553 return; /* no errors */
554
555 error32 = (stat32 >> 16) & 0x3ff;
556 stat32 = stat32 & 0x3ff;
e7ecd891 557
806c35f5
AC		 558 if(stat32 & 0x083)
559 sysbus_error(1, stat32 & 0x083, error_found, handle_error);
e7ecd891 560
806c35f5
AC		 561 if(stat32 & 0x37c)
562 sysbus_error(0, stat32 & 0x37c, error_found, handle_error);
e7ecd891 563
806c35f5
AC		 564 if(error32 & 0x083)
565 sysbus_error(1, error32 & 0x083, error_found, handle_error);
e7ecd891 566
806c35f5
AC		 567 if(error32 & 0x37c)
568 sysbus_error(0, error32 & 0x37c, error_found, handle_error);
569}
570
e7ecd891
DP		 571static void e752x_check_membuf (struct e752x_error_info *info,
572 int *error_found, int handle_error)
806c35f5
AC		 573{
574 u8 stat8;
575
576 stat8 = info->buf_ferr;
e7ecd891 577
806c35f5
AC		 578 if (stat8 & 0x0f) { /* Error, so process */
579 stat8 &= 0x0f;
580 membuf_error(stat8, error_found, handle_error);
581 }
e7ecd891 582
806c35f5 583 stat8 = info->buf_nerr;
e7ecd891 584
806c35f5
AC		 585 if (stat8 & 0x0f) { /* Error, so process */
586 stat8 &= 0x0f;
587 membuf_error(stat8, error_found, handle_error);
588 }
589}
590
591static void e752x_check_dram (struct mem_ctl_info *mci,
e7ecd891
DP		 592 struct e752x_error_info *info, int *error_found,
593 int handle_error)
806c35f5
AC		 594{
595 u16 error_one, error_next;
596
597 error_one = info->dram_ferr;
598 error_next = info->dram_nerr;
599
600 /* decode and report errors */
601 if(error_one & 0x0101) /* check first error correctable */
602 process_ce(mci, error_one, info->dram_sec1_add,
603 info->dram_sec1_syndrome, error_found,
604 handle_error);
605
606 if(error_next & 0x0101) /* check next error correctable */
607 process_ce(mci, error_next, info->dram_sec2_add,
608 info->dram_sec2_syndrome, error_found,
609 handle_error);
610
611 if(error_one & 0x4040)
612 process_ue_no_info_wr(mci, error_found, handle_error);
613
614 if(error_next & 0x4040)
615 process_ue_no_info_wr(mci, error_found, handle_error);
616
617 if(error_one & 0x2020)
618 process_ded_retry(mci, error_one, info->dram_retr_add,
619 error_found, handle_error);
620
621 if(error_next & 0x2020)
622 process_ded_retry(mci, error_next, info->dram_retr_add,
623 error_found, handle_error);
624
625 if(error_one & 0x0808)
626 process_threshold_ce(mci, error_one, error_found,
627 handle_error);
628
629 if(error_next & 0x0808)
630 process_threshold_ce(mci, error_next, error_found,
631 handle_error);
632
633 if(error_one & 0x0606)
634 process_ue(mci, error_one, info->dram_ded_add,
635 info->dram_scrb_add, error_found, handle_error);
636
637 if(error_next & 0x0606)
638 process_ue(mci, error_next, info->dram_ded_add,
639 info->dram_scrb_add, error_found, handle_error);
640}
641
642static void e752x_get_error_info (struct mem_ctl_info *mci,
e7ecd891 643 struct e752x_error_info *info)
806c35f5
AC		 644{
645 struct pci_dev *dev;
646 struct e752x_pvt *pvt;
647
648 memset(info, 0, sizeof(*info));
649 pvt = (struct e752x_pvt *) mci->pvt_info;
650 dev = pvt->dev_d0f1;
806c35f5
AC		 651 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
652
653 if (info->ferr_global) {
654 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
655 pci_read_config_word(dev, E752X_SYSBUS_FERR,
656 &info->sysbus_ferr);
657 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
658 pci_read_config_word(dev, E752X_DRAM_FERR,
659 &info->dram_ferr);
660 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
661 &info->dram_sec1_add);
662 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
663 &info->dram_sec1_syndrome);
664 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
665 &info->dram_ded_add);
666 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
667 &info->dram_scrb_add);
668 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
669 &info->dram_retr_add);
670
671 if (info->hi_ferr & 0x7f)
672 pci_write_config_byte(dev, E752X_HI_FERR,
673 info->hi_ferr);
674
675 if (info->sysbus_ferr)
676 pci_write_config_word(dev, E752X_SYSBUS_FERR,
677 info->sysbus_ferr);
678
679 if (info->buf_ferr & 0x0f)
680 pci_write_config_byte(dev, E752X_BUF_FERR,
681 info->buf_ferr);
682
683 if (info->dram_ferr)
684 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
685 info->dram_ferr, info->dram_ferr);
686
687 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
688 info->ferr_global);
689 }
690
691 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
692
693 if (info->nerr_global) {
694 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
695 pci_read_config_word(dev, E752X_SYSBUS_NERR,
696 &info->sysbus_nerr);
697 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
698 pci_read_config_word(dev, E752X_DRAM_NERR,
699 &info->dram_nerr);
700 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
701 &info->dram_sec2_add);
702 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
703 &info->dram_sec2_syndrome);
704
705 if (info->hi_nerr & 0x7f)
706 pci_write_config_byte(dev, E752X_HI_NERR,
707 info->hi_nerr);
708
709 if (info->sysbus_nerr)
710 pci_write_config_word(dev, E752X_SYSBUS_NERR,
711 info->sysbus_nerr);
712
713 if (info->buf_nerr & 0x0f)
714 pci_write_config_byte(dev, E752X_BUF_NERR,
715 info->buf_nerr);
716
717 if (info->dram_nerr)
718 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
719 info->dram_nerr, info->dram_nerr);
720
721 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
722 info->nerr_global);
723 }
724}
725
726static int e752x_process_error_info (struct mem_ctl_info *mci,
727 struct e752x_error_info *info, int handle_errors)
728{
729 u32 error32, stat32;
730 int error_found;
731
732 error_found = 0;
733 error32 = (info->ferr_global >> 18) & 0x3ff;
734 stat32 = (info->ferr_global >> 4) & 0x7ff;
735
736 if (error32)
737 global_error(1, error32, &error_found, handle_errors);
738
739 if (stat32)
740 global_error(0, stat32, &error_found, handle_errors);
741
742 error32 = (info->nerr_global >> 18) & 0x3ff;
743 stat32 = (info->nerr_global >> 4) & 0x7ff;
744
745 if (error32)
746 global_error(1, error32, &error_found, handle_errors);
747
748 if (stat32)
749 global_error(0, stat32, &error_found, handle_errors);
750
751 e752x_check_hub_interface(info, &error_found, handle_errors);
752 e752x_check_sysbus(info, &error_found, handle_errors);
753 e752x_check_membuf(info, &error_found, handle_errors);
754 e752x_check_dram(mci, info, &error_found, handle_errors);
755 return error_found;
756}
757
758static void e752x_check(struct mem_ctl_info *mci)
759{
760 struct e752x_error_info info;
e7ecd891 761
537fba28 762 debugf3("%s()\n", __func__);
806c35f5
AC		 763 e752x_get_error_info(mci, &info);
764 e752x_process_error_info(mci, &info, 1);
765}
766
13189525
DT		 767/* Return 1 if dual channel mode is active. Else return 0. */
768static inline int dual_channel_active(u16 ddrcsr)
769{
770 return (((ddrcsr >> 12) & 3) == 3);
771}
772
773static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
774 u16 ddrcsr)
775{
776 struct csrow_info *csrow;
777 unsigned long last_cumul_size;
778 int index, mem_dev, drc_chan;
779 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
780 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
781 u8 value;
782 u32 dra, drc, cumul_size;
783
784 pci_read_config_dword(pdev, E752X_DRA, &dra);
785 pci_read_config_dword(pdev, E752X_DRC, &drc);
786 drc_chan = dual_channel_active(ddrcsr);
787 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
788 drc_ddim = (drc >> 20) & 0x3;
789
790 /* The dram row boundary (DRB) reg values are boundary address for
791 * each DRAM row with a granularity of 64 or 128MB (single/dual
792 * channel operation). DRB regs are cumulative; therefore DRB7 will
793 * contain the total memory contained in all eight rows.
794 */
795 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
796 /* mem_dev 0=x8, 1=x4 */
797 mem_dev = (dra >> (index * 4 + 2)) & 0x3;
798 csrow = &mci->csrows[index];
799
800 mem_dev = (mem_dev == 2);
801 pci_read_config_byte(pdev, E752X_DRB + index, &value);
802 /* convert a 128 or 64 MiB DRB to a page size. */
803 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
804 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
805 cumul_size);
806 if (cumul_size == last_cumul_size)
807 continue; /* not populated */
808
809 csrow->first_page = last_cumul_size;
810 csrow->last_page = cumul_size - 1;
811 csrow->nr_pages = cumul_size - last_cumul_size;
812 last_cumul_size = cumul_size;
813 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
814 csrow->mtype = MEM_RDDR; /* only one type supported */
815 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
816
817 /*
818 * if single channel or x8 devices then SECDED
819 * if dual channel and x4 then S4ECD4ED
820 */
821 if (drc_ddim) {
822 if (drc_chan && mem_dev) {
823 csrow->edac_mode = EDAC_S4ECD4ED;
824 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
825 } else {
826 csrow->edac_mode = EDAC_SECDED;
827 mci->edac_cap |= EDAC_FLAG_SECDED;
828 }
829 } else
830 csrow->edac_mode = EDAC_NONE;
831 }
832}
833
834static void e752x_init_mem_map_table(struct pci_dev *pdev,
835 struct e752x_pvt *pvt)
806c35f5 836{
806c35f5 837 int index;
13189525
DT		 838 u8 value, last, row, stat8;
839
840 last = 0;
841 row = 0;
842
843 for (index = 0; index < 8; index += 2) {
844 pci_read_config_byte(pdev, E752X_DRB + index, &value);
845 /* test if there is a dimm in this slot */
846 if (value == last) {
847 /* no dimm in the slot, so flag it as empty */
848 pvt->map[index] = 0xff;
849 pvt->map[index + 1] = 0xff;
850 } else { /* there is a dimm in the slot */
851 pvt->map[index] = row;
852 row++;
853 last = value;
854 /* test the next value to see if the dimm is double
855 * sided
856 */
857 pci_read_config_byte(pdev, E752X_DRB + index + 1,
858 &value);
859 pvt->map[index + 1] = (value == last) ?
860 0xff : /* the dimm is single sided,
861 so flag as empty */
862 row; /* this is a double sided dimm
863 to save the next row # */
864 row++;
865 last = value;
866 }
867 }
868
869 /* set the map type. 1 = normal, 0 = reversed */
870 pci_read_config_byte(pdev, E752X_DRM, &stat8);
871 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
872}
873
874/* Return 0 on success or 1 on failure. */
875static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
876 struct e752x_pvt *pvt)
877{
878 struct pci_dev *dev;
879
880 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
881 pvt->dev_info->err_dev,
882 pvt->bridge_ck);
883
884 if (pvt->bridge_ck == NULL)
885 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
886 PCI_DEVFN(0, 1));
887
888 if (pvt->bridge_ck == NULL) {
889 e752x_printk(KERN_ERR, "error reporting device not found:"
890 "vendor %x device 0x%x (broken BIOS?)\n",
891 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
892 return 1;
893 }
894
895 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
896 NULL);
897
898 if (dev == NULL)
899 goto fail;
900
901 pvt->dev_d0f0 = dev;
902 pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
903
904 return 0;
905
906fail:
907 pci_dev_put(pvt->bridge_ck);
908 return 1;
909}
910
911static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
912{
913 struct pci_dev *dev;
914
915 dev = pvt->dev_d0f1;
916 /* Turn off error disable & SMI in case the BIOS turned it on */
917 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
918 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
919 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
920 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
921 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
922 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
923 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
924 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
925}
926
927static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
928{
3847bccc 929 u16 pci_data;
806c35f5 930 u8 stat8;
13189525
DT		 931 struct mem_ctl_info *mci;
932 struct e752x_pvt *pvt;
806c35f5 933 u16 ddrcsr;
e7ecd891 934 int drc_chan; /* Number of channels 0=1chan,1=2chan */
749ede57 935 struct e752x_error_info discard;
806c35f5 936
537fba28 937 debugf0("%s(): mci\n", __func__);
806c35f5
AC		 938 debugf0("Starting Probe1\n");
939
96941026 940 /* check to see if device 0 function 1 is enabled; if it isn't, we
941 * assume the BIOS has reserved it for a reason and is expecting
942 * exclusive access, we take care not to violate that assumption and
943 * fail the probe. */
806c35f5 944 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
96941026 945 if (!force_function_unhide && !(stat8 & (1 << 5))) {
946 printk(KERN_INFO "Contact your BIOS vendor to see if the "
947 "E752x error registers can be safely un-hidden\n");
13189525 948 return -ENOMEM;
96941026 949 }
806c35f5
AC		 950 stat8 |= (1 << 5);
951 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
952
806c35f5
AC		 953 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
954 /* FIXME: should check >>12 or 0xf, true for all? */
955 /* Dual channel = 1, Single channel = 0 */
13189525 956 drc_chan = dual_channel_active(ddrcsr);
806c35f5
AC		 957
958 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
959
960 if (mci == NULL) {
13189525 961 return -ENOMEM;
806c35f5
AC		 962 }
963
537fba28 964 debugf3("%s(): init mci\n", __func__);
806c35f5
AC		 965 mci->mtype_cap = MEM_FLAG_RDDR;
966 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
967 EDAC_FLAG_S4ECD4ED;
968 /* FIXME - what if different memory types are in different csrows? */
680cbbbb 969 mci->mod_name = EDAC_MOD_STR;
37f04581
DT		 970 mci->mod_ver = E752X_REVISION;
971 mci->dev = &pdev->dev;
806c35f5 972
537fba28 973 debugf3("%s(): init pvt\n", __func__);
806c35f5
AC		 974 pvt = (struct e752x_pvt *) mci->pvt_info;
975 pvt->dev_info = &e752x_devs[dev_idx];
13189525 976 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
e7ecd891 977
13189525
DT		 978 if (e752x_get_devs(pdev, dev_idx, pvt)) {
979 edac_mc_free(mci);
980 return -ENODEV;
806c35f5 981 }
806c35f5 982
537fba28 983 debugf3("%s(): more mci init\n", __func__);
806c35f5
AC		 984 mci->ctl_name = pvt->dev_info->ctl_name;
985 mci->edac_check = e752x_check;
986 mci->ctl_page_to_phys = ctl_page_to_phys;
987
13189525
DT		 988 e752x_init_csrows(mci, pdev, ddrcsr);
989 e752x_init_mem_map_table(pdev, pvt);
806c35f5
AC		 990
991 /* set the map type. 1 = normal, 0 = reversed */
37f04581 992 pci_read_config_byte(pdev, E752X_DRM, &stat8);
806c35f5
AC		 993 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
994
995 mci->edac_cap |= EDAC_FLAG_NONE;
537fba28 996 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
e7ecd891 997
806c35f5 998 /* load the top of low memory, remap base, and remap limit vars */
37f04581 999 pci_read_config_word(pdev, E752X_TOLM, &pci_data);
806c35f5 1000 pvt->tolm = ((u32) pci_data) << 4;
37f04581 1001 pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
806c35f5 1002 pvt->remapbase = ((u32) pci_data) << 14;
37f04581 1003 pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
806c35f5 1004 pvt->remaplimit = ((u32) pci_data) << 14;
537fba28 1005 e752x_printk(KERN_INFO,
e7ecd891
DP		 1006 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
1007 pvt->remapbase, pvt->remaplimit);
806c35f5 1008
2d7bbb91
DT		 1009 /* Here we assume that we will never see multiple instances of this
1010 * type of memory controller. The ID is therefore hardcoded to 0.
1011 */
1012 if (edac_mc_add_mc(mci,0)) {
537fba28 1013 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
806c35f5
AC		 1014 goto fail;
1015 }
1016
13189525 1017 e752x_init_error_reporting_regs(pvt);
e7ecd891 1018 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
806c35f5
AC		 1019
1020 /* get this far and it's successful */
537fba28 1021 debugf3("%s(): success\n", __func__);
806c35f5
AC		 1022 return 0;
1023
1024fail:
13189525
DT		 1025 pci_dev_put(pvt->dev_d0f0);
1026 pci_dev_put(pvt->dev_d0f1);
1027 pci_dev_put(pvt->bridge_ck);
1028 edac_mc_free(mci);
e7ecd891 1029
13189525 1030 return -ENODEV;
806c35f5
AC		 1031}
1032
1033/* returns count (>= 0), or negative on error */
1034static int __devinit e752x_init_one(struct pci_dev *pdev,
e7ecd891 1035 const struct pci_device_id *ent)
806c35f5 1036{
537fba28 1037 debugf0("%s()\n", __func__);
806c35f5
AC		 1038
1039 /* wake up and enable device */
1040 if(pci_enable_device(pdev) < 0)
1041 return -EIO;
e7ecd891 1042
806c35f5
AC		 1043 return e752x_probe1(pdev, ent->driver_data);
1044}
1045
806c35f5
AC		 1046static void __devexit e752x_remove_one(struct pci_dev *pdev)
1047{
1048 struct mem_ctl_info *mci;
1049 struct e752x_pvt *pvt;
1050
537fba28 1051 debugf0("%s()\n", __func__);
806c35f5 1052
37f04581 1053 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
806c35f5
AC		 1054 return;
1055
1056 pvt = (struct e752x_pvt *) mci->pvt_info;
1057 pci_dev_put(pvt->dev_d0f0);
1058 pci_dev_put(pvt->dev_d0f1);
1059 pci_dev_put(pvt->bridge_ck);
1060 edac_mc_free(mci);
1061}
1062
806c35f5 1063static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
e7ecd891
DP		 1064 {
1065 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1066 E7520
1067 },
1068 {
1069 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1070 E7525
1071 },
1072 {
1073 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1074 E7320
1075 },
1076 {
1077 0,
1078 } /* 0 terminated list. */
806c35f5
AC		 1079};
1080
1081MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1082
806c35f5 1083static struct pci_driver e752x_driver = {
680cbbbb 1084 .name = EDAC_MOD_STR,
0d38b049
RD		 1085 .probe = e752x_init_one,
1086 .remove = __devexit_p(e752x_remove_one),
1087 .id_table = e752x_pci_tbl,
806c35f5
AC		 1088};
1089
da9bb1d2 1090static int __init e752x_init(void)
806c35f5
AC		 1091{
1092 int pci_rc;
1093
537fba28 1094 debugf3("%s()\n", __func__);
806c35f5
AC		 1095 pci_rc = pci_register_driver(&e752x_driver);
1096 return (pci_rc < 0) ? pci_rc : 0;
1097}
1098
806c35f5
AC		 1099static void __exit e752x_exit(void)
1100{
537fba28 1101 debugf3("%s()\n", __func__);
806c35f5
AC		 1102 pci_unregister_driver(&e752x_driver);
1103}
1104
806c35f5
AC		 1105module_init(e752x_init);
1106module_exit(e752x_exit);
1107
1108MODULE_LICENSE("GPL");
1109MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1110MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
96941026 1111
1112module_param(force_function_unhide, int, 0444);
1113MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1114" 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");
1115
kernel source for telekom puls (alcatel/mediatek)