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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / e752x_edac.c
CommitLineData
806c35f5
AC		 1/*
2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e752x_chips" below for supported chipsets
8 *
9 * Written by Tom Zimmerman
10 *
11 * Contributors:
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
15 *
da9bb1d2 16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
806c35f5
AC		 17 *
18 */
19
806c35f5
AC		 20#include <linux/config.h>
21#include <linux/module.h>
22#include <linux/init.h>
806c35f5
AC		 23#include <linux/pci.h>
24#include <linux/pci_ids.h>
806c35f5 25#include <linux/slab.h>
806c35f5
AC		 26#include "edac_mc.h"
27
96941026 28static int force_function_unhide;
29
537fba28 30#define e752x_printk(level, fmt, arg...) \
e7ecd891 31 edac_printk(level, "e752x", fmt, ##arg)
537fba28
DP		 32
33#define e752x_mc_printk(mci, level, fmt, arg...) \
e7ecd891 34 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
537fba28 35
806c35f5
AC		 36#ifndef PCI_DEVICE_ID_INTEL_7520_0
37#define PCI_DEVICE_ID_INTEL_7520_0 0x3590
38#endif /* PCI_DEVICE_ID_INTEL_7520_0 */
39
40#ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
41#define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
42#endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
43
44#ifndef PCI_DEVICE_ID_INTEL_7525_0
45#define PCI_DEVICE_ID_INTEL_7525_0 0x359E
46#endif /* PCI_DEVICE_ID_INTEL_7525_0 */
47
48#ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
49#define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
50#endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
51
52#ifndef PCI_DEVICE_ID_INTEL_7320_0
53#define PCI_DEVICE_ID_INTEL_7320_0 0x3592
54#endif /* PCI_DEVICE_ID_INTEL_7320_0 */
55
56#ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
57#define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
58#endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
59
60#define E752X_NR_CSROWS 8 /* number of csrows */
61
806c35f5
AC		 62/* E752X register addresses - device 0 function 0 */
63#define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
64#define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
65 /*
66 * 31:30 Device width row 7
67 * 01=x8 10=x4 11=x8 DDR2
68 * 27:26 Device width row 6
69 * 23:22 Device width row 5
70 * 19:20 Device width row 4
71 * 15:14 Device width row 3
72 * 11:10 Device width row 2
73 * 7:6 Device width row 1
74 * 3:2 Device width row 0
75 */
76#define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
77 /* FIXME:IS THIS RIGHT? */
78 /*
79 * 22 Number channels 0=1,1=2
80 * 19:18 DRB Granularity 32/64MB
81 */
82#define E752X_DRM 0x80 /* Dimm mapping register */
83#define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
84 /*
85 * 14:12 1 single A, 2 single B, 3 dual
86 */
87#define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
88#define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
89#define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
90#define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
91
92/* E752X register addresses - device 0 function 1 */
93#define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
94#define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
95#define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
96#define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
97#define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
98#define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
99#define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
100#define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
101#define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
102#define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
103#define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
104#define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
105#define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
106#define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
107#define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
108#define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
109#define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
110#define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
111#define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
112#define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
113 /* error address register (32b) */
114 /*
115 * 31 Reserved
116 * 30:2 CE address (64 byte block 34:6)
117 * 1 Reserved
118 * 0 HiLoCS
119 */
120#define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
121 /* error address register (32b) */
122 /*
123 * 31 Reserved
124 * 30:2 CE address (64 byte block 34:6)
125 * 1 Reserved
126 * 0 HiLoCS
127 */
128#define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
129 /* error address register (32b) */
130 /*
131 * 31 Reserved
132 * 30:2 CE address (64 byte block 34:6)
133 * 1 Reserved
134 * 0 HiLoCS
135 */
136#define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
137 /* error address register (32b) */
138 /*
139 * 31 Reserved
140 * 30:2 CE address (64 byte block 34:6)
141 * 1 Reserved
142 * 0 HiLoCS
143 */
144#define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
145 /* error syndrome register (16b) */
146#define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
147 /* error syndrome register (16b) */
148#define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
149
150/* ICH5R register addresses - device 30 function 0 */
151#define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
152#define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
153#define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
154
155enum e752x_chips {
156 E7520 = 0,
157 E7525 = 1,
158 E7320 = 2
159};
160
806c35f5
AC		 161struct e752x_pvt {
162 struct pci_dev *bridge_ck;
163 struct pci_dev *dev_d0f0;
164 struct pci_dev *dev_d0f1;
165 u32 tolm;
166 u32 remapbase;
167 u32 remaplimit;
168 int mc_symmetric;
169 u8 map[8];
170 int map_type;
171 const struct e752x_dev_info *dev_info;
172};
173
806c35f5
AC		 174struct e752x_dev_info {
175 u16 err_dev;
3847bccc 176 u16 ctl_dev;
806c35f5
AC		 177 const char *ctl_name;
178};
179
180struct e752x_error_info {
181 u32 ferr_global;
182 u32 nerr_global;
183 u8 hi_ferr;
184 u8 hi_nerr;
185 u16 sysbus_ferr;
186 u16 sysbus_nerr;
187 u8 buf_ferr;
188 u8 buf_nerr;
189 u16 dram_ferr;
190 u16 dram_nerr;
191 u32 dram_sec1_add;
192 u32 dram_sec2_add;
193 u16 dram_sec1_syndrome;
194 u16 dram_sec2_syndrome;
195 u32 dram_ded_add;
196 u32 dram_scrb_add;
197 u32 dram_retr_add;
198};
199
200static const struct e752x_dev_info e752x_devs[] = {
201 [E7520] = {
e7ecd891
DP		 202 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
203 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
204 .ctl_name = "E7520"
205 },
806c35f5 206 [E7525] = {
e7ecd891
DP		 207 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
208 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
209 .ctl_name = "E7525"
210 },
806c35f5 211 [E7320] = {
e7ecd891
DP		 212 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
213 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
214 .ctl_name = "E7320"
215 },
806c35f5
AC		 216};
217
806c35f5 218static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
e7ecd891 219 unsigned long page)
806c35f5
AC		 220{
221 u32 remap;
222 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
223
537fba28 224 debugf3("%s()\n", __func__);
806c35f5
AC		 225
226 if (page < pvt->tolm)
227 return page;
e7ecd891 228
806c35f5
AC		 229 if ((page >= 0x100000) && (page < pvt->remapbase))
230 return page;
e7ecd891 231
806c35f5 232 remap = (page - pvt->tolm) + pvt->remapbase;
e7ecd891 233
806c35f5
AC		 234 if (remap < pvt->remaplimit)
235 return remap;
e7ecd891 236
537fba28 237 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
806c35f5
AC		 238 return pvt->tolm - 1;
239}
240
241static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
e7ecd891 242 u32 sec1_add, u16 sec1_syndrome)
806c35f5
AC		 243{
244 u32 page;
245 int row;
246 int channel;
247 int i;
248 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
249
537fba28 250 debugf3("%s()\n", __func__);
806c35f5
AC		 251
252 /* convert the addr to 4k page */
253 page = sec1_add >> (PAGE_SHIFT - 4);
254
255 /* FIXME - check for -1 */
256 if (pvt->mc_symmetric) {
257 /* chip select are bits 14 & 13 */
258 row = ((page >> 1) & 3);
537fba28 259 e752x_printk(KERN_WARNING,
e7ecd891
DP		 260 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
261 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
262 pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]);
806c35f5
AC		 263
264 /* test for channel remapping */
265 for (i = 0; i < 8; i++) {
266 if (pvt->map[i] == row)
267 break;
268 }
e7ecd891 269
537fba28 270 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
e7ecd891 271
806c35f5
AC		 272 if (i < 8)
273 row = i;
274 else
537fba28 275 e752x_mc_printk(mci, KERN_WARNING,
e7ecd891 276 "row %d not found in remap table\n", row);
806c35f5
AC		 277 } else
278 row = edac_mc_find_csrow_by_page(mci, page);
e7ecd891 279
806c35f5
AC		 280 /* 0 = channel A, 1 = channel B */
281 channel = !(error_one & 1);
282
283 if (!pvt->map_type)
284 row = 7 - row;
e7ecd891 285
806c35f5 286 edac_mc_handle_ce(mci, page, 0, sec1_syndrome, row, channel,
e7ecd891 287 "e752x CE");
806c35f5
AC		 288}
289
806c35f5
AC		 290static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
291 u32 sec1_add, u16 sec1_syndrome, int *error_found,
292 int handle_error)
293{
294 *error_found = 1;
295
296 if (handle_error)
297 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
298}
299
e7ecd891
DP		 300static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
301 u32 ded_add, u32 scrb_add)
806c35f5
AC		 302{
303 u32 error_2b, block_page;
304 int row;
305 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
306
537fba28 307 debugf3("%s()\n", __func__);
806c35f5
AC		 308
309 if (error_one & 0x0202) {
310 error_2b = ded_add;
e7ecd891 311
806c35f5
AC		 312 /* convert to 4k address */
313 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 314
806c35f5 315 row = pvt->mc_symmetric ?
e7ecd891
DP		 316 /* chip select are bits 14 & 13 */
317 ((block_page >> 1) & 3) :
318 edac_mc_find_csrow_by_page(mci, block_page);
319
806c35f5 320 edac_mc_handle_ue(mci, block_page, 0, row,
e7ecd891 321 "e752x UE from Read");
806c35f5
AC		 322 }
323 if (error_one & 0x0404) {
324 error_2b = scrb_add;
e7ecd891 325
806c35f5
AC		 326 /* convert to 4k address */
327 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 328
806c35f5 329 row = pvt->mc_symmetric ?
e7ecd891
DP		 330 /* chip select are bits 14 & 13 */
331 ((block_page >> 1) & 3) :
332 edac_mc_find_csrow_by_page(mci, block_page);
333
806c35f5 334 edac_mc_handle_ue(mci, block_page, 0, row,
e7ecd891 335 "e752x UE from Scruber");
806c35f5
AC		 336 }
337}
338
339static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
340 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
341{
342 *error_found = 1;
343
344 if (handle_error)
345 do_process_ue(mci, error_one, ded_add, scrb_add);
346}
347
348static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
349 int *error_found, int handle_error)
350{
351 *error_found = 1;
352
353 if (!handle_error)
354 return;
355
537fba28 356 debugf3("%s()\n", __func__);
806c35f5
AC		 357 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
358}
359
360static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
361 u32 retry_add)
362{
363 u32 error_1b, page;
364 int row;
365 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
366
367 error_1b = retry_add;
e7ecd891 368 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
806c35f5 369 row = pvt->mc_symmetric ?
e7ecd891
DP		 370 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
371 edac_mc_find_csrow_by_page(mci, page);
537fba28 372 e752x_mc_printk(mci, KERN_WARNING,
e7ecd891
DP		 373 "CE page 0x%lx, row %d : Memory read retry\n",
374 (long unsigned int) page, row);
806c35f5
AC		 375}
376
377static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
378 u32 retry_add, int *error_found, int handle_error)
379{
380 *error_found = 1;
381
382 if (handle_error)
383 do_process_ded_retry(mci, error, retry_add);
384}
385
386static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
387 int *error_found, int handle_error)
388{
389 *error_found = 1;
390
391 if (handle_error)
537fba28 392 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
806c35f5
AC		 393}
394
da9bb1d2 395static char *global_message[11] = {
806c35f5
AC		 396 "PCI Express C1", "PCI Express C", "PCI Express B1",
397 "PCI Express B", "PCI Express A1", "PCI Express A",
398 "DMA Controler", "HUB Interface", "System Bus",
399 "DRAM Controler", "Internal Buffer"
400};
401
da9bb1d2 402static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
806c35f5
AC		 403
404static void do_global_error(int fatal, u32 errors)
405{
406 int i;
407
408 for (i = 0; i < 11; i++) {
409 if (errors & (1 << i))
537fba28 410 e752x_printk(KERN_WARNING, "%sError %s\n",
e7ecd891 411 fatal_message[fatal], global_message[i]);
806c35f5
AC		 412 }
413}
414
415static inline void global_error(int fatal, u32 errors, int *error_found,
416 int handle_error)
417{
418 *error_found = 1;
419
420 if (handle_error)
421 do_global_error(fatal, errors);
422}
423
da9bb1d2 424static char *hub_message[7] = {
806c35f5
AC		 425 "HI Address or Command Parity", "HI Illegal Access",
426 "HI Internal Parity", "Out of Range Access",
427 "HI Data Parity", "Enhanced Config Access",
428 "Hub Interface Target Abort"
429};
430
431static void do_hub_error(int fatal, u8 errors)
432{
433 int i;
434
435 for (i = 0; i < 7; i++) {
436 if (errors & (1 << i))
537fba28 437 e752x_printk(KERN_WARNING, "%sError %s\n",
e7ecd891 438 fatal_message[fatal], hub_message[i]);
806c35f5
AC		 439 }
440}
441
442static inline void hub_error(int fatal, u8 errors, int *error_found,
443 int handle_error)
444{
445 *error_found = 1;
446
447 if (handle_error)
448 do_hub_error(fatal, errors);
449}
450
da9bb1d2 451static char *membuf_message[4] = {
806c35f5
AC		 452 "Internal PMWB to DRAM parity",
453 "Internal PMWB to System Bus Parity",
454 "Internal System Bus or IO to PMWB Parity",
455 "Internal DRAM to PMWB Parity"
456};
457
458static void do_membuf_error(u8 errors)
459{
460 int i;
461
462 for (i = 0; i < 4; i++) {
463 if (errors & (1 << i))
537fba28 464 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
e7ecd891 465 membuf_message[i]);
806c35f5
AC		 466 }
467}
468
469static inline void membuf_error(u8 errors, int *error_found, int handle_error)
470{
471 *error_found = 1;
472
473 if (handle_error)
474 do_membuf_error(errors);
475}
476
e009356f 477static char *sysbus_message[10] = {
806c35f5
AC		 478 "Addr or Request Parity",
479 "Data Strobe Glitch",
480 "Addr Strobe Glitch",
481 "Data Parity",
482 "Addr Above TOM",
483 "Non DRAM Lock Error",
484 "MCERR", "BINIT",
485 "Memory Parity",
486 "IO Subsystem Parity"
487};
488
489static void do_sysbus_error(int fatal, u32 errors)
490{
491 int i;
492
493 for (i = 0; i < 10; i++) {
494 if (errors & (1 << i))
537fba28 495 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
e009356f 496 fatal_message[fatal], sysbus_message[i]);
806c35f5
AC		 497 }
498}
499
500static inline void sysbus_error(int fatal, u32 errors, int *error_found,
501 int handle_error)
502{
503 *error_found = 1;
504
505 if (handle_error)
506 do_sysbus_error(fatal, errors);
507}
508
e7ecd891 509static void e752x_check_hub_interface(struct e752x_error_info *info,
806c35f5
AC		 510 int *error_found, int handle_error)
511{
512 u8 stat8;
513
514 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
e7ecd891 515
806c35f5 516 stat8 = info->hi_ferr;
e7ecd891 517
806c35f5
AC		 518 if(stat8 & 0x7f) { /* Error, so process */
519 stat8 &= 0x7f;
e7ecd891 520
806c35f5
AC		 521 if(stat8 & 0x2b)
522 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 523
806c35f5
AC		 524 if(stat8 & 0x54)
525 hub_error(0, stat8 & 0x54, error_found, handle_error);
526 }
e7ecd891 527
806c35f5 528 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
e7ecd891 529
806c35f5 530 stat8 = info->hi_nerr;
e7ecd891 531
806c35f5
AC		 532 if(stat8 & 0x7f) { /* Error, so process */
533 stat8 &= 0x7f;
e7ecd891 534
806c35f5
AC		 535 if (stat8 & 0x2b)
536 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 537
806c35f5
AC		 538 if(stat8 & 0x54)
539 hub_error(0, stat8 & 0x54, error_found, handle_error);
540 }
541}
542
e7ecd891
DP		 543static void e752x_check_sysbus(struct e752x_error_info *info,
544 int *error_found, int handle_error)
806c35f5
AC		 545{
546 u32 stat32, error32;
547
548 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
549 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
550
551 if (stat32 == 0)
552 return; /* no errors */
553
554 error32 = (stat32 >> 16) & 0x3ff;
555 stat32 = stat32 & 0x3ff;
e7ecd891 556
806c35f5
AC		 557 if(stat32 & 0x083)
558 sysbus_error(1, stat32 & 0x083, error_found, handle_error);
e7ecd891 559
806c35f5
AC		 560 if(stat32 & 0x37c)
561 sysbus_error(0, stat32 & 0x37c, error_found, handle_error);
e7ecd891 562
806c35f5
AC		 563 if(error32 & 0x083)
564 sysbus_error(1, error32 & 0x083, error_found, handle_error);
e7ecd891 565
806c35f5
AC		 566 if(error32 & 0x37c)
567 sysbus_error(0, error32 & 0x37c, error_found, handle_error);
568}
569
e7ecd891
DP		 570static void e752x_check_membuf (struct e752x_error_info *info,
571 int *error_found, int handle_error)
806c35f5
AC		 572{
573 u8 stat8;
574
575 stat8 = info->buf_ferr;
e7ecd891 576
806c35f5
AC		 577 if (stat8 & 0x0f) { /* Error, so process */
578 stat8 &= 0x0f;
579 membuf_error(stat8, error_found, handle_error);
580 }
e7ecd891 581
806c35f5 582 stat8 = info->buf_nerr;
e7ecd891 583
806c35f5
AC		 584 if (stat8 & 0x0f) { /* Error, so process */
585 stat8 &= 0x0f;
586 membuf_error(stat8, error_found, handle_error);
587 }
588}
589
590static void e752x_check_dram (struct mem_ctl_info *mci,
e7ecd891
DP		 591 struct e752x_error_info *info, int *error_found,
592 int handle_error)
806c35f5
AC		 593{
594 u16 error_one, error_next;
595
596 error_one = info->dram_ferr;
597 error_next = info->dram_nerr;
598
599 /* decode and report errors */
600 if(error_one & 0x0101) /* check first error correctable */
601 process_ce(mci, error_one, info->dram_sec1_add,
602 info->dram_sec1_syndrome, error_found,
603 handle_error);
604
605 if(error_next & 0x0101) /* check next error correctable */
606 process_ce(mci, error_next, info->dram_sec2_add,
607 info->dram_sec2_syndrome, error_found,
608 handle_error);
609
610 if(error_one & 0x4040)
611 process_ue_no_info_wr(mci, error_found, handle_error);
612
613 if(error_next & 0x4040)
614 process_ue_no_info_wr(mci, error_found, handle_error);
615
616 if(error_one & 0x2020)
617 process_ded_retry(mci, error_one, info->dram_retr_add,
618 error_found, handle_error);
619
620 if(error_next & 0x2020)
621 process_ded_retry(mci, error_next, info->dram_retr_add,
622 error_found, handle_error);
623
624 if(error_one & 0x0808)
625 process_threshold_ce(mci, error_one, error_found,
626 handle_error);
627
628 if(error_next & 0x0808)
629 process_threshold_ce(mci, error_next, error_found,
630 handle_error);
631
632 if(error_one & 0x0606)
633 process_ue(mci, error_one, info->dram_ded_add,
634 info->dram_scrb_add, error_found, handle_error);
635
636 if(error_next & 0x0606)
637 process_ue(mci, error_next, info->dram_ded_add,
638 info->dram_scrb_add, error_found, handle_error);
639}
640
641static void e752x_get_error_info (struct mem_ctl_info *mci,
e7ecd891 642 struct e752x_error_info *info)
806c35f5
AC		 643{
644 struct pci_dev *dev;
645 struct e752x_pvt *pvt;
646
647 memset(info, 0, sizeof(*info));
648 pvt = (struct e752x_pvt *) mci->pvt_info;
649 dev = pvt->dev_d0f1;
806c35f5
AC		 650 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
651
652 if (info->ferr_global) {
653 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
654 pci_read_config_word(dev, E752X_SYSBUS_FERR,
655 &info->sysbus_ferr);
656 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
657 pci_read_config_word(dev, E752X_DRAM_FERR,
658 &info->dram_ferr);
659 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
660 &info->dram_sec1_add);
661 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
662 &info->dram_sec1_syndrome);
663 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
664 &info->dram_ded_add);
665 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
666 &info->dram_scrb_add);
667 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
668 &info->dram_retr_add);
669
670 if (info->hi_ferr & 0x7f)
671 pci_write_config_byte(dev, E752X_HI_FERR,
672 info->hi_ferr);
673
674 if (info->sysbus_ferr)
675 pci_write_config_word(dev, E752X_SYSBUS_FERR,
676 info->sysbus_ferr);
677
678 if (info->buf_ferr & 0x0f)
679 pci_write_config_byte(dev, E752X_BUF_FERR,
680 info->buf_ferr);
681
682 if (info->dram_ferr)
683 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
684 info->dram_ferr, info->dram_ferr);
685
686 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
687 info->ferr_global);
688 }
689
690 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
691
692 if (info->nerr_global) {
693 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
694 pci_read_config_word(dev, E752X_SYSBUS_NERR,
695 &info->sysbus_nerr);
696 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
697 pci_read_config_word(dev, E752X_DRAM_NERR,
698 &info->dram_nerr);
699 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
700 &info->dram_sec2_add);
701 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
702 &info->dram_sec2_syndrome);
703
704 if (info->hi_nerr & 0x7f)
705 pci_write_config_byte(dev, E752X_HI_NERR,
706 info->hi_nerr);
707
708 if (info->sysbus_nerr)
709 pci_write_config_word(dev, E752X_SYSBUS_NERR,
710 info->sysbus_nerr);
711
712 if (info->buf_nerr & 0x0f)
713 pci_write_config_byte(dev, E752X_BUF_NERR,
714 info->buf_nerr);
715
716 if (info->dram_nerr)
717 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
718 info->dram_nerr, info->dram_nerr);
719
720 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
721 info->nerr_global);
722 }
723}
724
725static int e752x_process_error_info (struct mem_ctl_info *mci,
726 struct e752x_error_info *info, int handle_errors)
727{
728 u32 error32, stat32;
729 int error_found;
730
731 error_found = 0;
732 error32 = (info->ferr_global >> 18) & 0x3ff;
733 stat32 = (info->ferr_global >> 4) & 0x7ff;
734
735 if (error32)
736 global_error(1, error32, &error_found, handle_errors);
737
738 if (stat32)
739 global_error(0, stat32, &error_found, handle_errors);
740
741 error32 = (info->nerr_global >> 18) & 0x3ff;
742 stat32 = (info->nerr_global >> 4) & 0x7ff;
743
744 if (error32)
745 global_error(1, error32, &error_found, handle_errors);
746
747 if (stat32)
748 global_error(0, stat32, &error_found, handle_errors);
749
750 e752x_check_hub_interface(info, &error_found, handle_errors);
751 e752x_check_sysbus(info, &error_found, handle_errors);
752 e752x_check_membuf(info, &error_found, handle_errors);
753 e752x_check_dram(mci, info, &error_found, handle_errors);
754 return error_found;
755}
756
757static void e752x_check(struct mem_ctl_info *mci)
758{
759 struct e752x_error_info info;
e7ecd891 760
537fba28 761 debugf3("%s()\n", __func__);
806c35f5
AC		 762 e752x_get_error_info(mci, &info);
763 e752x_process_error_info(mci, &info, 1);
764}
765
766static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
767{
768 int rc = -ENODEV;
769 int index;
3847bccc 770 u16 pci_data;
806c35f5
AC		 771 u8 stat8;
772 struct mem_ctl_info *mci = NULL;
773 struct e752x_pvt *pvt = NULL;
774 u16 ddrcsr;
775 u32 drc;
e7ecd891
DP		 776 int drc_chan; /* Number of channels 0=1chan,1=2chan */
777 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
778 int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
806c35f5
AC		 779 u32 dra;
780 unsigned long last_cumul_size;
806c35f5 781 struct pci_dev *dev = NULL;
749ede57 782 struct e752x_error_info discard;
806c35f5 783
537fba28 784 debugf0("%s(): mci\n", __func__);
806c35f5
AC		 785 debugf0("Starting Probe1\n");
786
96941026 787 /* check to see if device 0 function 1 is enabled; if it isn't, we
788 * assume the BIOS has reserved it for a reason and is expecting
789 * exclusive access, we take care not to violate that assumption and
790 * fail the probe. */
806c35f5 791 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
96941026 792 if (!force_function_unhide && !(stat8 & (1 << 5))) {
793 printk(KERN_INFO "Contact your BIOS vendor to see if the "
794 "E752x error registers can be safely un-hidden\n");
795 goto fail;
796 }
806c35f5
AC		 797 stat8 |= (1 << 5);
798 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
799
800 /* need to find out the number of channels */
801 pci_read_config_dword(pdev, E752X_DRC, &drc);
802 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
803 /* FIXME: should check >>12 or 0xf, true for all? */
804 /* Dual channel = 1, Single channel = 0 */
805 drc_chan = (((ddrcsr >> 12) & 3) == 3);
806 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
807 drc_ddim = (drc >> 20) & 0x3;
808
809 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
810
811 if (mci == NULL) {
812 rc = -ENOMEM;
813 goto fail;
814 }
815
537fba28 816 debugf3("%s(): init mci\n", __func__);
806c35f5
AC		 817 mci->mtype_cap = MEM_FLAG_RDDR;
818 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
819 EDAC_FLAG_S4ECD4ED;
820 /* FIXME - what if different memory types are in different csrows? */
680cbbbb 821 mci->mod_name = EDAC_MOD_STR;
806c35f5
AC		 822 mci->mod_ver = "$Revision: 1.5.2.11 $";
823 mci->pdev = pdev;
824
537fba28 825 debugf3("%s(): init pvt\n", __func__);
806c35f5
AC		 826 pvt = (struct e752x_pvt *) mci->pvt_info;
827 pvt->dev_info = &e752x_devs[dev_idx];
828 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
e7ecd891
DP		 829 pvt->dev_info->err_dev,
830 pvt->bridge_ck);
831
806c35f5
AC		 832 if (pvt->bridge_ck == NULL)
833 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
e7ecd891
DP		 834 PCI_DEVFN(0, 1));
835
806c35f5 836 if (pvt->bridge_ck == NULL) {
537fba28 837 e752x_printk(KERN_ERR, "error reporting device not found:"
e7ecd891
DP		 838 "vendor %x device 0x%x (broken BIOS?)\n",
839 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
806c35f5
AC		 840 goto fail;
841 }
806c35f5 842
e7ecd891 843 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
537fba28 844 debugf3("%s(): more mci init\n", __func__);
806c35f5
AC		 845 mci->ctl_name = pvt->dev_info->ctl_name;
846 mci->edac_check = e752x_check;
847 mci->ctl_page_to_phys = ctl_page_to_phys;
848
849 /* find out the device types */
850 pci_read_config_dword(pdev, E752X_DRA, &dra);
851
852 /*
853 * The dram row boundary (DRB) reg values are boundary address for
854 * each DRAM row with a granularity of 64 or 128MB (single/dual
855 * channel operation). DRB regs are cumulative; therefore DRB7 will
856 * contain the total memory contained in all eight rows.
857 */
858 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
859 u8 value;
860 u32 cumul_size;
e7ecd891 861
806c35f5
AC		 862 /* mem_dev 0=x8, 1=x4 */
863 int mem_dev = (dra >> (index * 4 + 2)) & 0x3;
864 struct csrow_info *csrow = &mci->csrows[index];
865
866 mem_dev = (mem_dev == 2);
867 pci_read_config_byte(mci->pdev, E752X_DRB + index, &value);
868 /* convert a 128 or 64 MiB DRB to a page size. */
869 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
537fba28
DP		 870 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
871 cumul_size);
e7ecd891 872
806c35f5 873 if (cumul_size == last_cumul_size)
e7ecd891 874 continue; /* not populated */
806c35f5
AC		 875
876 csrow->first_page = last_cumul_size;
877 csrow->last_page = cumul_size - 1;
878 csrow->nr_pages = cumul_size - last_cumul_size;
879 last_cumul_size = cumul_size;
e7ecd891
DP		 880 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
881 csrow->mtype = MEM_RDDR; /* only one type supported */
806c35f5
AC		 882 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
883
884 /*
885 * if single channel or x8 devices then SECDED
886 * if dual channel and x4 then S4ECD4ED
887 */
888 if (drc_ddim) {
889 if (drc_chan && mem_dev) {
890 csrow->edac_mode = EDAC_S4ECD4ED;
891 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
892 } else {
893 csrow->edac_mode = EDAC_SECDED;
894 mci->edac_cap |= EDAC_FLAG_SECDED;
895 }
896 } else
897 csrow->edac_mode = EDAC_NONE;
898 }
899
900 /* Fill in the memory map table */
901 {
902 u8 value;
903 u8 last = 0;
904 u8 row = 0;
806c35f5 905
e7ecd891 906 for (index = 0; index < 8; index += 2) {
806c35f5 907 pci_read_config_byte(mci->pdev, E752X_DRB + index,
e7ecd891
DP		 908 &value);
909
806c35f5
AC		 910 /* test if there is a dimm in this slot */
911 if (value == last) {
912 /* no dimm in the slot, so flag it as empty */
913 pvt->map[index] = 0xff;
914 pvt->map[index + 1] = 0xff;
e7ecd891 915 } else { /* there is a dimm in the slot */
806c35f5
AC		 916 pvt->map[index] = row;
917 row++;
918 last = value;
919 /* test the next value to see if the dimm is
920 double sided */
921 pci_read_config_byte(mci->pdev,
e7ecd891
DP		 922 E752X_DRB + index + 1,
923 &value);
806c35f5 924 pvt->map[index + 1] = (value == last) ?
e7ecd891
DP		 925 0xff : /* the dimm is single sided,
926 * so flag as empty
927 */
928 row; /* this is a double sided dimm
929 * to save the next row #
930 */
806c35f5
AC		 931 row++;
932 last = value;
933 }
934 }
935 }
936
937 /* set the map type. 1 = normal, 0 = reversed */
938 pci_read_config_byte(mci->pdev, E752X_DRM, &stat8);
939 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
940
941 mci->edac_cap |= EDAC_FLAG_NONE;
537fba28 942 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
e7ecd891 943
806c35f5
AC		 944 /* load the top of low memory, remap base, and remap limit vars */
945 pci_read_config_word(mci->pdev, E752X_TOLM, &pci_data);
946 pvt->tolm = ((u32) pci_data) << 4;
947 pci_read_config_word(mci->pdev, E752X_REMAPBASE, &pci_data);
948 pvt->remapbase = ((u32) pci_data) << 14;
949 pci_read_config_word(mci->pdev, E752X_REMAPLIMIT, &pci_data);
950 pvt->remaplimit = ((u32) pci_data) << 14;
537fba28 951 e752x_printk(KERN_INFO,
e7ecd891
DP		 952 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
953 pvt->remapbase, pvt->remaplimit);
806c35f5
AC		 954
955 if (edac_mc_add_mc(mci)) {
537fba28 956 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
806c35f5
AC		 957 goto fail;
958 }
959
3847bccc 960 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
e7ecd891 961 NULL);
806c35f5 962 pvt->dev_d0f0 = dev;
806c35f5
AC		 963 /* find the error reporting device and clear errors */
964 dev = pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
965 /* Turn off error disable & SMI in case the BIOS turned it on */
966 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
967 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
968 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
969 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
970 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
971 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
972 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
973 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
e7ecd891
DP		 974
975 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
806c35f5
AC		 976
977 /* get this far and it's successful */
537fba28 978 debugf3("%s(): success\n", __func__);
806c35f5
AC		 979 return 0;
980
981fail:
982 if (mci) {
983 if (pvt->dev_d0f0)
984 pci_dev_put(pvt->dev_d0f0);
e7ecd891 985
806c35f5
AC		 986 if (pvt->dev_d0f1)
987 pci_dev_put(pvt->dev_d0f1);
e7ecd891 988
806c35f5
AC		 989 if (pvt->bridge_ck)
990 pci_dev_put(pvt->bridge_ck);
e7ecd891 991
806c35f5
AC		 992 edac_mc_free(mci);
993 }
e7ecd891 994
806c35f5
AC		 995 return rc;
996}
997
998/* returns count (>= 0), or negative on error */
999static int __devinit e752x_init_one(struct pci_dev *pdev,
e7ecd891 1000 const struct pci_device_id *ent)
806c35f5 1001{
537fba28 1002 debugf0("%s()\n", __func__);
806c35f5
AC		 1003
1004 /* wake up and enable device */
1005 if(pci_enable_device(pdev) < 0)
1006 return -EIO;
e7ecd891 1007
806c35f5
AC		 1008 return e752x_probe1(pdev, ent->driver_data);
1009}
1010
806c35f5
AC		 1011static void __devexit e752x_remove_one(struct pci_dev *pdev)
1012{
1013 struct mem_ctl_info *mci;
1014 struct e752x_pvt *pvt;
1015
537fba28 1016 debugf0("%s()\n", __func__);
806c35f5 1017
18dbc337 1018 if ((mci = edac_mc_del_mc(pdev)) == NULL)
806c35f5
AC		 1019 return;
1020
1021 pvt = (struct e752x_pvt *) mci->pvt_info;
1022 pci_dev_put(pvt->dev_d0f0);
1023 pci_dev_put(pvt->dev_d0f1);
1024 pci_dev_put(pvt->bridge_ck);
1025 edac_mc_free(mci);
1026}
1027
806c35f5 1028static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
e7ecd891
DP		 1029 {
1030 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1031 E7520
1032 },
1033 {
1034 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1035 E7525
1036 },
1037 {
1038 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1039 E7320
1040 },
1041 {
1042 0,
1043 } /* 0 terminated list. */
806c35f5
AC		 1044};
1045
1046MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1047
806c35f5 1048static struct pci_driver e752x_driver = {
680cbbbb 1049 .name = EDAC_MOD_STR,
0d38b049
RD		 1050 .probe = e752x_init_one,
1051 .remove = __devexit_p(e752x_remove_one),
1052 .id_table = e752x_pci_tbl,
806c35f5
AC		 1053};
1054
da9bb1d2 1055static int __init e752x_init(void)
806c35f5
AC		 1056{
1057 int pci_rc;
1058
537fba28 1059 debugf3("%s()\n", __func__);
806c35f5
AC		 1060 pci_rc = pci_register_driver(&e752x_driver);
1061 return (pci_rc < 0) ? pci_rc : 0;
1062}
1063
806c35f5
AC		 1064static void __exit e752x_exit(void)
1065{
537fba28 1066 debugf3("%s()\n", __func__);
806c35f5
AC		 1067 pci_unregister_driver(&e752x_driver);
1068}
1069
806c35f5
AC		 1070module_init(e752x_init);
1071module_exit(e752x_exit);
1072
1073MODULE_LICENSE("GPL");
1074MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1075MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
96941026 1076
1077module_param(force_function_unhide, int, 0444);
1078MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1079" 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");
1080
kernel source for telekom puls (alcatel/mediatek)