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[PATCH] EDAC: e752x byte access fix
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / e752x_edac.c
CommitLineData
806c35f5
AC		 1/*
2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e752x_chips" below for supported chipsets
8 *
9 * Written by Tom Zimmerman
10 *
11 * Contributors:
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
15 *
da9bb1d2 16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
806c35f5
AC		 17 *
18 */
19
806c35f5
AC		 20#include <linux/module.h>
21#include <linux/init.h>
806c35f5
AC		 22#include <linux/pci.h>
23#include <linux/pci_ids.h>
806c35f5 24#include <linux/slab.h>
806c35f5
AC		 25#include "edac_mc.h"
26
929a40ec
DT		 27#define E752X_REVISION " Ver: 2.0.1 " __DATE__
28#define EDAC_MOD_STR "e752x_edac"
37f04581 29
96941026 30static int force_function_unhide;
31
537fba28 32#define e752x_printk(level, fmt, arg...) \
e7ecd891 33 edac_printk(level, "e752x", fmt, ##arg)
537fba28
DP		 34
35#define e752x_mc_printk(mci, level, fmt, arg...) \
e7ecd891 36 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
537fba28 37
806c35f5
AC		 38#ifndef PCI_DEVICE_ID_INTEL_7520_0
39#define PCI_DEVICE_ID_INTEL_7520_0 0x3590
40#endif /* PCI_DEVICE_ID_INTEL_7520_0 */
41
42#ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
43#define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
44#endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
45
46#ifndef PCI_DEVICE_ID_INTEL_7525_0
47#define PCI_DEVICE_ID_INTEL_7525_0 0x359E
48#endif /* PCI_DEVICE_ID_INTEL_7525_0 */
49
50#ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
51#define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
52#endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
53
54#ifndef PCI_DEVICE_ID_INTEL_7320_0
55#define PCI_DEVICE_ID_INTEL_7320_0 0x3592
56#endif /* PCI_DEVICE_ID_INTEL_7320_0 */
57
58#ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
59#define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
60#endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
61
62#define E752X_NR_CSROWS 8 /* number of csrows */
63
806c35f5
AC		 64/* E752X register addresses - device 0 function 0 */
65#define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
66#define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
67 /*
68 * 31:30 Device width row 7
69 * 01=x8 10=x4 11=x8 DDR2
70 * 27:26 Device width row 6
71 * 23:22 Device width row 5
72 * 19:20 Device width row 4
73 * 15:14 Device width row 3
74 * 11:10 Device width row 2
75 * 7:6 Device width row 1
76 * 3:2 Device width row 0
77 */
78#define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
79 /* FIXME:IS THIS RIGHT? */
80 /*
81 * 22 Number channels 0=1,1=2
82 * 19:18 DRB Granularity 32/64MB
83 */
84#define E752X_DRM 0x80 /* Dimm mapping register */
85#define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
86 /*
87 * 14:12 1 single A, 2 single B, 3 dual
88 */
89#define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
90#define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
91#define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
92#define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
93
94/* E752X register addresses - device 0 function 1 */
95#define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
96#define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
97#define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
98#define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
99#define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
100#define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
101#define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
102#define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
103#define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
104#define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
105#define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
106#define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
107#define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
108#define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
109#define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
110#define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
111#define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
112#define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
113#define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
114#define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
115 /* error address register (32b) */
116 /*
117 * 31 Reserved
118 * 30:2 CE address (64 byte block 34:6)
119 * 1 Reserved
120 * 0 HiLoCS
121 */
122#define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
123 /* error address register (32b) */
124 /*
125 * 31 Reserved
126 * 30:2 CE address (64 byte block 34:6)
127 * 1 Reserved
128 * 0 HiLoCS
129 */
130#define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
131 /* error address register (32b) */
132 /*
133 * 31 Reserved
134 * 30:2 CE address (64 byte block 34:6)
135 * 1 Reserved
136 * 0 HiLoCS
137 */
138#define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
139 /* error address register (32b) */
140 /*
141 * 31 Reserved
142 * 30:2 CE address (64 byte block 34:6)
143 * 1 Reserved
144 * 0 HiLoCS
145 */
146#define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
147 /* error syndrome register (16b) */
148#define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
149 /* error syndrome register (16b) */
150#define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
151
152/* ICH5R register addresses - device 30 function 0 */
153#define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
154#define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
155#define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
156
157enum e752x_chips {
158 E7520 = 0,
159 E7525 = 1,
160 E7320 = 2
161};
162
806c35f5
AC		 163struct e752x_pvt {
164 struct pci_dev *bridge_ck;
165 struct pci_dev *dev_d0f0;
166 struct pci_dev *dev_d0f1;
167 u32 tolm;
168 u32 remapbase;
169 u32 remaplimit;
170 int mc_symmetric;
171 u8 map[8];
172 int map_type;
173 const struct e752x_dev_info *dev_info;
174};
175
806c35f5
AC		 176struct e752x_dev_info {
177 u16 err_dev;
3847bccc 178 u16 ctl_dev;
806c35f5
AC		 179 const char *ctl_name;
180};
181
182struct e752x_error_info {
183 u32 ferr_global;
184 u32 nerr_global;
185 u8 hi_ferr;
186 u8 hi_nerr;
187 u16 sysbus_ferr;
188 u16 sysbus_nerr;
189 u8 buf_ferr;
190 u8 buf_nerr;
191 u16 dram_ferr;
192 u16 dram_nerr;
193 u32 dram_sec1_add;
194 u32 dram_sec2_add;
195 u16 dram_sec1_syndrome;
196 u16 dram_sec2_syndrome;
197 u32 dram_ded_add;
198 u32 dram_scrb_add;
199 u32 dram_retr_add;
200};
201
202static const struct e752x_dev_info e752x_devs[] = {
203 [E7520] = {
e7ecd891
DP		 204 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
205 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
206 .ctl_name = "E7520"
207 },
806c35f5 208 [E7525] = {
e7ecd891
DP		 209 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
210 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
211 .ctl_name = "E7525"
212 },
806c35f5 213 [E7320] = {
e7ecd891
DP		 214 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
215 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
216 .ctl_name = "E7320"
217 },
806c35f5
AC		 218};
219
806c35f5 220static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
e7ecd891 221 unsigned long page)
806c35f5
AC		 222{
223 u32 remap;
224 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
225
537fba28 226 debugf3("%s()\n", __func__);
806c35f5
AC		 227
228 if (page < pvt->tolm)
229 return page;
e7ecd891 230
806c35f5
AC		 231 if ((page >= 0x100000) && (page < pvt->remapbase))
232 return page;
e7ecd891 233
806c35f5 234 remap = (page - pvt->tolm) + pvt->remapbase;
e7ecd891 235
806c35f5
AC		 236 if (remap < pvt->remaplimit)
237 return remap;
e7ecd891 238
537fba28 239 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
806c35f5
AC		 240 return pvt->tolm - 1;
241}
242
243static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
e7ecd891 244 u32 sec1_add, u16 sec1_syndrome)
806c35f5
AC		 245{
246 u32 page;
247 int row;
248 int channel;
249 int i;
250 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
251
537fba28 252 debugf3("%s()\n", __func__);
806c35f5
AC		 253
254 /* convert the addr to 4k page */
255 page = sec1_add >> (PAGE_SHIFT - 4);
256
257 /* FIXME - check for -1 */
258 if (pvt->mc_symmetric) {
259 /* chip select are bits 14 & 13 */
260 row = ((page >> 1) & 3);
537fba28 261 e752x_printk(KERN_WARNING,
e7ecd891
DP		 262 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
263 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
264 pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]);
806c35f5
AC		 265
266 /* test for channel remapping */
267 for (i = 0; i < 8; i++) {
268 if (pvt->map[i] == row)
269 break;
270 }
e7ecd891 271
537fba28 272 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
e7ecd891 273
806c35f5
AC		 274 if (i < 8)
275 row = i;
276 else
537fba28 277 e752x_mc_printk(mci, KERN_WARNING,
e7ecd891 278 "row %d not found in remap table\n", row);
806c35f5
AC		 279 } else
280 row = edac_mc_find_csrow_by_page(mci, page);
e7ecd891 281
806c35f5
AC		 282 /* 0 = channel A, 1 = channel B */
283 channel = !(error_one & 1);
284
285 if (!pvt->map_type)
286 row = 7 - row;
e7ecd891 287
806c35f5 288 edac_mc_handle_ce(mci, page, 0, sec1_syndrome, row, channel,
e7ecd891 289 "e752x CE");
806c35f5
AC		 290}
291
806c35f5
AC		 292static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
293 u32 sec1_add, u16 sec1_syndrome, int *error_found,
294 int handle_error)
295{
296 *error_found = 1;
297
298 if (handle_error)
299 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
300}
301
e7ecd891
DP		 302static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
303 u32 ded_add, u32 scrb_add)
806c35f5
AC		 304{
305 u32 error_2b, block_page;
306 int row;
307 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
308
537fba28 309 debugf3("%s()\n", __func__);
806c35f5
AC		 310
311 if (error_one & 0x0202) {
312 error_2b = ded_add;
e7ecd891 313
806c35f5
AC		 314 /* convert to 4k address */
315 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 316
806c35f5 317 row = pvt->mc_symmetric ?
e7ecd891
DP		 318 /* chip select are bits 14 & 13 */
319 ((block_page >> 1) & 3) :
320 edac_mc_find_csrow_by_page(mci, block_page);
321
806c35f5 322 edac_mc_handle_ue(mci, block_page, 0, row,
e7ecd891 323 "e752x UE from Read");
806c35f5
AC		 324 }
325 if (error_one & 0x0404) {
326 error_2b = scrb_add;
e7ecd891 327
806c35f5
AC		 328 /* convert to 4k address */
329 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 330
806c35f5 331 row = pvt->mc_symmetric ?
e7ecd891
DP		 332 /* chip select are bits 14 & 13 */
333 ((block_page >> 1) & 3) :
334 edac_mc_find_csrow_by_page(mci, block_page);
335
806c35f5 336 edac_mc_handle_ue(mci, block_page, 0, row,
e7ecd891 337 "e752x UE from Scruber");
806c35f5
AC		 338 }
339}
340
341static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
342 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
343{
344 *error_found = 1;
345
346 if (handle_error)
347 do_process_ue(mci, error_one, ded_add, scrb_add);
348}
349
350static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
351 int *error_found, int handle_error)
352{
353 *error_found = 1;
354
355 if (!handle_error)
356 return;
357
537fba28 358 debugf3("%s()\n", __func__);
806c35f5
AC		 359 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
360}
361
362static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
363 u32 retry_add)
364{
365 u32 error_1b, page;
366 int row;
367 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
368
369 error_1b = retry_add;
e7ecd891 370 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
806c35f5 371 row = pvt->mc_symmetric ?
e7ecd891
DP		 372 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
373 edac_mc_find_csrow_by_page(mci, page);
537fba28 374 e752x_mc_printk(mci, KERN_WARNING,
e7ecd891
DP		 375 "CE page 0x%lx, row %d : Memory read retry\n",
376 (long unsigned int) page, row);
806c35f5
AC		 377}
378
379static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
380 u32 retry_add, int *error_found, int handle_error)
381{
382 *error_found = 1;
383
384 if (handle_error)
385 do_process_ded_retry(mci, error, retry_add);
386}
387
388static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
389 int *error_found, int handle_error)
390{
391 *error_found = 1;
392
393 if (handle_error)
537fba28 394 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
806c35f5
AC		 395}
396
da9bb1d2 397static char *global_message[11] = {
806c35f5
AC		 398 "PCI Express C1", "PCI Express C", "PCI Express B1",
399 "PCI Express B", "PCI Express A1", "PCI Express A",
400 "DMA Controler", "HUB Interface", "System Bus",
401 "DRAM Controler", "Internal Buffer"
402};
403
da9bb1d2 404static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
806c35f5
AC		 405
406static void do_global_error(int fatal, u32 errors)
407{
408 int i;
409
410 for (i = 0; i < 11; i++) {
411 if (errors & (1 << i))
537fba28 412 e752x_printk(KERN_WARNING, "%sError %s\n",
e7ecd891 413 fatal_message[fatal], global_message[i]);
806c35f5
AC		 414 }
415}
416
417static inline void global_error(int fatal, u32 errors, int *error_found,
418 int handle_error)
419{
420 *error_found = 1;
421
422 if (handle_error)
423 do_global_error(fatal, errors);
424}
425
da9bb1d2 426static char *hub_message[7] = {
806c35f5
AC		 427 "HI Address or Command Parity", "HI Illegal Access",
428 "HI Internal Parity", "Out of Range Access",
429 "HI Data Parity", "Enhanced Config Access",
430 "Hub Interface Target Abort"
431};
432
433static void do_hub_error(int fatal, u8 errors)
434{
435 int i;
436
437 for (i = 0; i < 7; i++) {
438 if (errors & (1 << i))
537fba28 439 e752x_printk(KERN_WARNING, "%sError %s\n",
e7ecd891 440 fatal_message[fatal], hub_message[i]);
806c35f5
AC		 441 }
442}
443
444static inline void hub_error(int fatal, u8 errors, int *error_found,
445 int handle_error)
446{
447 *error_found = 1;
448
449 if (handle_error)
450 do_hub_error(fatal, errors);
451}
452
da9bb1d2 453static char *membuf_message[4] = {
806c35f5
AC		 454 "Internal PMWB to DRAM parity",
455 "Internal PMWB to System Bus Parity",
456 "Internal System Bus or IO to PMWB Parity",
457 "Internal DRAM to PMWB Parity"
458};
459
460static void do_membuf_error(u8 errors)
461{
462 int i;
463
464 for (i = 0; i < 4; i++) {
465 if (errors & (1 << i))
537fba28 466 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
e7ecd891 467 membuf_message[i]);
806c35f5
AC		 468 }
469}
470
471static inline void membuf_error(u8 errors, int *error_found, int handle_error)
472{
473 *error_found = 1;
474
475 if (handle_error)
476 do_membuf_error(errors);
477}
478
e009356f 479static char *sysbus_message[10] = {
806c35f5
AC		 480 "Addr or Request Parity",
481 "Data Strobe Glitch",
482 "Addr Strobe Glitch",
483 "Data Parity",
484 "Addr Above TOM",
485 "Non DRAM Lock Error",
486 "MCERR", "BINIT",
487 "Memory Parity",
488 "IO Subsystem Parity"
489};
490
491static void do_sysbus_error(int fatal, u32 errors)
492{
493 int i;
494
495 for (i = 0; i < 10; i++) {
496 if (errors & (1 << i))
537fba28 497 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
e009356f 498 fatal_message[fatal], sysbus_message[i]);
806c35f5
AC		 499 }
500}
501
502static inline void sysbus_error(int fatal, u32 errors, int *error_found,
503 int handle_error)
504{
505 *error_found = 1;
506
507 if (handle_error)
508 do_sysbus_error(fatal, errors);
509}
510
e7ecd891 511static void e752x_check_hub_interface(struct e752x_error_info *info,
806c35f5
AC		 512 int *error_found, int handle_error)
513{
514 u8 stat8;
515
516 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
e7ecd891 517
806c35f5 518 stat8 = info->hi_ferr;
e7ecd891 519
806c35f5
AC		 520 if(stat8 & 0x7f) { /* Error, so process */
521 stat8 &= 0x7f;
e7ecd891 522
806c35f5
AC		 523 if(stat8 & 0x2b)
524 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 525
806c35f5
AC		 526 if(stat8 & 0x54)
527 hub_error(0, stat8 & 0x54, error_found, handle_error);
528 }
e7ecd891 529
806c35f5 530 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
e7ecd891 531
806c35f5 532 stat8 = info->hi_nerr;
e7ecd891 533
806c35f5
AC		 534 if(stat8 & 0x7f) { /* Error, so process */
535 stat8 &= 0x7f;
e7ecd891 536
806c35f5
AC		 537 if (stat8 & 0x2b)
538 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 539
806c35f5
AC		 540 if(stat8 & 0x54)
541 hub_error(0, stat8 & 0x54, error_found, handle_error);
542 }
543}
544
e7ecd891
DP		 545static void e752x_check_sysbus(struct e752x_error_info *info,
546 int *error_found, int handle_error)
806c35f5
AC		 547{
548 u32 stat32, error32;
549
550 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
551 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
552
553 if (stat32 == 0)
554 return; /* no errors */
555
556 error32 = (stat32 >> 16) & 0x3ff;
557 stat32 = stat32 & 0x3ff;
e7ecd891 558
dfb2a763
BP		 559 if(stat32 & 0x087)
560 sysbus_error(1, stat32 & 0x087, error_found, handle_error);
e7ecd891 561
dfb2a763
BP		 562 if(stat32 & 0x378)
563 sysbus_error(0, stat32 & 0x378, error_found, handle_error);
e7ecd891 564
dfb2a763
BP		 565 if(error32 & 0x087)
566 sysbus_error(1, error32 & 0x087, error_found, handle_error);
e7ecd891 567
dfb2a763
BP		 568 if(error32 & 0x378)
569 sysbus_error(0, error32 & 0x378, error_found, handle_error);
806c35f5
AC		 570}
571
e7ecd891
DP		 572static void e752x_check_membuf (struct e752x_error_info *info,
573 int *error_found, int handle_error)
806c35f5
AC		 574{
575 u8 stat8;
576
577 stat8 = info->buf_ferr;
e7ecd891 578
806c35f5
AC		 579 if (stat8 & 0x0f) { /* Error, so process */
580 stat8 &= 0x0f;
581 membuf_error(stat8, error_found, handle_error);
582 }
e7ecd891 583
806c35f5 584 stat8 = info->buf_nerr;
e7ecd891 585
806c35f5
AC		 586 if (stat8 & 0x0f) { /* Error, so process */
587 stat8 &= 0x0f;
588 membuf_error(stat8, error_found, handle_error);
589 }
590}
591
592static void e752x_check_dram (struct mem_ctl_info *mci,
e7ecd891
DP		 593 struct e752x_error_info *info, int *error_found,
594 int handle_error)
806c35f5
AC		 595{
596 u16 error_one, error_next;
597
598 error_one = info->dram_ferr;
599 error_next = info->dram_nerr;
600
601 /* decode and report errors */
602 if(error_one & 0x0101) /* check first error correctable */
603 process_ce(mci, error_one, info->dram_sec1_add,
604 info->dram_sec1_syndrome, error_found,
605 handle_error);
606
607 if(error_next & 0x0101) /* check next error correctable */
608 process_ce(mci, error_next, info->dram_sec2_add,
609 info->dram_sec2_syndrome, error_found,
610 handle_error);
611
612 if(error_one & 0x4040)
613 process_ue_no_info_wr(mci, error_found, handle_error);
614
615 if(error_next & 0x4040)
616 process_ue_no_info_wr(mci, error_found, handle_error);
617
618 if(error_one & 0x2020)
619 process_ded_retry(mci, error_one, info->dram_retr_add,
620 error_found, handle_error);
621
622 if(error_next & 0x2020)
623 process_ded_retry(mci, error_next, info->dram_retr_add,
624 error_found, handle_error);
625
626 if(error_one & 0x0808)
627 process_threshold_ce(mci, error_one, error_found,
628 handle_error);
629
630 if(error_next & 0x0808)
631 process_threshold_ce(mci, error_next, error_found,
632 handle_error);
633
634 if(error_one & 0x0606)
635 process_ue(mci, error_one, info->dram_ded_add,
636 info->dram_scrb_add, error_found, handle_error);
637
638 if(error_next & 0x0606)
639 process_ue(mci, error_next, info->dram_ded_add,
640 info->dram_scrb_add, error_found, handle_error);
641}
642
643static void e752x_get_error_info (struct mem_ctl_info *mci,
e7ecd891 644 struct e752x_error_info *info)
806c35f5
AC		 645{
646 struct pci_dev *dev;
647 struct e752x_pvt *pvt;
648
649 memset(info, 0, sizeof(*info));
650 pvt = (struct e752x_pvt *) mci->pvt_info;
651 dev = pvt->dev_d0f1;
806c35f5
AC		 652 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
653
654 if (info->ferr_global) {
655 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
656 pci_read_config_word(dev, E752X_SYSBUS_FERR,
657 &info->sysbus_ferr);
658 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
659 pci_read_config_word(dev, E752X_DRAM_FERR,
660 &info->dram_ferr);
661 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
662 &info->dram_sec1_add);
663 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
664 &info->dram_sec1_syndrome);
665 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
666 &info->dram_ded_add);
667 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
668 &info->dram_scrb_add);
669 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
670 &info->dram_retr_add);
671
672 if (info->hi_ferr & 0x7f)
673 pci_write_config_byte(dev, E752X_HI_FERR,
674 info->hi_ferr);
675
676 if (info->sysbus_ferr)
677 pci_write_config_word(dev, E752X_SYSBUS_FERR,
678 info->sysbus_ferr);
679
680 if (info->buf_ferr & 0x0f)
681 pci_write_config_byte(dev, E752X_BUF_FERR,
682 info->buf_ferr);
683
684 if (info->dram_ferr)
685 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
686 info->dram_ferr, info->dram_ferr);
687
688 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
689 info->ferr_global);
690 }
691
692 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
693
694 if (info->nerr_global) {
695 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
696 pci_read_config_word(dev, E752X_SYSBUS_NERR,
697 &info->sysbus_nerr);
698 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
699 pci_read_config_word(dev, E752X_DRAM_NERR,
700 &info->dram_nerr);
701 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
702 &info->dram_sec2_add);
703 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
704 &info->dram_sec2_syndrome);
705
706 if (info->hi_nerr & 0x7f)
707 pci_write_config_byte(dev, E752X_HI_NERR,
708 info->hi_nerr);
709
710 if (info->sysbus_nerr)
711 pci_write_config_word(dev, E752X_SYSBUS_NERR,
712 info->sysbus_nerr);
713
714 if (info->buf_nerr & 0x0f)
715 pci_write_config_byte(dev, E752X_BUF_NERR,
716 info->buf_nerr);
717
718 if (info->dram_nerr)
719 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
720 info->dram_nerr, info->dram_nerr);
721
722 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
723 info->nerr_global);
724 }
725}
726
727static int e752x_process_error_info (struct mem_ctl_info *mci,
728 struct e752x_error_info *info, int handle_errors)
729{
730 u32 error32, stat32;
731 int error_found;
732
733 error_found = 0;
734 error32 = (info->ferr_global >> 18) & 0x3ff;
735 stat32 = (info->ferr_global >> 4) & 0x7ff;
736
737 if (error32)
738 global_error(1, error32, &error_found, handle_errors);
739
740 if (stat32)
741 global_error(0, stat32, &error_found, handle_errors);
742
743 error32 = (info->nerr_global >> 18) & 0x3ff;
744 stat32 = (info->nerr_global >> 4) & 0x7ff;
745
746 if (error32)
747 global_error(1, error32, &error_found, handle_errors);
748
749 if (stat32)
750 global_error(0, stat32, &error_found, handle_errors);
751
752 e752x_check_hub_interface(info, &error_found, handle_errors);
753 e752x_check_sysbus(info, &error_found, handle_errors);
754 e752x_check_membuf(info, &error_found, handle_errors);
755 e752x_check_dram(mci, info, &error_found, handle_errors);
756 return error_found;
757}
758
759static void e752x_check(struct mem_ctl_info *mci)
760{
761 struct e752x_error_info info;
e7ecd891 762
537fba28 763 debugf3("%s()\n", __func__);
806c35f5
AC		 764 e752x_get_error_info(mci, &info);
765 e752x_process_error_info(mci, &info, 1);
766}
767
13189525
DT		 768/* Return 1 if dual channel mode is active. Else return 0. */
769static inline int dual_channel_active(u16 ddrcsr)
770{
771 return (((ddrcsr >> 12) & 3) == 3);
772}
773
774static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
775 u16 ddrcsr)
776{
777 struct csrow_info *csrow;
778 unsigned long last_cumul_size;
779 int index, mem_dev, drc_chan;
780 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
781 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
782 u8 value;
783 u32 dra, drc, cumul_size;
784
9962fd01
BP		 785 dra = 0;
786 for (index=0; index < 4; index++) {
787 u8 dra_reg;
788 pci_read_config_byte(pdev, E752X_DRA+index, &dra_reg);
789 dra |= dra_reg << (index * 8);
790 }
13189525
DT		 791 pci_read_config_dword(pdev, E752X_DRC, &drc);
792 drc_chan = dual_channel_active(ddrcsr);
793 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
794 drc_ddim = (drc >> 20) & 0x3;
795
796 /* The dram row boundary (DRB) reg values are boundary address for
797 * each DRAM row with a granularity of 64 or 128MB (single/dual
798 * channel operation). DRB regs are cumulative; therefore DRB7 will
799 * contain the total memory contained in all eight rows.
800 */
801 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
802 /* mem_dev 0=x8, 1=x4 */
803 mem_dev = (dra >> (index * 4 + 2)) & 0x3;
804 csrow = &mci->csrows[index];
805
806 mem_dev = (mem_dev == 2);
807 pci_read_config_byte(pdev, E752X_DRB + index, &value);
808 /* convert a 128 or 64 MiB DRB to a page size. */
809 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
810 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
811 cumul_size);
812 if (cumul_size == last_cumul_size)
813 continue; /* not populated */
814
815 csrow->first_page = last_cumul_size;
816 csrow->last_page = cumul_size - 1;
817 csrow->nr_pages = cumul_size - last_cumul_size;
818 last_cumul_size = cumul_size;
819 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
820 csrow->mtype = MEM_RDDR; /* only one type supported */
821 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
822
823 /*
824 * if single channel or x8 devices then SECDED
825 * if dual channel and x4 then S4ECD4ED
826 */
827 if (drc_ddim) {
828 if (drc_chan && mem_dev) {
829 csrow->edac_mode = EDAC_S4ECD4ED;
830 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
831 } else {
832 csrow->edac_mode = EDAC_SECDED;
833 mci->edac_cap |= EDAC_FLAG_SECDED;
834 }
835 } else
836 csrow->edac_mode = EDAC_NONE;
837 }
838}
839
840static void e752x_init_mem_map_table(struct pci_dev *pdev,
841 struct e752x_pvt *pvt)
806c35f5 842{
806c35f5 843 int index;
13189525
DT		 844 u8 value, last, row, stat8;
845
846 last = 0;
847 row = 0;
848
849 for (index = 0; index < 8; index += 2) {
850 pci_read_config_byte(pdev, E752X_DRB + index, &value);
851 /* test if there is a dimm in this slot */
852 if (value == last) {
853 /* no dimm in the slot, so flag it as empty */
854 pvt->map[index] = 0xff;
855 pvt->map[index + 1] = 0xff;
856 } else { /* there is a dimm in the slot */
857 pvt->map[index] = row;
858 row++;
859 last = value;
860 /* test the next value to see if the dimm is double
861 * sided
862 */
863 pci_read_config_byte(pdev, E752X_DRB + index + 1,
864 &value);
865 pvt->map[index + 1] = (value == last) ?
866 0xff : /* the dimm is single sided,
867 so flag as empty */
868 row; /* this is a double sided dimm
869 to save the next row # */
870 row++;
871 last = value;
872 }
873 }
874
875 /* set the map type. 1 = normal, 0 = reversed */
876 pci_read_config_byte(pdev, E752X_DRM, &stat8);
877 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
878}
879
880/* Return 0 on success or 1 on failure. */
881static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
882 struct e752x_pvt *pvt)
883{
884 struct pci_dev *dev;
885
886 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
887 pvt->dev_info->err_dev,
888 pvt->bridge_ck);
889
890 if (pvt->bridge_ck == NULL)
891 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
892 PCI_DEVFN(0, 1));
893
894 if (pvt->bridge_ck == NULL) {
895 e752x_printk(KERN_ERR, "error reporting device not found:"
896 "vendor %x device 0x%x (broken BIOS?)\n",
897 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
898 return 1;
899 }
900
901 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
902 NULL);
903
904 if (dev == NULL)
905 goto fail;
906
907 pvt->dev_d0f0 = dev;
908 pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
909
910 return 0;
911
912fail:
913 pci_dev_put(pvt->bridge_ck);
914 return 1;
915}
916
917static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
918{
919 struct pci_dev *dev;
920
921 dev = pvt->dev_d0f1;
922 /* Turn off error disable & SMI in case the BIOS turned it on */
923 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
924 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
925 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
926 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
927 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
928 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
929 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
930 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
931}
932
933static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
934{
3847bccc 935 u16 pci_data;
806c35f5 936 u8 stat8;
13189525
DT		 937 struct mem_ctl_info *mci;
938 struct e752x_pvt *pvt;
806c35f5 939 u16 ddrcsr;
e7ecd891 940 int drc_chan; /* Number of channels 0=1chan,1=2chan */
749ede57 941 struct e752x_error_info discard;
806c35f5 942
537fba28 943 debugf0("%s(): mci\n", __func__);
806c35f5
AC		 944 debugf0("Starting Probe1\n");
945
96941026 946 /* check to see if device 0 function 1 is enabled; if it isn't, we
947 * assume the BIOS has reserved it for a reason and is expecting
948 * exclusive access, we take care not to violate that assumption and
949 * fail the probe. */
806c35f5 950 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
96941026 951 if (!force_function_unhide && !(stat8 & (1 << 5))) {
952 printk(KERN_INFO "Contact your BIOS vendor to see if the "
953 "E752x error registers can be safely un-hidden\n");
13189525 954 return -ENOMEM;
96941026 955 }
806c35f5
AC		 956 stat8 |= (1 << 5);
957 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
958
806c35f5
AC		 959 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
960 /* FIXME: should check >>12 or 0xf, true for all? */
961 /* Dual channel = 1, Single channel = 0 */
13189525 962 drc_chan = dual_channel_active(ddrcsr);
806c35f5
AC		 963
964 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
965
966 if (mci == NULL) {
13189525 967 return -ENOMEM;
806c35f5
AC		 968 }
969
537fba28 970 debugf3("%s(): init mci\n", __func__);
806c35f5
AC		 971 mci->mtype_cap = MEM_FLAG_RDDR;
972 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
973 EDAC_FLAG_S4ECD4ED;
974 /* FIXME - what if different memory types are in different csrows? */
680cbbbb 975 mci->mod_name = EDAC_MOD_STR;
37f04581
DT		 976 mci->mod_ver = E752X_REVISION;
977 mci->dev = &pdev->dev;
806c35f5 978
537fba28 979 debugf3("%s(): init pvt\n", __func__);
806c35f5
AC		 980 pvt = (struct e752x_pvt *) mci->pvt_info;
981 pvt->dev_info = &e752x_devs[dev_idx];
13189525 982 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
e7ecd891 983
13189525
DT		 984 if (e752x_get_devs(pdev, dev_idx, pvt)) {
985 edac_mc_free(mci);
986 return -ENODEV;
806c35f5 987 }
806c35f5 988
537fba28 989 debugf3("%s(): more mci init\n", __func__);
806c35f5
AC		 990 mci->ctl_name = pvt->dev_info->ctl_name;
991 mci->edac_check = e752x_check;
992 mci->ctl_page_to_phys = ctl_page_to_phys;
993
13189525
DT		 994 e752x_init_csrows(mci, pdev, ddrcsr);
995 e752x_init_mem_map_table(pdev, pvt);
806c35f5
AC		 996
997 /* set the map type. 1 = normal, 0 = reversed */
37f04581 998 pci_read_config_byte(pdev, E752X_DRM, &stat8);
806c35f5
AC		 999 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
1000
1001 mci->edac_cap |= EDAC_FLAG_NONE;
537fba28 1002 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
e7ecd891 1003
806c35f5 1004 /* load the top of low memory, remap base, and remap limit vars */
37f04581 1005 pci_read_config_word(pdev, E752X_TOLM, &pci_data);
806c35f5 1006 pvt->tolm = ((u32) pci_data) << 4;
37f04581 1007 pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
806c35f5 1008 pvt->remapbase = ((u32) pci_data) << 14;
37f04581 1009 pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
806c35f5 1010 pvt->remaplimit = ((u32) pci_data) << 14;
537fba28 1011 e752x_printk(KERN_INFO,
e7ecd891
DP		 1012 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
1013 pvt->remapbase, pvt->remaplimit);
806c35f5 1014
2d7bbb91
DT		 1015 /* Here we assume that we will never see multiple instances of this
1016 * type of memory controller. The ID is therefore hardcoded to 0.
1017 */
1018 if (edac_mc_add_mc(mci,0)) {
537fba28 1019 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
806c35f5
AC		 1020 goto fail;
1021 }
1022
13189525 1023 e752x_init_error_reporting_regs(pvt);
e7ecd891 1024 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
806c35f5
AC		 1025
1026 /* get this far and it's successful */
537fba28 1027 debugf3("%s(): success\n", __func__);
806c35f5
AC		 1028 return 0;
1029
1030fail:
13189525
DT		 1031 pci_dev_put(pvt->dev_d0f0);
1032 pci_dev_put(pvt->dev_d0f1);
1033 pci_dev_put(pvt->bridge_ck);
1034 edac_mc_free(mci);
e7ecd891 1035
13189525 1036 return -ENODEV;
806c35f5
AC		 1037}
1038
1039/* returns count (>= 0), or negative on error */
1040static int __devinit e752x_init_one(struct pci_dev *pdev,
e7ecd891 1041 const struct pci_device_id *ent)
806c35f5 1042{
537fba28 1043 debugf0("%s()\n", __func__);
806c35f5
AC		 1044
1045 /* wake up and enable device */
1046 if(pci_enable_device(pdev) < 0)
1047 return -EIO;
e7ecd891 1048
806c35f5
AC		 1049 return e752x_probe1(pdev, ent->driver_data);
1050}
1051
806c35f5
AC		 1052static void __devexit e752x_remove_one(struct pci_dev *pdev)
1053{
1054 struct mem_ctl_info *mci;
1055 struct e752x_pvt *pvt;
1056
537fba28 1057 debugf0("%s()\n", __func__);
806c35f5 1058
37f04581 1059 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
806c35f5
AC		 1060 return;
1061
1062 pvt = (struct e752x_pvt *) mci->pvt_info;
1063 pci_dev_put(pvt->dev_d0f0);
1064 pci_dev_put(pvt->dev_d0f1);
1065 pci_dev_put(pvt->bridge_ck);
1066 edac_mc_free(mci);
1067}
1068
806c35f5 1069static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
e7ecd891
DP		 1070 {
1071 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1072 E7520
1073 },
1074 {
1075 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1076 E7525
1077 },
1078 {
1079 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1080 E7320
1081 },
1082 {
1083 0,
1084 } /* 0 terminated list. */
806c35f5
AC		 1085};
1086
1087MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1088
806c35f5 1089static struct pci_driver e752x_driver = {
680cbbbb 1090 .name = EDAC_MOD_STR,
0d38b049
RD		 1091 .probe = e752x_init_one,
1092 .remove = __devexit_p(e752x_remove_one),
1093 .id_table = e752x_pci_tbl,
806c35f5
AC		 1094};
1095
da9bb1d2 1096static int __init e752x_init(void)
806c35f5
AC		 1097{
1098 int pci_rc;
1099
537fba28 1100 debugf3("%s()\n", __func__);
806c35f5
AC		 1101 pci_rc = pci_register_driver(&e752x_driver);
1102 return (pci_rc < 0) ? pci_rc : 0;
1103}
1104
806c35f5
AC		 1105static void __exit e752x_exit(void)
1106{
537fba28 1107 debugf3("%s()\n", __func__);
806c35f5
AC		 1108 pci_unregister_driver(&e752x_driver);
1109}
1110
806c35f5
AC		 1111module_init(e752x_init);
1112module_exit(e752x_exit);
1113
1114MODULE_LICENSE("GPL");
1115MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1116MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
96941026 1117
1118module_param(force_function_unhide, int, 0444);
1119MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1120" 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");
1121
kernel source for telekom puls (alcatel/mediatek)