Commit | Line | Data |
---|---|---|
806c35f5 AC |
1 | /* |
2 | * Intel e752x Memory Controller kernel module | |
3 | * (C) 2004 Linux Networx (http://lnxi.com) | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * See "enum e752x_chips" below for supported chipsets | |
8 | * | |
9 | * Written by Tom Zimmerman | |
10 | * | |
11 | * Contributors: | |
12 | * Thayne Harbaugh at realmsys.com (?) | |
13 | * Wang Zhenyu at intel.com | |
14 | * Dave Jiang at mvista.com | |
15 | * | |
da9bb1d2 | 16 | * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $ |
806c35f5 AC |
17 | * |
18 | */ | |
19 | ||
806c35f5 AC |
20 | #include <linux/module.h> |
21 | #include <linux/init.h> | |
806c35f5 AC |
22 | #include <linux/pci.h> |
23 | #include <linux/pci_ids.h> | |
806c35f5 | 24 | #include <linux/slab.h> |
c0d12172 | 25 | #include <linux/edac.h> |
20bcb7a8 | 26 | #include "edac_core.h" |
806c35f5 | 27 | |
20bcb7a8 | 28 | #define E752X_REVISION " Ver: 2.0.2 " __DATE__ |
929a40ec | 29 | #define EDAC_MOD_STR "e752x_edac" |
37f04581 | 30 | |
96941026 | 31 | static int force_function_unhide; |
32 | ||
91b99041 DJ |
33 | static struct edac_pci_ctl_info *e752x_pci; |
34 | ||
537fba28 | 35 | #define e752x_printk(level, fmt, arg...) \ |
e7ecd891 | 36 | edac_printk(level, "e752x", fmt, ##arg) |
537fba28 DP |
37 | |
38 | #define e752x_mc_printk(mci, level, fmt, arg...) \ | |
e7ecd891 | 39 | edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg) |
537fba28 | 40 | |
806c35f5 AC |
41 | #ifndef PCI_DEVICE_ID_INTEL_7520_0 |
42 | #define PCI_DEVICE_ID_INTEL_7520_0 0x3590 | |
43 | #endif /* PCI_DEVICE_ID_INTEL_7520_0 */ | |
44 | ||
45 | #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR | |
46 | #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591 | |
47 | #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */ | |
48 | ||
49 | #ifndef PCI_DEVICE_ID_INTEL_7525_0 | |
50 | #define PCI_DEVICE_ID_INTEL_7525_0 0x359E | |
51 | #endif /* PCI_DEVICE_ID_INTEL_7525_0 */ | |
52 | ||
53 | #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR | |
54 | #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593 | |
55 | #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */ | |
56 | ||
57 | #ifndef PCI_DEVICE_ID_INTEL_7320_0 | |
58 | #define PCI_DEVICE_ID_INTEL_7320_0 0x3592 | |
59 | #endif /* PCI_DEVICE_ID_INTEL_7320_0 */ | |
60 | ||
61 | #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR | |
62 | #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593 | |
63 | #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */ | |
64 | ||
5135b797 AK |
65 | #ifndef PCI_DEVICE_ID_INTEL_3100_0 |
66 | #define PCI_DEVICE_ID_INTEL_3100_0 0x35B0 | |
67 | #endif /* PCI_DEVICE_ID_INTEL_3100_0 */ | |
68 | ||
69 | #ifndef PCI_DEVICE_ID_INTEL_3100_1_ERR | |
70 | #define PCI_DEVICE_ID_INTEL_3100_1_ERR 0x35B1 | |
71 | #endif /* PCI_DEVICE_ID_INTEL_3100_1_ERR */ | |
72 | ||
806c35f5 AC |
73 | #define E752X_NR_CSROWS 8 /* number of csrows */ |
74 | ||
806c35f5 AC |
75 | /* E752X register addresses - device 0 function 0 */ |
76 | #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */ | |
77 | #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */ | |
78 | /* | |
79 | * 31:30 Device width row 7 | |
80 | * 01=x8 10=x4 11=x8 DDR2 | |
81 | * 27:26 Device width row 6 | |
82 | * 23:22 Device width row 5 | |
83 | * 19:20 Device width row 4 | |
84 | * 15:14 Device width row 3 | |
85 | * 11:10 Device width row 2 | |
86 | * 7:6 Device width row 1 | |
87 | * 3:2 Device width row 0 | |
88 | */ | |
89 | #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */ | |
90 | /* FIXME:IS THIS RIGHT? */ | |
91 | /* | |
92 | * 22 Number channels 0=1,1=2 | |
93 | * 19:18 DRB Granularity 32/64MB | |
94 | */ | |
95 | #define E752X_DRM 0x80 /* Dimm mapping register */ | |
96 | #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */ | |
97 | /* | |
98 | * 14:12 1 single A, 2 single B, 3 dual | |
99 | */ | |
100 | #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ | |
101 | #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ | |
102 | #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ | |
103 | #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */ | |
104 | ||
105 | /* E752X register addresses - device 0 function 1 */ | |
106 | #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */ | |
107 | #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */ | |
108 | #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */ | |
109 | #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */ | |
110 | #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */ | |
111 | #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */ | |
112 | #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */ | |
113 | #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */ | |
114 | #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */ | |
115 | #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */ | |
116 | #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */ | |
117 | #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */ | |
118 | #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */ | |
119 | #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */ | |
120 | #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */ | |
121 | #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */ | |
122 | #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */ | |
123 | #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */ | |
124 | #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */ | |
125 | #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */ | |
126 | /* error address register (32b) */ | |
127 | /* | |
128 | * 31 Reserved | |
129 | * 30:2 CE address (64 byte block 34:6) | |
130 | * 1 Reserved | |
131 | * 0 HiLoCS | |
132 | */ | |
133 | #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */ | |
134 | /* error address register (32b) */ | |
135 | /* | |
136 | * 31 Reserved | |
137 | * 30:2 CE address (64 byte block 34:6) | |
138 | * 1 Reserved | |
139 | * 0 HiLoCS | |
140 | */ | |
141 | #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */ | |
142 | /* error address register (32b) */ | |
143 | /* | |
144 | * 31 Reserved | |
145 | * 30:2 CE address (64 byte block 34:6) | |
146 | * 1 Reserved | |
147 | * 0 HiLoCS | |
148 | */ | |
149 | #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */ | |
150 | /* error address register (32b) */ | |
151 | /* | |
152 | * 31 Reserved | |
153 | * 30:2 CE address (64 byte block 34:6) | |
154 | * 1 Reserved | |
155 | * 0 HiLoCS | |
156 | */ | |
157 | #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */ | |
158 | /* error syndrome register (16b) */ | |
159 | #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */ | |
160 | /* error syndrome register (16b) */ | |
161 | #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */ | |
162 | ||
5135b797 AK |
163 | /* 3100 IMCH specific register addresses - device 0 function 1 */ |
164 | #define I3100_NSI_FERR 0x48 /* NSI first error reg (32b) */ | |
165 | #define I3100_NSI_NERR 0x4C /* NSI next error reg (32b) */ | |
166 | #define I3100_NSI_SMICMD 0x54 /* NSI SMI command register (32b) */ | |
167 | #define I3100_NSI_EMASK 0x90 /* NSI error mask register (32b) */ | |
168 | ||
806c35f5 AC |
169 | /* ICH5R register addresses - device 30 function 0 */ |
170 | #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */ | |
171 | #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */ | |
172 | #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */ | |
173 | ||
174 | enum e752x_chips { | |
175 | E7520 = 0, | |
176 | E7525 = 1, | |
5135b797 AK |
177 | E7320 = 2, |
178 | I3100 = 3 | |
806c35f5 AC |
179 | }; |
180 | ||
806c35f5 AC |
181 | struct e752x_pvt { |
182 | struct pci_dev *bridge_ck; | |
183 | struct pci_dev *dev_d0f0; | |
184 | struct pci_dev *dev_d0f1; | |
185 | u32 tolm; | |
186 | u32 remapbase; | |
187 | u32 remaplimit; | |
188 | int mc_symmetric; | |
189 | u8 map[8]; | |
190 | int map_type; | |
191 | const struct e752x_dev_info *dev_info; | |
192 | }; | |
193 | ||
806c35f5 AC |
194 | struct e752x_dev_info { |
195 | u16 err_dev; | |
3847bccc | 196 | u16 ctl_dev; |
806c35f5 AC |
197 | const char *ctl_name; |
198 | }; | |
199 | ||
200 | struct e752x_error_info { | |
201 | u32 ferr_global; | |
202 | u32 nerr_global; | |
5135b797 AK |
203 | u32 nsi_ferr; /* 3100 only */ |
204 | u32 nsi_nerr; /* 3100 only */ | |
205 | u8 hi_ferr; /* all but 3100 */ | |
206 | u8 hi_nerr; /* all but 3100 */ | |
806c35f5 AC |
207 | u16 sysbus_ferr; |
208 | u16 sysbus_nerr; | |
209 | u8 buf_ferr; | |
210 | u8 buf_nerr; | |
211 | u16 dram_ferr; | |
212 | u16 dram_nerr; | |
213 | u32 dram_sec1_add; | |
214 | u32 dram_sec2_add; | |
215 | u16 dram_sec1_syndrome; | |
216 | u16 dram_sec2_syndrome; | |
217 | u32 dram_ded_add; | |
218 | u32 dram_scrb_add; | |
219 | u32 dram_retr_add; | |
220 | }; | |
221 | ||
222 | static const struct e752x_dev_info e752x_devs[] = { | |
223 | [E7520] = { | |
052dfb45 DT |
224 | .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR, |
225 | .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0, | |
226 | .ctl_name = "E7520"}, | |
806c35f5 | 227 | [E7525] = { |
052dfb45 DT |
228 | .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR, |
229 | .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0, | |
230 | .ctl_name = "E7525"}, | |
806c35f5 | 231 | [E7320] = { |
052dfb45 DT |
232 | .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR, |
233 | .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0, | |
234 | .ctl_name = "E7320"}, | |
5135b797 AK |
235 | [I3100] = { |
236 | .err_dev = PCI_DEVICE_ID_INTEL_3100_1_ERR, | |
237 | .ctl_dev = PCI_DEVICE_ID_INTEL_3100_0, | |
238 | .ctl_name = "3100"}, | |
806c35f5 AC |
239 | }; |
240 | ||
806c35f5 | 241 | static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, |
052dfb45 | 242 | unsigned long page) |
806c35f5 AC |
243 | { |
244 | u32 remap; | |
203333cb | 245 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 246 | |
537fba28 | 247 | debugf3("%s()\n", __func__); |
806c35f5 AC |
248 | |
249 | if (page < pvt->tolm) | |
250 | return page; | |
e7ecd891 | 251 | |
806c35f5 AC |
252 | if ((page >= 0x100000) && (page < pvt->remapbase)) |
253 | return page; | |
e7ecd891 | 254 | |
806c35f5 | 255 | remap = (page - pvt->tolm) + pvt->remapbase; |
e7ecd891 | 256 | |
806c35f5 AC |
257 | if (remap < pvt->remaplimit) |
258 | return remap; | |
e7ecd891 | 259 | |
537fba28 | 260 | e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); |
806c35f5 AC |
261 | return pvt->tolm - 1; |
262 | } | |
263 | ||
264 | static void do_process_ce(struct mem_ctl_info *mci, u16 error_one, | |
052dfb45 | 265 | u32 sec1_add, u16 sec1_syndrome) |
806c35f5 AC |
266 | { |
267 | u32 page; | |
268 | int row; | |
269 | int channel; | |
270 | int i; | |
203333cb | 271 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 272 | |
537fba28 | 273 | debugf3("%s()\n", __func__); |
806c35f5 AC |
274 | |
275 | /* convert the addr to 4k page */ | |
276 | page = sec1_add >> (PAGE_SHIFT - 4); | |
277 | ||
278 | /* FIXME - check for -1 */ | |
279 | if (pvt->mc_symmetric) { | |
280 | /* chip select are bits 14 & 13 */ | |
281 | row = ((page >> 1) & 3); | |
537fba28 | 282 | e752x_printk(KERN_WARNING, |
052dfb45 DT |
283 | "Test row %d Table %d %d %d %d %d %d %d %d\n", row, |
284 | pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3], | |
285 | pvt->map[4], pvt->map[5], pvt->map[6], | |
286 | pvt->map[7]); | |
806c35f5 AC |
287 | |
288 | /* test for channel remapping */ | |
289 | for (i = 0; i < 8; i++) { | |
290 | if (pvt->map[i] == row) | |
291 | break; | |
292 | } | |
e7ecd891 | 293 | |
537fba28 | 294 | e752x_printk(KERN_WARNING, "Test computed row %d\n", i); |
e7ecd891 | 295 | |
806c35f5 AC |
296 | if (i < 8) |
297 | row = i; | |
298 | else | |
537fba28 | 299 | e752x_mc_printk(mci, KERN_WARNING, |
203333cb DJ |
300 | "row %d not found in remap table\n", |
301 | row); | |
806c35f5 AC |
302 | } else |
303 | row = edac_mc_find_csrow_by_page(mci, page); | |
e7ecd891 | 304 | |
806c35f5 AC |
305 | /* 0 = channel A, 1 = channel B */ |
306 | channel = !(error_one & 1); | |
307 | ||
84db003f MC |
308 | /* e752x mc reads 34:6 of the DRAM linear address */ |
309 | edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4), | |
052dfb45 | 310 | sec1_syndrome, row, channel, "e752x CE"); |
806c35f5 AC |
311 | } |
312 | ||
806c35f5 | 313 | static inline void process_ce(struct mem_ctl_info *mci, u16 error_one, |
052dfb45 DT |
314 | u32 sec1_add, u16 sec1_syndrome, int *error_found, |
315 | int handle_error) | |
806c35f5 AC |
316 | { |
317 | *error_found = 1; | |
318 | ||
319 | if (handle_error) | |
320 | do_process_ce(mci, error_one, sec1_add, sec1_syndrome); | |
321 | } | |
322 | ||
e7ecd891 | 323 | static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, |
052dfb45 | 324 | u32 ded_add, u32 scrb_add) |
806c35f5 AC |
325 | { |
326 | u32 error_2b, block_page; | |
327 | int row; | |
203333cb | 328 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 329 | |
537fba28 | 330 | debugf3("%s()\n", __func__); |
806c35f5 AC |
331 | |
332 | if (error_one & 0x0202) { | |
333 | error_2b = ded_add; | |
e7ecd891 | 334 | |
806c35f5 AC |
335 | /* convert to 4k address */ |
336 | block_page = error_2b >> (PAGE_SHIFT - 4); | |
e7ecd891 | 337 | |
806c35f5 | 338 | row = pvt->mc_symmetric ? |
052dfb45 DT |
339 | /* chip select are bits 14 & 13 */ |
340 | ((block_page >> 1) & 3) : | |
341 | edac_mc_find_csrow_by_page(mci, block_page); | |
e7ecd891 | 342 | |
84db003f MC |
343 | /* e752x mc reads 34:6 of the DRAM linear address */ |
344 | edac_mc_handle_ue(mci, block_page, | |
052dfb45 DT |
345 | offset_in_page(error_2b << 4), |
346 | row, "e752x UE from Read"); | |
806c35f5 AC |
347 | } |
348 | if (error_one & 0x0404) { | |
349 | error_2b = scrb_add; | |
e7ecd891 | 350 | |
806c35f5 AC |
351 | /* convert to 4k address */ |
352 | block_page = error_2b >> (PAGE_SHIFT - 4); | |
e7ecd891 | 353 | |
806c35f5 | 354 | row = pvt->mc_symmetric ? |
052dfb45 DT |
355 | /* chip select are bits 14 & 13 */ |
356 | ((block_page >> 1) & 3) : | |
357 | edac_mc_find_csrow_by_page(mci, block_page); | |
e7ecd891 | 358 | |
84db003f MC |
359 | /* e752x mc reads 34:6 of the DRAM linear address */ |
360 | edac_mc_handle_ue(mci, block_page, | |
052dfb45 DT |
361 | offset_in_page(error_2b << 4), |
362 | row, "e752x UE from Scruber"); | |
806c35f5 AC |
363 | } |
364 | } | |
365 | ||
366 | static inline void process_ue(struct mem_ctl_info *mci, u16 error_one, | |
052dfb45 DT |
367 | u32 ded_add, u32 scrb_add, int *error_found, |
368 | int handle_error) | |
806c35f5 AC |
369 | { |
370 | *error_found = 1; | |
371 | ||
372 | if (handle_error) | |
373 | do_process_ue(mci, error_one, ded_add, scrb_add); | |
374 | } | |
375 | ||
376 | static inline void process_ue_no_info_wr(struct mem_ctl_info *mci, | |
203333cb | 377 | int *error_found, int handle_error) |
806c35f5 AC |
378 | { |
379 | *error_found = 1; | |
380 | ||
381 | if (!handle_error) | |
382 | return; | |
383 | ||
537fba28 | 384 | debugf3("%s()\n", __func__); |
806c35f5 AC |
385 | edac_mc_handle_ue_no_info(mci, "e752x UE log memory write"); |
386 | } | |
387 | ||
388 | static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error, | |
203333cb | 389 | u32 retry_add) |
806c35f5 AC |
390 | { |
391 | u32 error_1b, page; | |
392 | int row; | |
203333cb | 393 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 AC |
394 | |
395 | error_1b = retry_add; | |
203333cb DJ |
396 | page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */ |
397 | row = pvt->mc_symmetric ? ((page >> 1) & 3) : /* chip select are bits 14 & 13 */ | |
052dfb45 | 398 | edac_mc_find_csrow_by_page(mci, page); |
537fba28 | 399 | e752x_mc_printk(mci, KERN_WARNING, |
203333cb DJ |
400 | "CE page 0x%lx, row %d : Memory read retry\n", |
401 | (long unsigned int)page, row); | |
806c35f5 AC |
402 | } |
403 | ||
404 | static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error, | |
052dfb45 DT |
405 | u32 retry_add, int *error_found, |
406 | int handle_error) | |
806c35f5 AC |
407 | { |
408 | *error_found = 1; | |
409 | ||
410 | if (handle_error) | |
411 | do_process_ded_retry(mci, error, retry_add); | |
412 | } | |
413 | ||
414 | static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error, | |
203333cb | 415 | int *error_found, int handle_error) |
806c35f5 AC |
416 | { |
417 | *error_found = 1; | |
418 | ||
419 | if (handle_error) | |
537fba28 | 420 | e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n"); |
806c35f5 AC |
421 | } |
422 | ||
da9bb1d2 | 423 | static char *global_message[11] = { |
806c35f5 AC |
424 | "PCI Express C1", "PCI Express C", "PCI Express B1", |
425 | "PCI Express B", "PCI Express A1", "PCI Express A", | |
5135b797 | 426 | "DMA Controler", "HUB or NS Interface", "System Bus", |
806c35f5 AC |
427 | "DRAM Controler", "Internal Buffer" |
428 | }; | |
429 | ||
da9bb1d2 | 430 | static char *fatal_message[2] = { "Non-Fatal ", "Fatal " }; |
806c35f5 AC |
431 | |
432 | static void do_global_error(int fatal, u32 errors) | |
433 | { | |
434 | int i; | |
435 | ||
436 | for (i = 0; i < 11; i++) { | |
437 | if (errors & (1 << i)) | |
537fba28 | 438 | e752x_printk(KERN_WARNING, "%sError %s\n", |
052dfb45 | 439 | fatal_message[fatal], global_message[i]); |
806c35f5 AC |
440 | } |
441 | } | |
442 | ||
443 | static inline void global_error(int fatal, u32 errors, int *error_found, | |
203333cb | 444 | int handle_error) |
806c35f5 AC |
445 | { |
446 | *error_found = 1; | |
447 | ||
448 | if (handle_error) | |
449 | do_global_error(fatal, errors); | |
450 | } | |
451 | ||
da9bb1d2 | 452 | static char *hub_message[7] = { |
806c35f5 AC |
453 | "HI Address or Command Parity", "HI Illegal Access", |
454 | "HI Internal Parity", "Out of Range Access", | |
455 | "HI Data Parity", "Enhanced Config Access", | |
456 | "Hub Interface Target Abort" | |
457 | }; | |
458 | ||
459 | static void do_hub_error(int fatal, u8 errors) | |
460 | { | |
461 | int i; | |
462 | ||
463 | for (i = 0; i < 7; i++) { | |
464 | if (errors & (1 << i)) | |
537fba28 | 465 | e752x_printk(KERN_WARNING, "%sError %s\n", |
052dfb45 | 466 | fatal_message[fatal], hub_message[i]); |
806c35f5 AC |
467 | } |
468 | } | |
469 | ||
470 | static inline void hub_error(int fatal, u8 errors, int *error_found, | |
052dfb45 | 471 | int handle_error) |
806c35f5 AC |
472 | { |
473 | *error_found = 1; | |
474 | ||
475 | if (handle_error) | |
476 | do_hub_error(fatal, errors); | |
477 | } | |
478 | ||
5135b797 AK |
479 | #define NSI_FATAL_MASK 0x0c080081 |
480 | #define NSI_NON_FATAL_MASK 0x23a0ba64 | |
481 | #define NSI_ERR_MASK (NSI_FATAL_MASK | NSI_NON_FATAL_MASK) | |
482 | ||
483 | static char *nsi_message[30] = { | |
484 | "NSI Link Down", /* NSI_FERR/NSI_NERR bit 0, fatal error */ | |
485 | "", /* reserved */ | |
486 | "NSI Parity Error", /* bit 2, non-fatal */ | |
487 | "", /* reserved */ | |
488 | "", /* reserved */ | |
489 | "Correctable Error Message", /* bit 5, non-fatal */ | |
490 | "Non-Fatal Error Message", /* bit 6, non-fatal */ | |
491 | "Fatal Error Message", /* bit 7, fatal */ | |
492 | "", /* reserved */ | |
493 | "Receiver Error", /* bit 9, non-fatal */ | |
494 | "", /* reserved */ | |
495 | "Bad TLP", /* bit 11, non-fatal */ | |
496 | "Bad DLLP", /* bit 12, non-fatal */ | |
497 | "REPLAY_NUM Rollover", /* bit 13, non-fatal */ | |
498 | "", /* reserved */ | |
499 | "Replay Timer Timeout", /* bit 15, non-fatal */ | |
500 | "", /* reserved */ | |
501 | "", /* reserved */ | |
502 | "", /* reserved */ | |
503 | "Data Link Protocol Error", /* bit 19, fatal */ | |
504 | "", /* reserved */ | |
505 | "Poisoned TLP", /* bit 21, non-fatal */ | |
506 | "", /* reserved */ | |
507 | "Completion Timeout", /* bit 23, non-fatal */ | |
508 | "Completer Abort", /* bit 24, non-fatal */ | |
509 | "Unexpected Completion", /* bit 25, non-fatal */ | |
510 | "Receiver Overflow", /* bit 26, fatal */ | |
511 | "Malformed TLP", /* bit 27, fatal */ | |
512 | "", /* reserved */ | |
513 | "Unsupported Request" /* bit 29, non-fatal */ | |
514 | }; | |
515 | ||
516 | static void do_nsi_error(int fatal, u32 errors) | |
517 | { | |
518 | int i; | |
519 | ||
520 | for (i = 0; i < 30; i++) { | |
521 | if (errors & (1 << i)) | |
522 | printk(KERN_WARNING "%sError %s\n", | |
523 | fatal_message[fatal], nsi_message[i]); | |
524 | } | |
525 | } | |
526 | ||
527 | static inline void nsi_error(int fatal, u32 errors, int *error_found, | |
528 | int handle_error) | |
529 | { | |
530 | *error_found = 1; | |
531 | ||
532 | if (handle_error) | |
533 | do_nsi_error(fatal, errors); | |
534 | } | |
535 | ||
da9bb1d2 | 536 | static char *membuf_message[4] = { |
806c35f5 AC |
537 | "Internal PMWB to DRAM parity", |
538 | "Internal PMWB to System Bus Parity", | |
539 | "Internal System Bus or IO to PMWB Parity", | |
540 | "Internal DRAM to PMWB Parity" | |
541 | }; | |
542 | ||
543 | static void do_membuf_error(u8 errors) | |
544 | { | |
545 | int i; | |
546 | ||
547 | for (i = 0; i < 4; i++) { | |
548 | if (errors & (1 << i)) | |
537fba28 | 549 | e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n", |
052dfb45 | 550 | membuf_message[i]); |
806c35f5 AC |
551 | } |
552 | } | |
553 | ||
554 | static inline void membuf_error(u8 errors, int *error_found, int handle_error) | |
555 | { | |
556 | *error_found = 1; | |
557 | ||
558 | if (handle_error) | |
559 | do_membuf_error(errors); | |
560 | } | |
561 | ||
e009356f | 562 | static char *sysbus_message[10] = { |
806c35f5 AC |
563 | "Addr or Request Parity", |
564 | "Data Strobe Glitch", | |
565 | "Addr Strobe Glitch", | |
566 | "Data Parity", | |
567 | "Addr Above TOM", | |
568 | "Non DRAM Lock Error", | |
569 | "MCERR", "BINIT", | |
570 | "Memory Parity", | |
571 | "IO Subsystem Parity" | |
572 | }; | |
573 | ||
574 | static void do_sysbus_error(int fatal, u32 errors) | |
575 | { | |
576 | int i; | |
577 | ||
578 | for (i = 0; i < 10; i++) { | |
579 | if (errors & (1 << i)) | |
537fba28 | 580 | e752x_printk(KERN_WARNING, "%sError System Bus %s\n", |
052dfb45 | 581 | fatal_message[fatal], sysbus_message[i]); |
806c35f5 AC |
582 | } |
583 | } | |
584 | ||
585 | static inline void sysbus_error(int fatal, u32 errors, int *error_found, | |
203333cb | 586 | int handle_error) |
806c35f5 AC |
587 | { |
588 | *error_found = 1; | |
589 | ||
590 | if (handle_error) | |
591 | do_sysbus_error(fatal, errors); | |
592 | } | |
593 | ||
e7ecd891 | 594 | static void e752x_check_hub_interface(struct e752x_error_info *info, |
052dfb45 | 595 | int *error_found, int handle_error) |
806c35f5 AC |
596 | { |
597 | u8 stat8; | |
598 | ||
599 | //pci_read_config_byte(dev,E752X_HI_FERR,&stat8); | |
e7ecd891 | 600 | |
806c35f5 | 601 | stat8 = info->hi_ferr; |
e7ecd891 | 602 | |
203333cb | 603 | if (stat8 & 0x7f) { /* Error, so process */ |
806c35f5 | 604 | stat8 &= 0x7f; |
e7ecd891 | 605 | |
203333cb | 606 | if (stat8 & 0x2b) |
806c35f5 | 607 | hub_error(1, stat8 & 0x2b, error_found, handle_error); |
e7ecd891 | 608 | |
203333cb | 609 | if (stat8 & 0x54) |
806c35f5 AC |
610 | hub_error(0, stat8 & 0x54, error_found, handle_error); |
611 | } | |
612 | //pci_read_config_byte(dev,E752X_HI_NERR,&stat8); | |
e7ecd891 | 613 | |
806c35f5 | 614 | stat8 = info->hi_nerr; |
e7ecd891 | 615 | |
203333cb | 616 | if (stat8 & 0x7f) { /* Error, so process */ |
806c35f5 | 617 | stat8 &= 0x7f; |
e7ecd891 | 618 | |
806c35f5 AC |
619 | if (stat8 & 0x2b) |
620 | hub_error(1, stat8 & 0x2b, error_found, handle_error); | |
e7ecd891 | 621 | |
203333cb | 622 | if (stat8 & 0x54) |
806c35f5 AC |
623 | hub_error(0, stat8 & 0x54, error_found, handle_error); |
624 | } | |
625 | } | |
626 | ||
5135b797 AK |
627 | static void e752x_check_ns_interface(struct e752x_error_info *info, |
628 | int *error_found, int handle_error) | |
629 | { | |
630 | u32 stat32; | |
631 | ||
632 | stat32 = info->nsi_ferr; | |
633 | if (stat32 & NSI_ERR_MASK) { /* Error, so process */ | |
634 | if (stat32 & NSI_FATAL_MASK) /* check for fatal errors */ | |
635 | nsi_error(1, stat32 & NSI_FATAL_MASK, error_found, | |
636 | handle_error); | |
637 | if (stat32 & NSI_NON_FATAL_MASK) /* check for non-fatal ones */ | |
638 | nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found, | |
639 | handle_error); | |
640 | } | |
641 | stat32 = info->nsi_nerr; | |
642 | if (stat32 & NSI_ERR_MASK) { | |
643 | if (stat32 & NSI_FATAL_MASK) | |
644 | nsi_error(1, stat32 & NSI_FATAL_MASK, error_found, | |
645 | handle_error); | |
646 | if (stat32 & NSI_NON_FATAL_MASK) | |
647 | nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found, | |
648 | handle_error); | |
649 | } | |
650 | } | |
651 | ||
e7ecd891 | 652 | static void e752x_check_sysbus(struct e752x_error_info *info, |
052dfb45 | 653 | int *error_found, int handle_error) |
806c35f5 AC |
654 | { |
655 | u32 stat32, error32; | |
656 | ||
657 | //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32); | |
658 | stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16); | |
659 | ||
660 | if (stat32 == 0) | |
203333cb | 661 | return; /* no errors */ |
806c35f5 AC |
662 | |
663 | error32 = (stat32 >> 16) & 0x3ff; | |
664 | stat32 = stat32 & 0x3ff; | |
e7ecd891 | 665 | |
203333cb | 666 | if (stat32 & 0x087) |
dfb2a763 | 667 | sysbus_error(1, stat32 & 0x087, error_found, handle_error); |
e7ecd891 | 668 | |
203333cb | 669 | if (stat32 & 0x378) |
dfb2a763 | 670 | sysbus_error(0, stat32 & 0x378, error_found, handle_error); |
e7ecd891 | 671 | |
203333cb | 672 | if (error32 & 0x087) |
dfb2a763 | 673 | sysbus_error(1, error32 & 0x087, error_found, handle_error); |
e7ecd891 | 674 | |
203333cb | 675 | if (error32 & 0x378) |
dfb2a763 | 676 | sysbus_error(0, error32 & 0x378, error_found, handle_error); |
806c35f5 AC |
677 | } |
678 | ||
203333cb | 679 | static void e752x_check_membuf(struct e752x_error_info *info, |
052dfb45 | 680 | int *error_found, int handle_error) |
806c35f5 AC |
681 | { |
682 | u8 stat8; | |
683 | ||
684 | stat8 = info->buf_ferr; | |
e7ecd891 | 685 | |
203333cb | 686 | if (stat8 & 0x0f) { /* Error, so process */ |
806c35f5 AC |
687 | stat8 &= 0x0f; |
688 | membuf_error(stat8, error_found, handle_error); | |
689 | } | |
e7ecd891 | 690 | |
806c35f5 | 691 | stat8 = info->buf_nerr; |
e7ecd891 | 692 | |
203333cb | 693 | if (stat8 & 0x0f) { /* Error, so process */ |
806c35f5 AC |
694 | stat8 &= 0x0f; |
695 | membuf_error(stat8, error_found, handle_error); | |
696 | } | |
697 | } | |
698 | ||
203333cb | 699 | static void e752x_check_dram(struct mem_ctl_info *mci, |
052dfb45 DT |
700 | struct e752x_error_info *info, int *error_found, |
701 | int handle_error) | |
806c35f5 AC |
702 | { |
703 | u16 error_one, error_next; | |
704 | ||
705 | error_one = info->dram_ferr; | |
706 | error_next = info->dram_nerr; | |
707 | ||
708 | /* decode and report errors */ | |
203333cb | 709 | if (error_one & 0x0101) /* check first error correctable */ |
806c35f5 | 710 | process_ce(mci, error_one, info->dram_sec1_add, |
052dfb45 | 711 | info->dram_sec1_syndrome, error_found, handle_error); |
806c35f5 | 712 | |
203333cb | 713 | if (error_next & 0x0101) /* check next error correctable */ |
806c35f5 | 714 | process_ce(mci, error_next, info->dram_sec2_add, |
052dfb45 | 715 | info->dram_sec2_syndrome, error_found, handle_error); |
806c35f5 | 716 | |
203333cb | 717 | if (error_one & 0x4040) |
806c35f5 AC |
718 | process_ue_no_info_wr(mci, error_found, handle_error); |
719 | ||
203333cb | 720 | if (error_next & 0x4040) |
806c35f5 AC |
721 | process_ue_no_info_wr(mci, error_found, handle_error); |
722 | ||
203333cb | 723 | if (error_one & 0x2020) |
806c35f5 | 724 | process_ded_retry(mci, error_one, info->dram_retr_add, |
052dfb45 | 725 | error_found, handle_error); |
806c35f5 | 726 | |
203333cb | 727 | if (error_next & 0x2020) |
806c35f5 | 728 | process_ded_retry(mci, error_next, info->dram_retr_add, |
052dfb45 | 729 | error_found, handle_error); |
806c35f5 | 730 | |
203333cb DJ |
731 | if (error_one & 0x0808) |
732 | process_threshold_ce(mci, error_one, error_found, handle_error); | |
806c35f5 | 733 | |
203333cb | 734 | if (error_next & 0x0808) |
806c35f5 | 735 | process_threshold_ce(mci, error_next, error_found, |
052dfb45 | 736 | handle_error); |
806c35f5 | 737 | |
203333cb | 738 | if (error_one & 0x0606) |
806c35f5 | 739 | process_ue(mci, error_one, info->dram_ded_add, |
052dfb45 | 740 | info->dram_scrb_add, error_found, handle_error); |
806c35f5 | 741 | |
203333cb | 742 | if (error_next & 0x0606) |
806c35f5 | 743 | process_ue(mci, error_next, info->dram_ded_add, |
052dfb45 | 744 | info->dram_scrb_add, error_found, handle_error); |
806c35f5 AC |
745 | } |
746 | ||
203333cb DJ |
747 | static void e752x_get_error_info(struct mem_ctl_info *mci, |
748 | struct e752x_error_info *info) | |
806c35f5 AC |
749 | { |
750 | struct pci_dev *dev; | |
751 | struct e752x_pvt *pvt; | |
752 | ||
753 | memset(info, 0, sizeof(*info)); | |
203333cb | 754 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 755 | dev = pvt->dev_d0f1; |
806c35f5 AC |
756 | pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global); |
757 | ||
758 | if (info->ferr_global) { | |
5135b797 AK |
759 | if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { |
760 | pci_read_config_dword(dev, I3100_NSI_FERR, | |
761 | &info->nsi_ferr); | |
762 | info->hi_ferr = 0; | |
763 | } else { | |
764 | pci_read_config_byte(dev, E752X_HI_FERR, | |
765 | &info->hi_ferr); | |
766 | info->nsi_ferr = 0; | |
767 | } | |
806c35f5 | 768 | pci_read_config_word(dev, E752X_SYSBUS_FERR, |
052dfb45 | 769 | &info->sysbus_ferr); |
806c35f5 | 770 | pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr); |
203333cb | 771 | pci_read_config_word(dev, E752X_DRAM_FERR, &info->dram_ferr); |
806c35f5 | 772 | pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD, |
052dfb45 | 773 | &info->dram_sec1_add); |
806c35f5 | 774 | pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME, |
052dfb45 | 775 | &info->dram_sec1_syndrome); |
806c35f5 | 776 | pci_read_config_dword(dev, E752X_DRAM_DED_ADD, |
052dfb45 | 777 | &info->dram_ded_add); |
806c35f5 | 778 | pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD, |
052dfb45 | 779 | &info->dram_scrb_add); |
806c35f5 | 780 | pci_read_config_dword(dev, E752X_DRAM_RETR_ADD, |
052dfb45 | 781 | &info->dram_retr_add); |
806c35f5 | 782 | |
5135b797 | 783 | /* ignore the reserved bits just in case */ |
806c35f5 AC |
784 | if (info->hi_ferr & 0x7f) |
785 | pci_write_config_byte(dev, E752X_HI_FERR, | |
052dfb45 | 786 | info->hi_ferr); |
806c35f5 | 787 | |
5135b797 AK |
788 | if (info->nsi_ferr & NSI_ERR_MASK) |
789 | pci_write_config_dword(dev, I3100_NSI_FERR, | |
790 | info->nsi_ferr); | |
791 | ||
806c35f5 AC |
792 | if (info->sysbus_ferr) |
793 | pci_write_config_word(dev, E752X_SYSBUS_FERR, | |
052dfb45 | 794 | info->sysbus_ferr); |
806c35f5 AC |
795 | |
796 | if (info->buf_ferr & 0x0f) | |
797 | pci_write_config_byte(dev, E752X_BUF_FERR, | |
052dfb45 | 798 | info->buf_ferr); |
806c35f5 AC |
799 | |
800 | if (info->dram_ferr) | |
801 | pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR, | |
203333cb | 802 | info->dram_ferr, info->dram_ferr); |
806c35f5 AC |
803 | |
804 | pci_write_config_dword(dev, E752X_FERR_GLOBAL, | |
052dfb45 | 805 | info->ferr_global); |
806c35f5 AC |
806 | } |
807 | ||
808 | pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global); | |
809 | ||
810 | if (info->nerr_global) { | |
5135b797 AK |
811 | if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { |
812 | pci_read_config_dword(dev, I3100_NSI_NERR, | |
813 | &info->nsi_nerr); | |
814 | info->hi_nerr = 0; | |
815 | } else { | |
816 | pci_read_config_byte(dev, E752X_HI_NERR, | |
817 | &info->hi_nerr); | |
818 | info->nsi_nerr = 0; | |
819 | } | |
806c35f5 | 820 | pci_read_config_word(dev, E752X_SYSBUS_NERR, |
052dfb45 | 821 | &info->sysbus_nerr); |
806c35f5 | 822 | pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr); |
203333cb | 823 | pci_read_config_word(dev, E752X_DRAM_NERR, &info->dram_nerr); |
806c35f5 | 824 | pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD, |
052dfb45 | 825 | &info->dram_sec2_add); |
806c35f5 | 826 | pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME, |
052dfb45 | 827 | &info->dram_sec2_syndrome); |
806c35f5 AC |
828 | |
829 | if (info->hi_nerr & 0x7f) | |
830 | pci_write_config_byte(dev, E752X_HI_NERR, | |
052dfb45 | 831 | info->hi_nerr); |
806c35f5 | 832 | |
5135b797 AK |
833 | if (info->nsi_nerr & NSI_ERR_MASK) |
834 | pci_write_config_dword(dev, I3100_NSI_NERR, | |
835 | info->nsi_nerr); | |
836 | ||
806c35f5 AC |
837 | if (info->sysbus_nerr) |
838 | pci_write_config_word(dev, E752X_SYSBUS_NERR, | |
052dfb45 | 839 | info->sysbus_nerr); |
806c35f5 AC |
840 | |
841 | if (info->buf_nerr & 0x0f) | |
842 | pci_write_config_byte(dev, E752X_BUF_NERR, | |
052dfb45 | 843 | info->buf_nerr); |
806c35f5 AC |
844 | |
845 | if (info->dram_nerr) | |
846 | pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR, | |
203333cb | 847 | info->dram_nerr, info->dram_nerr); |
806c35f5 AC |
848 | |
849 | pci_write_config_dword(dev, E752X_NERR_GLOBAL, | |
052dfb45 | 850 | info->nerr_global); |
806c35f5 AC |
851 | } |
852 | } | |
853 | ||
203333cb | 854 | static int e752x_process_error_info(struct mem_ctl_info *mci, |
052dfb45 DT |
855 | struct e752x_error_info *info, |
856 | int handle_errors) | |
806c35f5 AC |
857 | { |
858 | u32 error32, stat32; | |
859 | int error_found; | |
860 | ||
861 | error_found = 0; | |
862 | error32 = (info->ferr_global >> 18) & 0x3ff; | |
863 | stat32 = (info->ferr_global >> 4) & 0x7ff; | |
864 | ||
865 | if (error32) | |
866 | global_error(1, error32, &error_found, handle_errors); | |
867 | ||
868 | if (stat32) | |
869 | global_error(0, stat32, &error_found, handle_errors); | |
870 | ||
871 | error32 = (info->nerr_global >> 18) & 0x3ff; | |
872 | stat32 = (info->nerr_global >> 4) & 0x7ff; | |
873 | ||
874 | if (error32) | |
875 | global_error(1, error32, &error_found, handle_errors); | |
876 | ||
877 | if (stat32) | |
878 | global_error(0, stat32, &error_found, handle_errors); | |
879 | ||
880 | e752x_check_hub_interface(info, &error_found, handle_errors); | |
5135b797 | 881 | e752x_check_ns_interface(info, &error_found, handle_errors); |
806c35f5 AC |
882 | e752x_check_sysbus(info, &error_found, handle_errors); |
883 | e752x_check_membuf(info, &error_found, handle_errors); | |
884 | e752x_check_dram(mci, info, &error_found, handle_errors); | |
885 | return error_found; | |
886 | } | |
887 | ||
888 | static void e752x_check(struct mem_ctl_info *mci) | |
889 | { | |
890 | struct e752x_error_info info; | |
e7ecd891 | 891 | |
537fba28 | 892 | debugf3("%s()\n", __func__); |
806c35f5 AC |
893 | e752x_get_error_info(mci, &info); |
894 | e752x_process_error_info(mci, &info, 1); | |
895 | } | |
896 | ||
13189525 DT |
897 | /* Return 1 if dual channel mode is active. Else return 0. */ |
898 | static inline int dual_channel_active(u16 ddrcsr) | |
899 | { | |
900 | return (((ddrcsr >> 12) & 3) == 3); | |
901 | } | |
902 | ||
7297c261 MG |
903 | /* Remap csrow index numbers if map_type is "reverse" |
904 | */ | |
905 | static inline int remap_csrow_index(struct mem_ctl_info *mci, int index) | |
906 | { | |
907 | struct e752x_pvt *pvt = mci->pvt_info; | |
908 | ||
909 | if (!pvt->map_type) | |
910 | return (7 - index); | |
911 | ||
912 | return (index); | |
913 | } | |
914 | ||
13189525 | 915 | static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, |
052dfb45 | 916 | u16 ddrcsr) |
13189525 DT |
917 | { |
918 | struct csrow_info *csrow; | |
919 | unsigned long last_cumul_size; | |
920 | int index, mem_dev, drc_chan; | |
203333cb DJ |
921 | int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */ |
922 | int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */ | |
13189525 DT |
923 | u8 value; |
924 | u32 dra, drc, cumul_size; | |
925 | ||
9962fd01 | 926 | dra = 0; |
203333cb | 927 | for (index = 0; index < 4; index++) { |
9962fd01 | 928 | u8 dra_reg; |
203333cb | 929 | pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg); |
9962fd01 BP |
930 | dra |= dra_reg << (index * 8); |
931 | } | |
13189525 DT |
932 | pci_read_config_dword(pdev, E752X_DRC, &drc); |
933 | drc_chan = dual_channel_active(ddrcsr); | |
203333cb | 934 | drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */ |
13189525 DT |
935 | drc_ddim = (drc >> 20) & 0x3; |
936 | ||
937 | /* The dram row boundary (DRB) reg values are boundary address for | |
938 | * each DRAM row with a granularity of 64 or 128MB (single/dual | |
939 | * channel operation). DRB regs are cumulative; therefore DRB7 will | |
940 | * contain the total memory contained in all eight rows. | |
941 | */ | |
942 | for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) { | |
943 | /* mem_dev 0=x8, 1=x4 */ | |
944 | mem_dev = (dra >> (index * 4 + 2)) & 0x3; | |
7297c261 | 945 | csrow = &mci->csrows[remap_csrow_index(mci, index)]; |
13189525 DT |
946 | |
947 | mem_dev = (mem_dev == 2); | |
948 | pci_read_config_byte(pdev, E752X_DRB + index, &value); | |
949 | /* convert a 128 or 64 MiB DRB to a page size. */ | |
950 | cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); | |
951 | debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, | |
952 | cumul_size); | |
953 | if (cumul_size == last_cumul_size) | |
954 | continue; /* not populated */ | |
955 | ||
956 | csrow->first_page = last_cumul_size; | |
957 | csrow->last_page = cumul_size - 1; | |
958 | csrow->nr_pages = cumul_size - last_cumul_size; | |
959 | last_cumul_size = cumul_size; | |
960 | csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ | |
961 | csrow->mtype = MEM_RDDR; /* only one type supported */ | |
962 | csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; | |
963 | ||
964 | /* | |
965 | * if single channel or x8 devices then SECDED | |
966 | * if dual channel and x4 then S4ECD4ED | |
967 | */ | |
968 | if (drc_ddim) { | |
969 | if (drc_chan && mem_dev) { | |
970 | csrow->edac_mode = EDAC_S4ECD4ED; | |
971 | mci->edac_cap |= EDAC_FLAG_S4ECD4ED; | |
972 | } else { | |
973 | csrow->edac_mode = EDAC_SECDED; | |
974 | mci->edac_cap |= EDAC_FLAG_SECDED; | |
975 | } | |
976 | } else | |
977 | csrow->edac_mode = EDAC_NONE; | |
978 | } | |
979 | } | |
980 | ||
981 | static void e752x_init_mem_map_table(struct pci_dev *pdev, | |
052dfb45 | 982 | struct e752x_pvt *pvt) |
806c35f5 | 983 | { |
806c35f5 | 984 | int index; |
7297c261 | 985 | u8 value, last, row; |
13189525 DT |
986 | |
987 | last = 0; | |
988 | row = 0; | |
989 | ||
990 | for (index = 0; index < 8; index += 2) { | |
991 | pci_read_config_byte(pdev, E752X_DRB + index, &value); | |
992 | /* test if there is a dimm in this slot */ | |
993 | if (value == last) { | |
994 | /* no dimm in the slot, so flag it as empty */ | |
995 | pvt->map[index] = 0xff; | |
996 | pvt->map[index + 1] = 0xff; | |
203333cb | 997 | } else { /* there is a dimm in the slot */ |
13189525 DT |
998 | pvt->map[index] = row; |
999 | row++; | |
1000 | last = value; | |
1001 | /* test the next value to see if the dimm is double | |
1002 | * sided | |
1003 | */ | |
1004 | pci_read_config_byte(pdev, E752X_DRB + index + 1, | |
052dfb45 DT |
1005 | &value); |
1006 | ||
1007 | /* the dimm is single sided, so flag as empty */ | |
1008 | /* this is a double sided dimm to save the next row #*/ | |
1009 | pvt->map[index + 1] = (value == last) ? 0xff : row; | |
13189525 DT |
1010 | row++; |
1011 | last = value; | |
1012 | } | |
1013 | } | |
13189525 DT |
1014 | } |
1015 | ||
1016 | /* Return 0 on success or 1 on failure. */ | |
1017 | static int e752x_get_devs(struct pci_dev *pdev, int dev_idx, | |
052dfb45 | 1018 | struct e752x_pvt *pvt) |
13189525 DT |
1019 | { |
1020 | struct pci_dev *dev; | |
1021 | ||
1022 | pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, | |
203333cb | 1023 | pvt->dev_info->err_dev, pvt->bridge_ck); |
13189525 DT |
1024 | |
1025 | if (pvt->bridge_ck == NULL) | |
1026 | pvt->bridge_ck = pci_scan_single_device(pdev->bus, | |
1027 | PCI_DEVFN(0, 1)); | |
1028 | ||
1029 | if (pvt->bridge_ck == NULL) { | |
1030 | e752x_printk(KERN_ERR, "error reporting device not found:" | |
052dfb45 DT |
1031 | "vendor %x device 0x%x (broken BIOS?)\n", |
1032 | PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev); | |
13189525 DT |
1033 | return 1; |
1034 | } | |
1035 | ||
1036 | dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev, | |
052dfb45 | 1037 | NULL); |
13189525 DT |
1038 | |
1039 | if (dev == NULL) | |
1040 | goto fail; | |
1041 | ||
1042 | pvt->dev_d0f0 = dev; | |
1043 | pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck); | |
1044 | ||
1045 | return 0; | |
1046 | ||
052dfb45 | 1047 | fail: |
13189525 DT |
1048 | pci_dev_put(pvt->bridge_ck); |
1049 | return 1; | |
1050 | } | |
1051 | ||
1052 | static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt) | |
1053 | { | |
1054 | struct pci_dev *dev; | |
1055 | ||
1056 | dev = pvt->dev_d0f1; | |
1057 | /* Turn off error disable & SMI in case the BIOS turned it on */ | |
5135b797 AK |
1058 | if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { |
1059 | pci_write_config_dword(dev, I3100_NSI_EMASK, 0); | |
1060 | pci_write_config_dword(dev, I3100_NSI_SMICMD, 0); | |
1061 | } else { | |
1062 | pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00); | |
1063 | pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00); | |
1064 | } | |
13189525 DT |
1065 | pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00); |
1066 | pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00); | |
1067 | pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00); | |
1068 | pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00); | |
1069 | pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00); | |
1070 | pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00); | |
1071 | } | |
1072 | ||
1073 | static int e752x_probe1(struct pci_dev *pdev, int dev_idx) | |
1074 | { | |
3847bccc | 1075 | u16 pci_data; |
806c35f5 | 1076 | u8 stat8; |
13189525 DT |
1077 | struct mem_ctl_info *mci; |
1078 | struct e752x_pvt *pvt; | |
806c35f5 | 1079 | u16 ddrcsr; |
203333cb | 1080 | int drc_chan; /* Number of channels 0=1chan,1=2chan */ |
749ede57 | 1081 | struct e752x_error_info discard; |
806c35f5 | 1082 | |
537fba28 | 1083 | debugf0("%s(): mci\n", __func__); |
806c35f5 AC |
1084 | debugf0("Starting Probe1\n"); |
1085 | ||
c0d12172 | 1086 | /* make sure error reporting method is sane */ |
203333cb DJ |
1087 | switch (edac_op_state) { |
1088 | case EDAC_OPSTATE_POLL: | |
1089 | case EDAC_OPSTATE_NMI: | |
1090 | break; | |
1091 | default: | |
1092 | edac_op_state = EDAC_OPSTATE_POLL; | |
1093 | break; | |
c0d12172 DJ |
1094 | } |
1095 | ||
96941026 | 1096 | /* check to see if device 0 function 1 is enabled; if it isn't, we |
1097 | * assume the BIOS has reserved it for a reason and is expecting | |
1098 | * exclusive access, we take care not to violate that assumption and | |
1099 | * fail the probe. */ | |
806c35f5 | 1100 | pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8); |
96941026 | 1101 | if (!force_function_unhide && !(stat8 & (1 << 5))) { |
1102 | printk(KERN_INFO "Contact your BIOS vendor to see if the " | |
052dfb45 | 1103 | "E752x error registers can be safely un-hidden\n"); |
f9b5a5d1 | 1104 | return -ENODEV; |
96941026 | 1105 | } |
806c35f5 AC |
1106 | stat8 |= (1 << 5); |
1107 | pci_write_config_byte(pdev, E752X_DEVPRES1, stat8); | |
1108 | ||
806c35f5 AC |
1109 | pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr); |
1110 | /* FIXME: should check >>12 or 0xf, true for all? */ | |
1111 | /* Dual channel = 1, Single channel = 0 */ | |
13189525 | 1112 | drc_chan = dual_channel_active(ddrcsr); |
806c35f5 | 1113 | |
b8f6f975 | 1114 | mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1, 0); |
806c35f5 AC |
1115 | |
1116 | if (mci == NULL) { | |
13189525 | 1117 | return -ENOMEM; |
806c35f5 AC |
1118 | } |
1119 | ||
537fba28 | 1120 | debugf3("%s(): init mci\n", __func__); |
806c35f5 | 1121 | mci->mtype_cap = MEM_FLAG_RDDR; |
5135b797 AK |
1122 | /* 3100 IMCH supports SECDEC only */ |
1123 | mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED : | |
1124 | (EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED); | |
806c35f5 | 1125 | /* FIXME - what if different memory types are in different csrows? */ |
680cbbbb | 1126 | mci->mod_name = EDAC_MOD_STR; |
37f04581 DT |
1127 | mci->mod_ver = E752X_REVISION; |
1128 | mci->dev = &pdev->dev; | |
806c35f5 | 1129 | |
537fba28 | 1130 | debugf3("%s(): init pvt\n", __func__); |
203333cb | 1131 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 1132 | pvt->dev_info = &e752x_devs[dev_idx]; |
13189525 | 1133 | pvt->mc_symmetric = ((ddrcsr & 0x10) != 0); |
e7ecd891 | 1134 | |
13189525 DT |
1135 | if (e752x_get_devs(pdev, dev_idx, pvt)) { |
1136 | edac_mc_free(mci); | |
1137 | return -ENODEV; | |
806c35f5 | 1138 | } |
806c35f5 | 1139 | |
537fba28 | 1140 | debugf3("%s(): more mci init\n", __func__); |
806c35f5 | 1141 | mci->ctl_name = pvt->dev_info->ctl_name; |
c4192705 | 1142 | mci->dev_name = pci_name(pdev); |
806c35f5 AC |
1143 | mci->edac_check = e752x_check; |
1144 | mci->ctl_page_to_phys = ctl_page_to_phys; | |
1145 | ||
7297c261 MG |
1146 | /* set the map type. 1 = normal, 0 = reversed |
1147 | * Must be set before e752x_init_csrows in case csrow mapping | |
1148 | * is reversed. | |
1149 | */ | |
37f04581 | 1150 | pci_read_config_byte(pdev, E752X_DRM, &stat8); |
806c35f5 AC |
1151 | pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f)); |
1152 | ||
7297c261 MG |
1153 | e752x_init_csrows(mci, pdev, ddrcsr); |
1154 | e752x_init_mem_map_table(pdev, pvt); | |
1155 | ||
5135b797 AK |
1156 | if (dev_idx == I3100) |
1157 | mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */ | |
1158 | else | |
1159 | mci->edac_cap |= EDAC_FLAG_NONE; | |
537fba28 | 1160 | debugf3("%s(): tolm, remapbase, remaplimit\n", __func__); |
e7ecd891 | 1161 | |
806c35f5 | 1162 | /* load the top of low memory, remap base, and remap limit vars */ |
37f04581 | 1163 | pci_read_config_word(pdev, E752X_TOLM, &pci_data); |
806c35f5 | 1164 | pvt->tolm = ((u32) pci_data) << 4; |
37f04581 | 1165 | pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data); |
806c35f5 | 1166 | pvt->remapbase = ((u32) pci_data) << 14; |
37f04581 | 1167 | pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data); |
806c35f5 | 1168 | pvt->remaplimit = ((u32) pci_data) << 14; |
537fba28 | 1169 | e752x_printk(KERN_INFO, |
052dfb45 DT |
1170 | "tolm = %x, remapbase = %x, remaplimit = %x\n", |
1171 | pvt->tolm, pvt->remapbase, pvt->remaplimit); | |
806c35f5 | 1172 | |
2d7bbb91 DT |
1173 | /* Here we assume that we will never see multiple instances of this |
1174 | * type of memory controller. The ID is therefore hardcoded to 0. | |
1175 | */ | |
b8f6f975 | 1176 | if (edac_mc_add_mc(mci)) { |
537fba28 | 1177 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
806c35f5 AC |
1178 | goto fail; |
1179 | } | |
1180 | ||
13189525 | 1181 | e752x_init_error_reporting_regs(pvt); |
203333cb | 1182 | e752x_get_error_info(mci, &discard); /* clear other MCH errors */ |
806c35f5 | 1183 | |
91b99041 DJ |
1184 | /* allocating generic PCI control info */ |
1185 | e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); | |
1186 | if (!e752x_pci) { | |
1187 | printk(KERN_WARNING | |
052dfb45 | 1188 | "%s(): Unable to create PCI control\n", __func__); |
91b99041 | 1189 | printk(KERN_WARNING |
052dfb45 DT |
1190 | "%s(): PCI error report via EDAC not setup\n", |
1191 | __func__); | |
91b99041 DJ |
1192 | } |
1193 | ||
806c35f5 | 1194 | /* get this far and it's successful */ |
537fba28 | 1195 | debugf3("%s(): success\n", __func__); |
806c35f5 AC |
1196 | return 0; |
1197 | ||
052dfb45 | 1198 | fail: |
13189525 DT |
1199 | pci_dev_put(pvt->dev_d0f0); |
1200 | pci_dev_put(pvt->dev_d0f1); | |
1201 | pci_dev_put(pvt->bridge_ck); | |
1202 | edac_mc_free(mci); | |
e7ecd891 | 1203 | |
13189525 | 1204 | return -ENODEV; |
806c35f5 AC |
1205 | } |
1206 | ||
1207 | /* returns count (>= 0), or negative on error */ | |
1208 | static int __devinit e752x_init_one(struct pci_dev *pdev, | |
052dfb45 | 1209 | const struct pci_device_id *ent) |
806c35f5 | 1210 | { |
537fba28 | 1211 | debugf0("%s()\n", __func__); |
806c35f5 AC |
1212 | |
1213 | /* wake up and enable device */ | |
203333cb | 1214 | if (pci_enable_device(pdev) < 0) |
806c35f5 | 1215 | return -EIO; |
e7ecd891 | 1216 | |
806c35f5 AC |
1217 | return e752x_probe1(pdev, ent->driver_data); |
1218 | } | |
1219 | ||
806c35f5 AC |
1220 | static void __devexit e752x_remove_one(struct pci_dev *pdev) |
1221 | { | |
1222 | struct mem_ctl_info *mci; | |
1223 | struct e752x_pvt *pvt; | |
1224 | ||
537fba28 | 1225 | debugf0("%s()\n", __func__); |
806c35f5 | 1226 | |
91b99041 DJ |
1227 | if (e752x_pci) |
1228 | edac_pci_release_generic_ctl(e752x_pci); | |
1229 | ||
37f04581 | 1230 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
806c35f5 AC |
1231 | return; |
1232 | ||
203333cb | 1233 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 AC |
1234 | pci_dev_put(pvt->dev_d0f0); |
1235 | pci_dev_put(pvt->dev_d0f1); | |
1236 | pci_dev_put(pvt->bridge_ck); | |
1237 | edac_mc_free(mci); | |
1238 | } | |
1239 | ||
806c35f5 | 1240 | static const struct pci_device_id e752x_pci_tbl[] __devinitdata = { |
e7ecd891 | 1241 | { |
203333cb DJ |
1242 | PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1243 | E7520}, | |
e7ecd891 | 1244 | { |
203333cb DJ |
1245 | PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1246 | E7525}, | |
e7ecd891 | 1247 | { |
203333cb DJ |
1248 | PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1249 | E7320}, | |
5135b797 AK |
1250 | { |
1251 | PCI_VEND_DEV(INTEL, 3100_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1252 | I3100}, | |
e7ecd891 | 1253 | { |
203333cb DJ |
1254 | 0, |
1255 | } /* 0 terminated list. */ | |
806c35f5 AC |
1256 | }; |
1257 | ||
1258 | MODULE_DEVICE_TABLE(pci, e752x_pci_tbl); | |
1259 | ||
806c35f5 | 1260 | static struct pci_driver e752x_driver = { |
680cbbbb | 1261 | .name = EDAC_MOD_STR, |
0d38b049 RD |
1262 | .probe = e752x_init_one, |
1263 | .remove = __devexit_p(e752x_remove_one), | |
1264 | .id_table = e752x_pci_tbl, | |
806c35f5 AC |
1265 | }; |
1266 | ||
da9bb1d2 | 1267 | static int __init e752x_init(void) |
806c35f5 AC |
1268 | { |
1269 | int pci_rc; | |
1270 | ||
537fba28 | 1271 | debugf3("%s()\n", __func__); |
806c35f5 AC |
1272 | pci_rc = pci_register_driver(&e752x_driver); |
1273 | return (pci_rc < 0) ? pci_rc : 0; | |
1274 | } | |
1275 | ||
806c35f5 AC |
1276 | static void __exit e752x_exit(void) |
1277 | { | |
537fba28 | 1278 | debugf3("%s()\n", __func__); |
806c35f5 AC |
1279 | pci_unregister_driver(&e752x_driver); |
1280 | } | |
1281 | ||
806c35f5 AC |
1282 | module_init(e752x_init); |
1283 | module_exit(e752x_exit); | |
1284 | ||
1285 | MODULE_LICENSE("GPL"); | |
1286 | MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n"); | |
5135b797 | 1287 | MODULE_DESCRIPTION("MC support for Intel e752x/3100 memory controllers"); |
96941026 | 1288 | |
1289 | module_param(force_function_unhide, int, 0444); | |
1290 | MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:" | |
203333cb | 1291 | " 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access"); |
c0d12172 DJ |
1292 | module_param(edac_op_state, int, 0444); |
1293 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |