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edac: remove unneeded functions and add static accessor
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / e752x_edac.c
CommitLineData
806c35f5
AC		 1/*
2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e752x_chips" below for supported chipsets
8 *
9 * Written by Tom Zimmerman
10 *
11 * Contributors:
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
15 *
da9bb1d2 16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
806c35f5
AC		 17 *
18 */
19
806c35f5
AC		 20#include <linux/module.h>
21#include <linux/init.h>
806c35f5
AC		 22#include <linux/pci.h>
23#include <linux/pci_ids.h>
806c35f5 24#include <linux/slab.h>
c0d12172 25#include <linux/edac.h>
20bcb7a8 26#include "edac_core.h"
806c35f5 27
20bcb7a8 28#define E752X_REVISION " Ver: 2.0.2 " __DATE__
929a40ec 29#define EDAC_MOD_STR "e752x_edac"
37f04581 30
96941026 31static int force_function_unhide;
94ee1cf5 32static int sysbus_parity = -1;
96941026 33
91b99041
DJ		 34static struct edac_pci_ctl_info *e752x_pci;
35
537fba28 36#define e752x_printk(level, fmt, arg...) \
e7ecd891 37 edac_printk(level, "e752x", fmt, ##arg)
537fba28
DP		 38
39#define e752x_mc_printk(mci, level, fmt, arg...) \
e7ecd891 40 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
537fba28 41
806c35f5
AC		 42#ifndef PCI_DEVICE_ID_INTEL_7520_0
43#define PCI_DEVICE_ID_INTEL_7520_0 0x3590
44#endif /* PCI_DEVICE_ID_INTEL_7520_0 */
45
46#ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
47#define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
48#endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
49
50#ifndef PCI_DEVICE_ID_INTEL_7525_0
51#define PCI_DEVICE_ID_INTEL_7525_0 0x359E
52#endif /* PCI_DEVICE_ID_INTEL_7525_0 */
53
54#ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
55#define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
56#endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
57
58#ifndef PCI_DEVICE_ID_INTEL_7320_0
59#define PCI_DEVICE_ID_INTEL_7320_0 0x3592
60#endif /* PCI_DEVICE_ID_INTEL_7320_0 */
61
62#ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
63#define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
64#endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
65
5135b797
AK		 66#ifndef PCI_DEVICE_ID_INTEL_3100_0
67#define PCI_DEVICE_ID_INTEL_3100_0 0x35B0
68#endif /* PCI_DEVICE_ID_INTEL_3100_0 */
69
70#ifndef PCI_DEVICE_ID_INTEL_3100_1_ERR
71#define PCI_DEVICE_ID_INTEL_3100_1_ERR 0x35B1
72#endif /* PCI_DEVICE_ID_INTEL_3100_1_ERR */
73
806c35f5
AC		 74#define E752X_NR_CSROWS 8 /* number of csrows */
75
806c35f5
AC		 76/* E752X register addresses - device 0 function 0 */
77#define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
78#define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
79 /*
80 * 31:30 Device width row 7
81 * 01=x8 10=x4 11=x8 DDR2
82 * 27:26 Device width row 6
83 * 23:22 Device width row 5
84 * 19:20 Device width row 4
85 * 15:14 Device width row 3
86 * 11:10 Device width row 2
87 * 7:6 Device width row 1
88 * 3:2 Device width row 0
89 */
90#define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
91 /* FIXME:IS THIS RIGHT? */
92 /*
93 * 22 Number channels 0=1,1=2
94 * 19:18 DRB Granularity 32/64MB
95 */
96#define E752X_DRM 0x80 /* Dimm mapping register */
97#define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
98 /*
99 * 14:12 1 single A, 2 single B, 3 dual
100 */
101#define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
102#define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
103#define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
104#define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
105
106/* E752X register addresses - device 0 function 1 */
107#define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
108#define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
109#define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
110#define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
111#define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
112#define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
113#define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
114#define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
115#define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
116#define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
117#define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
118#define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
119#define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
120#define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
121#define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
122#define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
123#define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
124#define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
125#define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
126#define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
127 /* error address register (32b) */
128 /*
129 * 31 Reserved
130 * 30:2 CE address (64 byte block 34:6)
131 * 1 Reserved
132 * 0 HiLoCS
133 */
134#define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
135 /* error address register (32b) */
136 /*
137 * 31 Reserved
138 * 30:2 CE address (64 byte block 34:6)
139 * 1 Reserved
140 * 0 HiLoCS
141 */
142#define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
143 /* error address register (32b) */
144 /*
145 * 31 Reserved
146 * 30:2 CE address (64 byte block 34:6)
147 * 1 Reserved
148 * 0 HiLoCS
149 */
150#define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
151 /* error address register (32b) */
152 /*
153 * 31 Reserved
154 * 30:2 CE address (64 byte block 34:6)
155 * 1 Reserved
156 * 0 HiLoCS
157 */
158#define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
159 /* error syndrome register (16b) */
160#define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
161 /* error syndrome register (16b) */
162#define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
163
5135b797
AK		 164/* 3100 IMCH specific register addresses - device 0 function 1 */
165#define I3100_NSI_FERR 0x48 /* NSI first error reg (32b) */
166#define I3100_NSI_NERR 0x4C /* NSI next error reg (32b) */
167#define I3100_NSI_SMICMD 0x54 /* NSI SMI command register (32b) */
168#define I3100_NSI_EMASK 0x90 /* NSI error mask register (32b) */
169
806c35f5
AC		 170/* ICH5R register addresses - device 30 function 0 */
171#define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
172#define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
173#define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
174
175enum e752x_chips {
176 E7520 = 0,
177 E7525 = 1,
5135b797
AK		 178 E7320 = 2,
179 I3100 = 3
806c35f5
AC		 180};
181
806c35f5
AC		 182struct e752x_pvt {
183 struct pci_dev *bridge_ck;
184 struct pci_dev *dev_d0f0;
185 struct pci_dev *dev_d0f1;
186 u32 tolm;
187 u32 remapbase;
188 u32 remaplimit;
189 int mc_symmetric;
190 u8 map[8];
191 int map_type;
192 const struct e752x_dev_info *dev_info;
193};
194
806c35f5
AC		 195struct e752x_dev_info {
196 u16 err_dev;
3847bccc 197 u16 ctl_dev;
806c35f5
AC		 198 const char *ctl_name;
199};
200
201struct e752x_error_info {
202 u32 ferr_global;
203 u32 nerr_global;
5135b797
AK		 204 u32 nsi_ferr; /* 3100 only */
205 u32 nsi_nerr; /* 3100 only */
206 u8 hi_ferr; /* all but 3100 */
207 u8 hi_nerr; /* all but 3100 */
806c35f5
AC		 208 u16 sysbus_ferr;
209 u16 sysbus_nerr;
210 u8 buf_ferr;
211 u8 buf_nerr;
212 u16 dram_ferr;
213 u16 dram_nerr;
214 u32 dram_sec1_add;
215 u32 dram_sec2_add;
216 u16 dram_sec1_syndrome;
217 u16 dram_sec2_syndrome;
218 u32 dram_ded_add;
219 u32 dram_scrb_add;
220 u32 dram_retr_add;
221};
222
223static const struct e752x_dev_info e752x_devs[] = {
224 [E7520] = {
052dfb45
DT		 225 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
226 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
227 .ctl_name = "E7520"},
806c35f5 228 [E7525] = {
052dfb45
DT		 229 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
230 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
231 .ctl_name = "E7525"},
806c35f5 232 [E7320] = {
052dfb45
DT		 233 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
234 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
235 .ctl_name = "E7320"},
5135b797
AK		 236 [I3100] = {
237 .err_dev = PCI_DEVICE_ID_INTEL_3100_1_ERR,
238 .ctl_dev = PCI_DEVICE_ID_INTEL_3100_0,
239 .ctl_name = "3100"},
806c35f5
AC		 240};
241
806c35f5 242static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
052dfb45 243 unsigned long page)
806c35f5
AC		 244{
245 u32 remap;
203333cb 246 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 247
537fba28 248 debugf3("%s()\n", __func__);
806c35f5
AC		 249
250 if (page < pvt->tolm)
251 return page;
e7ecd891 252
806c35f5
AC		 253 if ((page >= 0x100000) && (page < pvt->remapbase))
254 return page;
e7ecd891 255
806c35f5 256 remap = (page - pvt->tolm) + pvt->remapbase;
e7ecd891 257
806c35f5
AC		 258 if (remap < pvt->remaplimit)
259 return remap;
e7ecd891 260
537fba28 261 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
806c35f5
AC		 262 return pvt->tolm - 1;
263}
264
265static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
052dfb45 266 u32 sec1_add, u16 sec1_syndrome)
806c35f5
AC		 267{
268 u32 page;
269 int row;
270 int channel;
271 int i;
203333cb 272 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 273
537fba28 274 debugf3("%s()\n", __func__);
806c35f5
AC		 275
276 /* convert the addr to 4k page */
277 page = sec1_add >> (PAGE_SHIFT - 4);
278
279 /* FIXME - check for -1 */
280 if (pvt->mc_symmetric) {
281 /* chip select are bits 14 & 13 */
282 row = ((page >> 1) & 3);
537fba28 283 e752x_printk(KERN_WARNING,
052dfb45
DT		 284 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
285 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
286 pvt->map[4], pvt->map[5], pvt->map[6],
287 pvt->map[7]);
806c35f5
AC		 288
289 /* test for channel remapping */
290 for (i = 0; i < 8; i++) {
291 if (pvt->map[i] == row)
292 break;
293 }
e7ecd891 294
537fba28 295 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
e7ecd891 296
806c35f5
AC		 297 if (i < 8)
298 row = i;
299 else
537fba28 300 e752x_mc_printk(mci, KERN_WARNING,
203333cb
DJ		 301 "row %d not found in remap table\n",
302 row);
806c35f5
AC		 303 } else
304 row = edac_mc_find_csrow_by_page(mci, page);
e7ecd891 305
806c35f5
AC		 306 /* 0 = channel A, 1 = channel B */
307 channel = !(error_one & 1);
308
84db003f
MC		 309 /* e752x mc reads 34:6 of the DRAM linear address */
310 edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4),
052dfb45 311 sec1_syndrome, row, channel, "e752x CE");
806c35f5
AC		 312}
313
806c35f5 314static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
052dfb45
DT		 315 u32 sec1_add, u16 sec1_syndrome, int *error_found,
316 int handle_error)
806c35f5
AC		 317{
318 *error_found = 1;
319
320 if (handle_error)
321 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
322}
323
e7ecd891 324static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
052dfb45 325 u32 ded_add, u32 scrb_add)
806c35f5
AC		 326{
327 u32 error_2b, block_page;
328 int row;
203333cb 329 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 330
537fba28 331 debugf3("%s()\n", __func__);
806c35f5
AC		 332
333 if (error_one & 0x0202) {
334 error_2b = ded_add;
e7ecd891 335
806c35f5
AC		 336 /* convert to 4k address */
337 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 338
806c35f5 339 row = pvt->mc_symmetric ?
052dfb45
DT		 340 /* chip select are bits 14 & 13 */
341 ((block_page >> 1) & 3) :
342 edac_mc_find_csrow_by_page(mci, block_page);
e7ecd891 343
84db003f
MC		 344 /* e752x mc reads 34:6 of the DRAM linear address */
345 edac_mc_handle_ue(mci, block_page,
052dfb45
DT		 346 offset_in_page(error_2b << 4),
347 row, "e752x UE from Read");
806c35f5
AC		 348 }
349 if (error_one & 0x0404) {
350 error_2b = scrb_add;
e7ecd891 351
806c35f5
AC		 352 /* convert to 4k address */
353 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 354
806c35f5 355 row = pvt->mc_symmetric ?
052dfb45
DT		 356 /* chip select are bits 14 & 13 */
357 ((block_page >> 1) & 3) :
358 edac_mc_find_csrow_by_page(mci, block_page);
e7ecd891 359
84db003f
MC		 360 /* e752x mc reads 34:6 of the DRAM linear address */
361 edac_mc_handle_ue(mci, block_page,
052dfb45
DT		 362 offset_in_page(error_2b << 4),
363 row, "e752x UE from Scruber");
806c35f5
AC		 364 }
365}
366
367static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
052dfb45
DT		 368 u32 ded_add, u32 scrb_add, int *error_found,
369 int handle_error)
806c35f5
AC		 370{
371 *error_found = 1;
372
373 if (handle_error)
374 do_process_ue(mci, error_one, ded_add, scrb_add);
375}
376
377static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
203333cb 378 int *error_found, int handle_error)
806c35f5
AC		 379{
380 *error_found = 1;
381
382 if (!handle_error)
383 return;
384
537fba28 385 debugf3("%s()\n", __func__);
806c35f5
AC		 386 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
387}
388
389static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
203333cb 390 u32 retry_add)
806c35f5
AC		 391{
392 u32 error_1b, page;
393 int row;
203333cb 394 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5
AC		 395
396 error_1b = retry_add;
203333cb
DJ		 397 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
398 row = pvt->mc_symmetric ? ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
052dfb45 399 edac_mc_find_csrow_by_page(mci, page);
537fba28 400 e752x_mc_printk(mci, KERN_WARNING,
203333cb
DJ		 401 "CE page 0x%lx, row %d : Memory read retry\n",
402 (long unsigned int)page, row);
806c35f5
AC		 403}
404
405static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
052dfb45
DT		 406 u32 retry_add, int *error_found,
407 int handle_error)
806c35f5
AC		 408{
409 *error_found = 1;
410
411 if (handle_error)
412 do_process_ded_retry(mci, error, retry_add);
413}
414
415static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
203333cb 416 int *error_found, int handle_error)
806c35f5
AC		 417{
418 *error_found = 1;
419
420 if (handle_error)
537fba28 421 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
806c35f5
AC		 422}
423
da9bb1d2 424static char *global_message[11] = {
806c35f5
AC		 425 "PCI Express C1", "PCI Express C", "PCI Express B1",
426 "PCI Express B", "PCI Express A1", "PCI Express A",
5135b797 427 "DMA Controler", "HUB or NS Interface", "System Bus",
806c35f5
AC		 428 "DRAM Controler", "Internal Buffer"
429};
430
da9bb1d2 431static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
806c35f5
AC		 432
433static void do_global_error(int fatal, u32 errors)
434{
435 int i;
436
437 for (i = 0; i < 11; i++) {
438 if (errors & (1 << i))
537fba28 439 e752x_printk(KERN_WARNING, "%sError %s\n",
052dfb45 440 fatal_message[fatal], global_message[i]);
806c35f5
AC		 441 }
442}
443
444static inline void global_error(int fatal, u32 errors, int *error_found,
203333cb 445 int handle_error)
806c35f5
AC		 446{
447 *error_found = 1;
448
449 if (handle_error)
450 do_global_error(fatal, errors);
451}
452
da9bb1d2 453static char *hub_message[7] = {
806c35f5
AC		 454 "HI Address or Command Parity", "HI Illegal Access",
455 "HI Internal Parity", "Out of Range Access",
456 "HI Data Parity", "Enhanced Config Access",
457 "Hub Interface Target Abort"
458};
459
460static void do_hub_error(int fatal, u8 errors)
461{
462 int i;
463
464 for (i = 0; i < 7; i++) {
465 if (errors & (1 << i))
537fba28 466 e752x_printk(KERN_WARNING, "%sError %s\n",
052dfb45 467 fatal_message[fatal], hub_message[i]);
806c35f5
AC		 468 }
469}
470
471static inline void hub_error(int fatal, u8 errors, int *error_found,
052dfb45 472 int handle_error)
806c35f5
AC		 473{
474 *error_found = 1;
475
476 if (handle_error)
477 do_hub_error(fatal, errors);
478}
479
5135b797
AK		 480#define NSI_FATAL_MASK 0x0c080081
481#define NSI_NON_FATAL_MASK 0x23a0ba64
482#define NSI_ERR_MASK (NSI_FATAL_MASK | NSI_NON_FATAL_MASK)
483
484static char *nsi_message[30] = {
485 "NSI Link Down", /* NSI_FERR/NSI_NERR bit 0, fatal error */
486 "", /* reserved */
487 "NSI Parity Error", /* bit 2, non-fatal */
488 "", /* reserved */
489 "", /* reserved */
490 "Correctable Error Message", /* bit 5, non-fatal */
491 "Non-Fatal Error Message", /* bit 6, non-fatal */
492 "Fatal Error Message", /* bit 7, fatal */
493 "", /* reserved */
494 "Receiver Error", /* bit 9, non-fatal */
495 "", /* reserved */
496 "Bad TLP", /* bit 11, non-fatal */
497 "Bad DLLP", /* bit 12, non-fatal */
498 "REPLAY_NUM Rollover", /* bit 13, non-fatal */
499 "", /* reserved */
500 "Replay Timer Timeout", /* bit 15, non-fatal */
501 "", /* reserved */
502 "", /* reserved */
503 "", /* reserved */
504 "Data Link Protocol Error", /* bit 19, fatal */
505 "", /* reserved */
506 "Poisoned TLP", /* bit 21, non-fatal */
507 "", /* reserved */
508 "Completion Timeout", /* bit 23, non-fatal */
509 "Completer Abort", /* bit 24, non-fatal */
510 "Unexpected Completion", /* bit 25, non-fatal */
511 "Receiver Overflow", /* bit 26, fatal */
512 "Malformed TLP", /* bit 27, fatal */
513 "", /* reserved */
514 "Unsupported Request" /* bit 29, non-fatal */
515};
516
517static void do_nsi_error(int fatal, u32 errors)
518{
519 int i;
520
521 for (i = 0; i < 30; i++) {
522 if (errors & (1 << i))
523 printk(KERN_WARNING "%sError %s\n",
524 fatal_message[fatal], nsi_message[i]);
525 }
526}
527
528static inline void nsi_error(int fatal, u32 errors, int *error_found,
529 int handle_error)
530{
531 *error_found = 1;
532
533 if (handle_error)
534 do_nsi_error(fatal, errors);
535}
536
da9bb1d2 537static char *membuf_message[4] = {
806c35f5
AC		 538 "Internal PMWB to DRAM parity",
539 "Internal PMWB to System Bus Parity",
540 "Internal System Bus or IO to PMWB Parity",
541 "Internal DRAM to PMWB Parity"
542};
543
544static void do_membuf_error(u8 errors)
545{
546 int i;
547
548 for (i = 0; i < 4; i++) {
549 if (errors & (1 << i))
537fba28 550 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
052dfb45 551 membuf_message[i]);
806c35f5
AC		 552 }
553}
554
555static inline void membuf_error(u8 errors, int *error_found, int handle_error)
556{
557 *error_found = 1;
558
559 if (handle_error)
560 do_membuf_error(errors);
561}
562
e009356f 563static char *sysbus_message[10] = {
806c35f5
AC		 564 "Addr or Request Parity",
565 "Data Strobe Glitch",
566 "Addr Strobe Glitch",
567 "Data Parity",
568 "Addr Above TOM",
569 "Non DRAM Lock Error",
570 "MCERR", "BINIT",
571 "Memory Parity",
572 "IO Subsystem Parity"
573};
574
575static void do_sysbus_error(int fatal, u32 errors)
576{
577 int i;
578
579 for (i = 0; i < 10; i++) {
580 if (errors & (1 << i))
537fba28 581 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
052dfb45 582 fatal_message[fatal], sysbus_message[i]);
806c35f5
AC		 583 }
584}
585
586static inline void sysbus_error(int fatal, u32 errors, int *error_found,
203333cb 587 int handle_error)
806c35f5
AC		 588{
589 *error_found = 1;
590
591 if (handle_error)
592 do_sysbus_error(fatal, errors);
593}
594
e7ecd891 595static void e752x_check_hub_interface(struct e752x_error_info *info,
052dfb45 596 int *error_found, int handle_error)
806c35f5
AC		 597{
598 u8 stat8;
599
600 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
e7ecd891 601
806c35f5 602 stat8 = info->hi_ferr;
e7ecd891 603
203333cb 604 if (stat8 & 0x7f) { /* Error, so process */
806c35f5 605 stat8 &= 0x7f;
e7ecd891 606
203333cb 607 if (stat8 & 0x2b)
806c35f5 608 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 609
203333cb 610 if (stat8 & 0x54)
806c35f5
AC		 611 hub_error(0, stat8 & 0x54, error_found, handle_error);
612 }
613 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
e7ecd891 614
806c35f5 615 stat8 = info->hi_nerr;
e7ecd891 616
203333cb 617 if (stat8 & 0x7f) { /* Error, so process */
806c35f5 618 stat8 &= 0x7f;
e7ecd891 619
806c35f5
AC		 620 if (stat8 & 0x2b)
621 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 622
203333cb 623 if (stat8 & 0x54)
806c35f5
AC		 624 hub_error(0, stat8 & 0x54, error_found, handle_error);
625 }
626}
627
5135b797
AK		 628static void e752x_check_ns_interface(struct e752x_error_info *info,
629 int *error_found, int handle_error)
630{
631 u32 stat32;
632
633 stat32 = info->nsi_ferr;
634 if (stat32 & NSI_ERR_MASK) { /* Error, so process */
635 if (stat32 & NSI_FATAL_MASK) /* check for fatal errors */
636 nsi_error(1, stat32 & NSI_FATAL_MASK, error_found,
637 handle_error);
638 if (stat32 & NSI_NON_FATAL_MASK) /* check for non-fatal ones */
639 nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found,
640 handle_error);
641 }
642 stat32 = info->nsi_nerr;
643 if (stat32 & NSI_ERR_MASK) {
644 if (stat32 & NSI_FATAL_MASK)
645 nsi_error(1, stat32 & NSI_FATAL_MASK, error_found,
646 handle_error);
647 if (stat32 & NSI_NON_FATAL_MASK)
648 nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found,
649 handle_error);
650 }
651}
652
e7ecd891 653static void e752x_check_sysbus(struct e752x_error_info *info,
052dfb45 654 int *error_found, int handle_error)
806c35f5
AC		 655{
656 u32 stat32, error32;
657
658 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
659 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
660
661 if (stat32 == 0)
203333cb 662 return; /* no errors */
806c35f5
AC		 663
664 error32 = (stat32 >> 16) & 0x3ff;
665 stat32 = stat32 & 0x3ff;
e7ecd891 666
203333cb 667 if (stat32 & 0x087)
dfb2a763 668 sysbus_error(1, stat32 & 0x087, error_found, handle_error);
e7ecd891 669
203333cb 670 if (stat32 & 0x378)
dfb2a763 671 sysbus_error(0, stat32 & 0x378, error_found, handle_error);
e7ecd891 672
203333cb 673 if (error32 & 0x087)
dfb2a763 674 sysbus_error(1, error32 & 0x087, error_found, handle_error);
e7ecd891 675
203333cb 676 if (error32 & 0x378)
dfb2a763 677 sysbus_error(0, error32 & 0x378, error_found, handle_error);
806c35f5
AC		 678}
679
203333cb 680static void e752x_check_membuf(struct e752x_error_info *info,
052dfb45 681 int *error_found, int handle_error)
806c35f5
AC		 682{
683 u8 stat8;
684
685 stat8 = info->buf_ferr;
e7ecd891 686
203333cb 687 if (stat8 & 0x0f) { /* Error, so process */
806c35f5
AC		 688 stat8 &= 0x0f;
689 membuf_error(stat8, error_found, handle_error);
690 }
e7ecd891 691
806c35f5 692 stat8 = info->buf_nerr;
e7ecd891 693
203333cb 694 if (stat8 & 0x0f) { /* Error, so process */
806c35f5
AC		 695 stat8 &= 0x0f;
696 membuf_error(stat8, error_found, handle_error);
697 }
698}
699
203333cb 700static void e752x_check_dram(struct mem_ctl_info *mci,
052dfb45
DT		 701 struct e752x_error_info *info, int *error_found,
702 int handle_error)
806c35f5
AC		 703{
704 u16 error_one, error_next;
705
706 error_one = info->dram_ferr;
707 error_next = info->dram_nerr;
708
709 /* decode and report errors */
203333cb 710 if (error_one & 0x0101) /* check first error correctable */
806c35f5 711 process_ce(mci, error_one, info->dram_sec1_add,
052dfb45 712 info->dram_sec1_syndrome, error_found, handle_error);
806c35f5 713
203333cb 714 if (error_next & 0x0101) /* check next error correctable */
806c35f5 715 process_ce(mci, error_next, info->dram_sec2_add,
052dfb45 716 info->dram_sec2_syndrome, error_found, handle_error);
806c35f5 717
203333cb 718 if (error_one & 0x4040)
806c35f5
AC		 719 process_ue_no_info_wr(mci, error_found, handle_error);
720
203333cb 721 if (error_next & 0x4040)
806c35f5
AC		 722 process_ue_no_info_wr(mci, error_found, handle_error);
723
203333cb 724 if (error_one & 0x2020)
806c35f5 725 process_ded_retry(mci, error_one, info->dram_retr_add,
052dfb45 726 error_found, handle_error);
806c35f5 727
203333cb 728 if (error_next & 0x2020)
806c35f5 729 process_ded_retry(mci, error_next, info->dram_retr_add,
052dfb45 730 error_found, handle_error);
806c35f5 731
203333cb
DJ		 732 if (error_one & 0x0808)
733 process_threshold_ce(mci, error_one, error_found, handle_error);
806c35f5 734
203333cb 735 if (error_next & 0x0808)
806c35f5 736 process_threshold_ce(mci, error_next, error_found,
052dfb45 737 handle_error);
806c35f5 738
203333cb 739 if (error_one & 0x0606)
806c35f5 740 process_ue(mci, error_one, info->dram_ded_add,
052dfb45 741 info->dram_scrb_add, error_found, handle_error);
806c35f5 742
203333cb 743 if (error_next & 0x0606)
806c35f5 744 process_ue(mci, error_next, info->dram_ded_add,
052dfb45 745 info->dram_scrb_add, error_found, handle_error);
806c35f5
AC		 746}
747
203333cb
DJ		 748static void e752x_get_error_info(struct mem_ctl_info *mci,
749 struct e752x_error_info *info)
806c35f5
AC		 750{
751 struct pci_dev *dev;
752 struct e752x_pvt *pvt;
753
754 memset(info, 0, sizeof(*info));
203333cb 755 pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 756 dev = pvt->dev_d0f1;
806c35f5
AC		 757 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
758
759 if (info->ferr_global) {
5135b797
AK		 760 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
761 pci_read_config_dword(dev, I3100_NSI_FERR,
762 &info->nsi_ferr);
763 info->hi_ferr = 0;
764 } else {
765 pci_read_config_byte(dev, E752X_HI_FERR,
766 &info->hi_ferr);
767 info->nsi_ferr = 0;
768 }
806c35f5 769 pci_read_config_word(dev, E752X_SYSBUS_FERR,
052dfb45 770 &info->sysbus_ferr);
806c35f5 771 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
203333cb 772 pci_read_config_word(dev, E752X_DRAM_FERR, &info->dram_ferr);
806c35f5 773 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
052dfb45 774 &info->dram_sec1_add);
806c35f5 775 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
052dfb45 776 &info->dram_sec1_syndrome);
806c35f5 777 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
052dfb45 778 &info->dram_ded_add);
806c35f5 779 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
052dfb45 780 &info->dram_scrb_add);
806c35f5 781 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
052dfb45 782 &info->dram_retr_add);
806c35f5 783
5135b797 784 /* ignore the reserved bits just in case */
806c35f5
AC		 785 if (info->hi_ferr & 0x7f)
786 pci_write_config_byte(dev, E752X_HI_FERR,
052dfb45 787 info->hi_ferr);
806c35f5 788
5135b797
AK		 789 if (info->nsi_ferr & NSI_ERR_MASK)
790 pci_write_config_dword(dev, I3100_NSI_FERR,
791 info->nsi_ferr);
792
806c35f5
AC		 793 if (info->sysbus_ferr)
794 pci_write_config_word(dev, E752X_SYSBUS_FERR,
052dfb45 795 info->sysbus_ferr);
806c35f5
AC		 796
797 if (info->buf_ferr & 0x0f)
798 pci_write_config_byte(dev, E752X_BUF_FERR,
052dfb45 799 info->buf_ferr);
806c35f5
AC		 800
801 if (info->dram_ferr)
802 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
203333cb 803 info->dram_ferr, info->dram_ferr);
806c35f5
AC		 804
805 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
052dfb45 806 info->ferr_global);
806c35f5
AC		 807 }
808
809 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
810
811 if (info->nerr_global) {
5135b797
AK		 812 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
813 pci_read_config_dword(dev, I3100_NSI_NERR,
814 &info->nsi_nerr);
815 info->hi_nerr = 0;
816 } else {
817 pci_read_config_byte(dev, E752X_HI_NERR,
818 &info->hi_nerr);
819 info->nsi_nerr = 0;
820 }
806c35f5 821 pci_read_config_word(dev, E752X_SYSBUS_NERR,
052dfb45 822 &info->sysbus_nerr);
806c35f5 823 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
203333cb 824 pci_read_config_word(dev, E752X_DRAM_NERR, &info->dram_nerr);
806c35f5 825 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
052dfb45 826 &info->dram_sec2_add);
806c35f5 827 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
052dfb45 828 &info->dram_sec2_syndrome);
806c35f5
AC		 829
830 if (info->hi_nerr & 0x7f)
831 pci_write_config_byte(dev, E752X_HI_NERR,
052dfb45 832 info->hi_nerr);
806c35f5 833
5135b797
AK		 834 if (info->nsi_nerr & NSI_ERR_MASK)
835 pci_write_config_dword(dev, I3100_NSI_NERR,
836 info->nsi_nerr);
837
806c35f5
AC		 838 if (info->sysbus_nerr)
839 pci_write_config_word(dev, E752X_SYSBUS_NERR,
052dfb45 840 info->sysbus_nerr);
806c35f5
AC		 841
842 if (info->buf_nerr & 0x0f)
843 pci_write_config_byte(dev, E752X_BUF_NERR,
052dfb45 844 info->buf_nerr);
806c35f5
AC		 845
846 if (info->dram_nerr)
847 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
203333cb 848 info->dram_nerr, info->dram_nerr);
806c35f5
AC		 849
850 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
052dfb45 851 info->nerr_global);
806c35f5
AC		 852 }
853}
854
203333cb 855static int e752x_process_error_info(struct mem_ctl_info *mci,
052dfb45
DT		 856 struct e752x_error_info *info,
857 int handle_errors)
806c35f5
AC		 858{
859 u32 error32, stat32;
860 int error_found;
861
862 error_found = 0;
863 error32 = (info->ferr_global >> 18) & 0x3ff;
864 stat32 = (info->ferr_global >> 4) & 0x7ff;
865
866 if (error32)
867 global_error(1, error32, &error_found, handle_errors);
868
869 if (stat32)
870 global_error(0, stat32, &error_found, handle_errors);
871
872 error32 = (info->nerr_global >> 18) & 0x3ff;
873 stat32 = (info->nerr_global >> 4) & 0x7ff;
874
875 if (error32)
876 global_error(1, error32, &error_found, handle_errors);
877
878 if (stat32)
879 global_error(0, stat32, &error_found, handle_errors);
880
881 e752x_check_hub_interface(info, &error_found, handle_errors);
5135b797 882 e752x_check_ns_interface(info, &error_found, handle_errors);
806c35f5
AC		 883 e752x_check_sysbus(info, &error_found, handle_errors);
884 e752x_check_membuf(info, &error_found, handle_errors);
885 e752x_check_dram(mci, info, &error_found, handle_errors);
886 return error_found;
887}
888
889static void e752x_check(struct mem_ctl_info *mci)
890{
891 struct e752x_error_info info;
e7ecd891 892
537fba28 893 debugf3("%s()\n", __func__);
806c35f5
AC		 894 e752x_get_error_info(mci, &info);
895 e752x_process_error_info(mci, &info, 1);
896}
897
13189525
DT		 898/* Return 1 if dual channel mode is active. Else return 0. */
899static inline int dual_channel_active(u16 ddrcsr)
900{
901 return (((ddrcsr >> 12) & 3) == 3);
902}
903
7297c261
MG		 904/* Remap csrow index numbers if map_type is "reverse"
905 */
906static inline int remap_csrow_index(struct mem_ctl_info *mci, int index)
907{
908 struct e752x_pvt *pvt = mci->pvt_info;
909
910 if (!pvt->map_type)
911 return (7 - index);
912
913 return (index);
914}
915
13189525 916static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
052dfb45 917 u16 ddrcsr)
13189525
DT		 918{
919 struct csrow_info *csrow;
920 unsigned long last_cumul_size;
921 int index, mem_dev, drc_chan;
203333cb
DJ		 922 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
923 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
13189525
DT		 924 u8 value;
925 u32 dra, drc, cumul_size;
926
9962fd01 927 dra = 0;
203333cb 928 for (index = 0; index < 4; index++) {
9962fd01 929 u8 dra_reg;
203333cb 930 pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg);
9962fd01
BP		 931 dra |= dra_reg << (index * 8);
932 }
13189525
DT		 933 pci_read_config_dword(pdev, E752X_DRC, &drc);
934 drc_chan = dual_channel_active(ddrcsr);
203333cb 935 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
13189525
DT		 936 drc_ddim = (drc >> 20) & 0x3;
937
938 /* The dram row boundary (DRB) reg values are boundary address for
939 * each DRAM row with a granularity of 64 or 128MB (single/dual
940 * channel operation). DRB regs are cumulative; therefore DRB7 will
941 * contain the total memory contained in all eight rows.
942 */
943 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
944 /* mem_dev 0=x8, 1=x4 */
945 mem_dev = (dra >> (index * 4 + 2)) & 0x3;
7297c261 946 csrow = &mci->csrows[remap_csrow_index(mci, index)];
13189525
DT		 947
948 mem_dev = (mem_dev == 2);
949 pci_read_config_byte(pdev, E752X_DRB + index, &value);
950 /* convert a 128 or 64 MiB DRB to a page size. */
951 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
952 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
953 cumul_size);
954 if (cumul_size == last_cumul_size)
955 continue; /* not populated */
956
957 csrow->first_page = last_cumul_size;
958 csrow->last_page = cumul_size - 1;
959 csrow->nr_pages = cumul_size - last_cumul_size;
960 last_cumul_size = cumul_size;
961 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
962 csrow->mtype = MEM_RDDR; /* only one type supported */
963 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
964
965 /*
966 * if single channel or x8 devices then SECDED
967 * if dual channel and x4 then S4ECD4ED
968 */
969 if (drc_ddim) {
970 if (drc_chan && mem_dev) {
971 csrow->edac_mode = EDAC_S4ECD4ED;
972 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
973 } else {
974 csrow->edac_mode = EDAC_SECDED;
975 mci->edac_cap |= EDAC_FLAG_SECDED;
976 }
977 } else
978 csrow->edac_mode = EDAC_NONE;
979 }
980}
981
982static void e752x_init_mem_map_table(struct pci_dev *pdev,
052dfb45 983 struct e752x_pvt *pvt)
806c35f5 984{
806c35f5 985 int index;
7297c261 986 u8 value, last, row;
13189525
DT		 987
988 last = 0;
989 row = 0;
990
991 for (index = 0; index < 8; index += 2) {
992 pci_read_config_byte(pdev, E752X_DRB + index, &value);
993 /* test if there is a dimm in this slot */
994 if (value == last) {
995 /* no dimm in the slot, so flag it as empty */
996 pvt->map[index] = 0xff;
997 pvt->map[index + 1] = 0xff;
203333cb 998 } else { /* there is a dimm in the slot */
13189525
DT		 999 pvt->map[index] = row;
1000 row++;
1001 last = value;
1002 /* test the next value to see if the dimm is double
1003 * sided
1004 */
1005 pci_read_config_byte(pdev, E752X_DRB + index + 1,
052dfb45
DT		 1006 &value);
1007
1008 /* the dimm is single sided, so flag as empty */
1009 /* this is a double sided dimm to save the next row #*/
1010 pvt->map[index + 1] = (value == last) ? 0xff : row;
13189525
DT		 1011 row++;
1012 last = value;
1013 }
1014 }
13189525
DT		 1015}
1016
1017/* Return 0 on success or 1 on failure. */
1018static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
052dfb45 1019 struct e752x_pvt *pvt)
13189525
DT		 1020{
1021 struct pci_dev *dev;
1022
1023 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
203333cb 1024 pvt->dev_info->err_dev, pvt->bridge_ck);
13189525
DT		 1025
1026 if (pvt->bridge_ck == NULL)
1027 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
1028 PCI_DEVFN(0, 1));
1029
1030 if (pvt->bridge_ck == NULL) {
1031 e752x_printk(KERN_ERR, "error reporting device not found:"
052dfb45
DT		 1032 "vendor %x device 0x%x (broken BIOS?)\n",
1033 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
13189525
DT		 1034 return 1;
1035 }
1036
1037 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
052dfb45 1038 NULL);
13189525
DT		 1039
1040 if (dev == NULL)
1041 goto fail;
1042
1043 pvt->dev_d0f0 = dev;
1044 pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
1045
1046 return 0;
1047
052dfb45 1048fail:
13189525
DT		 1049 pci_dev_put(pvt->bridge_ck);
1050 return 1;
1051}
1052
94ee1cf5
PT		 1053/* Setup system bus parity mask register.
1054 * Sysbus parity supported on:
1055 * e7320/e7520/e7525 + Xeon
1056 * i3100 + Xeon/Celeron
1057 * Sysbus parity not supported on:
1058 * i3100 + Pentium M/Celeron M/Core Duo/Core2 Duo
1059 */
1060static void e752x_init_sysbus_parity_mask(struct e752x_pvt *pvt)
1061{
1062 char *cpu_id = cpu_data(0).x86_model_id;
1063 struct pci_dev *dev = pvt->dev_d0f1;
1064 int enable = 1;
1065
1066 /* Allow module paramter override, else see if CPU supports parity */
1067 if (sysbus_parity != -1) {
1068 enable = sysbus_parity;
1069 } else if (cpu_id[0] &&
1070 ((strstr(cpu_id, "Pentium") && strstr(cpu_id, " M ")) ||
1071 (strstr(cpu_id, "Celeron") && strstr(cpu_id, " M ")) ||
1072 (strstr(cpu_id, "Core") && strstr(cpu_id, "Duo")))) {
1073 e752x_printk(KERN_INFO, "System Bus Parity not "
1074 "supported by CPU, disabling\n");
1075 enable = 0;
1076 }
1077
1078 if (enable)
1079 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0000);
1080 else
1081 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0309);
1082}
1083
13189525
DT		 1084static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
1085{
1086 struct pci_dev *dev;
1087
1088 dev = pvt->dev_d0f1;
1089 /* Turn off error disable & SMI in case the BIOS turned it on */
5135b797
AK		 1090 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
1091 pci_write_config_dword(dev, I3100_NSI_EMASK, 0);
1092 pci_write_config_dword(dev, I3100_NSI_SMICMD, 0);
1093 } else {
1094 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
1095 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
1096 }
94ee1cf5
PT		 1097
1098 e752x_init_sysbus_parity_mask(pvt);
1099
13189525
DT		 1100 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
1101 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
1102 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
1103 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
1104 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
1105}
1106
1107static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1108{
3847bccc 1109 u16 pci_data;
806c35f5 1110 u8 stat8;
13189525
DT		 1111 struct mem_ctl_info *mci;
1112 struct e752x_pvt *pvt;
806c35f5 1113 u16 ddrcsr;
203333cb 1114 int drc_chan; /* Number of channels 0=1chan,1=2chan */
749ede57 1115 struct e752x_error_info discard;
806c35f5 1116
537fba28 1117 debugf0("%s(): mci\n", __func__);
806c35f5
AC		 1118 debugf0("Starting Probe1\n");
1119
c0d12172 1120 /* make sure error reporting method is sane */
203333cb
DJ		 1121 switch (edac_op_state) {
1122 case EDAC_OPSTATE_POLL:
1123 case EDAC_OPSTATE_NMI:
1124 break;
1125 default:
1126 edac_op_state = EDAC_OPSTATE_POLL;
1127 break;
c0d12172
DJ		 1128 }
1129
96941026 1130 /* check to see if device 0 function 1 is enabled; if it isn't, we
1131 * assume the BIOS has reserved it for a reason and is expecting
1132 * exclusive access, we take care not to violate that assumption and
1133 * fail the probe. */
806c35f5 1134 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
96941026 1135 if (!force_function_unhide && !(stat8 & (1 << 5))) {
1136 printk(KERN_INFO "Contact your BIOS vendor to see if the "
052dfb45 1137 "E752x error registers can be safely un-hidden\n");
f9b5a5d1 1138 return -ENODEV;
96941026 1139 }
806c35f5
AC		 1140 stat8 |= (1 << 5);
1141 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
1142
806c35f5
AC		 1143 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
1144 /* FIXME: should check >>12 or 0xf, true for all? */
1145 /* Dual channel = 1, Single channel = 0 */
13189525 1146 drc_chan = dual_channel_active(ddrcsr);
806c35f5 1147
b8f6f975 1148 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1, 0);
806c35f5
AC		 1149
1150 if (mci == NULL) {
13189525 1151 return -ENOMEM;
806c35f5
AC		 1152 }
1153
537fba28 1154 debugf3("%s(): init mci\n", __func__);
806c35f5 1155 mci->mtype_cap = MEM_FLAG_RDDR;
5135b797
AK		 1156 /* 3100 IMCH supports SECDEC only */
1157 mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED :
1158 (EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED);
806c35f5 1159 /* FIXME - what if different memory types are in different csrows? */
680cbbbb 1160 mci->mod_name = EDAC_MOD_STR;
37f04581
DT		 1161 mci->mod_ver = E752X_REVISION;
1162 mci->dev = &pdev->dev;
806c35f5 1163
537fba28 1164 debugf3("%s(): init pvt\n", __func__);
203333cb 1165 pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 1166 pvt->dev_info = &e752x_devs[dev_idx];
13189525 1167 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
e7ecd891 1168
13189525
DT		 1169 if (e752x_get_devs(pdev, dev_idx, pvt)) {
1170 edac_mc_free(mci);
1171 return -ENODEV;
806c35f5 1172 }
806c35f5 1173
537fba28 1174 debugf3("%s(): more mci init\n", __func__);
806c35f5 1175 mci->ctl_name = pvt->dev_info->ctl_name;
c4192705 1176 mci->dev_name = pci_name(pdev);
806c35f5
AC		 1177 mci->edac_check = e752x_check;
1178 mci->ctl_page_to_phys = ctl_page_to_phys;
1179
7297c261
MG		 1180 /* set the map type. 1 = normal, 0 = reversed
1181 * Must be set before e752x_init_csrows in case csrow mapping
1182 * is reversed.
1183 */
37f04581 1184 pci_read_config_byte(pdev, E752X_DRM, &stat8);
806c35f5
AC		 1185 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
1186
7297c261
MG		 1187 e752x_init_csrows(mci, pdev, ddrcsr);
1188 e752x_init_mem_map_table(pdev, pvt);
1189
5135b797
AK		 1190 if (dev_idx == I3100)
1191 mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */
1192 else
1193 mci->edac_cap |= EDAC_FLAG_NONE;
537fba28 1194 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
e7ecd891 1195
806c35f5 1196 /* load the top of low memory, remap base, and remap limit vars */
37f04581 1197 pci_read_config_word(pdev, E752X_TOLM, &pci_data);
806c35f5 1198 pvt->tolm = ((u32) pci_data) << 4;
37f04581 1199 pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
806c35f5 1200 pvt->remapbase = ((u32) pci_data) << 14;
37f04581 1201 pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
806c35f5 1202 pvt->remaplimit = ((u32) pci_data) << 14;
537fba28 1203 e752x_printk(KERN_INFO,
052dfb45
DT		 1204 "tolm = %x, remapbase = %x, remaplimit = %x\n",
1205 pvt->tolm, pvt->remapbase, pvt->remaplimit);
806c35f5 1206
2d7bbb91
DT		 1207 /* Here we assume that we will never see multiple instances of this
1208 * type of memory controller. The ID is therefore hardcoded to 0.
1209 */
b8f6f975 1210 if (edac_mc_add_mc(mci)) {
537fba28 1211 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
806c35f5
AC		 1212 goto fail;
1213 }
1214
13189525 1215 e752x_init_error_reporting_regs(pvt);
203333cb 1216 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
806c35f5 1217
91b99041
DJ		 1218 /* allocating generic PCI control info */
1219 e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1220 if (!e752x_pci) {
1221 printk(KERN_WARNING
052dfb45 1222 "%s(): Unable to create PCI control\n", __func__);
91b99041 1223 printk(KERN_WARNING
052dfb45
DT		 1224 "%s(): PCI error report via EDAC not setup\n",
1225 __func__);
91b99041
DJ		 1226 }
1227
806c35f5 1228 /* get this far and it's successful */
537fba28 1229 debugf3("%s(): success\n", __func__);
806c35f5
AC		 1230 return 0;
1231
052dfb45 1232fail:
13189525
DT		 1233 pci_dev_put(pvt->dev_d0f0);
1234 pci_dev_put(pvt->dev_d0f1);
1235 pci_dev_put(pvt->bridge_ck);
1236 edac_mc_free(mci);
e7ecd891 1237
13189525 1238 return -ENODEV;
806c35f5
AC		 1239}
1240
1241/* returns count (>= 0), or negative on error */
1242static int __devinit e752x_init_one(struct pci_dev *pdev,
052dfb45 1243 const struct pci_device_id *ent)
806c35f5 1244{
537fba28 1245 debugf0("%s()\n", __func__);
806c35f5
AC		 1246
1247 /* wake up and enable device */
203333cb 1248 if (pci_enable_device(pdev) < 0)
806c35f5 1249 return -EIO;
e7ecd891 1250
806c35f5
AC		 1251 return e752x_probe1(pdev, ent->driver_data);
1252}
1253
806c35f5
AC		 1254static void __devexit e752x_remove_one(struct pci_dev *pdev)
1255{
1256 struct mem_ctl_info *mci;
1257 struct e752x_pvt *pvt;
1258
537fba28 1259 debugf0("%s()\n", __func__);
806c35f5 1260
91b99041
DJ		 1261 if (e752x_pci)
1262 edac_pci_release_generic_ctl(e752x_pci);
1263
37f04581 1264 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
806c35f5
AC		 1265 return;
1266
203333cb 1267 pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5
AC		 1268 pci_dev_put(pvt->dev_d0f0);
1269 pci_dev_put(pvt->dev_d0f1);
1270 pci_dev_put(pvt->bridge_ck);
1271 edac_mc_free(mci);
1272}
1273
806c35f5 1274static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
e7ecd891 1275 {
203333cb
DJ		 1276 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1277 E7520},
e7ecd891 1278 {
203333cb
DJ		 1279 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1280 E7525},
e7ecd891 1281 {
203333cb
DJ		 1282 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1283 E7320},
5135b797
AK		 1284 {
1285 PCI_VEND_DEV(INTEL, 3100_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1286 I3100},
e7ecd891 1287 {
203333cb
DJ		 1288 0,
1289 } /* 0 terminated list. */
806c35f5
AC		 1290};
1291
1292MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1293
806c35f5 1294static struct pci_driver e752x_driver = {
680cbbbb 1295 .name = EDAC_MOD_STR,
0d38b049
RD		 1296 .probe = e752x_init_one,
1297 .remove = __devexit_p(e752x_remove_one),
1298 .id_table = e752x_pci_tbl,
806c35f5
AC		 1299};
1300
da9bb1d2 1301static int __init e752x_init(void)
806c35f5
AC		 1302{
1303 int pci_rc;
1304
537fba28 1305 debugf3("%s()\n", __func__);
806c35f5
AC		 1306 pci_rc = pci_register_driver(&e752x_driver);
1307 return (pci_rc < 0) ? pci_rc : 0;
1308}
1309
806c35f5
AC		 1310static void __exit e752x_exit(void)
1311{
537fba28 1312 debugf3("%s()\n", __func__);
806c35f5
AC		 1313 pci_unregister_driver(&e752x_driver);
1314}
1315
806c35f5
AC		 1316module_init(e752x_init);
1317module_exit(e752x_exit);
1318
1319MODULE_LICENSE("GPL");
1320MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
5135b797 1321MODULE_DESCRIPTION("MC support for Intel e752x/3100 memory controllers");
96941026 1322
1323module_param(force_function_unhide, int, 0444);
1324MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
203333cb 1325 " 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");
c0d12172
DJ		 1326module_param(edac_op_state, int, 0444);
1327MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
94ee1cf5
PT		 1328
1329module_param(sysbus_parity, int, 0444);
1330MODULE_PARM_DESC(sysbus_parity, "0=disable system bus parity checking,"
1331 " 1=enable system bus parity checking, default=auto-detect");
kernel source for telekom puls (alcatel/mediatek)