Commit | Line | Data |
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806c35f5 AC |
1 | /* |
2 | * Intel e752x Memory Controller kernel module | |
3 | * (C) 2004 Linux Networx (http://lnxi.com) | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * See "enum e752x_chips" below for supported chipsets | |
8 | * | |
9 | * Written by Tom Zimmerman | |
10 | * | |
11 | * Contributors: | |
12 | * Thayne Harbaugh at realmsys.com (?) | |
13 | * Wang Zhenyu at intel.com | |
14 | * Dave Jiang at mvista.com | |
15 | * | |
da9bb1d2 | 16 | * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $ |
806c35f5 AC |
17 | * |
18 | */ | |
19 | ||
806c35f5 AC |
20 | #include <linux/module.h> |
21 | #include <linux/init.h> | |
806c35f5 AC |
22 | #include <linux/pci.h> |
23 | #include <linux/pci_ids.h> | |
806c35f5 | 24 | #include <linux/slab.h> |
c0d12172 | 25 | #include <linux/edac.h> |
20bcb7a8 | 26 | #include "edac_core.h" |
806c35f5 | 27 | |
20bcb7a8 | 28 | #define E752X_REVISION " Ver: 2.0.2 " __DATE__ |
929a40ec | 29 | #define EDAC_MOD_STR "e752x_edac" |
37f04581 | 30 | |
96941026 | 31 | static int force_function_unhide; |
32 | ||
91b99041 DJ |
33 | static struct edac_pci_ctl_info *e752x_pci; |
34 | ||
537fba28 | 35 | #define e752x_printk(level, fmt, arg...) \ |
e7ecd891 | 36 | edac_printk(level, "e752x", fmt, ##arg) |
537fba28 DP |
37 | |
38 | #define e752x_mc_printk(mci, level, fmt, arg...) \ | |
e7ecd891 | 39 | edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg) |
537fba28 | 40 | |
806c35f5 AC |
41 | #ifndef PCI_DEVICE_ID_INTEL_7520_0 |
42 | #define PCI_DEVICE_ID_INTEL_7520_0 0x3590 | |
43 | #endif /* PCI_DEVICE_ID_INTEL_7520_0 */ | |
44 | ||
45 | #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR | |
46 | #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591 | |
47 | #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */ | |
48 | ||
49 | #ifndef PCI_DEVICE_ID_INTEL_7525_0 | |
50 | #define PCI_DEVICE_ID_INTEL_7525_0 0x359E | |
51 | #endif /* PCI_DEVICE_ID_INTEL_7525_0 */ | |
52 | ||
53 | #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR | |
54 | #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593 | |
55 | #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */ | |
56 | ||
57 | #ifndef PCI_DEVICE_ID_INTEL_7320_0 | |
58 | #define PCI_DEVICE_ID_INTEL_7320_0 0x3592 | |
59 | #endif /* PCI_DEVICE_ID_INTEL_7320_0 */ | |
60 | ||
61 | #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR | |
62 | #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593 | |
63 | #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */ | |
64 | ||
65 | #define E752X_NR_CSROWS 8 /* number of csrows */ | |
66 | ||
806c35f5 AC |
67 | /* E752X register addresses - device 0 function 0 */ |
68 | #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */ | |
69 | #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */ | |
70 | /* | |
71 | * 31:30 Device width row 7 | |
72 | * 01=x8 10=x4 11=x8 DDR2 | |
73 | * 27:26 Device width row 6 | |
74 | * 23:22 Device width row 5 | |
75 | * 19:20 Device width row 4 | |
76 | * 15:14 Device width row 3 | |
77 | * 11:10 Device width row 2 | |
78 | * 7:6 Device width row 1 | |
79 | * 3:2 Device width row 0 | |
80 | */ | |
81 | #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */ | |
82 | /* FIXME:IS THIS RIGHT? */ | |
83 | /* | |
84 | * 22 Number channels 0=1,1=2 | |
85 | * 19:18 DRB Granularity 32/64MB | |
86 | */ | |
87 | #define E752X_DRM 0x80 /* Dimm mapping register */ | |
88 | #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */ | |
89 | /* | |
90 | * 14:12 1 single A, 2 single B, 3 dual | |
91 | */ | |
92 | #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ | |
93 | #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ | |
94 | #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ | |
95 | #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */ | |
96 | ||
97 | /* E752X register addresses - device 0 function 1 */ | |
98 | #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */ | |
99 | #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */ | |
100 | #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */ | |
101 | #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */ | |
102 | #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */ | |
103 | #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */ | |
104 | #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */ | |
105 | #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */ | |
106 | #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */ | |
107 | #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */ | |
108 | #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */ | |
109 | #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */ | |
110 | #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */ | |
111 | #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */ | |
112 | #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */ | |
113 | #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */ | |
114 | #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */ | |
115 | #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */ | |
116 | #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */ | |
117 | #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */ | |
118 | /* error address register (32b) */ | |
119 | /* | |
120 | * 31 Reserved | |
121 | * 30:2 CE address (64 byte block 34:6) | |
122 | * 1 Reserved | |
123 | * 0 HiLoCS | |
124 | */ | |
125 | #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */ | |
126 | /* error address register (32b) */ | |
127 | /* | |
128 | * 31 Reserved | |
129 | * 30:2 CE address (64 byte block 34:6) | |
130 | * 1 Reserved | |
131 | * 0 HiLoCS | |
132 | */ | |
133 | #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */ | |
134 | /* error address register (32b) */ | |
135 | /* | |
136 | * 31 Reserved | |
137 | * 30:2 CE address (64 byte block 34:6) | |
138 | * 1 Reserved | |
139 | * 0 HiLoCS | |
140 | */ | |
141 | #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */ | |
142 | /* error address register (32b) */ | |
143 | /* | |
144 | * 31 Reserved | |
145 | * 30:2 CE address (64 byte block 34:6) | |
146 | * 1 Reserved | |
147 | * 0 HiLoCS | |
148 | */ | |
149 | #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */ | |
150 | /* error syndrome register (16b) */ | |
151 | #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */ | |
152 | /* error syndrome register (16b) */ | |
153 | #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */ | |
154 | ||
155 | /* ICH5R register addresses - device 30 function 0 */ | |
156 | #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */ | |
157 | #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */ | |
158 | #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */ | |
159 | ||
160 | enum e752x_chips { | |
161 | E7520 = 0, | |
162 | E7525 = 1, | |
163 | E7320 = 2 | |
164 | }; | |
165 | ||
806c35f5 AC |
166 | struct e752x_pvt { |
167 | struct pci_dev *bridge_ck; | |
168 | struct pci_dev *dev_d0f0; | |
169 | struct pci_dev *dev_d0f1; | |
170 | u32 tolm; | |
171 | u32 remapbase; | |
172 | u32 remaplimit; | |
173 | int mc_symmetric; | |
174 | u8 map[8]; | |
175 | int map_type; | |
176 | const struct e752x_dev_info *dev_info; | |
177 | }; | |
178 | ||
806c35f5 AC |
179 | struct e752x_dev_info { |
180 | u16 err_dev; | |
3847bccc | 181 | u16 ctl_dev; |
806c35f5 AC |
182 | const char *ctl_name; |
183 | }; | |
184 | ||
185 | struct e752x_error_info { | |
186 | u32 ferr_global; | |
187 | u32 nerr_global; | |
188 | u8 hi_ferr; | |
189 | u8 hi_nerr; | |
190 | u16 sysbus_ferr; | |
191 | u16 sysbus_nerr; | |
192 | u8 buf_ferr; | |
193 | u8 buf_nerr; | |
194 | u16 dram_ferr; | |
195 | u16 dram_nerr; | |
196 | u32 dram_sec1_add; | |
197 | u32 dram_sec2_add; | |
198 | u16 dram_sec1_syndrome; | |
199 | u16 dram_sec2_syndrome; | |
200 | u32 dram_ded_add; | |
201 | u32 dram_scrb_add; | |
202 | u32 dram_retr_add; | |
203 | }; | |
204 | ||
205 | static const struct e752x_dev_info e752x_devs[] = { | |
206 | [E7520] = { | |
052dfb45 DT |
207 | .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR, |
208 | .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0, | |
209 | .ctl_name = "E7520"}, | |
806c35f5 | 210 | [E7525] = { |
052dfb45 DT |
211 | .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR, |
212 | .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0, | |
213 | .ctl_name = "E7525"}, | |
806c35f5 | 214 | [E7320] = { |
052dfb45 DT |
215 | .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR, |
216 | .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0, | |
217 | .ctl_name = "E7320"}, | |
806c35f5 AC |
218 | }; |
219 | ||
806c35f5 | 220 | static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, |
052dfb45 | 221 | unsigned long page) |
806c35f5 AC |
222 | { |
223 | u32 remap; | |
203333cb | 224 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 225 | |
537fba28 | 226 | debugf3("%s()\n", __func__); |
806c35f5 AC |
227 | |
228 | if (page < pvt->tolm) | |
229 | return page; | |
e7ecd891 | 230 | |
806c35f5 AC |
231 | if ((page >= 0x100000) && (page < pvt->remapbase)) |
232 | return page; | |
e7ecd891 | 233 | |
806c35f5 | 234 | remap = (page - pvt->tolm) + pvt->remapbase; |
e7ecd891 | 235 | |
806c35f5 AC |
236 | if (remap < pvt->remaplimit) |
237 | return remap; | |
e7ecd891 | 238 | |
537fba28 | 239 | e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); |
806c35f5 AC |
240 | return pvt->tolm - 1; |
241 | } | |
242 | ||
243 | static void do_process_ce(struct mem_ctl_info *mci, u16 error_one, | |
052dfb45 | 244 | u32 sec1_add, u16 sec1_syndrome) |
806c35f5 AC |
245 | { |
246 | u32 page; | |
247 | int row; | |
248 | int channel; | |
249 | int i; | |
203333cb | 250 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 251 | |
537fba28 | 252 | debugf3("%s()\n", __func__); |
806c35f5 AC |
253 | |
254 | /* convert the addr to 4k page */ | |
255 | page = sec1_add >> (PAGE_SHIFT - 4); | |
256 | ||
257 | /* FIXME - check for -1 */ | |
258 | if (pvt->mc_symmetric) { | |
259 | /* chip select are bits 14 & 13 */ | |
260 | row = ((page >> 1) & 3); | |
537fba28 | 261 | e752x_printk(KERN_WARNING, |
052dfb45 DT |
262 | "Test row %d Table %d %d %d %d %d %d %d %d\n", row, |
263 | pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3], | |
264 | pvt->map[4], pvt->map[5], pvt->map[6], | |
265 | pvt->map[7]); | |
806c35f5 AC |
266 | |
267 | /* test for channel remapping */ | |
268 | for (i = 0; i < 8; i++) { | |
269 | if (pvt->map[i] == row) | |
270 | break; | |
271 | } | |
e7ecd891 | 272 | |
537fba28 | 273 | e752x_printk(KERN_WARNING, "Test computed row %d\n", i); |
e7ecd891 | 274 | |
806c35f5 AC |
275 | if (i < 8) |
276 | row = i; | |
277 | else | |
537fba28 | 278 | e752x_mc_printk(mci, KERN_WARNING, |
203333cb DJ |
279 | "row %d not found in remap table\n", |
280 | row); | |
806c35f5 AC |
281 | } else |
282 | row = edac_mc_find_csrow_by_page(mci, page); | |
e7ecd891 | 283 | |
806c35f5 AC |
284 | /* 0 = channel A, 1 = channel B */ |
285 | channel = !(error_one & 1); | |
286 | ||
287 | if (!pvt->map_type) | |
288 | row = 7 - row; | |
e7ecd891 | 289 | |
84db003f MC |
290 | /* e752x mc reads 34:6 of the DRAM linear address */ |
291 | edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4), | |
052dfb45 | 292 | sec1_syndrome, row, channel, "e752x CE"); |
806c35f5 AC |
293 | } |
294 | ||
806c35f5 | 295 | static inline void process_ce(struct mem_ctl_info *mci, u16 error_one, |
052dfb45 DT |
296 | u32 sec1_add, u16 sec1_syndrome, int *error_found, |
297 | int handle_error) | |
806c35f5 AC |
298 | { |
299 | *error_found = 1; | |
300 | ||
301 | if (handle_error) | |
302 | do_process_ce(mci, error_one, sec1_add, sec1_syndrome); | |
303 | } | |
304 | ||
e7ecd891 | 305 | static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, |
052dfb45 | 306 | u32 ded_add, u32 scrb_add) |
806c35f5 AC |
307 | { |
308 | u32 error_2b, block_page; | |
309 | int row; | |
203333cb | 310 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 311 | |
537fba28 | 312 | debugf3("%s()\n", __func__); |
806c35f5 AC |
313 | |
314 | if (error_one & 0x0202) { | |
315 | error_2b = ded_add; | |
e7ecd891 | 316 | |
806c35f5 AC |
317 | /* convert to 4k address */ |
318 | block_page = error_2b >> (PAGE_SHIFT - 4); | |
e7ecd891 | 319 | |
806c35f5 | 320 | row = pvt->mc_symmetric ? |
052dfb45 DT |
321 | /* chip select are bits 14 & 13 */ |
322 | ((block_page >> 1) & 3) : | |
323 | edac_mc_find_csrow_by_page(mci, block_page); | |
e7ecd891 | 324 | |
84db003f MC |
325 | /* e752x mc reads 34:6 of the DRAM linear address */ |
326 | edac_mc_handle_ue(mci, block_page, | |
052dfb45 DT |
327 | offset_in_page(error_2b << 4), |
328 | row, "e752x UE from Read"); | |
806c35f5 AC |
329 | } |
330 | if (error_one & 0x0404) { | |
331 | error_2b = scrb_add; | |
e7ecd891 | 332 | |
806c35f5 AC |
333 | /* convert to 4k address */ |
334 | block_page = error_2b >> (PAGE_SHIFT - 4); | |
e7ecd891 | 335 | |
806c35f5 | 336 | row = pvt->mc_symmetric ? |
052dfb45 DT |
337 | /* chip select are bits 14 & 13 */ |
338 | ((block_page >> 1) & 3) : | |
339 | edac_mc_find_csrow_by_page(mci, block_page); | |
e7ecd891 | 340 | |
84db003f MC |
341 | /* e752x mc reads 34:6 of the DRAM linear address */ |
342 | edac_mc_handle_ue(mci, block_page, | |
052dfb45 DT |
343 | offset_in_page(error_2b << 4), |
344 | row, "e752x UE from Scruber"); | |
806c35f5 AC |
345 | } |
346 | } | |
347 | ||
348 | static inline void process_ue(struct mem_ctl_info *mci, u16 error_one, | |
052dfb45 DT |
349 | u32 ded_add, u32 scrb_add, int *error_found, |
350 | int handle_error) | |
806c35f5 AC |
351 | { |
352 | *error_found = 1; | |
353 | ||
354 | if (handle_error) | |
355 | do_process_ue(mci, error_one, ded_add, scrb_add); | |
356 | } | |
357 | ||
358 | static inline void process_ue_no_info_wr(struct mem_ctl_info *mci, | |
203333cb | 359 | int *error_found, int handle_error) |
806c35f5 AC |
360 | { |
361 | *error_found = 1; | |
362 | ||
363 | if (!handle_error) | |
364 | return; | |
365 | ||
537fba28 | 366 | debugf3("%s()\n", __func__); |
806c35f5 AC |
367 | edac_mc_handle_ue_no_info(mci, "e752x UE log memory write"); |
368 | } | |
369 | ||
370 | static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error, | |
203333cb | 371 | u32 retry_add) |
806c35f5 AC |
372 | { |
373 | u32 error_1b, page; | |
374 | int row; | |
203333cb | 375 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 AC |
376 | |
377 | error_1b = retry_add; | |
203333cb DJ |
378 | page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */ |
379 | row = pvt->mc_symmetric ? ((page >> 1) & 3) : /* chip select are bits 14 & 13 */ | |
052dfb45 | 380 | edac_mc_find_csrow_by_page(mci, page); |
537fba28 | 381 | e752x_mc_printk(mci, KERN_WARNING, |
203333cb DJ |
382 | "CE page 0x%lx, row %d : Memory read retry\n", |
383 | (long unsigned int)page, row); | |
806c35f5 AC |
384 | } |
385 | ||
386 | static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error, | |
052dfb45 DT |
387 | u32 retry_add, int *error_found, |
388 | int handle_error) | |
806c35f5 AC |
389 | { |
390 | *error_found = 1; | |
391 | ||
392 | if (handle_error) | |
393 | do_process_ded_retry(mci, error, retry_add); | |
394 | } | |
395 | ||
396 | static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error, | |
203333cb | 397 | int *error_found, int handle_error) |
806c35f5 AC |
398 | { |
399 | *error_found = 1; | |
400 | ||
401 | if (handle_error) | |
537fba28 | 402 | e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n"); |
806c35f5 AC |
403 | } |
404 | ||
da9bb1d2 | 405 | static char *global_message[11] = { |
806c35f5 AC |
406 | "PCI Express C1", "PCI Express C", "PCI Express B1", |
407 | "PCI Express B", "PCI Express A1", "PCI Express A", | |
408 | "DMA Controler", "HUB Interface", "System Bus", | |
409 | "DRAM Controler", "Internal Buffer" | |
410 | }; | |
411 | ||
da9bb1d2 | 412 | static char *fatal_message[2] = { "Non-Fatal ", "Fatal " }; |
806c35f5 AC |
413 | |
414 | static void do_global_error(int fatal, u32 errors) | |
415 | { | |
416 | int i; | |
417 | ||
418 | for (i = 0; i < 11; i++) { | |
419 | if (errors & (1 << i)) | |
537fba28 | 420 | e752x_printk(KERN_WARNING, "%sError %s\n", |
052dfb45 | 421 | fatal_message[fatal], global_message[i]); |
806c35f5 AC |
422 | } |
423 | } | |
424 | ||
425 | static inline void global_error(int fatal, u32 errors, int *error_found, | |
203333cb | 426 | int handle_error) |
806c35f5 AC |
427 | { |
428 | *error_found = 1; | |
429 | ||
430 | if (handle_error) | |
431 | do_global_error(fatal, errors); | |
432 | } | |
433 | ||
da9bb1d2 | 434 | static char *hub_message[7] = { |
806c35f5 AC |
435 | "HI Address or Command Parity", "HI Illegal Access", |
436 | "HI Internal Parity", "Out of Range Access", | |
437 | "HI Data Parity", "Enhanced Config Access", | |
438 | "Hub Interface Target Abort" | |
439 | }; | |
440 | ||
441 | static void do_hub_error(int fatal, u8 errors) | |
442 | { | |
443 | int i; | |
444 | ||
445 | for (i = 0; i < 7; i++) { | |
446 | if (errors & (1 << i)) | |
537fba28 | 447 | e752x_printk(KERN_WARNING, "%sError %s\n", |
052dfb45 | 448 | fatal_message[fatal], hub_message[i]); |
806c35f5 AC |
449 | } |
450 | } | |
451 | ||
452 | static inline void hub_error(int fatal, u8 errors, int *error_found, | |
052dfb45 | 453 | int handle_error) |
806c35f5 AC |
454 | { |
455 | *error_found = 1; | |
456 | ||
457 | if (handle_error) | |
458 | do_hub_error(fatal, errors); | |
459 | } | |
460 | ||
da9bb1d2 | 461 | static char *membuf_message[4] = { |
806c35f5 AC |
462 | "Internal PMWB to DRAM parity", |
463 | "Internal PMWB to System Bus Parity", | |
464 | "Internal System Bus or IO to PMWB Parity", | |
465 | "Internal DRAM to PMWB Parity" | |
466 | }; | |
467 | ||
468 | static void do_membuf_error(u8 errors) | |
469 | { | |
470 | int i; | |
471 | ||
472 | for (i = 0; i < 4; i++) { | |
473 | if (errors & (1 << i)) | |
537fba28 | 474 | e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n", |
052dfb45 | 475 | membuf_message[i]); |
806c35f5 AC |
476 | } |
477 | } | |
478 | ||
479 | static inline void membuf_error(u8 errors, int *error_found, int handle_error) | |
480 | { | |
481 | *error_found = 1; | |
482 | ||
483 | if (handle_error) | |
484 | do_membuf_error(errors); | |
485 | } | |
486 | ||
e009356f | 487 | static char *sysbus_message[10] = { |
806c35f5 AC |
488 | "Addr or Request Parity", |
489 | "Data Strobe Glitch", | |
490 | "Addr Strobe Glitch", | |
491 | "Data Parity", | |
492 | "Addr Above TOM", | |
493 | "Non DRAM Lock Error", | |
494 | "MCERR", "BINIT", | |
495 | "Memory Parity", | |
496 | "IO Subsystem Parity" | |
497 | }; | |
498 | ||
499 | static void do_sysbus_error(int fatal, u32 errors) | |
500 | { | |
501 | int i; | |
502 | ||
503 | for (i = 0; i < 10; i++) { | |
504 | if (errors & (1 << i)) | |
537fba28 | 505 | e752x_printk(KERN_WARNING, "%sError System Bus %s\n", |
052dfb45 | 506 | fatal_message[fatal], sysbus_message[i]); |
806c35f5 AC |
507 | } |
508 | } | |
509 | ||
510 | static inline void sysbus_error(int fatal, u32 errors, int *error_found, | |
203333cb | 511 | int handle_error) |
806c35f5 AC |
512 | { |
513 | *error_found = 1; | |
514 | ||
515 | if (handle_error) | |
516 | do_sysbus_error(fatal, errors); | |
517 | } | |
518 | ||
e7ecd891 | 519 | static void e752x_check_hub_interface(struct e752x_error_info *info, |
052dfb45 | 520 | int *error_found, int handle_error) |
806c35f5 AC |
521 | { |
522 | u8 stat8; | |
523 | ||
524 | //pci_read_config_byte(dev,E752X_HI_FERR,&stat8); | |
e7ecd891 | 525 | |
806c35f5 | 526 | stat8 = info->hi_ferr; |
e7ecd891 | 527 | |
203333cb | 528 | if (stat8 & 0x7f) { /* Error, so process */ |
806c35f5 | 529 | stat8 &= 0x7f; |
e7ecd891 | 530 | |
203333cb | 531 | if (stat8 & 0x2b) |
806c35f5 | 532 | hub_error(1, stat8 & 0x2b, error_found, handle_error); |
e7ecd891 | 533 | |
203333cb | 534 | if (stat8 & 0x54) |
806c35f5 AC |
535 | hub_error(0, stat8 & 0x54, error_found, handle_error); |
536 | } | |
537 | //pci_read_config_byte(dev,E752X_HI_NERR,&stat8); | |
e7ecd891 | 538 | |
806c35f5 | 539 | stat8 = info->hi_nerr; |
e7ecd891 | 540 | |
203333cb | 541 | if (stat8 & 0x7f) { /* Error, so process */ |
806c35f5 | 542 | stat8 &= 0x7f; |
e7ecd891 | 543 | |
806c35f5 AC |
544 | if (stat8 & 0x2b) |
545 | hub_error(1, stat8 & 0x2b, error_found, handle_error); | |
e7ecd891 | 546 | |
203333cb | 547 | if (stat8 & 0x54) |
806c35f5 AC |
548 | hub_error(0, stat8 & 0x54, error_found, handle_error); |
549 | } | |
550 | } | |
551 | ||
e7ecd891 | 552 | static void e752x_check_sysbus(struct e752x_error_info *info, |
052dfb45 | 553 | int *error_found, int handle_error) |
806c35f5 AC |
554 | { |
555 | u32 stat32, error32; | |
556 | ||
557 | //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32); | |
558 | stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16); | |
559 | ||
560 | if (stat32 == 0) | |
203333cb | 561 | return; /* no errors */ |
806c35f5 AC |
562 | |
563 | error32 = (stat32 >> 16) & 0x3ff; | |
564 | stat32 = stat32 & 0x3ff; | |
e7ecd891 | 565 | |
203333cb | 566 | if (stat32 & 0x087) |
dfb2a763 | 567 | sysbus_error(1, stat32 & 0x087, error_found, handle_error); |
e7ecd891 | 568 | |
203333cb | 569 | if (stat32 & 0x378) |
dfb2a763 | 570 | sysbus_error(0, stat32 & 0x378, error_found, handle_error); |
e7ecd891 | 571 | |
203333cb | 572 | if (error32 & 0x087) |
dfb2a763 | 573 | sysbus_error(1, error32 & 0x087, error_found, handle_error); |
e7ecd891 | 574 | |
203333cb | 575 | if (error32 & 0x378) |
dfb2a763 | 576 | sysbus_error(0, error32 & 0x378, error_found, handle_error); |
806c35f5 AC |
577 | } |
578 | ||
203333cb | 579 | static void e752x_check_membuf(struct e752x_error_info *info, |
052dfb45 | 580 | int *error_found, int handle_error) |
806c35f5 AC |
581 | { |
582 | u8 stat8; | |
583 | ||
584 | stat8 = info->buf_ferr; | |
e7ecd891 | 585 | |
203333cb | 586 | if (stat8 & 0x0f) { /* Error, so process */ |
806c35f5 AC |
587 | stat8 &= 0x0f; |
588 | membuf_error(stat8, error_found, handle_error); | |
589 | } | |
e7ecd891 | 590 | |
806c35f5 | 591 | stat8 = info->buf_nerr; |
e7ecd891 | 592 | |
203333cb | 593 | if (stat8 & 0x0f) { /* Error, so process */ |
806c35f5 AC |
594 | stat8 &= 0x0f; |
595 | membuf_error(stat8, error_found, handle_error); | |
596 | } | |
597 | } | |
598 | ||
203333cb | 599 | static void e752x_check_dram(struct mem_ctl_info *mci, |
052dfb45 DT |
600 | struct e752x_error_info *info, int *error_found, |
601 | int handle_error) | |
806c35f5 AC |
602 | { |
603 | u16 error_one, error_next; | |
604 | ||
605 | error_one = info->dram_ferr; | |
606 | error_next = info->dram_nerr; | |
607 | ||
608 | /* decode and report errors */ | |
203333cb | 609 | if (error_one & 0x0101) /* check first error correctable */ |
806c35f5 | 610 | process_ce(mci, error_one, info->dram_sec1_add, |
052dfb45 | 611 | info->dram_sec1_syndrome, error_found, handle_error); |
806c35f5 | 612 | |
203333cb | 613 | if (error_next & 0x0101) /* check next error correctable */ |
806c35f5 | 614 | process_ce(mci, error_next, info->dram_sec2_add, |
052dfb45 | 615 | info->dram_sec2_syndrome, error_found, handle_error); |
806c35f5 | 616 | |
203333cb | 617 | if (error_one & 0x4040) |
806c35f5 AC |
618 | process_ue_no_info_wr(mci, error_found, handle_error); |
619 | ||
203333cb | 620 | if (error_next & 0x4040) |
806c35f5 AC |
621 | process_ue_no_info_wr(mci, error_found, handle_error); |
622 | ||
203333cb | 623 | if (error_one & 0x2020) |
806c35f5 | 624 | process_ded_retry(mci, error_one, info->dram_retr_add, |
052dfb45 | 625 | error_found, handle_error); |
806c35f5 | 626 | |
203333cb | 627 | if (error_next & 0x2020) |
806c35f5 | 628 | process_ded_retry(mci, error_next, info->dram_retr_add, |
052dfb45 | 629 | error_found, handle_error); |
806c35f5 | 630 | |
203333cb DJ |
631 | if (error_one & 0x0808) |
632 | process_threshold_ce(mci, error_one, error_found, handle_error); | |
806c35f5 | 633 | |
203333cb | 634 | if (error_next & 0x0808) |
806c35f5 | 635 | process_threshold_ce(mci, error_next, error_found, |
052dfb45 | 636 | handle_error); |
806c35f5 | 637 | |
203333cb | 638 | if (error_one & 0x0606) |
806c35f5 | 639 | process_ue(mci, error_one, info->dram_ded_add, |
052dfb45 | 640 | info->dram_scrb_add, error_found, handle_error); |
806c35f5 | 641 | |
203333cb | 642 | if (error_next & 0x0606) |
806c35f5 | 643 | process_ue(mci, error_next, info->dram_ded_add, |
052dfb45 | 644 | info->dram_scrb_add, error_found, handle_error); |
806c35f5 AC |
645 | } |
646 | ||
203333cb DJ |
647 | static void e752x_get_error_info(struct mem_ctl_info *mci, |
648 | struct e752x_error_info *info) | |
806c35f5 AC |
649 | { |
650 | struct pci_dev *dev; | |
651 | struct e752x_pvt *pvt; | |
652 | ||
653 | memset(info, 0, sizeof(*info)); | |
203333cb | 654 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 655 | dev = pvt->dev_d0f1; |
806c35f5 AC |
656 | pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global); |
657 | ||
658 | if (info->ferr_global) { | |
659 | pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr); | |
660 | pci_read_config_word(dev, E752X_SYSBUS_FERR, | |
052dfb45 | 661 | &info->sysbus_ferr); |
806c35f5 | 662 | pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr); |
203333cb | 663 | pci_read_config_word(dev, E752X_DRAM_FERR, &info->dram_ferr); |
806c35f5 | 664 | pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD, |
052dfb45 | 665 | &info->dram_sec1_add); |
806c35f5 | 666 | pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME, |
052dfb45 | 667 | &info->dram_sec1_syndrome); |
806c35f5 | 668 | pci_read_config_dword(dev, E752X_DRAM_DED_ADD, |
052dfb45 | 669 | &info->dram_ded_add); |
806c35f5 | 670 | pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD, |
052dfb45 | 671 | &info->dram_scrb_add); |
806c35f5 | 672 | pci_read_config_dword(dev, E752X_DRAM_RETR_ADD, |
052dfb45 | 673 | &info->dram_retr_add); |
806c35f5 AC |
674 | |
675 | if (info->hi_ferr & 0x7f) | |
676 | pci_write_config_byte(dev, E752X_HI_FERR, | |
052dfb45 | 677 | info->hi_ferr); |
806c35f5 AC |
678 | |
679 | if (info->sysbus_ferr) | |
680 | pci_write_config_word(dev, E752X_SYSBUS_FERR, | |
052dfb45 | 681 | info->sysbus_ferr); |
806c35f5 AC |
682 | |
683 | if (info->buf_ferr & 0x0f) | |
684 | pci_write_config_byte(dev, E752X_BUF_FERR, | |
052dfb45 | 685 | info->buf_ferr); |
806c35f5 AC |
686 | |
687 | if (info->dram_ferr) | |
688 | pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR, | |
203333cb | 689 | info->dram_ferr, info->dram_ferr); |
806c35f5 AC |
690 | |
691 | pci_write_config_dword(dev, E752X_FERR_GLOBAL, | |
052dfb45 | 692 | info->ferr_global); |
806c35f5 AC |
693 | } |
694 | ||
695 | pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global); | |
696 | ||
697 | if (info->nerr_global) { | |
698 | pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr); | |
699 | pci_read_config_word(dev, E752X_SYSBUS_NERR, | |
052dfb45 | 700 | &info->sysbus_nerr); |
806c35f5 | 701 | pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr); |
203333cb | 702 | pci_read_config_word(dev, E752X_DRAM_NERR, &info->dram_nerr); |
806c35f5 | 703 | pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD, |
052dfb45 | 704 | &info->dram_sec2_add); |
806c35f5 | 705 | pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME, |
052dfb45 | 706 | &info->dram_sec2_syndrome); |
806c35f5 AC |
707 | |
708 | if (info->hi_nerr & 0x7f) | |
709 | pci_write_config_byte(dev, E752X_HI_NERR, | |
052dfb45 | 710 | info->hi_nerr); |
806c35f5 AC |
711 | |
712 | if (info->sysbus_nerr) | |
713 | pci_write_config_word(dev, E752X_SYSBUS_NERR, | |
052dfb45 | 714 | info->sysbus_nerr); |
806c35f5 AC |
715 | |
716 | if (info->buf_nerr & 0x0f) | |
717 | pci_write_config_byte(dev, E752X_BUF_NERR, | |
052dfb45 | 718 | info->buf_nerr); |
806c35f5 AC |
719 | |
720 | if (info->dram_nerr) | |
721 | pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR, | |
203333cb | 722 | info->dram_nerr, info->dram_nerr); |
806c35f5 AC |
723 | |
724 | pci_write_config_dword(dev, E752X_NERR_GLOBAL, | |
052dfb45 | 725 | info->nerr_global); |
806c35f5 AC |
726 | } |
727 | } | |
728 | ||
203333cb | 729 | static int e752x_process_error_info(struct mem_ctl_info *mci, |
052dfb45 DT |
730 | struct e752x_error_info *info, |
731 | int handle_errors) | |
806c35f5 AC |
732 | { |
733 | u32 error32, stat32; | |
734 | int error_found; | |
735 | ||
736 | error_found = 0; | |
737 | error32 = (info->ferr_global >> 18) & 0x3ff; | |
738 | stat32 = (info->ferr_global >> 4) & 0x7ff; | |
739 | ||
740 | if (error32) | |
741 | global_error(1, error32, &error_found, handle_errors); | |
742 | ||
743 | if (stat32) | |
744 | global_error(0, stat32, &error_found, handle_errors); | |
745 | ||
746 | error32 = (info->nerr_global >> 18) & 0x3ff; | |
747 | stat32 = (info->nerr_global >> 4) & 0x7ff; | |
748 | ||
749 | if (error32) | |
750 | global_error(1, error32, &error_found, handle_errors); | |
751 | ||
752 | if (stat32) | |
753 | global_error(0, stat32, &error_found, handle_errors); | |
754 | ||
755 | e752x_check_hub_interface(info, &error_found, handle_errors); | |
756 | e752x_check_sysbus(info, &error_found, handle_errors); | |
757 | e752x_check_membuf(info, &error_found, handle_errors); | |
758 | e752x_check_dram(mci, info, &error_found, handle_errors); | |
759 | return error_found; | |
760 | } | |
761 | ||
762 | static void e752x_check(struct mem_ctl_info *mci) | |
763 | { | |
764 | struct e752x_error_info info; | |
e7ecd891 | 765 | |
537fba28 | 766 | debugf3("%s()\n", __func__); |
806c35f5 AC |
767 | e752x_get_error_info(mci, &info); |
768 | e752x_process_error_info(mci, &info, 1); | |
769 | } | |
770 | ||
13189525 DT |
771 | /* Return 1 if dual channel mode is active. Else return 0. */ |
772 | static inline int dual_channel_active(u16 ddrcsr) | |
773 | { | |
774 | return (((ddrcsr >> 12) & 3) == 3); | |
775 | } | |
776 | ||
777 | static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, | |
052dfb45 | 778 | u16 ddrcsr) |
13189525 DT |
779 | { |
780 | struct csrow_info *csrow; | |
781 | unsigned long last_cumul_size; | |
782 | int index, mem_dev, drc_chan; | |
203333cb DJ |
783 | int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */ |
784 | int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */ | |
13189525 DT |
785 | u8 value; |
786 | u32 dra, drc, cumul_size; | |
787 | ||
9962fd01 | 788 | dra = 0; |
203333cb | 789 | for (index = 0; index < 4; index++) { |
9962fd01 | 790 | u8 dra_reg; |
203333cb | 791 | pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg); |
9962fd01 BP |
792 | dra |= dra_reg << (index * 8); |
793 | } | |
13189525 DT |
794 | pci_read_config_dword(pdev, E752X_DRC, &drc); |
795 | drc_chan = dual_channel_active(ddrcsr); | |
203333cb | 796 | drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */ |
13189525 DT |
797 | drc_ddim = (drc >> 20) & 0x3; |
798 | ||
799 | /* The dram row boundary (DRB) reg values are boundary address for | |
800 | * each DRAM row with a granularity of 64 or 128MB (single/dual | |
801 | * channel operation). DRB regs are cumulative; therefore DRB7 will | |
802 | * contain the total memory contained in all eight rows. | |
803 | */ | |
804 | for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) { | |
805 | /* mem_dev 0=x8, 1=x4 */ | |
806 | mem_dev = (dra >> (index * 4 + 2)) & 0x3; | |
807 | csrow = &mci->csrows[index]; | |
808 | ||
809 | mem_dev = (mem_dev == 2); | |
810 | pci_read_config_byte(pdev, E752X_DRB + index, &value); | |
811 | /* convert a 128 or 64 MiB DRB to a page size. */ | |
812 | cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); | |
813 | debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, | |
814 | cumul_size); | |
815 | if (cumul_size == last_cumul_size) | |
816 | continue; /* not populated */ | |
817 | ||
818 | csrow->first_page = last_cumul_size; | |
819 | csrow->last_page = cumul_size - 1; | |
820 | csrow->nr_pages = cumul_size - last_cumul_size; | |
821 | last_cumul_size = cumul_size; | |
822 | csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ | |
823 | csrow->mtype = MEM_RDDR; /* only one type supported */ | |
824 | csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; | |
825 | ||
826 | /* | |
827 | * if single channel or x8 devices then SECDED | |
828 | * if dual channel and x4 then S4ECD4ED | |
829 | */ | |
830 | if (drc_ddim) { | |
831 | if (drc_chan && mem_dev) { | |
832 | csrow->edac_mode = EDAC_S4ECD4ED; | |
833 | mci->edac_cap |= EDAC_FLAG_S4ECD4ED; | |
834 | } else { | |
835 | csrow->edac_mode = EDAC_SECDED; | |
836 | mci->edac_cap |= EDAC_FLAG_SECDED; | |
837 | } | |
838 | } else | |
839 | csrow->edac_mode = EDAC_NONE; | |
840 | } | |
841 | } | |
842 | ||
843 | static void e752x_init_mem_map_table(struct pci_dev *pdev, | |
052dfb45 | 844 | struct e752x_pvt *pvt) |
806c35f5 | 845 | { |
806c35f5 | 846 | int index; |
13189525 DT |
847 | u8 value, last, row, stat8; |
848 | ||
849 | last = 0; | |
850 | row = 0; | |
851 | ||
852 | for (index = 0; index < 8; index += 2) { | |
853 | pci_read_config_byte(pdev, E752X_DRB + index, &value); | |
854 | /* test if there is a dimm in this slot */ | |
855 | if (value == last) { | |
856 | /* no dimm in the slot, so flag it as empty */ | |
857 | pvt->map[index] = 0xff; | |
858 | pvt->map[index + 1] = 0xff; | |
203333cb | 859 | } else { /* there is a dimm in the slot */ |
13189525 DT |
860 | pvt->map[index] = row; |
861 | row++; | |
862 | last = value; | |
863 | /* test the next value to see if the dimm is double | |
864 | * sided | |
865 | */ | |
866 | pci_read_config_byte(pdev, E752X_DRB + index + 1, | |
052dfb45 DT |
867 | &value); |
868 | ||
869 | /* the dimm is single sided, so flag as empty */ | |
870 | /* this is a double sided dimm to save the next row #*/ | |
871 | pvt->map[index + 1] = (value == last) ? 0xff : row; | |
13189525 DT |
872 | row++; |
873 | last = value; | |
874 | } | |
875 | } | |
876 | ||
877 | /* set the map type. 1 = normal, 0 = reversed */ | |
878 | pci_read_config_byte(pdev, E752X_DRM, &stat8); | |
879 | pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f)); | |
880 | } | |
881 | ||
882 | /* Return 0 on success or 1 on failure. */ | |
883 | static int e752x_get_devs(struct pci_dev *pdev, int dev_idx, | |
052dfb45 | 884 | struct e752x_pvt *pvt) |
13189525 DT |
885 | { |
886 | struct pci_dev *dev; | |
887 | ||
888 | pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, | |
203333cb | 889 | pvt->dev_info->err_dev, pvt->bridge_ck); |
13189525 DT |
890 | |
891 | if (pvt->bridge_ck == NULL) | |
892 | pvt->bridge_ck = pci_scan_single_device(pdev->bus, | |
893 | PCI_DEVFN(0, 1)); | |
894 | ||
895 | if (pvt->bridge_ck == NULL) { | |
896 | e752x_printk(KERN_ERR, "error reporting device not found:" | |
052dfb45 DT |
897 | "vendor %x device 0x%x (broken BIOS?)\n", |
898 | PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev); | |
13189525 DT |
899 | return 1; |
900 | } | |
901 | ||
902 | dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev, | |
052dfb45 | 903 | NULL); |
13189525 DT |
904 | |
905 | if (dev == NULL) | |
906 | goto fail; | |
907 | ||
908 | pvt->dev_d0f0 = dev; | |
909 | pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck); | |
910 | ||
911 | return 0; | |
912 | ||
052dfb45 | 913 | fail: |
13189525 DT |
914 | pci_dev_put(pvt->bridge_ck); |
915 | return 1; | |
916 | } | |
917 | ||
918 | static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt) | |
919 | { | |
920 | struct pci_dev *dev; | |
921 | ||
922 | dev = pvt->dev_d0f1; | |
923 | /* Turn off error disable & SMI in case the BIOS turned it on */ | |
924 | pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00); | |
925 | pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00); | |
926 | pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00); | |
927 | pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00); | |
928 | pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00); | |
929 | pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00); | |
930 | pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00); | |
931 | pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00); | |
932 | } | |
933 | ||
934 | static int e752x_probe1(struct pci_dev *pdev, int dev_idx) | |
935 | { | |
3847bccc | 936 | u16 pci_data; |
806c35f5 | 937 | u8 stat8; |
13189525 DT |
938 | struct mem_ctl_info *mci; |
939 | struct e752x_pvt *pvt; | |
806c35f5 | 940 | u16 ddrcsr; |
203333cb | 941 | int drc_chan; /* Number of channels 0=1chan,1=2chan */ |
749ede57 | 942 | struct e752x_error_info discard; |
806c35f5 | 943 | |
537fba28 | 944 | debugf0("%s(): mci\n", __func__); |
806c35f5 AC |
945 | debugf0("Starting Probe1\n"); |
946 | ||
c0d12172 | 947 | /* make sure error reporting method is sane */ |
203333cb DJ |
948 | switch (edac_op_state) { |
949 | case EDAC_OPSTATE_POLL: | |
950 | case EDAC_OPSTATE_NMI: | |
951 | break; | |
952 | default: | |
953 | edac_op_state = EDAC_OPSTATE_POLL; | |
954 | break; | |
c0d12172 DJ |
955 | } |
956 | ||
96941026 | 957 | /* check to see if device 0 function 1 is enabled; if it isn't, we |
958 | * assume the BIOS has reserved it for a reason and is expecting | |
959 | * exclusive access, we take care not to violate that assumption and | |
960 | * fail the probe. */ | |
806c35f5 | 961 | pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8); |
96941026 | 962 | if (!force_function_unhide && !(stat8 & (1 << 5))) { |
963 | printk(KERN_INFO "Contact your BIOS vendor to see if the " | |
052dfb45 | 964 | "E752x error registers can be safely un-hidden\n"); |
13189525 | 965 | return -ENOMEM; |
96941026 | 966 | } |
806c35f5 AC |
967 | stat8 |= (1 << 5); |
968 | pci_write_config_byte(pdev, E752X_DEVPRES1, stat8); | |
969 | ||
806c35f5 AC |
970 | pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr); |
971 | /* FIXME: should check >>12 or 0xf, true for all? */ | |
972 | /* Dual channel = 1, Single channel = 0 */ | |
13189525 | 973 | drc_chan = dual_channel_active(ddrcsr); |
806c35f5 AC |
974 | |
975 | mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1); | |
976 | ||
977 | if (mci == NULL) { | |
13189525 | 978 | return -ENOMEM; |
806c35f5 AC |
979 | } |
980 | ||
537fba28 | 981 | debugf3("%s(): init mci\n", __func__); |
806c35f5 AC |
982 | mci->mtype_cap = MEM_FLAG_RDDR; |
983 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | | |
052dfb45 | 984 | EDAC_FLAG_S4ECD4ED; |
806c35f5 | 985 | /* FIXME - what if different memory types are in different csrows? */ |
680cbbbb | 986 | mci->mod_name = EDAC_MOD_STR; |
37f04581 DT |
987 | mci->mod_ver = E752X_REVISION; |
988 | mci->dev = &pdev->dev; | |
806c35f5 | 989 | |
537fba28 | 990 | debugf3("%s(): init pvt\n", __func__); |
203333cb | 991 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 992 | pvt->dev_info = &e752x_devs[dev_idx]; |
13189525 | 993 | pvt->mc_symmetric = ((ddrcsr & 0x10) != 0); |
e7ecd891 | 994 | |
13189525 DT |
995 | if (e752x_get_devs(pdev, dev_idx, pvt)) { |
996 | edac_mc_free(mci); | |
997 | return -ENODEV; | |
806c35f5 | 998 | } |
806c35f5 | 999 | |
537fba28 | 1000 | debugf3("%s(): more mci init\n", __func__); |
806c35f5 | 1001 | mci->ctl_name = pvt->dev_info->ctl_name; |
c4192705 | 1002 | mci->dev_name = pci_name(pdev); |
806c35f5 AC |
1003 | mci->edac_check = e752x_check; |
1004 | mci->ctl_page_to_phys = ctl_page_to_phys; | |
1005 | ||
13189525 DT |
1006 | e752x_init_csrows(mci, pdev, ddrcsr); |
1007 | e752x_init_mem_map_table(pdev, pvt); | |
806c35f5 AC |
1008 | |
1009 | /* set the map type. 1 = normal, 0 = reversed */ | |
37f04581 | 1010 | pci_read_config_byte(pdev, E752X_DRM, &stat8); |
806c35f5 AC |
1011 | pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f)); |
1012 | ||
1013 | mci->edac_cap |= EDAC_FLAG_NONE; | |
537fba28 | 1014 | debugf3("%s(): tolm, remapbase, remaplimit\n", __func__); |
e7ecd891 | 1015 | |
806c35f5 | 1016 | /* load the top of low memory, remap base, and remap limit vars */ |
37f04581 | 1017 | pci_read_config_word(pdev, E752X_TOLM, &pci_data); |
806c35f5 | 1018 | pvt->tolm = ((u32) pci_data) << 4; |
37f04581 | 1019 | pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data); |
806c35f5 | 1020 | pvt->remapbase = ((u32) pci_data) << 14; |
37f04581 | 1021 | pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data); |
806c35f5 | 1022 | pvt->remaplimit = ((u32) pci_data) << 14; |
537fba28 | 1023 | e752x_printk(KERN_INFO, |
052dfb45 DT |
1024 | "tolm = %x, remapbase = %x, remaplimit = %x\n", |
1025 | pvt->tolm, pvt->remapbase, pvt->remaplimit); | |
806c35f5 | 1026 | |
2d7bbb91 DT |
1027 | /* Here we assume that we will never see multiple instances of this |
1028 | * type of memory controller. The ID is therefore hardcoded to 0. | |
1029 | */ | |
203333cb | 1030 | if (edac_mc_add_mc(mci, 0)) { |
537fba28 | 1031 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
806c35f5 AC |
1032 | goto fail; |
1033 | } | |
1034 | ||
13189525 | 1035 | e752x_init_error_reporting_regs(pvt); |
203333cb | 1036 | e752x_get_error_info(mci, &discard); /* clear other MCH errors */ |
806c35f5 | 1037 | |
91b99041 DJ |
1038 | /* allocating generic PCI control info */ |
1039 | e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); | |
1040 | if (!e752x_pci) { | |
1041 | printk(KERN_WARNING | |
052dfb45 | 1042 | "%s(): Unable to create PCI control\n", __func__); |
91b99041 | 1043 | printk(KERN_WARNING |
052dfb45 DT |
1044 | "%s(): PCI error report via EDAC not setup\n", |
1045 | __func__); | |
91b99041 DJ |
1046 | } |
1047 | ||
806c35f5 | 1048 | /* get this far and it's successful */ |
537fba28 | 1049 | debugf3("%s(): success\n", __func__); |
806c35f5 AC |
1050 | return 0; |
1051 | ||
052dfb45 | 1052 | fail: |
13189525 DT |
1053 | pci_dev_put(pvt->dev_d0f0); |
1054 | pci_dev_put(pvt->dev_d0f1); | |
1055 | pci_dev_put(pvt->bridge_ck); | |
1056 | edac_mc_free(mci); | |
e7ecd891 | 1057 | |
13189525 | 1058 | return -ENODEV; |
806c35f5 AC |
1059 | } |
1060 | ||
1061 | /* returns count (>= 0), or negative on error */ | |
1062 | static int __devinit e752x_init_one(struct pci_dev *pdev, | |
052dfb45 | 1063 | const struct pci_device_id *ent) |
806c35f5 | 1064 | { |
537fba28 | 1065 | debugf0("%s()\n", __func__); |
806c35f5 AC |
1066 | |
1067 | /* wake up and enable device */ | |
203333cb | 1068 | if (pci_enable_device(pdev) < 0) |
806c35f5 | 1069 | return -EIO; |
e7ecd891 | 1070 | |
806c35f5 AC |
1071 | return e752x_probe1(pdev, ent->driver_data); |
1072 | } | |
1073 | ||
806c35f5 AC |
1074 | static void __devexit e752x_remove_one(struct pci_dev *pdev) |
1075 | { | |
1076 | struct mem_ctl_info *mci; | |
1077 | struct e752x_pvt *pvt; | |
1078 | ||
537fba28 | 1079 | debugf0("%s()\n", __func__); |
806c35f5 | 1080 | |
91b99041 DJ |
1081 | if (e752x_pci) |
1082 | edac_pci_release_generic_ctl(e752x_pci); | |
1083 | ||
37f04581 | 1084 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
806c35f5 AC |
1085 | return; |
1086 | ||
203333cb | 1087 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 AC |
1088 | pci_dev_put(pvt->dev_d0f0); |
1089 | pci_dev_put(pvt->dev_d0f1); | |
1090 | pci_dev_put(pvt->bridge_ck); | |
1091 | edac_mc_free(mci); | |
1092 | } | |
1093 | ||
806c35f5 | 1094 | static const struct pci_device_id e752x_pci_tbl[] __devinitdata = { |
e7ecd891 | 1095 | { |
203333cb DJ |
1096 | PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1097 | E7520}, | |
e7ecd891 | 1098 | { |
203333cb DJ |
1099 | PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1100 | E7525}, | |
e7ecd891 | 1101 | { |
203333cb DJ |
1102 | PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1103 | E7320}, | |
e7ecd891 | 1104 | { |
203333cb DJ |
1105 | 0, |
1106 | } /* 0 terminated list. */ | |
806c35f5 AC |
1107 | }; |
1108 | ||
1109 | MODULE_DEVICE_TABLE(pci, e752x_pci_tbl); | |
1110 | ||
806c35f5 | 1111 | static struct pci_driver e752x_driver = { |
680cbbbb | 1112 | .name = EDAC_MOD_STR, |
0d38b049 RD |
1113 | .probe = e752x_init_one, |
1114 | .remove = __devexit_p(e752x_remove_one), | |
1115 | .id_table = e752x_pci_tbl, | |
806c35f5 AC |
1116 | }; |
1117 | ||
da9bb1d2 | 1118 | static int __init e752x_init(void) |
806c35f5 AC |
1119 | { |
1120 | int pci_rc; | |
1121 | ||
537fba28 | 1122 | debugf3("%s()\n", __func__); |
806c35f5 AC |
1123 | pci_rc = pci_register_driver(&e752x_driver); |
1124 | return (pci_rc < 0) ? pci_rc : 0; | |
1125 | } | |
1126 | ||
806c35f5 AC |
1127 | static void __exit e752x_exit(void) |
1128 | { | |
537fba28 | 1129 | debugf3("%s()\n", __func__); |
806c35f5 AC |
1130 | pci_unregister_driver(&e752x_driver); |
1131 | } | |
1132 | ||
806c35f5 AC |
1133 | module_init(e752x_init); |
1134 | module_exit(e752x_exit); | |
1135 | ||
1136 | MODULE_LICENSE("GPL"); | |
1137 | MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n"); | |
1138 | MODULE_DESCRIPTION("MC support for Intel e752x memory controllers"); | |
96941026 | 1139 | |
1140 | module_param(force_function_unhide, int, 0444); | |
1141 | MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:" | |
203333cb | 1142 | " 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access"); |
c0d12172 DJ |
1143 | module_param(edac_op_state, int, 0444); |
1144 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |