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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / e752x_edac.c
CommitLineData
806c35f5
AC		 1/*
2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e752x_chips" below for supported chipsets
8 *
9 * Written by Tom Zimmerman
10 *
11 * Contributors:
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
15 *
da9bb1d2 16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
806c35f5
AC		 17 *
18 */
19
806c35f5
AC		 20#include <linux/module.h>
21#include <linux/init.h>
806c35f5
AC		 22#include <linux/pci.h>
23#include <linux/pci_ids.h>
806c35f5 24#include <linux/slab.h>
c0d12172 25#include <linux/edac.h>
20bcb7a8 26#include "edac_core.h"
806c35f5 27
20bcb7a8 28#define E752X_REVISION " Ver: 2.0.2 " __DATE__
929a40ec 29#define EDAC_MOD_STR "e752x_edac"
37f04581 30
96941026 31static int force_function_unhide;
32
91b99041
DJ		 33static struct edac_pci_ctl_info *e752x_pci;
34
537fba28 35#define e752x_printk(level, fmt, arg...) \
e7ecd891 36 edac_printk(level, "e752x", fmt, ##arg)
537fba28
DP		 37
38#define e752x_mc_printk(mci, level, fmt, arg...) \
e7ecd891 39 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
537fba28 40
806c35f5
AC		 41#ifndef PCI_DEVICE_ID_INTEL_7520_0
42#define PCI_DEVICE_ID_INTEL_7520_0 0x3590
43#endif /* PCI_DEVICE_ID_INTEL_7520_0 */
44
45#ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
46#define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
47#endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
48
49#ifndef PCI_DEVICE_ID_INTEL_7525_0
50#define PCI_DEVICE_ID_INTEL_7525_0 0x359E
51#endif /* PCI_DEVICE_ID_INTEL_7525_0 */
52
53#ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
54#define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
55#endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
56
57#ifndef PCI_DEVICE_ID_INTEL_7320_0
58#define PCI_DEVICE_ID_INTEL_7320_0 0x3592
59#endif /* PCI_DEVICE_ID_INTEL_7320_0 */
60
61#ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
62#define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
63#endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
64
65#define E752X_NR_CSROWS 8 /* number of csrows */
66
806c35f5
AC		 67/* E752X register addresses - device 0 function 0 */
68#define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
69#define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
70 /*
71 * 31:30 Device width row 7
72 * 01=x8 10=x4 11=x8 DDR2
73 * 27:26 Device width row 6
74 * 23:22 Device width row 5
75 * 19:20 Device width row 4
76 * 15:14 Device width row 3
77 * 11:10 Device width row 2
78 * 7:6 Device width row 1
79 * 3:2 Device width row 0
80 */
81#define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
82 /* FIXME:IS THIS RIGHT? */
83 /*
84 * 22 Number channels 0=1,1=2
85 * 19:18 DRB Granularity 32/64MB
86 */
87#define E752X_DRM 0x80 /* Dimm mapping register */
88#define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
89 /*
90 * 14:12 1 single A, 2 single B, 3 dual
91 */
92#define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
93#define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
94#define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
95#define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
96
97/* E752X register addresses - device 0 function 1 */
98#define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
99#define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
100#define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
101#define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
102#define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
103#define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
104#define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
105#define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
106#define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
107#define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
108#define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
109#define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
110#define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
111#define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
112#define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
113#define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
114#define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
115#define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
116#define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
117#define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
118 /* error address register (32b) */
119 /*
120 * 31 Reserved
121 * 30:2 CE address (64 byte block 34:6)
122 * 1 Reserved
123 * 0 HiLoCS
124 */
125#define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
126 /* error address register (32b) */
127 /*
128 * 31 Reserved
129 * 30:2 CE address (64 byte block 34:6)
130 * 1 Reserved
131 * 0 HiLoCS
132 */
133#define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
134 /* error address register (32b) */
135 /*
136 * 31 Reserved
137 * 30:2 CE address (64 byte block 34:6)
138 * 1 Reserved
139 * 0 HiLoCS
140 */
141#define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
142 /* error address register (32b) */
143 /*
144 * 31 Reserved
145 * 30:2 CE address (64 byte block 34:6)
146 * 1 Reserved
147 * 0 HiLoCS
148 */
149#define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
150 /* error syndrome register (16b) */
151#define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
152 /* error syndrome register (16b) */
153#define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
154
155/* ICH5R register addresses - device 30 function 0 */
156#define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
157#define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
158#define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
159
160enum e752x_chips {
161 E7520 = 0,
162 E7525 = 1,
163 E7320 = 2
164};
165
806c35f5
AC		 166struct e752x_pvt {
167 struct pci_dev *bridge_ck;
168 struct pci_dev *dev_d0f0;
169 struct pci_dev *dev_d0f1;
170 u32 tolm;
171 u32 remapbase;
172 u32 remaplimit;
173 int mc_symmetric;
174 u8 map[8];
175 int map_type;
176 const struct e752x_dev_info *dev_info;
177};
178
806c35f5
AC		 179struct e752x_dev_info {
180 u16 err_dev;
3847bccc 181 u16 ctl_dev;
806c35f5
AC		 182 const char *ctl_name;
183};
184
185struct e752x_error_info {
186 u32 ferr_global;
187 u32 nerr_global;
188 u8 hi_ferr;
189 u8 hi_nerr;
190 u16 sysbus_ferr;
191 u16 sysbus_nerr;
192 u8 buf_ferr;
193 u8 buf_nerr;
194 u16 dram_ferr;
195 u16 dram_nerr;
196 u32 dram_sec1_add;
197 u32 dram_sec2_add;
198 u16 dram_sec1_syndrome;
199 u16 dram_sec2_syndrome;
200 u32 dram_ded_add;
201 u32 dram_scrb_add;
202 u32 dram_retr_add;
203};
204
205static const struct e752x_dev_info e752x_devs[] = {
206 [E7520] = {
052dfb45
DT		 207 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
208 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
209 .ctl_name = "E7520"},
806c35f5 210 [E7525] = {
052dfb45
DT		 211 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
212 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
213 .ctl_name = "E7525"},
806c35f5 214 [E7320] = {
052dfb45
DT		 215 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
216 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
217 .ctl_name = "E7320"},
806c35f5
AC		 218};
219
806c35f5 220static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
052dfb45 221 unsigned long page)
806c35f5
AC		 222{
223 u32 remap;
203333cb 224 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 225
537fba28 226 debugf3("%s()\n", __func__);
806c35f5
AC		 227
228 if (page < pvt->tolm)
229 return page;
e7ecd891 230
806c35f5
AC		 231 if ((page >= 0x100000) && (page < pvt->remapbase))
232 return page;
e7ecd891 233
806c35f5 234 remap = (page - pvt->tolm) + pvt->remapbase;
e7ecd891 235
806c35f5
AC		 236 if (remap < pvt->remaplimit)
237 return remap;
e7ecd891 238
537fba28 239 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
806c35f5
AC		 240 return pvt->tolm - 1;
241}
242
243static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
052dfb45 244 u32 sec1_add, u16 sec1_syndrome)
806c35f5
AC		 245{
246 u32 page;
247 int row;
248 int channel;
249 int i;
203333cb 250 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 251
537fba28 252 debugf3("%s()\n", __func__);
806c35f5
AC		 253
254 /* convert the addr to 4k page */
255 page = sec1_add >> (PAGE_SHIFT - 4);
256
257 /* FIXME - check for -1 */
258 if (pvt->mc_symmetric) {
259 /* chip select are bits 14 & 13 */
260 row = ((page >> 1) & 3);
537fba28 261 e752x_printk(KERN_WARNING,
052dfb45
DT		 262 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
263 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
264 pvt->map[4], pvt->map[5], pvt->map[6],
265 pvt->map[7]);
806c35f5
AC		 266
267 /* test for channel remapping */
268 for (i = 0; i < 8; i++) {
269 if (pvt->map[i] == row)
270 break;
271 }
e7ecd891 272
537fba28 273 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
e7ecd891 274
806c35f5
AC		 275 if (i < 8)
276 row = i;
277 else
537fba28 278 e752x_mc_printk(mci, KERN_WARNING,
203333cb
DJ		 279 "row %d not found in remap table\n",
280 row);
806c35f5
AC		 281 } else
282 row = edac_mc_find_csrow_by_page(mci, page);
e7ecd891 283
806c35f5
AC		 284 /* 0 = channel A, 1 = channel B */
285 channel = !(error_one & 1);
286
84db003f
MC		 287 /* e752x mc reads 34:6 of the DRAM linear address */
288 edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4),
052dfb45 289 sec1_syndrome, row, channel, "e752x CE");
806c35f5
AC		 290}
291
806c35f5 292static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
052dfb45
DT		 293 u32 sec1_add, u16 sec1_syndrome, int *error_found,
294 int handle_error)
806c35f5
AC		 295{
296 *error_found = 1;
297
298 if (handle_error)
299 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
300}
301
e7ecd891 302static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
052dfb45 303 u32 ded_add, u32 scrb_add)
806c35f5
AC		 304{
305 u32 error_2b, block_page;
306 int row;
203333cb 307 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 308
537fba28 309 debugf3("%s()\n", __func__);
806c35f5
AC		 310
311 if (error_one & 0x0202) {
312 error_2b = ded_add;
e7ecd891 313
806c35f5
AC		 314 /* convert to 4k address */
315 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 316
806c35f5 317 row = pvt->mc_symmetric ?
052dfb45
DT		 318 /* chip select are bits 14 & 13 */
319 ((block_page >> 1) & 3) :
320 edac_mc_find_csrow_by_page(mci, block_page);
e7ecd891 321
84db003f
MC		 322 /* e752x mc reads 34:6 of the DRAM linear address */
323 edac_mc_handle_ue(mci, block_page,
052dfb45
DT		 324 offset_in_page(error_2b << 4),
325 row, "e752x UE from Read");
806c35f5
AC		 326 }
327 if (error_one & 0x0404) {
328 error_2b = scrb_add;
e7ecd891 329
806c35f5
AC		 330 /* convert to 4k address */
331 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 332
806c35f5 333 row = pvt->mc_symmetric ?
052dfb45
DT		 334 /* chip select are bits 14 & 13 */
335 ((block_page >> 1) & 3) :
336 edac_mc_find_csrow_by_page(mci, block_page);
e7ecd891 337
84db003f
MC		 338 /* e752x mc reads 34:6 of the DRAM linear address */
339 edac_mc_handle_ue(mci, block_page,
052dfb45
DT		 340 offset_in_page(error_2b << 4),
341 row, "e752x UE from Scruber");
806c35f5
AC		 342 }
343}
344
345static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
052dfb45
DT		 346 u32 ded_add, u32 scrb_add, int *error_found,
347 int handle_error)
806c35f5
AC		 348{
349 *error_found = 1;
350
351 if (handle_error)
352 do_process_ue(mci, error_one, ded_add, scrb_add);
353}
354
355static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
203333cb 356 int *error_found, int handle_error)
806c35f5
AC		 357{
358 *error_found = 1;
359
360 if (!handle_error)
361 return;
362
537fba28 363 debugf3("%s()\n", __func__);
806c35f5
AC		 364 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
365}
366
367static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
203333cb 368 u32 retry_add)
806c35f5
AC		 369{
370 u32 error_1b, page;
371 int row;
203333cb 372 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5
AC		 373
374 error_1b = retry_add;
203333cb
DJ		 375 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
376 row = pvt->mc_symmetric ? ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
052dfb45 377 edac_mc_find_csrow_by_page(mci, page);
537fba28 378 e752x_mc_printk(mci, KERN_WARNING,
203333cb
DJ		 379 "CE page 0x%lx, row %d : Memory read retry\n",
380 (long unsigned int)page, row);
806c35f5
AC		 381}
382
383static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
052dfb45
DT		 384 u32 retry_add, int *error_found,
385 int handle_error)
806c35f5
AC		 386{
387 *error_found = 1;
388
389 if (handle_error)
390 do_process_ded_retry(mci, error, retry_add);
391}
392
393static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
203333cb 394 int *error_found, int handle_error)
806c35f5
AC		 395{
396 *error_found = 1;
397
398 if (handle_error)
537fba28 399 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
806c35f5
AC		 400}
401
da9bb1d2 402static char *global_message[11] = {
806c35f5
AC		 403 "PCI Express C1", "PCI Express C", "PCI Express B1",
404 "PCI Express B", "PCI Express A1", "PCI Express A",
405 "DMA Controler", "HUB Interface", "System Bus",
406 "DRAM Controler", "Internal Buffer"
407};
408
da9bb1d2 409static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
806c35f5
AC		 410
411static void do_global_error(int fatal, u32 errors)
412{
413 int i;
414
415 for (i = 0; i < 11; i++) {
416 if (errors & (1 << i))
537fba28 417 e752x_printk(KERN_WARNING, "%sError %s\n",
052dfb45 418 fatal_message[fatal], global_message[i]);
806c35f5
AC		 419 }
420}
421
422static inline void global_error(int fatal, u32 errors, int *error_found,
203333cb 423 int handle_error)
806c35f5
AC		 424{
425 *error_found = 1;
426
427 if (handle_error)
428 do_global_error(fatal, errors);
429}
430
da9bb1d2 431static char *hub_message[7] = {
806c35f5
AC		 432 "HI Address or Command Parity", "HI Illegal Access",
433 "HI Internal Parity", "Out of Range Access",
434 "HI Data Parity", "Enhanced Config Access",
435 "Hub Interface Target Abort"
436};
437
438static void do_hub_error(int fatal, u8 errors)
439{
440 int i;
441
442 for (i = 0; i < 7; i++) {
443 if (errors & (1 << i))
537fba28 444 e752x_printk(KERN_WARNING, "%sError %s\n",
052dfb45 445 fatal_message[fatal], hub_message[i]);
806c35f5
AC		 446 }
447}
448
449static inline void hub_error(int fatal, u8 errors, int *error_found,
052dfb45 450 int handle_error)
806c35f5
AC		 451{
452 *error_found = 1;
453
454 if (handle_error)
455 do_hub_error(fatal, errors);
456}
457
da9bb1d2 458static char *membuf_message[4] = {
806c35f5
AC		 459 "Internal PMWB to DRAM parity",
460 "Internal PMWB to System Bus Parity",
461 "Internal System Bus or IO to PMWB Parity",
462 "Internal DRAM to PMWB Parity"
463};
464
465static void do_membuf_error(u8 errors)
466{
467 int i;
468
469 for (i = 0; i < 4; i++) {
470 if (errors & (1 << i))
537fba28 471 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
052dfb45 472 membuf_message[i]);
806c35f5
AC		 473 }
474}
475
476static inline void membuf_error(u8 errors, int *error_found, int handle_error)
477{
478 *error_found = 1;
479
480 if (handle_error)
481 do_membuf_error(errors);
482}
483
e009356f 484static char *sysbus_message[10] = {
806c35f5
AC		 485 "Addr or Request Parity",
486 "Data Strobe Glitch",
487 "Addr Strobe Glitch",
488 "Data Parity",
489 "Addr Above TOM",
490 "Non DRAM Lock Error",
491 "MCERR", "BINIT",
492 "Memory Parity",
493 "IO Subsystem Parity"
494};
495
496static void do_sysbus_error(int fatal, u32 errors)
497{
498 int i;
499
500 for (i = 0; i < 10; i++) {
501 if (errors & (1 << i))
537fba28 502 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
052dfb45 503 fatal_message[fatal], sysbus_message[i]);
806c35f5
AC		 504 }
505}
506
507static inline void sysbus_error(int fatal, u32 errors, int *error_found,
203333cb 508 int handle_error)
806c35f5
AC		 509{
510 *error_found = 1;
511
512 if (handle_error)
513 do_sysbus_error(fatal, errors);
514}
515
e7ecd891 516static void e752x_check_hub_interface(struct e752x_error_info *info,
052dfb45 517 int *error_found, int handle_error)
806c35f5
AC		 518{
519 u8 stat8;
520
521 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
e7ecd891 522
806c35f5 523 stat8 = info->hi_ferr;
e7ecd891 524
203333cb 525 if (stat8 & 0x7f) { /* Error, so process */
806c35f5 526 stat8 &= 0x7f;
e7ecd891 527
203333cb 528 if (stat8 & 0x2b)
806c35f5 529 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 530
203333cb 531 if (stat8 & 0x54)
806c35f5
AC		 532 hub_error(0, stat8 & 0x54, error_found, handle_error);
533 }
534 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
e7ecd891 535
806c35f5 536 stat8 = info->hi_nerr;
e7ecd891 537
203333cb 538 if (stat8 & 0x7f) { /* Error, so process */
806c35f5 539 stat8 &= 0x7f;
e7ecd891 540
806c35f5
AC		 541 if (stat8 & 0x2b)
542 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 543
203333cb 544 if (stat8 & 0x54)
806c35f5
AC		 545 hub_error(0, stat8 & 0x54, error_found, handle_error);
546 }
547}
548
e7ecd891 549static void e752x_check_sysbus(struct e752x_error_info *info,
052dfb45 550 int *error_found, int handle_error)
806c35f5
AC		 551{
552 u32 stat32, error32;
553
554 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
555 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
556
557 if (stat32 == 0)
203333cb 558 return; /* no errors */
806c35f5
AC		 559
560 error32 = (stat32 >> 16) & 0x3ff;
561 stat32 = stat32 & 0x3ff;
e7ecd891 562
203333cb 563 if (stat32 & 0x087)
dfb2a763 564 sysbus_error(1, stat32 & 0x087, error_found, handle_error);
e7ecd891 565
203333cb 566 if (stat32 & 0x378)
dfb2a763 567 sysbus_error(0, stat32 & 0x378, error_found, handle_error);
e7ecd891 568
203333cb 569 if (error32 & 0x087)
dfb2a763 570 sysbus_error(1, error32 & 0x087, error_found, handle_error);
e7ecd891 571
203333cb 572 if (error32 & 0x378)
dfb2a763 573 sysbus_error(0, error32 & 0x378, error_found, handle_error);
806c35f5
AC		 574}
575
203333cb 576static void e752x_check_membuf(struct e752x_error_info *info,
052dfb45 577 int *error_found, int handle_error)
806c35f5
AC		 578{
579 u8 stat8;
580
581 stat8 = info->buf_ferr;
e7ecd891 582
203333cb 583 if (stat8 & 0x0f) { /* Error, so process */
806c35f5
AC		 584 stat8 &= 0x0f;
585 membuf_error(stat8, error_found, handle_error);
586 }
e7ecd891 587
806c35f5 588 stat8 = info->buf_nerr;
e7ecd891 589
203333cb 590 if (stat8 & 0x0f) { /* Error, so process */
806c35f5
AC		 591 stat8 &= 0x0f;
592 membuf_error(stat8, error_found, handle_error);
593 }
594}
595
203333cb 596static void e752x_check_dram(struct mem_ctl_info *mci,
052dfb45
DT		 597 struct e752x_error_info *info, int *error_found,
598 int handle_error)
806c35f5
AC		 599{
600 u16 error_one, error_next;
601
602 error_one = info->dram_ferr;
603 error_next = info->dram_nerr;
604
605 /* decode and report errors */
203333cb 606 if (error_one & 0x0101) /* check first error correctable */
806c35f5 607 process_ce(mci, error_one, info->dram_sec1_add,
052dfb45 608 info->dram_sec1_syndrome, error_found, handle_error);
806c35f5 609
203333cb 610 if (error_next & 0x0101) /* check next error correctable */
806c35f5 611 process_ce(mci, error_next, info->dram_sec2_add,
052dfb45 612 info->dram_sec2_syndrome, error_found, handle_error);
806c35f5 613
203333cb 614 if (error_one & 0x4040)
806c35f5
AC		 615 process_ue_no_info_wr(mci, error_found, handle_error);
616
203333cb 617 if (error_next & 0x4040)
806c35f5
AC		 618 process_ue_no_info_wr(mci, error_found, handle_error);
619
203333cb 620 if (error_one & 0x2020)
806c35f5 621 process_ded_retry(mci, error_one, info->dram_retr_add,
052dfb45 622 error_found, handle_error);
806c35f5 623
203333cb 624 if (error_next & 0x2020)
806c35f5 625 process_ded_retry(mci, error_next, info->dram_retr_add,
052dfb45 626 error_found, handle_error);
806c35f5 627
203333cb
DJ		 628 if (error_one & 0x0808)
629 process_threshold_ce(mci, error_one, error_found, handle_error);
806c35f5 630
203333cb 631 if (error_next & 0x0808)
806c35f5 632 process_threshold_ce(mci, error_next, error_found,
052dfb45 633 handle_error);
806c35f5 634
203333cb 635 if (error_one & 0x0606)
806c35f5 636 process_ue(mci, error_one, info->dram_ded_add,
052dfb45 637 info->dram_scrb_add, error_found, handle_error);
806c35f5 638
203333cb 639 if (error_next & 0x0606)
806c35f5 640 process_ue(mci, error_next, info->dram_ded_add,
052dfb45 641 info->dram_scrb_add, error_found, handle_error);
806c35f5
AC		 642}
643
203333cb
DJ		 644static void e752x_get_error_info(struct mem_ctl_info *mci,
645 struct e752x_error_info *info)
806c35f5
AC		 646{
647 struct pci_dev *dev;
648 struct e752x_pvt *pvt;
649
650 memset(info, 0, sizeof(*info));
203333cb 651 pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 652 dev = pvt->dev_d0f1;
806c35f5
AC		 653 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
654
655 if (info->ferr_global) {
656 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
657 pci_read_config_word(dev, E752X_SYSBUS_FERR,
052dfb45 658 &info->sysbus_ferr);
806c35f5 659 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
203333cb 660 pci_read_config_word(dev, E752X_DRAM_FERR, &info->dram_ferr);
806c35f5 661 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
052dfb45 662 &info->dram_sec1_add);
806c35f5 663 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
052dfb45 664 &info->dram_sec1_syndrome);
806c35f5 665 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
052dfb45 666 &info->dram_ded_add);
806c35f5 667 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
052dfb45 668 &info->dram_scrb_add);
806c35f5 669 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
052dfb45 670 &info->dram_retr_add);
806c35f5
AC		 671
672 if (info->hi_ferr & 0x7f)
673 pci_write_config_byte(dev, E752X_HI_FERR,
052dfb45 674 info->hi_ferr);
806c35f5
AC		 675
676 if (info->sysbus_ferr)
677 pci_write_config_word(dev, E752X_SYSBUS_FERR,
052dfb45 678 info->sysbus_ferr);
806c35f5
AC		 679
680 if (info->buf_ferr & 0x0f)
681 pci_write_config_byte(dev, E752X_BUF_FERR,
052dfb45 682 info->buf_ferr);
806c35f5
AC		 683
684 if (info->dram_ferr)
685 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
203333cb 686 info->dram_ferr, info->dram_ferr);
806c35f5
AC		 687
688 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
052dfb45 689 info->ferr_global);
806c35f5
AC		 690 }
691
692 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
693
694 if (info->nerr_global) {
695 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
696 pci_read_config_word(dev, E752X_SYSBUS_NERR,
052dfb45 697 &info->sysbus_nerr);
806c35f5 698 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
203333cb 699 pci_read_config_word(dev, E752X_DRAM_NERR, &info->dram_nerr);
806c35f5 700 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
052dfb45 701 &info->dram_sec2_add);
806c35f5 702 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
052dfb45 703 &info->dram_sec2_syndrome);
806c35f5
AC		 704
705 if (info->hi_nerr & 0x7f)
706 pci_write_config_byte(dev, E752X_HI_NERR,
052dfb45 707 info->hi_nerr);
806c35f5
AC		 708
709 if (info->sysbus_nerr)
710 pci_write_config_word(dev, E752X_SYSBUS_NERR,
052dfb45 711 info->sysbus_nerr);
806c35f5
AC		 712
713 if (info->buf_nerr & 0x0f)
714 pci_write_config_byte(dev, E752X_BUF_NERR,
052dfb45 715 info->buf_nerr);
806c35f5
AC		 716
717 if (info->dram_nerr)
718 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
203333cb 719 info->dram_nerr, info->dram_nerr);
806c35f5
AC		 720
721 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
052dfb45 722 info->nerr_global);
806c35f5
AC		 723 }
724}
725
203333cb 726static int e752x_process_error_info(struct mem_ctl_info *mci,
052dfb45
DT		 727 struct e752x_error_info *info,
728 int handle_errors)
806c35f5
AC		 729{
730 u32 error32, stat32;
731 int error_found;
732
733 error_found = 0;
734 error32 = (info->ferr_global >> 18) & 0x3ff;
735 stat32 = (info->ferr_global >> 4) & 0x7ff;
736
737 if (error32)
738 global_error(1, error32, &error_found, handle_errors);
739
740 if (stat32)
741 global_error(0, stat32, &error_found, handle_errors);
742
743 error32 = (info->nerr_global >> 18) & 0x3ff;
744 stat32 = (info->nerr_global >> 4) & 0x7ff;
745
746 if (error32)
747 global_error(1, error32, &error_found, handle_errors);
748
749 if (stat32)
750 global_error(0, stat32, &error_found, handle_errors);
751
752 e752x_check_hub_interface(info, &error_found, handle_errors);
753 e752x_check_sysbus(info, &error_found, handle_errors);
754 e752x_check_membuf(info, &error_found, handle_errors);
755 e752x_check_dram(mci, info, &error_found, handle_errors);
756 return error_found;
757}
758
759static void e752x_check(struct mem_ctl_info *mci)
760{
761 struct e752x_error_info info;
e7ecd891 762
537fba28 763 debugf3("%s()\n", __func__);
806c35f5
AC		 764 e752x_get_error_info(mci, &info);
765 e752x_process_error_info(mci, &info, 1);
766}
767
13189525
DT		 768/* Return 1 if dual channel mode is active. Else return 0. */
769static inline int dual_channel_active(u16 ddrcsr)
770{
771 return (((ddrcsr >> 12) & 3) == 3);
772}
773
7297c261
MG		 774/* Remap csrow index numbers if map_type is "reverse"
775 */
776static inline int remap_csrow_index(struct mem_ctl_info *mci, int index)
777{
778 struct e752x_pvt *pvt = mci->pvt_info;
779
780 if (!pvt->map_type)
781 return (7 - index);
782
783 return (index);
784}
785
13189525 786static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
052dfb45 787 u16 ddrcsr)
13189525
DT		 788{
789 struct csrow_info *csrow;
790 unsigned long last_cumul_size;
791 int index, mem_dev, drc_chan;
203333cb
DJ		 792 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
793 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
13189525
DT		 794 u8 value;
795 u32 dra, drc, cumul_size;
796
9962fd01 797 dra = 0;
203333cb 798 for (index = 0; index < 4; index++) {
9962fd01 799 u8 dra_reg;
203333cb 800 pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg);
9962fd01
BP		 801 dra |= dra_reg << (index * 8);
802 }
13189525
DT		 803 pci_read_config_dword(pdev, E752X_DRC, &drc);
804 drc_chan = dual_channel_active(ddrcsr);
203333cb 805 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
13189525
DT		 806 drc_ddim = (drc >> 20) & 0x3;
807
808 /* The dram row boundary (DRB) reg values are boundary address for
809 * each DRAM row with a granularity of 64 or 128MB (single/dual
810 * channel operation). DRB regs are cumulative; therefore DRB7 will
811 * contain the total memory contained in all eight rows.
812 */
813 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
814 /* mem_dev 0=x8, 1=x4 */
815 mem_dev = (dra >> (index * 4 + 2)) & 0x3;
7297c261 816 csrow = &mci->csrows[remap_csrow_index(mci, index)];
13189525
DT		 817
818 mem_dev = (mem_dev == 2);
819 pci_read_config_byte(pdev, E752X_DRB + index, &value);
820 /* convert a 128 or 64 MiB DRB to a page size. */
821 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
822 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
823 cumul_size);
824 if (cumul_size == last_cumul_size)
825 continue; /* not populated */
826
827 csrow->first_page = last_cumul_size;
828 csrow->last_page = cumul_size - 1;
829 csrow->nr_pages = cumul_size - last_cumul_size;
830 last_cumul_size = cumul_size;
831 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
832 csrow->mtype = MEM_RDDR; /* only one type supported */
833 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
834
835 /*
836 * if single channel or x8 devices then SECDED
837 * if dual channel and x4 then S4ECD4ED
838 */
839 if (drc_ddim) {
840 if (drc_chan && mem_dev) {
841 csrow->edac_mode = EDAC_S4ECD4ED;
842 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
843 } else {
844 csrow->edac_mode = EDAC_SECDED;
845 mci->edac_cap |= EDAC_FLAG_SECDED;
846 }
847 } else
848 csrow->edac_mode = EDAC_NONE;
849 }
850}
851
852static void e752x_init_mem_map_table(struct pci_dev *pdev,
052dfb45 853 struct e752x_pvt *pvt)
806c35f5 854{
806c35f5 855 int index;
7297c261 856 u8 value, last, row;
13189525
DT		 857
858 last = 0;
859 row = 0;
860
861 for (index = 0; index < 8; index += 2) {
862 pci_read_config_byte(pdev, E752X_DRB + index, &value);
863 /* test if there is a dimm in this slot */
864 if (value == last) {
865 /* no dimm in the slot, so flag it as empty */
866 pvt->map[index] = 0xff;
867 pvt->map[index + 1] = 0xff;
203333cb 868 } else { /* there is a dimm in the slot */
13189525
DT		 869 pvt->map[index] = row;
870 row++;
871 last = value;
872 /* test the next value to see if the dimm is double
873 * sided
874 */
875 pci_read_config_byte(pdev, E752X_DRB + index + 1,
052dfb45
DT		 876 &value);
877
878 /* the dimm is single sided, so flag as empty */
879 /* this is a double sided dimm to save the next row #*/
880 pvt->map[index + 1] = (value == last) ? 0xff : row;
13189525
DT		 881 row++;
882 last = value;
883 }
884 }
13189525
DT		 885}
886
887/* Return 0 on success or 1 on failure. */
888static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
052dfb45 889 struct e752x_pvt *pvt)
13189525
DT		 890{
891 struct pci_dev *dev;
892
893 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
203333cb 894 pvt->dev_info->err_dev, pvt->bridge_ck);
13189525
DT		 895
896 if (pvt->bridge_ck == NULL)
897 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
898 PCI_DEVFN(0, 1));
899
900 if (pvt->bridge_ck == NULL) {
901 e752x_printk(KERN_ERR, "error reporting device not found:"
052dfb45
DT		 902 "vendor %x device 0x%x (broken BIOS?)\n",
903 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
13189525
DT		 904 return 1;
905 }
906
907 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
052dfb45 908 NULL);
13189525
DT		 909
910 if (dev == NULL)
911 goto fail;
912
913 pvt->dev_d0f0 = dev;
914 pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
915
916 return 0;
917
052dfb45 918fail:
13189525
DT		 919 pci_dev_put(pvt->bridge_ck);
920 return 1;
921}
922
923static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
924{
925 struct pci_dev *dev;
926
927 dev = pvt->dev_d0f1;
928 /* Turn off error disable & SMI in case the BIOS turned it on */
929 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
930 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
931 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
932 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
933 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
934 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
935 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
936 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
937}
938
939static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
940{
3847bccc 941 u16 pci_data;
806c35f5 942 u8 stat8;
13189525
DT		 943 struct mem_ctl_info *mci;
944 struct e752x_pvt *pvt;
806c35f5 945 u16 ddrcsr;
203333cb 946 int drc_chan; /* Number of channels 0=1chan,1=2chan */
749ede57 947 struct e752x_error_info discard;
806c35f5 948
537fba28 949 debugf0("%s(): mci\n", __func__);
806c35f5
AC		 950 debugf0("Starting Probe1\n");
951
c0d12172 952 /* make sure error reporting method is sane */
203333cb
DJ		 953 switch (edac_op_state) {
954 case EDAC_OPSTATE_POLL:
955 case EDAC_OPSTATE_NMI:
956 break;
957 default:
958 edac_op_state = EDAC_OPSTATE_POLL;
959 break;
c0d12172
DJ		 960 }
961
96941026 962 /* check to see if device 0 function 1 is enabled; if it isn't, we
963 * assume the BIOS has reserved it for a reason and is expecting
964 * exclusive access, we take care not to violate that assumption and
965 * fail the probe. */
806c35f5 966 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
96941026 967 if (!force_function_unhide && !(stat8 & (1 << 5))) {
968 printk(KERN_INFO "Contact your BIOS vendor to see if the "
052dfb45 969 "E752x error registers can be safely un-hidden\n");
f9b5a5d1 970 return -ENODEV;
96941026 971 }
806c35f5
AC		 972 stat8 |= (1 << 5);
973 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
974
806c35f5
AC		 975 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
976 /* FIXME: should check >>12 or 0xf, true for all? */
977 /* Dual channel = 1, Single channel = 0 */
13189525 978 drc_chan = dual_channel_active(ddrcsr);
806c35f5 979
b8f6f975 980 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1, 0);
806c35f5
AC		 981
982 if (mci == NULL) {
13189525 983 return -ENOMEM;
806c35f5
AC		 984 }
985
537fba28 986 debugf3("%s(): init mci\n", __func__);
806c35f5
AC		 987 mci->mtype_cap = MEM_FLAG_RDDR;
988 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
052dfb45 989 EDAC_FLAG_S4ECD4ED;
806c35f5 990 /* FIXME - what if different memory types are in different csrows? */
680cbbbb 991 mci->mod_name = EDAC_MOD_STR;
37f04581
DT		 992 mci->mod_ver = E752X_REVISION;
993 mci->dev = &pdev->dev;
806c35f5 994
537fba28 995 debugf3("%s(): init pvt\n", __func__);
203333cb 996 pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5 997 pvt->dev_info = &e752x_devs[dev_idx];
13189525 998 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
e7ecd891 999
13189525
DT		 1000 if (e752x_get_devs(pdev, dev_idx, pvt)) {
1001 edac_mc_free(mci);
1002 return -ENODEV;
806c35f5 1003 }
806c35f5 1004
537fba28 1005 debugf3("%s(): more mci init\n", __func__);
806c35f5 1006 mci->ctl_name = pvt->dev_info->ctl_name;
c4192705 1007 mci->dev_name = pci_name(pdev);
806c35f5
AC		 1008 mci->edac_check = e752x_check;
1009 mci->ctl_page_to_phys = ctl_page_to_phys;
1010
7297c261
MG		 1011 /* set the map type. 1 = normal, 0 = reversed
1012 * Must be set before e752x_init_csrows in case csrow mapping
1013 * is reversed.
1014 */
37f04581 1015 pci_read_config_byte(pdev, E752X_DRM, &stat8);
806c35f5
AC		 1016 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
1017
7297c261
MG		 1018 e752x_init_csrows(mci, pdev, ddrcsr);
1019 e752x_init_mem_map_table(pdev, pvt);
1020
806c35f5 1021 mci->edac_cap |= EDAC_FLAG_NONE;
537fba28 1022 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
e7ecd891 1023
806c35f5 1024 /* load the top of low memory, remap base, and remap limit vars */
37f04581 1025 pci_read_config_word(pdev, E752X_TOLM, &pci_data);
806c35f5 1026 pvt->tolm = ((u32) pci_data) << 4;
37f04581 1027 pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
806c35f5 1028 pvt->remapbase = ((u32) pci_data) << 14;
37f04581 1029 pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
806c35f5 1030 pvt->remaplimit = ((u32) pci_data) << 14;
537fba28 1031 e752x_printk(KERN_INFO,
052dfb45
DT		 1032 "tolm = %x, remapbase = %x, remaplimit = %x\n",
1033 pvt->tolm, pvt->remapbase, pvt->remaplimit);
806c35f5 1034
2d7bbb91
DT		 1035 /* Here we assume that we will never see multiple instances of this
1036 * type of memory controller. The ID is therefore hardcoded to 0.
1037 */
b8f6f975 1038 if (edac_mc_add_mc(mci)) {
537fba28 1039 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
806c35f5
AC		 1040 goto fail;
1041 }
1042
13189525 1043 e752x_init_error_reporting_regs(pvt);
203333cb 1044 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
806c35f5 1045
91b99041
DJ		 1046 /* allocating generic PCI control info */
1047 e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1048 if (!e752x_pci) {
1049 printk(KERN_WARNING
052dfb45 1050 "%s(): Unable to create PCI control\n", __func__);
91b99041 1051 printk(KERN_WARNING
052dfb45
DT		 1052 "%s(): PCI error report via EDAC not setup\n",
1053 __func__);
91b99041
DJ		 1054 }
1055
806c35f5 1056 /* get this far and it's successful */
537fba28 1057 debugf3("%s(): success\n", __func__);
806c35f5
AC		 1058 return 0;
1059
052dfb45 1060fail:
13189525
DT		 1061 pci_dev_put(pvt->dev_d0f0);
1062 pci_dev_put(pvt->dev_d0f1);
1063 pci_dev_put(pvt->bridge_ck);
1064 edac_mc_free(mci);
e7ecd891 1065
13189525 1066 return -ENODEV;
806c35f5
AC		 1067}
1068
1069/* returns count (>= 0), or negative on error */
1070static int __devinit e752x_init_one(struct pci_dev *pdev,
052dfb45 1071 const struct pci_device_id *ent)
806c35f5 1072{
537fba28 1073 debugf0("%s()\n", __func__);
806c35f5
AC		 1074
1075 /* wake up and enable device */
203333cb 1076 if (pci_enable_device(pdev) < 0)
806c35f5 1077 return -EIO;
e7ecd891 1078
806c35f5
AC		 1079 return e752x_probe1(pdev, ent->driver_data);
1080}
1081
806c35f5
AC		 1082static void __devexit e752x_remove_one(struct pci_dev *pdev)
1083{
1084 struct mem_ctl_info *mci;
1085 struct e752x_pvt *pvt;
1086
537fba28 1087 debugf0("%s()\n", __func__);
806c35f5 1088
91b99041
DJ		 1089 if (e752x_pci)
1090 edac_pci_release_generic_ctl(e752x_pci);
1091
37f04581 1092 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
806c35f5
AC		 1093 return;
1094
203333cb 1095 pvt = (struct e752x_pvt *)mci->pvt_info;
806c35f5
AC		 1096 pci_dev_put(pvt->dev_d0f0);
1097 pci_dev_put(pvt->dev_d0f1);
1098 pci_dev_put(pvt->bridge_ck);
1099 edac_mc_free(mci);
1100}
1101
806c35f5 1102static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
e7ecd891 1103 {
203333cb
DJ		 1104 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1105 E7520},
e7ecd891 1106 {
203333cb
DJ		 1107 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1108 E7525},
e7ecd891 1109 {
203333cb
DJ		 1110 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1111 E7320},
e7ecd891 1112 {
203333cb
DJ		 1113 0,
1114 } /* 0 terminated list. */
806c35f5
AC		 1115};
1116
1117MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1118
806c35f5 1119static struct pci_driver e752x_driver = {
680cbbbb 1120 .name = EDAC_MOD_STR,
0d38b049
RD		 1121 .probe = e752x_init_one,
1122 .remove = __devexit_p(e752x_remove_one),
1123 .id_table = e752x_pci_tbl,
806c35f5
AC		 1124};
1125
da9bb1d2 1126static int __init e752x_init(void)
806c35f5
AC		 1127{
1128 int pci_rc;
1129
537fba28 1130 debugf3("%s()\n", __func__);
806c35f5
AC		 1131 pci_rc = pci_register_driver(&e752x_driver);
1132 return (pci_rc < 0) ? pci_rc : 0;
1133}
1134
806c35f5
AC		 1135static void __exit e752x_exit(void)
1136{
537fba28 1137 debugf3("%s()\n", __func__);
806c35f5
AC		 1138 pci_unregister_driver(&e752x_driver);
1139}
1140
806c35f5
AC		 1141module_init(e752x_init);
1142module_exit(e752x_exit);
1143
1144MODULE_LICENSE("GPL");
1145MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1146MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
96941026 1147
1148module_param(force_function_unhide, int, 0444);
1149MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
203333cb 1150 " 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");
c0d12172
DJ		 1151module_param(edac_op_state, int, 0444);
1152MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
kernel source for telekom puls (alcatel/mediatek)