projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
RAS: Add a tracepoint for reporting memory controller events
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / cpc925_edac.c
CommitLineData
2a9036af
HC		 1/*
2 * cpc925_edac.c, EDAC driver for IBM CPC925 Bridge and Memory Controller.
3 *
4 * Copyright (c) 2008 Wind River Systems, Inc.
5 *
6 * Authors: Cao Qingtao <qingtao.cao@windriver.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 * See the GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/io.h>
25#include <linux/edac.h>
26#include <linux/of.h>
27#include <linux/platform_device.h>
5a0e3ad6 28#include <linux/gfp.h>
2a9036af
HC		 29
30#include "edac_core.h"
31#include "edac_module.h"
32
152ba394 33#define CPC925_EDAC_REVISION " Ver: 1.0.0"
2a9036af
HC		 34#define CPC925_EDAC_MOD_STR "cpc925_edac"
35
36#define cpc925_printk(level, fmt, arg...) \
37 edac_printk(level, "CPC925", fmt, ##arg)
38
39#define cpc925_mc_printk(mci, level, fmt, arg...) \
40 edac_mc_chipset_printk(mci, level, "CPC925", fmt, ##arg)
41
42/*
43 * CPC925 registers are of 32 bits with bit0 defined at the
44 * most significant bit and bit31 at that of least significant.
45 */
46#define CPC925_BITS_PER_REG 32
47#define CPC925_BIT(nr) (1UL << (CPC925_BITS_PER_REG - 1 - nr))
48
49/*
50 * EDAC device names for the error detections of
51 * CPU Interface and Hypertransport Link.
52 */
53#define CPC925_CPU_ERR_DEV "cpu"
54#define CPC925_HT_LINK_DEV "htlink"
55
56/* Suppose DDR Refresh cycle is 15.6 microsecond */
57#define CPC925_REF_FREQ 0xFA69
58#define CPC925_SCRUB_BLOCK_SIZE 64 /* bytes */
59#define CPC925_NR_CSROWS 8
60
61/*
62 * All registers and bits definitions are taken from
63 * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02".
64 */
65
66/*
67 * CPU and Memory Controller Registers
68 */
69/************************************************************
70 * Processor Interface Exception Mask Register (APIMASK)
71 ************************************************************/
72#define REG_APIMASK_OFFSET 0x30070
73enum apimask_bits {
74 APIMASK_DART = CPC925_BIT(0), /* DART Exception */
75 APIMASK_ADI0 = CPC925_BIT(1), /* Handshake Error on PI0_ADI */
76 APIMASK_ADI1 = CPC925_BIT(2), /* Handshake Error on PI1_ADI */
77 APIMASK_STAT = CPC925_BIT(3), /* Status Exception */
78 APIMASK_DERR = CPC925_BIT(4), /* Data Error Exception */
79 APIMASK_ADRS0 = CPC925_BIT(5), /* Addressing Exception on PI0 */
80 APIMASK_ADRS1 = CPC925_BIT(6), /* Addressing Exception on PI1 */
81 /* BIT(7) Reserved */
82 APIMASK_ECC_UE_H = CPC925_BIT(8), /* UECC upper */
83 APIMASK_ECC_CE_H = CPC925_BIT(9), /* CECC upper */
84 APIMASK_ECC_UE_L = CPC925_BIT(10), /* UECC lower */
85 APIMASK_ECC_CE_L = CPC925_BIT(11), /* CECC lower */
86
87 CPU_MASK_ENABLE = (APIMASK_DART | APIMASK_ADI0 | APIMASK_ADI1 |
88 APIMASK_STAT | APIMASK_DERR | APIMASK_ADRS0 |
89 APIMASK_ADRS1),
90 ECC_MASK_ENABLE = (APIMASK_ECC_UE_H | APIMASK_ECC_CE_H |
91 APIMASK_ECC_UE_L | APIMASK_ECC_CE_L),
92};
ce395088 93#define APIMASK_ADI(n) CPC925_BIT(((n)+1))
2a9036af
HC		 94
95/************************************************************
96 * Processor Interface Exception Register (APIEXCP)
97 ************************************************************/
98#define REG_APIEXCP_OFFSET 0x30060
99enum apiexcp_bits {
100 APIEXCP_DART = CPC925_BIT(0), /* DART Exception */
101 APIEXCP_ADI0 = CPC925_BIT(1), /* Handshake Error on PI0_ADI */
102 APIEXCP_ADI1 = CPC925_BIT(2), /* Handshake Error on PI1_ADI */
103 APIEXCP_STAT = CPC925_BIT(3), /* Status Exception */
104 APIEXCP_DERR = CPC925_BIT(4), /* Data Error Exception */
105 APIEXCP_ADRS0 = CPC925_BIT(5), /* Addressing Exception on PI0 */
106 APIEXCP_ADRS1 = CPC925_BIT(6), /* Addressing Exception on PI1 */
107 /* BIT(7) Reserved */
108 APIEXCP_ECC_UE_H = CPC925_BIT(8), /* UECC upper */
109 APIEXCP_ECC_CE_H = CPC925_BIT(9), /* CECC upper */
110 APIEXCP_ECC_UE_L = CPC925_BIT(10), /* UECC lower */
111 APIEXCP_ECC_CE_L = CPC925_BIT(11), /* CECC lower */
112
113 CPU_EXCP_DETECTED = (APIEXCP_DART | APIEXCP_ADI0 | APIEXCP_ADI1 |
114 APIEXCP_STAT | APIEXCP_DERR | APIEXCP_ADRS0 |
115 APIEXCP_ADRS1),
116 UECC_EXCP_DETECTED = (APIEXCP_ECC_UE_H | APIEXCP_ECC_UE_L),
117 CECC_EXCP_DETECTED = (APIEXCP_ECC_CE_H | APIEXCP_ECC_CE_L),
118 ECC_EXCP_DETECTED = (UECC_EXCP_DETECTED | CECC_EXCP_DETECTED),
119};
120
121/************************************************************
122 * Memory Bus Configuration Register (MBCR)
123************************************************************/
124#define REG_MBCR_OFFSET 0x2190
125#define MBCR_64BITCFG_SHIFT 23
126#define MBCR_64BITCFG_MASK (1UL << MBCR_64BITCFG_SHIFT)
127#define MBCR_64BITBUS_SHIFT 22
128#define MBCR_64BITBUS_MASK (1UL << MBCR_64BITBUS_SHIFT)
129
130/************************************************************
131 * Memory Bank Mode Register (MBMR)
132************************************************************/
133#define REG_MBMR_OFFSET 0x21C0
134#define MBMR_MODE_MAX_VALUE 0xF
135#define MBMR_MODE_SHIFT 25
136#define MBMR_MODE_MASK (MBMR_MODE_MAX_VALUE << MBMR_MODE_SHIFT)
137#define MBMR_BBA_SHIFT 24
138#define MBMR_BBA_MASK (1UL << MBMR_BBA_SHIFT)
139
140/************************************************************
141 * Memory Bank Boundary Address Register (MBBAR)
142 ************************************************************/
143#define REG_MBBAR_OFFSET 0x21D0
144#define MBBAR_BBA_MAX_VALUE 0xFF
145#define MBBAR_BBA_SHIFT 24
146#define MBBAR_BBA_MASK (MBBAR_BBA_MAX_VALUE << MBBAR_BBA_SHIFT)
147
148/************************************************************
149 * Memory Scrub Control Register (MSCR)
150 ************************************************************/
151#define REG_MSCR_OFFSET 0x2400
152#define MSCR_SCRUB_MOD_MASK 0xC0000000 /* scrub_mod - bit0:1*/
153#define MSCR_BACKGR_SCRUB 0x40000000 /* 01 */
154#define MSCR_SI_SHIFT 16 /* si - bit8:15*/
155#define MSCR_SI_MAX_VALUE 0xFF
156#define MSCR_SI_MASK (MSCR_SI_MAX_VALUE << MSCR_SI_SHIFT)
157
158/************************************************************
159 * Memory Scrub Range Start Register (MSRSR)
160 ************************************************************/
161#define REG_MSRSR_OFFSET 0x2410
162
163/************************************************************
164 * Memory Scrub Range End Register (MSRER)
165 ************************************************************/
166#define REG_MSRER_OFFSET 0x2420
167
168/************************************************************
169 * Memory Scrub Pattern Register (MSPR)
170 ************************************************************/
171#define REG_MSPR_OFFSET 0x2430
172
173/************************************************************
174 * Memory Check Control Register (MCCR)
175 ************************************************************/
176#define REG_MCCR_OFFSET 0x2440
177enum mccr_bits {
178 MCCR_ECC_EN = CPC925_BIT(0), /* ECC high and low check */
179};
180
181/************************************************************
182 * Memory Check Range End Register (MCRER)
183 ************************************************************/
184#define REG_MCRER_OFFSET 0x2450
185
186/************************************************************
187 * Memory Error Address Register (MEAR)
188 ************************************************************/
189#define REG_MEAR_OFFSET 0x2460
190#define MEAR_BCNT_MAX_VALUE 0x3
191#define MEAR_BCNT_SHIFT 30
192#define MEAR_BCNT_MASK (MEAR_BCNT_MAX_VALUE << MEAR_BCNT_SHIFT)
193#define MEAR_RANK_MAX_VALUE 0x7
194#define MEAR_RANK_SHIFT 27
195#define MEAR_RANK_MASK (MEAR_RANK_MAX_VALUE << MEAR_RANK_SHIFT)
196#define MEAR_COL_MAX_VALUE 0x7FF
197#define MEAR_COL_SHIFT 16
198#define MEAR_COL_MASK (MEAR_COL_MAX_VALUE << MEAR_COL_SHIFT)
199#define MEAR_BANK_MAX_VALUE 0x3
200#define MEAR_BANK_SHIFT 14
201#define MEAR_BANK_MASK (MEAR_BANK_MAX_VALUE << MEAR_BANK_SHIFT)
202#define MEAR_ROW_MASK 0x00003FFF
203
204/************************************************************
205 * Memory Error Syndrome Register (MESR)
206 ************************************************************/
207#define REG_MESR_OFFSET 0x2470
208#define MESR_ECC_SYN_H_MASK 0xFF00
209#define MESR_ECC_SYN_L_MASK 0x00FF
210
211/************************************************************
212 * Memory Mode Control Register (MMCR)
213 ************************************************************/
214#define REG_MMCR_OFFSET 0x2500
215enum mmcr_bits {
216 MMCR_REG_DIMM_MODE = CPC925_BIT(3),
217};
218
219/*
220 * HyperTransport Link Registers
221 */
222/************************************************************
223 * Error Handling/Enumeration Scratch Pad Register (ERRCTRL)
224 ************************************************************/
225#define REG_ERRCTRL_OFFSET 0x70140
226enum errctrl_bits { /* nonfatal interrupts for */
227 ERRCTRL_SERR_NF = CPC925_BIT(0), /* system error */
228 ERRCTRL_CRC_NF = CPC925_BIT(1), /* CRC error */
229 ERRCTRL_RSP_NF = CPC925_BIT(2), /* Response error */
230 ERRCTRL_EOC_NF = CPC925_BIT(3), /* End-Of-Chain error */
231 ERRCTRL_OVF_NF = CPC925_BIT(4), /* Overflow error */
232 ERRCTRL_PROT_NF = CPC925_BIT(5), /* Protocol error */
233
234 ERRCTRL_RSP_ERR = CPC925_BIT(6), /* Response error received */
235 ERRCTRL_CHN_FAL = CPC925_BIT(7), /* Sync flooding detected */
236
237 HT_ERRCTRL_ENABLE = (ERRCTRL_SERR_NF | ERRCTRL_CRC_NF |
238 ERRCTRL_RSP_NF | ERRCTRL_EOC_NF |
239 ERRCTRL_OVF_NF | ERRCTRL_PROT_NF),
240 HT_ERRCTRL_DETECTED = (ERRCTRL_RSP_ERR | ERRCTRL_CHN_FAL),
241};
242
243/************************************************************
244 * Link Configuration and Link Control Register (LINKCTRL)
245 ************************************************************/
246#define REG_LINKCTRL_OFFSET 0x70110
247enum linkctrl_bits {
248 LINKCTRL_CRC_ERR = (CPC925_BIT(22) | CPC925_BIT(23)),
249 LINKCTRL_LINK_FAIL = CPC925_BIT(27),
250
251 HT_LINKCTRL_DETECTED = (LINKCTRL_CRC_ERR | LINKCTRL_LINK_FAIL),
252};
253
254/************************************************************
255 * Link FreqCap/Error/Freq/Revision ID Register (LINKERR)
256 ************************************************************/
257#define REG_LINKERR_OFFSET 0x70120
258enum linkerr_bits {
259 LINKERR_EOC_ERR = CPC925_BIT(17), /* End-Of-Chain error */
260 LINKERR_OVF_ERR = CPC925_BIT(18), /* Receive Buffer Overflow */
261 LINKERR_PROT_ERR = CPC925_BIT(19), /* Protocol error */
262
263 HT_LINKERR_DETECTED = (LINKERR_EOC_ERR | LINKERR_OVF_ERR |
264 LINKERR_PROT_ERR),
265};
266
267/************************************************************
268 * Bridge Control Register (BRGCTRL)
269 ************************************************************/
270#define REG_BRGCTRL_OFFSET 0x70300
271enum brgctrl_bits {
272 BRGCTRL_DETSERR = CPC925_BIT(0), /* SERR on Secondary Bus */
273 BRGCTRL_SECBUSRESET = CPC925_BIT(9), /* Secondary Bus Reset */
274};
275
276/* Private structure for edac memory controller */
277struct cpc925_mc_pdata {
278 void __iomem *vbase;
279 unsigned long total_mem;
280 const char *name;
281 int edac_idx;
282};
283
284/* Private structure for common edac device */
285struct cpc925_dev_info {
286 void __iomem *vbase;
287 struct platform_device *pdev;
288 char *ctl_name;
289 int edac_idx;
290 struct edac_device_ctl_info *edac_dev;
291 void (*init)(struct cpc925_dev_info *dev_info);
292 void (*exit)(struct cpc925_dev_info *dev_info);
293 void (*check)(struct edac_device_ctl_info *edac_dev);
294};
295
296/* Get total memory size from Open Firmware DTB */
297static void get_total_mem(struct cpc925_mc_pdata *pdata)
298{
299 struct device_node *np = NULL;
300 const unsigned int *reg, *reg_end;
301 int len, sw, aw;
302 unsigned long start, size;
303
304 np = of_find_node_by_type(NULL, "memory");
305 if (!np)
306 return;
307
308 aw = of_n_addr_cells(np);
309 sw = of_n_size_cells(np);
310 reg = (const unsigned int *)of_get_property(np, "reg", &len);
311 reg_end = reg + len/4;
312
313 pdata->total_mem = 0;
314 do {
315 start = of_read_number(reg, aw);
316 reg += aw;
317 size = of_read_number(reg, sw);
318 reg += sw;
319 debugf1("%s: start 0x%lx, size 0x%lx\n", __func__,
320 start, size);
321 pdata->total_mem += size;
322 } while (reg < reg_end);
323
324 of_node_put(np);
325 debugf0("%s: total_mem 0x%lx\n", __func__, pdata->total_mem);
326}
327
328static void cpc925_init_csrows(struct mem_ctl_info *mci)
329{
330 struct cpc925_mc_pdata *pdata = mci->pvt_info;
331 struct csrow_info *csrow;
084a4fcc
MCC		 332 struct dimm_info *dimm;
333 int index, j;
2a9036af 334 u32 mbmr, mbbar, bba;
a895bf8b 335 unsigned long row_size, nr_pages, last_nr_pages = 0;
2a9036af
HC		 336
337 get_total_mem(pdata);
338
339 for (index = 0; index < mci->nr_csrows; index++) {
340 mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET +
341 0x20 * index);
342 mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET +
343 0x20 + index);
344 bba = (((mbmr & MBMR_BBA_MASK) >> MBMR_BBA_SHIFT) << 8) |
345 ((mbbar & MBBAR_BBA_MASK) >> MBBAR_BBA_SHIFT);
346
347 if (bba == 0)
348 continue; /* not populated */
349
350 csrow = &mci->csrows[index];
351
352 row_size = bba * (1UL << 28); /* 256M */
353 csrow->first_page = last_nr_pages;
a895bf8b
MCC		 354 nr_pages = row_size >> PAGE_SHIFT;
355 csrow->last_page = csrow->first_page + nr_pages - 1;
2a9036af
HC		 356 last_nr_pages = csrow->last_page + 1;
357
084a4fcc
MCC		 358 for (j = 0; j < csrow->nr_channels; j++) {
359 dimm = csrow->channels[j].dimm;
a895bf8b
MCC		 360
361 dimm->nr_pages = nr_pages / csrow->nr_channels;
084a4fcc
MCC		 362 dimm->mtype = MEM_RDDR;
363 dimm->edac_mode = EDAC_SECDED;
364
365 switch (csrow->nr_channels) {
366 case 1: /* Single channel */
367 dimm->grain = 32; /* four-beat burst of 32 bytes */
368 break;
369 case 2: /* Dual channel */
370 default:
371 dimm->grain = 64; /* four-beat burst of 64 bytes */
372 break;
373 }
374
375 switch ((mbmr & MBMR_MODE_MASK) >> MBMR_MODE_SHIFT) {
376 case 6: /* 0110, no way to differentiate X8 VS X16 */
377 case 5: /* 0101 */
378 case 8: /* 1000 */
379 dimm->dtype = DEV_X16;
380 break;
381 case 7: /* 0111 */
382 case 9: /* 1001 */
383 dimm->dtype = DEV_X8;
384 break;
385 default:
386 dimm->dtype = DEV_UNKNOWN;
387 break;
388 }
2a9036af
HC		 389 }
390 }
391}
392
393/* Enable memory controller ECC detection */
394static void cpc925_mc_init(struct mem_ctl_info *mci)
395{
396 struct cpc925_mc_pdata *pdata = mci->pvt_info;
397 u32 apimask;
398 u32 mccr;
399
400 /* Enable various ECC error exceptions */
401 apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET);
402 if ((apimask & ECC_MASK_ENABLE) == 0) {
403 apimask |= ECC_MASK_ENABLE;
404 __raw_writel(apimask, pdata->vbase + REG_APIMASK_OFFSET);
405 }
406
407 /* Enable ECC detection */
408 mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET);
409 if ((mccr & MCCR_ECC_EN) == 0) {
410 mccr |= MCCR_ECC_EN;
411 __raw_writel(mccr, pdata->vbase + REG_MCCR_OFFSET);
412 }
413}
414
415/* Disable memory controller ECC detection */
416static void cpc925_mc_exit(struct mem_ctl_info *mci)
417{
418 /*
419 * WARNING:
420 * We are supposed to clear the ECC error detection bits,
421 * and it will be no problem to do so. However, once they
422 * are cleared here if we want to re-install CPC925 EDAC
423 * module later, setting them up in cpc925_mc_init() will
424 * trigger machine check exception.
425 * Also, it's ok to leave ECC error detection bits enabled,
426 * since they are reset to 1 by default or by boot loader.
427 */
428
429 return;
430}
431
432/*
433 * Revert DDR column/row/bank addresses into page frame number and
434 * offset in page.
435 *
436 * Suppose memory mode is 0x0111(128-bit mode, identical DIMM pairs),
437 * physical address(PA) bits to column address(CA) bits mappings are:
438 * CA 0 1 2 3 4 5 6 7 8 9 10
439 * PA 59 58 57 56 55 54 53 52 51 50 49
440 *
441 * physical address(PA) bits to bank address(BA) bits mappings are:
442 * BA 0 1
443 * PA 43 44
444 *
445 * physical address(PA) bits to row address(RA) bits mappings are:
446 * RA 0 1 2 3 4 5 6 7 8 9 10 11 12
447 * PA 36 35 34 48 47 46 45 40 41 42 39 38 37
448 */
449static void cpc925_mc_get_pfn(struct mem_ctl_info *mci, u32 mear,
450 unsigned long *pfn, unsigned long *offset, int *csrow)
451{
452 u32 bcnt, rank, col, bank, row;
453 u32 c;
454 unsigned long pa;
455 int i;
456
457 bcnt = (mear & MEAR_BCNT_MASK) >> MEAR_BCNT_SHIFT;
458 rank = (mear & MEAR_RANK_MASK) >> MEAR_RANK_SHIFT;
459 col = (mear & MEAR_COL_MASK) >> MEAR_COL_SHIFT;
460 bank = (mear & MEAR_BANK_MASK) >> MEAR_BANK_SHIFT;
461 row = mear & MEAR_ROW_MASK;
462
463 *csrow = rank;
464
465#ifdef CONFIG_EDAC_DEBUG
466 if (mci->csrows[rank].first_page == 0) {
467 cpc925_mc_printk(mci, KERN_ERR, "ECC occurs in a "
468 "non-populated csrow, broken hardware?\n");
469 return;
470 }
471#endif
472
473 /* Revert csrow number */
474 pa = mci->csrows[rank].first_page << PAGE_SHIFT;
475
476 /* Revert column address */
477 col += bcnt;
478 for (i = 0; i < 11; i++) {
479 c = col & 0x1;
480 col >>= 1;
481 pa |= c << (14 - i);
482 }
483
484 /* Revert bank address */
485 pa |= bank << 19;
486
487 /* Revert row address, in 4 steps */
488 for (i = 0; i < 3; i++) {
489 c = row & 0x1;
490 row >>= 1;
491 pa |= c << (26 - i);
492 }
493
494 for (i = 0; i < 3; i++) {
495 c = row & 0x1;
496 row >>= 1;
497 pa |= c << (21 + i);
498 }
499
500 for (i = 0; i < 4; i++) {
501 c = row & 0x1;
502 row >>= 1;
503 pa |= c << (18 - i);
504 }
505
506 for (i = 0; i < 3; i++) {
507 c = row & 0x1;
508 row >>= 1;
509 pa |= c << (29 - i);
510 }
511
512 *offset = pa & (PAGE_SIZE - 1);
513 *pfn = pa >> PAGE_SHIFT;
514
515 debugf0("%s: ECC physical address 0x%lx\n", __func__, pa);
516}
517
518static int cpc925_mc_find_channel(struct mem_ctl_info *mci, u16 syndrome)
519{
520 if ((syndrome & MESR_ECC_SYN_H_MASK) == 0)
521 return 0;
522
523 if ((syndrome & MESR_ECC_SYN_L_MASK) == 0)
524 return 1;
525
526 cpc925_mc_printk(mci, KERN_INFO, "Unexpected syndrome value: 0x%x\n",
527 syndrome);
528 return 1;
529}
530
531/* Check memory controller registers for ECC errors */
532static void cpc925_mc_check(struct mem_ctl_info *mci)
533{
534 struct cpc925_mc_pdata *pdata = mci->pvt_info;
535 u32 apiexcp;
536 u32 mear;
537 u32 mesr;
538 u16 syndrome;
539 unsigned long pfn = 0, offset = 0;
540 int csrow = 0, channel = 0;
541
542 /* APIEXCP is cleared when read */
543 apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET);
544 if ((apiexcp & ECC_EXCP_DETECTED) == 0)
545 return;
546
547 mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET);
548 syndrome = mesr | (MESR_ECC_SYN_H_MASK | MESR_ECC_SYN_L_MASK);
549
550 mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET);
551
552 /* Revert column/row addresses into page frame number, etc */
553 cpc925_mc_get_pfn(mci, mear, &pfn, &offset, &csrow);
554
555 if (apiexcp & CECC_EXCP_DETECTED) {
556 cpc925_mc_printk(mci, KERN_INFO, "DRAM CECC Fault\n");
557 channel = cpc925_mc_find_channel(mci, syndrome);
df62b1e6
MCC		 558 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
559 pfn, offset, syndrome,
560 csrow, channel, -1,
561 mci->ctl_name, "", NULL);
2a9036af
HC		 562 }
563
564 if (apiexcp & UECC_EXCP_DETECTED) {
565 cpc925_mc_printk(mci, KERN_INFO, "DRAM UECC Fault\n");
df62b1e6
MCC		 566 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
567 pfn, offset, 0,
568 csrow, -1, -1,
569 mci->ctl_name, "", NULL);
2a9036af
HC		 570 }
571
572 cpc925_mc_printk(mci, KERN_INFO, "Dump registers:\n");
573 cpc925_mc_printk(mci, KERN_INFO, "APIMASK 0x%08x\n",
574 __raw_readl(pdata->vbase + REG_APIMASK_OFFSET));
575 cpc925_mc_printk(mci, KERN_INFO, "APIEXCP 0x%08x\n",
576 apiexcp);
577 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Ctrl 0x%08x\n",
578 __raw_readl(pdata->vbase + REG_MSCR_OFFSET));
579 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge Start 0x%08x\n",
580 __raw_readl(pdata->vbase + REG_MSRSR_OFFSET));
581 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge End 0x%08x\n",
582 __raw_readl(pdata->vbase + REG_MSRER_OFFSET));
583 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Pattern 0x%08x\n",
584 __raw_readl(pdata->vbase + REG_MSPR_OFFSET));
585 cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Ctrl 0x%08x\n",
586 __raw_readl(pdata->vbase + REG_MCCR_OFFSET));
587 cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Rge End 0x%08x\n",
588 __raw_readl(pdata->vbase + REG_MCRER_OFFSET));
589 cpc925_mc_printk(mci, KERN_INFO, "Mem Err Address 0x%08x\n",
590 mesr);
591 cpc925_mc_printk(mci, KERN_INFO, "Mem Err Syndrome 0x%08x\n",
592 syndrome);
593}
594
595/******************** CPU err device********************************/
ce395088
DES		 596static u32 cpc925_cpu_mask_disabled(void)
597{
598 struct device_node *cpus;
599 struct device_node *cpunode = NULL;
600 static u32 mask = 0;
601
602 /* use cached value if available */
603 if (mask != 0)
604 return mask;
605
606 mask = APIMASK_ADI0 | APIMASK_ADI1;
607
608 cpus = of_find_node_by_path("/cpus");
609 if (cpus == NULL) {
610 cpc925_printk(KERN_DEBUG, "No /cpus node !\n");
611 return 0;
612 }
613
614 while ((cpunode = of_get_next_child(cpus, cpunode)) != NULL) {
615 const u32 *reg = of_get_property(cpunode, "reg", NULL);
616
617 if (strcmp(cpunode->type, "cpu")) {
618 cpc925_printk(KERN_ERR, "Not a cpu node in /cpus: %s\n", cpunode->name);
619 continue;
620 }
621
622 if (reg == NULL || *reg > 2) {
623 cpc925_printk(KERN_ERR, "Bad reg value at %s\n", cpunode->full_name);
624 continue;
625 }
626
627 mask &= ~APIMASK_ADI(*reg);
628 }
629
630 if (mask != (APIMASK_ADI0 | APIMASK_ADI1)) {
631 /* We assume that each CPU sits on it's own PI and that
632 * for present CPUs the reg property equals to the PI
633 * interface id */
634 cpc925_printk(KERN_WARNING,
635 "Assuming PI id is equal to CPU MPIC id!\n");
636 }
637
638 of_node_put(cpunode);
639 of_node_put(cpus);
640
641 return mask;
642}
643
2a9036af
HC		 644/* Enable CPU Errors detection */
645static void cpc925_cpu_init(struct cpc925_dev_info *dev_info)
646{
647 u32 apimask;
ce395088 648 u32 cpumask;
2a9036af
HC		 649
650 apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
ce395088
DES		 651
652 cpumask = cpc925_cpu_mask_disabled();
653 if (apimask & cpumask) {
654 cpc925_printk(KERN_WARNING, "CPU(s) not present, "
655 "but enabled in APIMASK, disabling\n");
656 apimask &= ~cpumask;
2a9036af 657 }
ce395088
DES		 658
659 if ((apimask & CPU_MASK_ENABLE) == 0)
660 apimask |= CPU_MASK_ENABLE;
661
662 __raw_writel(apimask, dev_info->vbase + REG_APIMASK_OFFSET);
2a9036af
HC		 663}
664
665/* Disable CPU Errors detection */
666static void cpc925_cpu_exit(struct cpc925_dev_info *dev_info)
667{
668 /*
669 * WARNING:
670 * We are supposed to clear the CPU error detection bits,
671 * and it will be no problem to do so. However, once they
672 * are cleared here if we want to re-install CPC925 EDAC
673 * module later, setting them up in cpc925_cpu_init() will
674 * trigger machine check exception.
675 * Also, it's ok to leave CPU error detection bits enabled,
676 * since they are reset to 1 by default.
677 */
678
679 return;
680}
681
682/* Check for CPU Errors */
683static void cpc925_cpu_check(struct edac_device_ctl_info *edac_dev)
684{
685 struct cpc925_dev_info *dev_info = edac_dev->pvt_info;
686 u32 apiexcp;
687 u32 apimask;
688
689 /* APIEXCP is cleared when read */
690 apiexcp = __raw_readl(dev_info->vbase + REG_APIEXCP_OFFSET);
691 if ((apiexcp & CPU_EXCP_DETECTED) == 0)
692 return;
693
ce395088
DES		 694 if ((apiexcp & ~cpc925_cpu_mask_disabled()) == 0)
695 return;
696
2a9036af
HC		 697 apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
698 cpc925_printk(KERN_INFO, "Processor Interface Fault\n"
699 "Processor Interface register dump:\n");
700 cpc925_printk(KERN_INFO, "APIMASK 0x%08x\n", apimask);
701 cpc925_printk(KERN_INFO, "APIEXCP 0x%08x\n", apiexcp);
702
703 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
704}
705
706/******************** HT Link err device****************************/
707/* Enable HyperTransport Link Error detection */
708static void cpc925_htlink_init(struct cpc925_dev_info *dev_info)
709{
710 u32 ht_errctrl;
711
712 ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
713 if ((ht_errctrl & HT_ERRCTRL_ENABLE) == 0) {
714 ht_errctrl |= HT_ERRCTRL_ENABLE;
715 __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
716 }
717}
718
719/* Disable HyperTransport Link Error detection */
720static void cpc925_htlink_exit(struct cpc925_dev_info *dev_info)
721{
722 u32 ht_errctrl;
723
724 ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
725 ht_errctrl &= ~HT_ERRCTRL_ENABLE;
726 __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
727}
728
729/* Check for HyperTransport Link errors */
730static void cpc925_htlink_check(struct edac_device_ctl_info *edac_dev)
731{
732 struct cpc925_dev_info *dev_info = edac_dev->pvt_info;
733 u32 brgctrl = __raw_readl(dev_info->vbase + REG_BRGCTRL_OFFSET);
734 u32 linkctrl = __raw_readl(dev_info->vbase + REG_LINKCTRL_OFFSET);
735 u32 errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
736 u32 linkerr = __raw_readl(dev_info->vbase + REG_LINKERR_OFFSET);
737
738 if (!((brgctrl & BRGCTRL_DETSERR) ||
739 (linkctrl & HT_LINKCTRL_DETECTED) ||
740 (errctrl & HT_ERRCTRL_DETECTED) ||
741 (linkerr & HT_LINKERR_DETECTED)))
742 return;
743
744 cpc925_printk(KERN_INFO, "HT Link Fault\n"
745 "HT register dump:\n");
746 cpc925_printk(KERN_INFO, "Bridge Ctrl 0x%08x\n",
747 brgctrl);
748 cpc925_printk(KERN_INFO, "Link Config Ctrl 0x%08x\n",
749 linkctrl);
750 cpc925_printk(KERN_INFO, "Error Enum and Ctrl 0x%08x\n",
751 errctrl);
752 cpc925_printk(KERN_INFO, "Link Error 0x%08x\n",
753 linkerr);
754
755 /* Clear by write 1 */
756 if (brgctrl & BRGCTRL_DETSERR)
757 __raw_writel(BRGCTRL_DETSERR,
758 dev_info->vbase + REG_BRGCTRL_OFFSET);
759
760 if (linkctrl & HT_LINKCTRL_DETECTED)
761 __raw_writel(HT_LINKCTRL_DETECTED,
762 dev_info->vbase + REG_LINKCTRL_OFFSET);
763
764 /* Initiate Secondary Bus Reset to clear the chain failure */
765 if (errctrl & ERRCTRL_CHN_FAL)
766 __raw_writel(BRGCTRL_SECBUSRESET,
767 dev_info->vbase + REG_BRGCTRL_OFFSET);
768
769 if (errctrl & ERRCTRL_RSP_ERR)
770 __raw_writel(ERRCTRL_RSP_ERR,
771 dev_info->vbase + REG_ERRCTRL_OFFSET);
772
773 if (linkerr & HT_LINKERR_DETECTED)
774 __raw_writel(HT_LINKERR_DETECTED,
775 dev_info->vbase + REG_LINKERR_OFFSET);
776
777 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
778}
779
780static struct cpc925_dev_info cpc925_devs[] = {
781 {
782 .ctl_name = CPC925_CPU_ERR_DEV,
783 .init = cpc925_cpu_init,
784 .exit = cpc925_cpu_exit,
785 .check = cpc925_cpu_check,
786 },
787 {
788 .ctl_name = CPC925_HT_LINK_DEV,
789 .init = cpc925_htlink_init,
790 .exit = cpc925_htlink_exit,
791 .check = cpc925_htlink_check,
792 },
793 {0}, /* Terminated by NULL */
794};
795
796/*
797 * Add CPU Err detection and HyperTransport Link Err detection
798 * as common "edac_device", they have no corresponding device
799 * nodes in the Open Firmware DTB and we have to add platform
800 * devices for them. Also, they will share the MMIO with that
801 * of memory controller.
802 */
803static void cpc925_add_edac_devices(void __iomem *vbase)
804{
805 struct cpc925_dev_info *dev_info;
806
807 if (!vbase) {
808 cpc925_printk(KERN_ERR, "MMIO not established yet\n");
809 return;
810 }
811
812 for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) {
813 dev_info->vbase = vbase;
814 dev_info->pdev = platform_device_register_simple(
815 dev_info->ctl_name, 0, NULL, 0);
816 if (IS_ERR(dev_info->pdev)) {
817 cpc925_printk(KERN_ERR,
818 "Can't register platform device for %s\n",
819 dev_info->ctl_name);
820 continue;
821 }
822
823 /*
824 * Don't have to allocate private structure but
825 * make use of cpc925_devs[] instead.
826 */
827 dev_info->edac_idx = edac_device_alloc_index();
828 dev_info->edac_dev =
829 edac_device_alloc_ctl_info(0, dev_info->ctl_name,
830 1, NULL, 0, 0, NULL, 0, dev_info->edac_idx);
831 if (!dev_info->edac_dev) {
832 cpc925_printk(KERN_ERR, "No memory for edac device\n");
833 goto err1;
834 }
835
836 dev_info->edac_dev->pvt_info = dev_info;
837 dev_info->edac_dev->dev = &dev_info->pdev->dev;
838 dev_info->edac_dev->ctl_name = dev_info->ctl_name;
839 dev_info->edac_dev->mod_name = CPC925_EDAC_MOD_STR;
840 dev_info->edac_dev->dev_name = dev_name(&dev_info->pdev->dev);
841
842 if (edac_op_state == EDAC_OPSTATE_POLL)
843 dev_info->edac_dev->edac_check = dev_info->check;
844
845 if (dev_info->init)
846 dev_info->init(dev_info);
847
848 if (edac_device_add_device(dev_info->edac_dev) > 0) {
849 cpc925_printk(KERN_ERR,
850 "Unable to add edac device for %s\n",
851 dev_info->ctl_name);
852 goto err2;
853 }
854
855 debugf0("%s: Successfully added edac device for %s\n",
856 __func__, dev_info->ctl_name);
857
858 continue;
859
860err2:
861 if (dev_info->exit)
862 dev_info->exit(dev_info);
863 edac_device_free_ctl_info(dev_info->edac_dev);
864err1:
865 platform_device_unregister(dev_info->pdev);
866 }
867}
868
869/*
870 * Delete the common "edac_device" for CPU Err Detection
871 * and HyperTransport Link Err Detection
872 */
873static void cpc925_del_edac_devices(void)
874{
875 struct cpc925_dev_info *dev_info;
876
877 for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) {
878 if (dev_info->edac_dev) {
879 edac_device_del_device(dev_info->edac_dev->dev);
880 edac_device_free_ctl_info(dev_info->edac_dev);
881 platform_device_unregister(dev_info->pdev);
882 }
883
884 if (dev_info->exit)
885 dev_info->exit(dev_info);
886
887 debugf0("%s: Successfully deleted edac device for %s\n",
888 __func__, dev_info->ctl_name);
889 }
890}
891
25985edc 892/* Convert current back-ground scrub rate into byte/sec bandwidth */
39094443 893static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci)
2a9036af
HC		 894{
895 struct cpc925_mc_pdata *pdata = mci->pvt_info;
39094443 896 int bw;
2a9036af
HC		 897 u32 mscr;
898 u8 si;
899
900 mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET);
901 si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT;
902
903 debugf0("%s, Mem Scrub Ctrl Register 0x%x\n", __func__, mscr);
904
905 if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) ||
906 (si == 0)) {
907 cpc925_mc_printk(mci, KERN_INFO, "Scrub mode not enabled\n");
39094443 908 bw = 0;
2a9036af 909 } else
39094443 910 bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si;
2a9036af 911
39094443 912 return bw;
2a9036af
HC		 913}
914
915/* Return 0 for single channel; 1 for dual channel */
916static int cpc925_mc_get_channels(void __iomem *vbase)
917{
918 int dual = 0;
919 u32 mbcr;
920
921 mbcr = __raw_readl(vbase + REG_MBCR_OFFSET);
922
923 /*
924 * Dual channel only when 128-bit wide physical bus
925 * and 128-bit configuration.
926 */
927 if (((mbcr & MBCR_64BITCFG_MASK) == 0) &&
928 ((mbcr & MBCR_64BITBUS_MASK) == 0))
929 dual = 1;
930
931 debugf0("%s: %s channel\n", __func__,
932 (dual > 0) ? "Dual" : "Single");
933
934 return dual;
935}
936
937static int __devinit cpc925_probe(struct platform_device *pdev)
938{
939 static int edac_mc_idx;
940 struct mem_ctl_info *mci;
df62b1e6 941 struct edac_mc_layer layers[2];
2a9036af
HC		 942 void __iomem *vbase;
943 struct cpc925_mc_pdata *pdata;
944 struct resource *r;
945 int res = 0, nr_channels;
946
947 debugf0("%s: %s platform device found!\n", __func__, pdev->name);
948
949 if (!devres_open_group(&pdev->dev, cpc925_probe, GFP_KERNEL)) {
950 res = -ENOMEM;
951 goto out;
952 }
953
954 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
955 if (!r) {
956 cpc925_printk(KERN_ERR, "Unable to get resource\n");
957 res = -ENOENT;
958 goto err1;
959 }
960
961 if (!devm_request_mem_region(&pdev->dev,
962 r->start,
30a61fff 963 resource_size(r),
2a9036af
HC		 964 pdev->name)) {
965 cpc925_printk(KERN_ERR, "Unable to request mem region\n");
966 res = -EBUSY;
967 goto err1;
968 }
969
30a61fff 970 vbase = devm_ioremap(&pdev->dev, r->start, resource_size(r));
2a9036af
HC		 971 if (!vbase) {
972 cpc925_printk(KERN_ERR, "Unable to ioremap device\n");
973 res = -ENOMEM;
974 goto err2;
975 }
976
084a4fcc 977 nr_channels = cpc925_mc_get_channels(vbase) + 1;
df62b1e6
MCC		 978
979 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
980 layers[0].size = CPC925_NR_CSROWS;
981 layers[0].is_virt_csrow = true;
982 layers[1].type = EDAC_MC_LAYER_CHANNEL;
983 layers[1].size = nr_channels;
984 layers[1].is_virt_csrow = false;
ca0907b9 985 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
df62b1e6 986 sizeof(struct cpc925_mc_pdata));
2a9036af
HC		 987 if (!mci) {
988 cpc925_printk(KERN_ERR, "No memory for mem_ctl_info\n");
989 res = -ENOMEM;
990 goto err2;
991 }
992
993 pdata = mci->pvt_info;
994 pdata->vbase = vbase;
995 pdata->edac_idx = edac_mc_idx++;
996 pdata->name = pdev->name;
997
998 mci->dev = &pdev->dev;
999 platform_set_drvdata(pdev, mci);
1000 mci->dev_name = dev_name(&pdev->dev);
1001 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
1002 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
1003 mci->edac_cap = EDAC_FLAG_SECDED;
1004 mci->mod_name = CPC925_EDAC_MOD_STR;
1005 mci->mod_ver = CPC925_EDAC_REVISION;
1006 mci->ctl_name = pdev->name;
1007
1008 if (edac_op_state == EDAC_OPSTATE_POLL)
1009 mci->edac_check = cpc925_mc_check;
1010
1011 mci->ctl_page_to_phys = NULL;
1012 mci->scrub_mode = SCRUB_SW_SRC;
1013 mci->set_sdram_scrub_rate = NULL;
1014 mci->get_sdram_scrub_rate = cpc925_get_sdram_scrub_rate;
1015
1016 cpc925_init_csrows(mci);
1017
1018 /* Setup memory controller registers */
1019 cpc925_mc_init(mci);
1020
1021 if (edac_mc_add_mc(mci) > 0) {
1022 cpc925_mc_printk(mci, KERN_ERR, "Failed edac_mc_add_mc()\n");
1023 goto err3;
1024 }
1025
1026 cpc925_add_edac_devices(vbase);
1027
1028 /* get this far and it's successful */
1029 debugf0("%s: success\n", __func__);
1030
1031 res = 0;
1032 goto out;
1033
1034err3:
1035 cpc925_mc_exit(mci);
1036 edac_mc_free(mci);
1037err2:
30a61fff 1038 devm_release_mem_region(&pdev->dev, r->start, resource_size(r));
2a9036af
HC		 1039err1:
1040 devres_release_group(&pdev->dev, cpc925_probe);
1041out:
1042 return res;
1043}
1044
1045static int cpc925_remove(struct platform_device *pdev)
1046{
1047 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
1048
1049 /*
1050 * Delete common edac devices before edac mc, because
1051 * the former share the MMIO of the latter.
1052 */
1053 cpc925_del_edac_devices();
1054 cpc925_mc_exit(mci);
1055
1056 edac_mc_del_mc(&pdev->dev);
1057 edac_mc_free(mci);
1058
1059 return 0;
1060}
1061
1062static struct platform_driver cpc925_edac_driver = {
1063 .probe = cpc925_probe,
1064 .remove = cpc925_remove,
1065 .driver = {
1066 .name = "cpc925_edac",
1067 }
1068};
1069
1070static int __init cpc925_edac_init(void)
1071{
1072 int ret = 0;
1073
1074 printk(KERN_INFO "IBM CPC925 EDAC driver " CPC925_EDAC_REVISION "\n");
1075 printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc\n");
1076
1077 /* Only support POLL mode so far */
1078 edac_op_state = EDAC_OPSTATE_POLL;
1079
1080 ret = platform_driver_register(&cpc925_edac_driver);
1081 if (ret) {
1082 printk(KERN_WARNING "Failed to register %s\n",
1083 CPC925_EDAC_MOD_STR);
1084 }
1085
1086 return ret;
1087}
1088
1089static void __exit cpc925_edac_exit(void)
1090{
1091 platform_driver_unregister(&cpc925_edac_driver);
1092}
1093
1094module_init(cpc925_edac_init);
1095module_exit(cpc925_edac_exit);
1096
1097MODULE_LICENSE("GPL");
1098MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>");
1099MODULE_DESCRIPTION("IBM CPC925 Bridge and MC EDAC kernel module");
kernel source for telekom puls (alcatel/mediatek)