Commit | Line | Data |
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806c35f5 AC |
1 | /* |
2 | * AMD 76x Memory Controller kernel module | |
3 | * (C) 2003 Linux Networx (http://lnxi.com) | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
9 | * http://www.anime.net/~goemon/linux-ecc/ | |
10 | * | |
11 | * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $ | |
12 | * | |
13 | */ | |
14 | ||
806c35f5 AC |
15 | #include <linux/module.h> |
16 | #include <linux/init.h> | |
806c35f5 AC |
17 | #include <linux/pci.h> |
18 | #include <linux/pci_ids.h> | |
806c35f5 | 19 | #include <linux/slab.h> |
20bcb7a8 | 20 | #include "edac_core.h" |
806c35f5 | 21 | |
20bcb7a8 | 22 | #define AMD76X_REVISION " Ver: 2.0.2 " __DATE__ |
929a40ec | 23 | #define EDAC_MOD_STR "amd76x_edac" |
37f04581 | 24 | |
537fba28 | 25 | #define amd76x_printk(level, fmt, arg...) \ |
e7ecd891 | 26 | edac_printk(level, "amd76x", fmt, ##arg) |
537fba28 DP |
27 | |
28 | #define amd76x_mc_printk(mci, level, fmt, arg...) \ | |
e7ecd891 | 29 | edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg) |
537fba28 | 30 | |
806c35f5 AC |
31 | #define AMD76X_NR_CSROWS 8 |
32 | #define AMD76X_NR_CHANS 1 | |
33 | #define AMD76X_NR_DIMMS 4 | |
34 | ||
806c35f5 | 35 | /* AMD 76x register addresses - device 0 function 0 - PCI bridge */ |
e7ecd891 | 36 | |
806c35f5 AC |
37 | #define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b) |
38 | * | |
39 | * 31:16 reserved | |
40 | * 15:14 SERR enabled: x1=ue 1x=ce | |
41 | * 13 reserved | |
42 | * 12 diag: disabled, enabled | |
43 | * 11:10 mode: dis, EC, ECC, ECC+scrub | |
44 | * 9:8 status: x1=ue 1x=ce | |
45 | * 7:4 UE cs row | |
46 | * 3:0 CE cs row | |
47 | */ | |
e7ecd891 | 48 | |
806c35f5 AC |
49 | #define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b) |
50 | * | |
51 | * 31:26 clock disable 5 - 0 | |
52 | * 25 SDRAM init | |
53 | * 24 reserved | |
54 | * 23 mode register service | |
55 | * 22:21 suspend to RAM | |
56 | * 20 burst refresh enable | |
57 | * 19 refresh disable | |
58 | * 18 reserved | |
59 | * 17:16 cycles-per-refresh | |
60 | * 15:8 reserved | |
61 | * 7:0 x4 mode enable 7 - 0 | |
62 | */ | |
e7ecd891 | 63 | |
806c35f5 AC |
64 | #define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b) |
65 | * | |
66 | * 31:23 chip-select base | |
67 | * 22:16 reserved | |
68 | * 15:7 chip-select mask | |
69 | * 6:3 reserved | |
70 | * 2:1 address mode | |
71 | * 0 chip-select enable | |
72 | */ | |
73 | ||
806c35f5 AC |
74 | struct amd76x_error_info { |
75 | u32 ecc_mode_status; | |
76 | }; | |
77 | ||
806c35f5 AC |
78 | enum amd76x_chips { |
79 | AMD761 = 0, | |
80 | AMD762 | |
81 | }; | |
82 | ||
806c35f5 AC |
83 | struct amd76x_dev_info { |
84 | const char *ctl_name; | |
85 | }; | |
86 | ||
806c35f5 | 87 | static const struct amd76x_dev_info amd76x_devs[] = { |
e7ecd891 | 88 | [AMD761] = { |
67cb2b61 | 89 | .ctl_name = "AMD761"}, |
e7ecd891 | 90 | [AMD762] = { |
67cb2b61 | 91 | .ctl_name = "AMD762"}, |
806c35f5 AC |
92 | }; |
93 | ||
806c35f5 AC |
94 | /** |
95 | * amd76x_get_error_info - fetch error information | |
96 | * @mci: Memory controller | |
97 | * @info: Info to fill in | |
98 | * | |
99 | * Fetch and store the AMD76x ECC status. Clear pending status | |
100 | * on the chip so that further errors will be reported | |
101 | */ | |
e7ecd891 | 102 | static void amd76x_get_error_info(struct mem_ctl_info *mci, |
67cb2b61 | 103 | struct amd76x_error_info *info) |
806c35f5 | 104 | { |
37f04581 DT |
105 | struct pci_dev *pdev; |
106 | ||
107 | pdev = to_pci_dev(mci->dev); | |
108 | pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, | |
67cb2b61 | 109 | &info->ecc_mode_status); |
806c35f5 AC |
110 | |
111 | if (info->ecc_mode_status & BIT(8)) | |
37f04581 | 112 | pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS, |
67cb2b61 | 113 | (u32) BIT(8), (u32) BIT(8)); |
806c35f5 AC |
114 | |
115 | if (info->ecc_mode_status & BIT(9)) | |
37f04581 | 116 | pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS, |
67cb2b61 | 117 | (u32) BIT(9), (u32) BIT(9)); |
806c35f5 AC |
118 | } |
119 | ||
806c35f5 AC |
120 | /** |
121 | * amd76x_process_error_info - Error check | |
122 | * @mci: Memory controller | |
123 | * @info: Previously fetched information from chip | |
124 | * @handle_errors: 1 if we should do recovery | |
125 | * | |
126 | * Process the chip state and decide if an error has occurred. | |
127 | * A return of 1 indicates an error. Also if handle_errors is true | |
128 | * then attempt to handle and clean up after the error | |
129 | */ | |
e7ecd891 | 130 | static int amd76x_process_error_info(struct mem_ctl_info *mci, |
67cb2b61 DT |
131 | struct amd76x_error_info *info, |
132 | int handle_errors) | |
806c35f5 AC |
133 | { |
134 | int error_found; | |
135 | u32 row; | |
136 | ||
137 | error_found = 0; | |
138 | ||
139 | /* | |
67cb2b61 | 140 | * Check for an uncorrectable error |
806c35f5 AC |
141 | */ |
142 | if (info->ecc_mode_status & BIT(8)) { | |
143 | error_found = 1; | |
144 | ||
145 | if (handle_errors) { | |
146 | row = (info->ecc_mode_status >> 4) & 0xf; | |
e7ecd891 | 147 | edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0, |
67cb2b61 | 148 | row, mci->ctl_name); |
806c35f5 AC |
149 | } |
150 | } | |
151 | ||
152 | /* | |
67cb2b61 | 153 | * Check for a correctable error |
806c35f5 AC |
154 | */ |
155 | if (info->ecc_mode_status & BIT(9)) { | |
156 | error_found = 1; | |
157 | ||
158 | if (handle_errors) { | |
159 | row = info->ecc_mode_status & 0xf; | |
e7ecd891 | 160 | edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0, |
67cb2b61 | 161 | 0, row, 0, mci->ctl_name); |
806c35f5 AC |
162 | } |
163 | } | |
e7ecd891 | 164 | |
806c35f5 AC |
165 | return error_found; |
166 | } | |
167 | ||
168 | /** | |
169 | * amd76x_check - Poll the controller | |
170 | * @mci: Memory controller | |
171 | * | |
172 | * Called by the poll handlers this function reads the status | |
173 | * from the controller and checks for errors. | |
174 | */ | |
806c35f5 AC |
175 | static void amd76x_check(struct mem_ctl_info *mci) |
176 | { | |
177 | struct amd76x_error_info info; | |
537fba28 | 178 | debugf3("%s()\n", __func__); |
806c35f5 AC |
179 | amd76x_get_error_info(mci, &info); |
180 | amd76x_process_error_info(mci, &info, 1); | |
181 | } | |
182 | ||
13189525 | 183 | static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, |
67cb2b61 | 184 | enum edac_type edac_mode) |
13189525 DT |
185 | { |
186 | struct csrow_info *csrow; | |
187 | u32 mba, mba_base, mba_mask, dms; | |
188 | int index; | |
189 | ||
190 | for (index = 0; index < mci->nr_csrows; index++) { | |
191 | csrow = &mci->csrows[index]; | |
192 | ||
193 | /* find the DRAM Chip Select Base address and mask */ | |
194 | pci_read_config_dword(pdev, | |
67cb2b61 | 195 | AMD76X_MEM_BASE_ADDR + (index * 4), &mba); |
13189525 DT |
196 | |
197 | if (!(mba & BIT(0))) | |
198 | continue; | |
199 | ||
200 | mba_base = mba & 0xff800000UL; | |
201 | mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL; | |
202 | pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms); | |
203 | csrow->first_page = mba_base >> PAGE_SHIFT; | |
204 | csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT; | |
205 | csrow->last_page = csrow->first_page + csrow->nr_pages - 1; | |
206 | csrow->page_mask = mba_mask >> PAGE_SHIFT; | |
207 | csrow->grain = csrow->nr_pages << PAGE_SHIFT; | |
208 | csrow->mtype = MEM_RDDR; | |
209 | csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN; | |
210 | csrow->edac_mode = edac_mode; | |
211 | } | |
212 | } | |
213 | ||
806c35f5 AC |
214 | /** |
215 | * amd76x_probe1 - Perform set up for detected device | |
216 | * @pdev; PCI device detected | |
217 | * @dev_idx: Device type index | |
218 | * | |
219 | * We have found an AMD76x and now need to set up the memory | |
220 | * controller status reporting. We configure and set up the | |
221 | * memory controller reporting and claim the device. | |
222 | */ | |
806c35f5 AC |
223 | static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) |
224 | { | |
13189525 | 225 | static const enum edac_type ems_modes[] = { |
806c35f5 AC |
226 | EDAC_NONE, |
227 | EDAC_EC, | |
228 | EDAC_SECDED, | |
229 | EDAC_SECDED | |
230 | }; | |
13189525 | 231 | struct mem_ctl_info *mci = NULL; |
806c35f5 AC |
232 | u32 ems; |
233 | u32 ems_mode; | |
749ede57 | 234 | struct amd76x_error_info discard; |
806c35f5 | 235 | |
537fba28 | 236 | debugf0("%s()\n", __func__); |
806c35f5 AC |
237 | pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems); |
238 | ems_mode = (ems >> 10) & 0x3; | |
806c35f5 AC |
239 | mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS); |
240 | ||
241 | if (mci == NULL) { | |
13189525 | 242 | return -ENOMEM; |
806c35f5 AC |
243 | } |
244 | ||
537fba28 | 245 | debugf0("%s(): mci = %p\n", __func__, mci); |
37f04581 | 246 | mci->dev = &pdev->dev; |
806c35f5 | 247 | mci->mtype_cap = MEM_FLAG_RDDR; |
806c35f5 AC |
248 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
249 | mci->edac_cap = ems_mode ? | |
67cb2b61 | 250 | (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE; |
680cbbbb | 251 | mci->mod_name = EDAC_MOD_STR; |
37f04581 | 252 | mci->mod_ver = AMD76X_REVISION; |
806c35f5 | 253 | mci->ctl_name = amd76x_devs[dev_idx].ctl_name; |
c4192705 | 254 | mci->dev_name = pci_name(pdev); |
806c35f5 AC |
255 | mci->edac_check = amd76x_check; |
256 | mci->ctl_page_to_phys = NULL; | |
257 | ||
13189525 | 258 | amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]); |
67cb2b61 | 259 | amd76x_get_error_info(mci, &discard); /* clear counters */ |
806c35f5 | 260 | |
2d7bbb91 DT |
261 | /* Here we assume that we will never see multiple instances of this |
262 | * type of memory controller. The ID is therefore hardcoded to 0. | |
263 | */ | |
67cb2b61 | 264 | if (edac_mc_add_mc(mci, 0)) { |
537fba28 | 265 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
806c35f5 AC |
266 | goto fail; |
267 | } | |
268 | ||
269 | /* get this far and it's successful */ | |
537fba28 | 270 | debugf3("%s(): success\n", __func__); |
806c35f5 AC |
271 | return 0; |
272 | ||
67cb2b61 | 273 | fail: |
13189525 DT |
274 | edac_mc_free(mci); |
275 | return -ENODEV; | |
806c35f5 AC |
276 | } |
277 | ||
278 | /* returns count (>= 0), or negative on error */ | |
279 | static int __devinit amd76x_init_one(struct pci_dev *pdev, | |
67cb2b61 | 280 | const struct pci_device_id *ent) |
806c35f5 | 281 | { |
537fba28 | 282 | debugf0("%s()\n", __func__); |
806c35f5 AC |
283 | |
284 | /* don't need to call pci_device_enable() */ | |
285 | return amd76x_probe1(pdev, ent->driver_data); | |
286 | } | |
287 | ||
806c35f5 AC |
288 | /** |
289 | * amd76x_remove_one - driver shutdown | |
290 | * @pdev: PCI device being handed back | |
291 | * | |
292 | * Called when the driver is unloaded. Find the matching mci | |
293 | * structure for the device then delete the mci and free the | |
294 | * resources. | |
295 | */ | |
806c35f5 AC |
296 | static void __devexit amd76x_remove_one(struct pci_dev *pdev) |
297 | { | |
298 | struct mem_ctl_info *mci; | |
299 | ||
537fba28 | 300 | debugf0("%s()\n", __func__); |
806c35f5 | 301 | |
37f04581 | 302 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
806c35f5 | 303 | return; |
18dbc337 | 304 | |
806c35f5 AC |
305 | edac_mc_free(mci); |
306 | } | |
307 | ||
806c35f5 | 308 | static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = { |
e7ecd891 | 309 | { |
67cb2b61 DT |
310 | PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
311 | AMD762}, | |
e7ecd891 | 312 | { |
67cb2b61 DT |
313 | PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
314 | AMD761}, | |
e7ecd891 | 315 | { |
67cb2b61 DT |
316 | 0, |
317 | } /* 0 terminated list. */ | |
806c35f5 AC |
318 | }; |
319 | ||
320 | MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl); | |
321 | ||
806c35f5 | 322 | static struct pci_driver amd76x_driver = { |
680cbbbb | 323 | .name = EDAC_MOD_STR, |
806c35f5 AC |
324 | .probe = amd76x_init_one, |
325 | .remove = __devexit_p(amd76x_remove_one), | |
326 | .id_table = amd76x_pci_tbl, | |
327 | }; | |
328 | ||
da9bb1d2 | 329 | static int __init amd76x_init(void) |
806c35f5 AC |
330 | { |
331 | return pci_register_driver(&amd76x_driver); | |
332 | } | |
333 | ||
334 | static void __exit amd76x_exit(void) | |
335 | { | |
336 | pci_unregister_driver(&amd76x_driver); | |
337 | } | |
338 | ||
339 | module_init(amd76x_init); | |
340 | module_exit(amd76x_exit); | |
341 | ||
342 | MODULE_LICENSE("GPL"); | |
343 | MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh"); | |
344 | MODULE_DESCRIPTION("MC support for AMD 76x memory controllers"); |