Commit | Line | Data |
---|---|---|
806c35f5 AC |
1 | /* |
2 | * AMD 76x Memory Controller kernel module | |
3 | * (C) 2003 Linux Networx (http://lnxi.com) | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
9 | * http://www.anime.net/~goemon/linux-ecc/ | |
10 | * | |
11 | * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $ | |
12 | * | |
13 | */ | |
14 | ||
15 | ||
16 | #include <linux/config.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/pci_ids.h> | |
22 | ||
23 | #include <linux/slab.h> | |
24 | ||
25 | #include "edac_mc.h" | |
26 | ||
27 | ||
537fba28 DP |
28 | #define amd76x_printk(level, fmt, arg...) \ |
29 | edac_printk(level, "amd76x", fmt, ##arg) | |
30 | ||
31 | ||
32 | #define amd76x_mc_printk(mci, level, fmt, arg...) \ | |
33 | edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg) | |
34 | ||
35 | ||
806c35f5 AC |
36 | #define AMD76X_NR_CSROWS 8 |
37 | #define AMD76X_NR_CHANS 1 | |
38 | #define AMD76X_NR_DIMMS 4 | |
39 | ||
40 | ||
41 | /* AMD 76x register addresses - device 0 function 0 - PCI bridge */ | |
42 | #define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b) | |
43 | * | |
44 | * 31:16 reserved | |
45 | * 15:14 SERR enabled: x1=ue 1x=ce | |
46 | * 13 reserved | |
47 | * 12 diag: disabled, enabled | |
48 | * 11:10 mode: dis, EC, ECC, ECC+scrub | |
49 | * 9:8 status: x1=ue 1x=ce | |
50 | * 7:4 UE cs row | |
51 | * 3:0 CE cs row | |
52 | */ | |
53 | #define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b) | |
54 | * | |
55 | * 31:26 clock disable 5 - 0 | |
56 | * 25 SDRAM init | |
57 | * 24 reserved | |
58 | * 23 mode register service | |
59 | * 22:21 suspend to RAM | |
60 | * 20 burst refresh enable | |
61 | * 19 refresh disable | |
62 | * 18 reserved | |
63 | * 17:16 cycles-per-refresh | |
64 | * 15:8 reserved | |
65 | * 7:0 x4 mode enable 7 - 0 | |
66 | */ | |
67 | #define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b) | |
68 | * | |
69 | * 31:23 chip-select base | |
70 | * 22:16 reserved | |
71 | * 15:7 chip-select mask | |
72 | * 6:3 reserved | |
73 | * 2:1 address mode | |
74 | * 0 chip-select enable | |
75 | */ | |
76 | ||
77 | ||
78 | struct amd76x_error_info { | |
79 | u32 ecc_mode_status; | |
80 | }; | |
81 | ||
82 | ||
83 | enum amd76x_chips { | |
84 | AMD761 = 0, | |
85 | AMD762 | |
86 | }; | |
87 | ||
88 | ||
89 | struct amd76x_dev_info { | |
90 | const char *ctl_name; | |
91 | }; | |
92 | ||
93 | ||
94 | static const struct amd76x_dev_info amd76x_devs[] = { | |
95 | [AMD761] = {.ctl_name = "AMD761"}, | |
96 | [AMD762] = {.ctl_name = "AMD762"}, | |
97 | }; | |
98 | ||
99 | ||
100 | /** | |
101 | * amd76x_get_error_info - fetch error information | |
102 | * @mci: Memory controller | |
103 | * @info: Info to fill in | |
104 | * | |
105 | * Fetch and store the AMD76x ECC status. Clear pending status | |
106 | * on the chip so that further errors will be reported | |
107 | */ | |
108 | ||
109 | static void amd76x_get_error_info (struct mem_ctl_info *mci, | |
110 | struct amd76x_error_info *info) | |
111 | { | |
112 | pci_read_config_dword(mci->pdev, AMD76X_ECC_MODE_STATUS, | |
113 | &info->ecc_mode_status); | |
114 | ||
115 | if (info->ecc_mode_status & BIT(8)) | |
116 | pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS, | |
117 | (u32) BIT(8), (u32) BIT(8)); | |
118 | ||
119 | if (info->ecc_mode_status & BIT(9)) | |
120 | pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS, | |
121 | (u32) BIT(9), (u32) BIT(9)); | |
122 | } | |
123 | ||
124 | ||
125 | /** | |
126 | * amd76x_process_error_info - Error check | |
127 | * @mci: Memory controller | |
128 | * @info: Previously fetched information from chip | |
129 | * @handle_errors: 1 if we should do recovery | |
130 | * | |
131 | * Process the chip state and decide if an error has occurred. | |
132 | * A return of 1 indicates an error. Also if handle_errors is true | |
133 | * then attempt to handle and clean up after the error | |
134 | */ | |
135 | ||
136 | static int amd76x_process_error_info (struct mem_ctl_info *mci, | |
137 | struct amd76x_error_info *info, int handle_errors) | |
138 | { | |
139 | int error_found; | |
140 | u32 row; | |
141 | ||
142 | error_found = 0; | |
143 | ||
144 | /* | |
145 | * Check for an uncorrectable error | |
146 | */ | |
147 | if (info->ecc_mode_status & BIT(8)) { | |
148 | error_found = 1; | |
149 | ||
150 | if (handle_errors) { | |
151 | row = (info->ecc_mode_status >> 4) & 0xf; | |
152 | edac_mc_handle_ue(mci, | |
153 | mci->csrows[row].first_page, 0, row, | |
154 | mci->ctl_name); | |
155 | } | |
156 | } | |
157 | ||
158 | /* | |
159 | * Check for a correctable error | |
160 | */ | |
161 | if (info->ecc_mode_status & BIT(9)) { | |
162 | error_found = 1; | |
163 | ||
164 | if (handle_errors) { | |
165 | row = info->ecc_mode_status & 0xf; | |
166 | edac_mc_handle_ce(mci, | |
167 | mci->csrows[row].first_page, 0, 0, row, 0, | |
168 | mci->ctl_name); | |
169 | } | |
170 | } | |
171 | return error_found; | |
172 | } | |
173 | ||
174 | /** | |
175 | * amd76x_check - Poll the controller | |
176 | * @mci: Memory controller | |
177 | * | |
178 | * Called by the poll handlers this function reads the status | |
179 | * from the controller and checks for errors. | |
180 | */ | |
181 | ||
182 | static void amd76x_check(struct mem_ctl_info *mci) | |
183 | { | |
184 | struct amd76x_error_info info; | |
537fba28 | 185 | debugf3("%s()\n", __func__); |
806c35f5 AC |
186 | amd76x_get_error_info(mci, &info); |
187 | amd76x_process_error_info(mci, &info, 1); | |
188 | } | |
189 | ||
190 | ||
191 | /** | |
192 | * amd76x_probe1 - Perform set up for detected device | |
193 | * @pdev; PCI device detected | |
194 | * @dev_idx: Device type index | |
195 | * | |
196 | * We have found an AMD76x and now need to set up the memory | |
197 | * controller status reporting. We configure and set up the | |
198 | * memory controller reporting and claim the device. | |
199 | */ | |
200 | ||
201 | static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) | |
202 | { | |
203 | int rc = -ENODEV; | |
204 | int index; | |
205 | struct mem_ctl_info *mci = NULL; | |
206 | enum edac_type ems_modes[] = { | |
207 | EDAC_NONE, | |
208 | EDAC_EC, | |
209 | EDAC_SECDED, | |
210 | EDAC_SECDED | |
211 | }; | |
212 | u32 ems; | |
213 | u32 ems_mode; | |
749ede57 | 214 | struct amd76x_error_info discard; |
806c35f5 | 215 | |
537fba28 | 216 | debugf0("%s()\n", __func__); |
806c35f5 AC |
217 | |
218 | pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems); | |
219 | ems_mode = (ems >> 10) & 0x3; | |
220 | ||
221 | mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS); | |
222 | ||
223 | if (mci == NULL) { | |
224 | rc = -ENOMEM; | |
225 | goto fail; | |
226 | } | |
227 | ||
537fba28 | 228 | debugf0("%s(): mci = %p\n", __func__, mci); |
806c35f5 | 229 | |
225159bd | 230 | mci->pdev = pdev; |
806c35f5 AC |
231 | mci->mtype_cap = MEM_FLAG_RDDR; |
232 | ||
233 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; | |
234 | mci->edac_cap = ems_mode ? | |
235 | (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE; | |
236 | ||
680cbbbb | 237 | mci->mod_name = EDAC_MOD_STR; |
806c35f5 AC |
238 | mci->mod_ver = "$Revision: 1.4.2.5 $"; |
239 | mci->ctl_name = amd76x_devs[dev_idx].ctl_name; | |
240 | mci->edac_check = amd76x_check; | |
241 | mci->ctl_page_to_phys = NULL; | |
242 | ||
243 | for (index = 0; index < mci->nr_csrows; index++) { | |
244 | struct csrow_info *csrow = &mci->csrows[index]; | |
245 | u32 mba; | |
246 | u32 mba_base; | |
247 | u32 mba_mask; | |
248 | u32 dms; | |
249 | ||
250 | /* find the DRAM Chip Select Base address and mask */ | |
251 | pci_read_config_dword(mci->pdev, | |
252 | AMD76X_MEM_BASE_ADDR + (index * 4), | |
253 | &mba); | |
254 | ||
255 | if (!(mba & BIT(0))) | |
256 | continue; | |
257 | ||
258 | mba_base = mba & 0xff800000UL; | |
259 | mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL; | |
260 | ||
261 | pci_read_config_dword(mci->pdev, AMD76X_DRAM_MODE_STATUS, | |
262 | &dms); | |
263 | ||
264 | csrow->first_page = mba_base >> PAGE_SHIFT; | |
265 | csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT; | |
266 | csrow->last_page = csrow->first_page + csrow->nr_pages - 1; | |
267 | csrow->page_mask = mba_mask >> PAGE_SHIFT; | |
268 | csrow->grain = csrow->nr_pages << PAGE_SHIFT; | |
269 | csrow->mtype = MEM_RDDR; | |
270 | csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN; | |
271 | csrow->edac_mode = ems_modes[ems_mode]; | |
272 | } | |
273 | ||
749ede57 | 274 | amd76x_get_error_info(mci, &discard); /* clear counters */ |
806c35f5 AC |
275 | |
276 | if (edac_mc_add_mc(mci)) { | |
537fba28 | 277 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
806c35f5 AC |
278 | goto fail; |
279 | } | |
280 | ||
281 | /* get this far and it's successful */ | |
537fba28 | 282 | debugf3("%s(): success\n", __func__); |
806c35f5 AC |
283 | return 0; |
284 | ||
285 | fail: | |
225159bd | 286 | if (mci != NULL) |
806c35f5 | 287 | edac_mc_free(mci); |
806c35f5 AC |
288 | return rc; |
289 | } | |
290 | ||
291 | /* returns count (>= 0), or negative on error */ | |
292 | static int __devinit amd76x_init_one(struct pci_dev *pdev, | |
293 | const struct pci_device_id *ent) | |
294 | { | |
537fba28 | 295 | debugf0("%s()\n", __func__); |
806c35f5 AC |
296 | |
297 | /* don't need to call pci_device_enable() */ | |
298 | return amd76x_probe1(pdev, ent->driver_data); | |
299 | } | |
300 | ||
301 | ||
302 | /** | |
303 | * amd76x_remove_one - driver shutdown | |
304 | * @pdev: PCI device being handed back | |
305 | * | |
306 | * Called when the driver is unloaded. Find the matching mci | |
307 | * structure for the device then delete the mci and free the | |
308 | * resources. | |
309 | */ | |
310 | ||
311 | static void __devexit amd76x_remove_one(struct pci_dev *pdev) | |
312 | { | |
313 | struct mem_ctl_info *mci; | |
314 | ||
537fba28 | 315 | debugf0("%s()\n", __func__); |
806c35f5 AC |
316 | |
317 | if ((mci = edac_mc_find_mci_by_pdev(pdev)) == NULL) | |
318 | return; | |
319 | if (edac_mc_del_mc(mci)) | |
320 | return; | |
806c35f5 AC |
321 | edac_mc_free(mci); |
322 | } | |
323 | ||
324 | ||
325 | static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = { | |
326 | {PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
327 | AMD762}, | |
328 | {PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
329 | AMD761}, | |
330 | {0,} /* 0 terminated list. */ | |
331 | }; | |
332 | ||
333 | MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl); | |
334 | ||
335 | ||
336 | static struct pci_driver amd76x_driver = { | |
680cbbbb | 337 | .name = EDAC_MOD_STR, |
806c35f5 AC |
338 | .probe = amd76x_init_one, |
339 | .remove = __devexit_p(amd76x_remove_one), | |
340 | .id_table = amd76x_pci_tbl, | |
341 | }; | |
342 | ||
da9bb1d2 | 343 | static int __init amd76x_init(void) |
806c35f5 AC |
344 | { |
345 | return pci_register_driver(&amd76x_driver); | |
346 | } | |
347 | ||
348 | static void __exit amd76x_exit(void) | |
349 | { | |
350 | pci_unregister_driver(&amd76x_driver); | |
351 | } | |
352 | ||
353 | module_init(amd76x_init); | |
354 | module_exit(amd76x_exit); | |
355 | ||
356 | MODULE_LICENSE("GPL"); | |
357 | MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh"); | |
358 | MODULE_DESCRIPTION("MC support for AMD 76x memory controllers"); |