Commit | Line | Data |
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806c35f5 AC |
1 | /* |
2 | * AMD 76x Memory Controller kernel module | |
3 | * (C) 2003 Linux Networx (http://lnxi.com) | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
9 | * http://www.anime.net/~goemon/linux-ecc/ | |
10 | * | |
11 | * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $ | |
12 | * | |
13 | */ | |
14 | ||
806c35f5 AC |
15 | #include <linux/config.h> |
16 | #include <linux/module.h> | |
17 | #include <linux/init.h> | |
806c35f5 AC |
18 | #include <linux/pci.h> |
19 | #include <linux/pci_ids.h> | |
806c35f5 | 20 | #include <linux/slab.h> |
806c35f5 AC |
21 | #include "edac_mc.h" |
22 | ||
37f04581 DT |
23 | #define AMD76X_REVISION " Ver: 2.0.0 " __DATE__ |
24 | ||
25 | ||
537fba28 | 26 | #define amd76x_printk(level, fmt, arg...) \ |
e7ecd891 | 27 | edac_printk(level, "amd76x", fmt, ##arg) |
537fba28 DP |
28 | |
29 | #define amd76x_mc_printk(mci, level, fmt, arg...) \ | |
e7ecd891 | 30 | edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg) |
537fba28 | 31 | |
806c35f5 AC |
32 | #define AMD76X_NR_CSROWS 8 |
33 | #define AMD76X_NR_CHANS 1 | |
34 | #define AMD76X_NR_DIMMS 4 | |
35 | ||
806c35f5 | 36 | /* AMD 76x register addresses - device 0 function 0 - PCI bridge */ |
e7ecd891 | 37 | |
806c35f5 AC |
38 | #define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b) |
39 | * | |
40 | * 31:16 reserved | |
41 | * 15:14 SERR enabled: x1=ue 1x=ce | |
42 | * 13 reserved | |
43 | * 12 diag: disabled, enabled | |
44 | * 11:10 mode: dis, EC, ECC, ECC+scrub | |
45 | * 9:8 status: x1=ue 1x=ce | |
46 | * 7:4 UE cs row | |
47 | * 3:0 CE cs row | |
48 | */ | |
e7ecd891 | 49 | |
806c35f5 AC |
50 | #define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b) |
51 | * | |
52 | * 31:26 clock disable 5 - 0 | |
53 | * 25 SDRAM init | |
54 | * 24 reserved | |
55 | * 23 mode register service | |
56 | * 22:21 suspend to RAM | |
57 | * 20 burst refresh enable | |
58 | * 19 refresh disable | |
59 | * 18 reserved | |
60 | * 17:16 cycles-per-refresh | |
61 | * 15:8 reserved | |
62 | * 7:0 x4 mode enable 7 - 0 | |
63 | */ | |
e7ecd891 | 64 | |
806c35f5 AC |
65 | #define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b) |
66 | * | |
67 | * 31:23 chip-select base | |
68 | * 22:16 reserved | |
69 | * 15:7 chip-select mask | |
70 | * 6:3 reserved | |
71 | * 2:1 address mode | |
72 | * 0 chip-select enable | |
73 | */ | |
74 | ||
806c35f5 AC |
75 | struct amd76x_error_info { |
76 | u32 ecc_mode_status; | |
77 | }; | |
78 | ||
806c35f5 AC |
79 | enum amd76x_chips { |
80 | AMD761 = 0, | |
81 | AMD762 | |
82 | }; | |
83 | ||
806c35f5 AC |
84 | struct amd76x_dev_info { |
85 | const char *ctl_name; | |
86 | }; | |
87 | ||
806c35f5 | 88 | static const struct amd76x_dev_info amd76x_devs[] = { |
e7ecd891 DP |
89 | [AMD761] = { |
90 | .ctl_name = "AMD761" | |
91 | }, | |
92 | [AMD762] = { | |
93 | .ctl_name = "AMD762" | |
94 | }, | |
806c35f5 AC |
95 | }; |
96 | ||
806c35f5 AC |
97 | /** |
98 | * amd76x_get_error_info - fetch error information | |
99 | * @mci: Memory controller | |
100 | * @info: Info to fill in | |
101 | * | |
102 | * Fetch and store the AMD76x ECC status. Clear pending status | |
103 | * on the chip so that further errors will be reported | |
104 | */ | |
e7ecd891 DP |
105 | static void amd76x_get_error_info(struct mem_ctl_info *mci, |
106 | struct amd76x_error_info *info) | |
806c35f5 | 107 | { |
37f04581 DT |
108 | struct pci_dev *pdev; |
109 | ||
110 | pdev = to_pci_dev(mci->dev); | |
111 | pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, | |
806c35f5 AC |
112 | &info->ecc_mode_status); |
113 | ||
114 | if (info->ecc_mode_status & BIT(8)) | |
37f04581 | 115 | pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS, |
e7ecd891 | 116 | (u32) BIT(8), (u32) BIT(8)); |
806c35f5 AC |
117 | |
118 | if (info->ecc_mode_status & BIT(9)) | |
37f04581 | 119 | pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS, |
e7ecd891 | 120 | (u32) BIT(9), (u32) BIT(9)); |
806c35f5 AC |
121 | } |
122 | ||
806c35f5 AC |
123 | /** |
124 | * amd76x_process_error_info - Error check | |
125 | * @mci: Memory controller | |
126 | * @info: Previously fetched information from chip | |
127 | * @handle_errors: 1 if we should do recovery | |
128 | * | |
129 | * Process the chip state and decide if an error has occurred. | |
130 | * A return of 1 indicates an error. Also if handle_errors is true | |
131 | * then attempt to handle and clean up after the error | |
132 | */ | |
e7ecd891 | 133 | static int amd76x_process_error_info(struct mem_ctl_info *mci, |
806c35f5 AC |
134 | struct amd76x_error_info *info, int handle_errors) |
135 | { | |
136 | int error_found; | |
137 | u32 row; | |
138 | ||
139 | error_found = 0; | |
140 | ||
141 | /* | |
142 | * Check for an uncorrectable error | |
143 | */ | |
144 | if (info->ecc_mode_status & BIT(8)) { | |
145 | error_found = 1; | |
146 | ||
147 | if (handle_errors) { | |
148 | row = (info->ecc_mode_status >> 4) & 0xf; | |
e7ecd891 DP |
149 | edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0, |
150 | row, mci->ctl_name); | |
806c35f5 AC |
151 | } |
152 | } | |
153 | ||
154 | /* | |
155 | * Check for a correctable error | |
156 | */ | |
157 | if (info->ecc_mode_status & BIT(9)) { | |
158 | error_found = 1; | |
159 | ||
160 | if (handle_errors) { | |
161 | row = info->ecc_mode_status & 0xf; | |
e7ecd891 DP |
162 | edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0, |
163 | 0, row, 0, mci->ctl_name); | |
806c35f5 AC |
164 | } |
165 | } | |
e7ecd891 | 166 | |
806c35f5 AC |
167 | return error_found; |
168 | } | |
169 | ||
170 | /** | |
171 | * amd76x_check - Poll the controller | |
172 | * @mci: Memory controller | |
173 | * | |
174 | * Called by the poll handlers this function reads the status | |
175 | * from the controller and checks for errors. | |
176 | */ | |
806c35f5 AC |
177 | static void amd76x_check(struct mem_ctl_info *mci) |
178 | { | |
179 | struct amd76x_error_info info; | |
537fba28 | 180 | debugf3("%s()\n", __func__); |
806c35f5 AC |
181 | amd76x_get_error_info(mci, &info); |
182 | amd76x_process_error_info(mci, &info, 1); | |
183 | } | |
184 | ||
806c35f5 AC |
185 | /** |
186 | * amd76x_probe1 - Perform set up for detected device | |
187 | * @pdev; PCI device detected | |
188 | * @dev_idx: Device type index | |
189 | * | |
190 | * We have found an AMD76x and now need to set up the memory | |
191 | * controller status reporting. We configure and set up the | |
192 | * memory controller reporting and claim the device. | |
193 | */ | |
806c35f5 AC |
194 | static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) |
195 | { | |
196 | int rc = -ENODEV; | |
197 | int index; | |
198 | struct mem_ctl_info *mci = NULL; | |
199 | enum edac_type ems_modes[] = { | |
200 | EDAC_NONE, | |
201 | EDAC_EC, | |
202 | EDAC_SECDED, | |
203 | EDAC_SECDED | |
204 | }; | |
205 | u32 ems; | |
206 | u32 ems_mode; | |
749ede57 | 207 | struct amd76x_error_info discard; |
806c35f5 | 208 | |
537fba28 | 209 | debugf0("%s()\n", __func__); |
806c35f5 AC |
210 | pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems); |
211 | ems_mode = (ems >> 10) & 0x3; | |
806c35f5 AC |
212 | mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS); |
213 | ||
214 | if (mci == NULL) { | |
215 | rc = -ENOMEM; | |
216 | goto fail; | |
217 | } | |
218 | ||
537fba28 | 219 | debugf0("%s(): mci = %p\n", __func__, mci); |
37f04581 | 220 | mci->dev = &pdev->dev; |
806c35f5 | 221 | mci->mtype_cap = MEM_FLAG_RDDR; |
806c35f5 AC |
222 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
223 | mci->edac_cap = ems_mode ? | |
e7ecd891 | 224 | (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE; |
680cbbbb | 225 | mci->mod_name = EDAC_MOD_STR; |
37f04581 | 226 | mci->mod_ver = AMD76X_REVISION; |
806c35f5 AC |
227 | mci->ctl_name = amd76x_devs[dev_idx].ctl_name; |
228 | mci->edac_check = amd76x_check; | |
229 | mci->ctl_page_to_phys = NULL; | |
230 | ||
231 | for (index = 0; index < mci->nr_csrows; index++) { | |
232 | struct csrow_info *csrow = &mci->csrows[index]; | |
233 | u32 mba; | |
234 | u32 mba_base; | |
235 | u32 mba_mask; | |
236 | u32 dms; | |
237 | ||
238 | /* find the DRAM Chip Select Base address and mask */ | |
37f04581 | 239 | pci_read_config_dword(pdev, |
e7ecd891 | 240 | AMD76X_MEM_BASE_ADDR + (index * 4), &mba); |
806c35f5 AC |
241 | |
242 | if (!(mba & BIT(0))) | |
243 | continue; | |
244 | ||
245 | mba_base = mba & 0xff800000UL; | |
246 | mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL; | |
37f04581 | 247 | pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms); |
806c35f5 AC |
248 | csrow->first_page = mba_base >> PAGE_SHIFT; |
249 | csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT; | |
250 | csrow->last_page = csrow->first_page + csrow->nr_pages - 1; | |
251 | csrow->page_mask = mba_mask >> PAGE_SHIFT; | |
252 | csrow->grain = csrow->nr_pages << PAGE_SHIFT; | |
253 | csrow->mtype = MEM_RDDR; | |
254 | csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN; | |
255 | csrow->edac_mode = ems_modes[ems_mode]; | |
256 | } | |
257 | ||
749ede57 | 258 | amd76x_get_error_info(mci, &discard); /* clear counters */ |
806c35f5 | 259 | |
2d7bbb91 DT |
260 | /* Here we assume that we will never see multiple instances of this |
261 | * type of memory controller. The ID is therefore hardcoded to 0. | |
262 | */ | |
263 | if (edac_mc_add_mc(mci,0)) { | |
537fba28 | 264 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
806c35f5 AC |
265 | goto fail; |
266 | } | |
267 | ||
268 | /* get this far and it's successful */ | |
537fba28 | 269 | debugf3("%s(): success\n", __func__); |
806c35f5 AC |
270 | return 0; |
271 | ||
272 | fail: | |
225159bd | 273 | if (mci != NULL) |
806c35f5 | 274 | edac_mc_free(mci); |
806c35f5 AC |
275 | return rc; |
276 | } | |
277 | ||
278 | /* returns count (>= 0), or negative on error */ | |
279 | static int __devinit amd76x_init_one(struct pci_dev *pdev, | |
e7ecd891 | 280 | const struct pci_device_id *ent) |
806c35f5 | 281 | { |
537fba28 | 282 | debugf0("%s()\n", __func__); |
806c35f5 AC |
283 | |
284 | /* don't need to call pci_device_enable() */ | |
285 | return amd76x_probe1(pdev, ent->driver_data); | |
286 | } | |
287 | ||
806c35f5 AC |
288 | /** |
289 | * amd76x_remove_one - driver shutdown | |
290 | * @pdev: PCI device being handed back | |
291 | * | |
292 | * Called when the driver is unloaded. Find the matching mci | |
293 | * structure for the device then delete the mci and free the | |
294 | * resources. | |
295 | */ | |
806c35f5 AC |
296 | static void __devexit amd76x_remove_one(struct pci_dev *pdev) |
297 | { | |
298 | struct mem_ctl_info *mci; | |
299 | ||
537fba28 | 300 | debugf0("%s()\n", __func__); |
806c35f5 | 301 | |
37f04581 | 302 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
806c35f5 | 303 | return; |
18dbc337 | 304 | |
806c35f5 AC |
305 | edac_mc_free(mci); |
306 | } | |
307 | ||
806c35f5 | 308 | static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = { |
e7ecd891 DP |
309 | { |
310 | PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
311 | AMD762 | |
312 | }, | |
313 | { | |
314 | PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
315 | AMD761 | |
316 | }, | |
317 | { | |
318 | 0, | |
319 | } /* 0 terminated list. */ | |
806c35f5 AC |
320 | }; |
321 | ||
322 | MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl); | |
323 | ||
806c35f5 | 324 | static struct pci_driver amd76x_driver = { |
680cbbbb | 325 | .name = EDAC_MOD_STR, |
806c35f5 AC |
326 | .probe = amd76x_init_one, |
327 | .remove = __devexit_p(amd76x_remove_one), | |
328 | .id_table = amd76x_pci_tbl, | |
329 | }; | |
330 | ||
da9bb1d2 | 331 | static int __init amd76x_init(void) |
806c35f5 AC |
332 | { |
333 | return pci_register_driver(&amd76x_driver); | |
334 | } | |
335 | ||
336 | static void __exit amd76x_exit(void) | |
337 | { | |
338 | pci_unregister_driver(&amd76x_driver); | |
339 | } | |
340 | ||
341 | module_init(amd76x_init); | |
342 | module_exit(amd76x_exit); | |
343 | ||
344 | MODULE_LICENSE("GPL"); | |
345 | MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh"); | |
346 | MODULE_DESCRIPTION("MC support for AMD 76x memory controllers"); |