Commit | Line | Data |
---|---|---|
cfe40fdb DT |
1 | /* |
2 | * AMD64 class Memory Controller kernel module | |
3 | * | |
4 | * Copyright (c) 2009 SoftwareBitMaker. | |
5 | * Copyright (c) 2009 Advanced Micro Devices, Inc. | |
6 | * | |
7 | * This file may be distributed under the terms of the | |
8 | * GNU General Public License. | |
9 | * | |
10 | * Originally Written by Thayne Harbaugh | |
11 | * | |
12 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
13 | * - K8 CPU Revision D and greater support | |
14 | * | |
15 | * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>: | |
16 | * - Module largely rewritten, with new (and hopefully correct) | |
17 | * code for dealing with node and chip select interleaving, | |
18 | * various code cleanup, and bug fixes | |
19 | * - Added support for memory hoisting using DRAM hole address | |
20 | * register | |
21 | * | |
22 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
23 | * -K8 Rev (1207) revision support added, required Revision | |
24 | * specific mini-driver code to support Rev F as well as | |
25 | * prior revisions | |
26 | * | |
27 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
28 | * -Family 10h revision support added. New PCI Device IDs, | |
29 | * indicating new changes. Actual registers modified | |
30 | * were slight, less than the Rev E to Rev F transition | |
31 | * but changing the PCI Device ID was the proper thing to | |
32 | * do, as it provides for almost automactic family | |
33 | * detection. The mods to Rev F required more family | |
34 | * information detection. | |
35 | * | |
36 | * Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>: | |
37 | * - misc fixes and code cleanups | |
38 | * | |
39 | * This module is based on the following documents | |
40 | * (available from http://www.amd.com/): | |
41 | * | |
42 | * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD | |
43 | * Opteron Processors | |
44 | * AMD publication #: 26094 | |
45 | *` Revision: 3.26 | |
46 | * | |
47 | * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh | |
48 | * Processors | |
49 | * AMD publication #: 32559 | |
50 | * Revision: 3.00 | |
51 | * Issue Date: May 2006 | |
52 | * | |
53 | * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h | |
54 | * Processors | |
55 | * AMD publication #: 31116 | |
56 | * Revision: 3.00 | |
57 | * Issue Date: September 07, 2007 | |
58 | * | |
59 | * Sections in the first 2 documents are no longer in sync with each other. | |
60 | * The Family 10h BKDG was totally re-written from scratch with a new | |
61 | * presentation model. | |
62 | * Therefore, comments that refer to a Document section might be off. | |
63 | */ | |
64 | ||
65 | #include <linux/module.h> | |
66 | #include <linux/ctype.h> | |
67 | #include <linux/init.h> | |
68 | #include <linux/pci.h> | |
69 | #include <linux/pci_ids.h> | |
70 | #include <linux/slab.h> | |
71 | #include <linux/mmzone.h> | |
72 | #include <linux/edac.h> | |
f9431992 | 73 | #include <asm/msr.h> |
cfe40fdb | 74 | #include "edac_core.h" |
47ca08a4 | 75 | #include "mce_amd.h" |
cfe40fdb | 76 | |
24f9a7fe BP |
77 | #define amd64_debug(fmt, arg...) \ |
78 | edac_printk(KERN_DEBUG, "amd64", fmt, ##arg) | |
cfe40fdb | 79 | |
24f9a7fe BP |
80 | #define amd64_info(fmt, arg...) \ |
81 | edac_printk(KERN_INFO, "amd64", fmt, ##arg) | |
82 | ||
83 | #define amd64_notice(fmt, arg...) \ | |
84 | edac_printk(KERN_NOTICE, "amd64", fmt, ##arg) | |
85 | ||
86 | #define amd64_warn(fmt, arg...) \ | |
87 | edac_printk(KERN_WARNING, "amd64", fmt, ##arg) | |
88 | ||
89 | #define amd64_err(fmt, arg...) \ | |
90 | edac_printk(KERN_ERR, "amd64", fmt, ##arg) | |
91 | ||
92 | #define amd64_mc_warn(mci, fmt, arg...) \ | |
93 | edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) | |
94 | ||
95 | #define amd64_mc_err(mci, fmt, arg...) \ | |
96 | edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) | |
cfe40fdb DT |
97 | |
98 | /* | |
99 | * Throughout the comments in this code, the following terms are used: | |
100 | * | |
101 | * SysAddr, DramAddr, and InputAddr | |
102 | * | |
103 | * These terms come directly from the amd64 documentation | |
104 | * (AMD publication #26094). They are defined as follows: | |
105 | * | |
106 | * SysAddr: | |
107 | * This is a physical address generated by a CPU core or a device | |
108 | * doing DMA. If generated by a CPU core, a SysAddr is the result of | |
109 | * a virtual to physical address translation by the CPU core's address | |
110 | * translation mechanism (MMU). | |
111 | * | |
112 | * DramAddr: | |
113 | * A DramAddr is derived from a SysAddr by subtracting an offset that | |
114 | * depends on which node the SysAddr maps to and whether the SysAddr | |
115 | * is within a range affected by memory hoisting. The DRAM Base | |
116 | * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers | |
117 | * determine which node a SysAddr maps to. | |
118 | * | |
119 | * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr | |
120 | * is within the range of addresses specified by this register, then | |
121 | * a value x from the DHAR is subtracted from the SysAddr to produce a | |
122 | * DramAddr. Here, x represents the base address for the node that | |
123 | * the SysAddr maps to plus an offset due to memory hoisting. See | |
124 | * section 3.4.8 and the comments in amd64_get_dram_hole_info() and | |
125 | * sys_addr_to_dram_addr() below for more information. | |
126 | * | |
127 | * If the SysAddr is not affected by the DHAR then a value y is | |
128 | * subtracted from the SysAddr to produce a DramAddr. Here, y is the | |
129 | * base address for the node that the SysAddr maps to. See section | |
130 | * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more | |
131 | * information. | |
132 | * | |
133 | * InputAddr: | |
134 | * A DramAddr is translated to an InputAddr before being passed to the | |
135 | * memory controller for the node that the DramAddr is associated | |
136 | * with. The memory controller then maps the InputAddr to a csrow. | |
137 | * If node interleaving is not in use, then the InputAddr has the same | |
138 | * value as the DramAddr. Otherwise, the InputAddr is produced by | |
139 | * discarding the bits used for node interleaving from the DramAddr. | |
140 | * See section 3.4.4 for more information. | |
141 | * | |
142 | * The memory controller for a given node uses its DRAM CS Base and | |
143 | * DRAM CS Mask registers to map an InputAddr to a csrow. See | |
144 | * sections 3.5.4 and 3.5.5 for more information. | |
145 | */ | |
146 | ||
24f9a7fe | 147 | #define EDAC_AMD64_VERSION "v3.3.0" |
cfe40fdb DT |
148 | #define EDAC_MOD_STR "amd64_edac" |
149 | ||
150 | /* Extended Model from CPUID, for CPU Revision numbers */ | |
1433eb99 BP |
151 | #define K8_REV_D 1 |
152 | #define K8_REV_E 2 | |
153 | #define K8_REV_F 4 | |
cfe40fdb DT |
154 | |
155 | /* Hardware limit on ChipSelect rows per MC and processors per system */ | |
9d858bb1 | 156 | #define MAX_CS_COUNT 8 |
cfe40fdb DT |
157 | #define DRAM_REG_COUNT 8 |
158 | ||
f6d6ae96 BP |
159 | #define ON true |
160 | #define OFF false | |
cfe40fdb DT |
161 | |
162 | /* | |
163 | * PCI-defined configuration space registers | |
164 | */ | |
165 | ||
166 | ||
167 | /* | |
168 | * Function 1 - Address Map | |
169 | */ | |
170 | #define K8_DRAM_BASE_LOW 0x40 | |
171 | #define K8_DRAM_LIMIT_LOW 0x44 | |
172 | #define K8_DHAR 0xf0 | |
173 | ||
174 | #define DHAR_VALID BIT(0) | |
175 | #define F10_DRAM_MEM_HOIST_VALID BIT(1) | |
176 | ||
177 | #define DHAR_BASE_MASK 0xff000000 | |
178 | #define dhar_base(dhar) (dhar & DHAR_BASE_MASK) | |
179 | ||
180 | #define K8_DHAR_OFFSET_MASK 0x0000ff00 | |
181 | #define k8_dhar_offset(dhar) ((dhar & K8_DHAR_OFFSET_MASK) << 16) | |
182 | ||
183 | #define F10_DHAR_OFFSET_MASK 0x0000ff80 | |
184 | /* NOTE: Extra mask bit vs K8 */ | |
185 | #define f10_dhar_offset(dhar) ((dhar & F10_DHAR_OFFSET_MASK) << 16) | |
186 | ||
187 | ||
188 | /* F10 High BASE/LIMIT registers */ | |
189 | #define F10_DRAM_BASE_HIGH 0x140 | |
190 | #define F10_DRAM_LIMIT_HIGH 0x144 | |
191 | ||
192 | ||
193 | /* | |
194 | * Function 2 - DRAM controller | |
195 | */ | |
196 | #define K8_DCSB0 0x40 | |
197 | #define F10_DCSB1 0x140 | |
198 | ||
199 | #define K8_DCSB_CS_ENABLE BIT(0) | |
200 | #define K8_DCSB_NPT_SPARE BIT(1) | |
201 | #define K8_DCSB_NPT_TESTFAIL BIT(2) | |
202 | ||
203 | /* | |
204 | * REV E: select [31:21] and [15:9] from DCSB and the shift amount to form | |
205 | * the address | |
206 | */ | |
207 | #define REV_E_DCSB_BASE_BITS (0xFFE0FE00ULL) | |
208 | #define REV_E_DCS_SHIFT 4 | |
cfe40fdb DT |
209 | |
210 | #define REV_F_F1Xh_DCSB_BASE_BITS (0x1FF83FE0ULL) | |
211 | #define REV_F_F1Xh_DCS_SHIFT 8 | |
212 | ||
213 | /* | |
214 | * REV F and later: selects [28:19] and [13:5] from DCSB and the shift amount | |
215 | * to form the address | |
216 | */ | |
217 | #define REV_F_DCSB_BASE_BITS (0x1FF83FE0ULL) | |
218 | #define REV_F_DCS_SHIFT 8 | |
cfe40fdb DT |
219 | |
220 | /* DRAM CS Mask Registers */ | |
221 | #define K8_DCSM0 0x60 | |
222 | #define F10_DCSM1 0x160 | |
223 | ||
224 | /* REV E: select [29:21] and [15:9] from DCSM */ | |
225 | #define REV_E_DCSM_MASK_BITS 0x3FE0FE00 | |
226 | ||
227 | /* unused bits [24:20] and [12:0] */ | |
228 | #define REV_E_DCS_NOTUSED_BITS 0x01F01FFF | |
229 | ||
230 | /* REV F and later: select [28:19] and [13:5] from DCSM */ | |
231 | #define REV_F_F1Xh_DCSM_MASK_BITS 0x1FF83FE0 | |
232 | ||
233 | /* unused bits [26:22] and [12:0] */ | |
234 | #define REV_F_F1Xh_DCS_NOTUSED_BITS 0x07C01FFF | |
235 | ||
236 | #define DBAM0 0x80 | |
237 | #define DBAM1 0x180 | |
238 | ||
239 | /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ | |
240 | #define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF) | |
241 | ||
242 | #define DBAM_MAX_VALUE 11 | |
243 | ||
244 | ||
245 | #define F10_DCLR_0 0x90 | |
246 | #define F10_DCLR_1 0x190 | |
247 | #define REVE_WIDTH_128 BIT(16) | |
248 | #define F10_WIDTH_128 BIT(11) | |
249 | ||
250 | ||
251 | #define F10_DCHR_0 0x94 | |
252 | #define F10_DCHR_1 0x194 | |
253 | ||
254 | #define F10_DCHR_FOUR_RANK_DIMM BIT(18) | |
1433eb99 | 255 | #define DDR3_MODE BIT(8) |
cfe40fdb DT |
256 | #define F10_DCHR_MblMode BIT(6) |
257 | ||
258 | ||
259 | #define F10_DCTL_SEL_LOW 0x110 | |
69542650 BP |
260 | #define dct_sel_baseaddr(pvt) ((pvt->dram_ctl_select_low) & 0xFFFFF800) |
261 | #define dct_sel_interleave_addr(pvt) (((pvt->dram_ctl_select_low) >> 6) & 0x3) | |
262 | #define dct_high_range_enabled(pvt) (pvt->dram_ctl_select_low & BIT(0)) | |
263 | #define dct_interleave_enabled(pvt) (pvt->dram_ctl_select_low & BIT(2)) | |
264 | #define dct_ganging_enabled(pvt) (pvt->dram_ctl_select_low & BIT(4)) | |
265 | #define dct_data_intlv_enabled(pvt) (pvt->dram_ctl_select_low & BIT(5)) | |
266 | #define dct_dram_enabled(pvt) (pvt->dram_ctl_select_low & BIT(8)) | |
267 | #define dct_memory_cleared(pvt) (pvt->dram_ctl_select_low & BIT(10)) | |
cfe40fdb DT |
268 | |
269 | #define F10_DCTL_SEL_HIGH 0x114 | |
270 | ||
cfe40fdb DT |
271 | /* |
272 | * Function 3 - Misc Control | |
273 | */ | |
274 | #define K8_NBCTL 0x40 | |
275 | ||
276 | /* Correctable ECC error reporting enable */ | |
277 | #define K8_NBCTL_CECCEn BIT(0) | |
278 | ||
279 | /* UnCorrectable ECC error reporting enable */ | |
280 | #define K8_NBCTL_UECCEn BIT(1) | |
281 | ||
282 | #define K8_NBCFG 0x44 | |
283 | #define K8_NBCFG_CHIPKILL BIT(23) | |
284 | #define K8_NBCFG_ECC_ENABLE BIT(22) | |
285 | ||
286 | #define K8_NBSL 0x48 | |
287 | ||
288 | ||
cfe40fdb DT |
289 | /* Family F10h: Normalized Extended Error Codes */ |
290 | #define F10_NBSL_EXT_ERR_RES 0x0 | |
cfe40fdb | 291 | #define F10_NBSL_EXT_ERR_ECC 0x8 |
cfe40fdb DT |
292 | |
293 | /* Next two are overloaded values */ | |
294 | #define F10_NBSL_EXT_ERR_LINK_PROTO 0xB | |
295 | #define F10_NBSL_EXT_ERR_L3_PROTO 0xB | |
296 | ||
297 | #define F10_NBSL_EXT_ERR_NB_ARRAY 0xC | |
298 | #define F10_NBSL_EXT_ERR_DRAM_PARITY 0xD | |
299 | #define F10_NBSL_EXT_ERR_LINK_RETRY 0xE | |
300 | ||
301 | /* Next two are overloaded values */ | |
302 | #define F10_NBSL_EXT_ERR_GART_WALK 0xF | |
303 | #define F10_NBSL_EXT_ERR_DEV_WALK 0xF | |
304 | ||
305 | /* 0x10 to 0x1B: Reserved */ | |
306 | #define F10_NBSL_EXT_ERR_L3_DATA 0x1C | |
307 | #define F10_NBSL_EXT_ERR_L3_TAG 0x1D | |
308 | #define F10_NBSL_EXT_ERR_L3_LRU 0x1E | |
309 | ||
310 | /* K8: Normalized Extended Error Codes */ | |
311 | #define K8_NBSL_EXT_ERR_ECC 0x0 | |
312 | #define K8_NBSL_EXT_ERR_CRC 0x1 | |
313 | #define K8_NBSL_EXT_ERR_SYNC 0x2 | |
314 | #define K8_NBSL_EXT_ERR_MST 0x3 | |
315 | #define K8_NBSL_EXT_ERR_TGT 0x4 | |
316 | #define K8_NBSL_EXT_ERR_GART 0x5 | |
317 | #define K8_NBSL_EXT_ERR_RMW 0x6 | |
318 | #define K8_NBSL_EXT_ERR_WDT 0x7 | |
319 | #define K8_NBSL_EXT_ERR_CHIPKILL_ECC 0x8 | |
320 | #define K8_NBSL_EXT_ERR_DRAM_PARITY 0xD | |
321 | ||
cfe40fdb DT |
322 | /* |
323 | * The following are for BUS type errors AFTER values have been normalized by | |
324 | * shifting right | |
325 | */ | |
326 | #define K8_NBSL_PP_SRC 0x0 | |
327 | #define K8_NBSL_PP_RES 0x1 | |
328 | #define K8_NBSL_PP_OBS 0x2 | |
329 | #define K8_NBSL_PP_GENERIC 0x3 | |
330 | ||
cfe40fdb | 331 | #define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF) |
cfe40fdb | 332 | |
cfe40fdb DT |
333 | #define K8_NBEAL 0x50 |
334 | #define K8_NBEAH 0x54 | |
335 | #define K8_SCRCTRL 0x58 | |
336 | ||
337 | #define F10_NB_CFG_LOW 0x88 | |
cfe40fdb DT |
338 | |
339 | #define F10_ONLINE_SPARE 0xB0 | |
340 | #define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1)) | |
341 | #define F10_ONLINE_SPARE_SWAPDONE1(x) ((x) & BIT(3)) | |
342 | #define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007) | |
343 | #define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007) | |
344 | ||
345 | #define F10_NB_ARRAY_ADDR 0xB8 | |
346 | ||
347 | #define F10_NB_ARRAY_DRAM_ECC 0x80000000 | |
348 | ||
349 | /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ | |
350 | #define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1) | |
351 | ||
352 | #define F10_NB_ARRAY_DATA 0xBC | |
353 | ||
354 | #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ | |
355 | (BIT(((word) & 0xF) + 20) | \ | |
94baaee4 | 356 | BIT(17) | bits) |
cfe40fdb DT |
357 | |
358 | #define SET_NB_DRAM_INJECTION_READ(word, bits) \ | |
359 | (BIT(((word) & 0xF) + 20) | \ | |
94baaee4 | 360 | BIT(16) | bits) |
cfe40fdb DT |
361 | |
362 | #define K8_NBCAP 0xE8 | |
363 | #define K8_NBCAP_CORES (BIT(12)|BIT(13)) | |
364 | #define K8_NBCAP_CHIPKILL BIT(4) | |
365 | #define K8_NBCAP_SECDED BIT(3) | |
cfe40fdb DT |
366 | #define K8_NBCAP_DCT_DUAL BIT(0) |
367 | ||
ad6a32e9 BP |
368 | #define EXT_NB_MCA_CFG 0x180 |
369 | ||
f6d6ae96 | 370 | /* MSRs */ |
cfe40fdb DT |
371 | #define K8_MSR_MCGCTL_NBE BIT(4) |
372 | ||
373 | #define K8_MSR_MC4CTL 0x0410 | |
374 | #define K8_MSR_MC4STAT 0x0411 | |
375 | #define K8_MSR_MC4ADDR 0x0412 | |
376 | ||
377 | /* AMD sets the first MC device at device ID 0x18. */ | |
37da0450 | 378 | static inline int get_node_id(struct pci_dev *pdev) |
cfe40fdb DT |
379 | { |
380 | return PCI_SLOT(pdev->devfn) - 0x18; | |
381 | } | |
382 | ||
383 | enum amd64_chipset_families { | |
384 | K8_CPUS = 0, | |
385 | F10_CPUS, | |
cfe40fdb DT |
386 | }; |
387 | ||
cfe40fdb DT |
388 | /* Error injection control structure */ |
389 | struct error_injection { | |
390 | u32 section; | |
391 | u32 word; | |
392 | u32 bit_map; | |
393 | }; | |
394 | ||
395 | struct amd64_pvt { | |
b8cfa02f BP |
396 | struct low_ops *ops; |
397 | ||
cfe40fdb | 398 | /* pci_device handles which we utilize */ |
8d5b5d9c | 399 | struct pci_dev *F1, *F2, *F3; |
cfe40fdb DT |
400 | |
401 | int mc_node_id; /* MC index of this MC node */ | |
402 | int ext_model; /* extended model value of this node */ | |
cfe40fdb DT |
403 | int channel_count; |
404 | ||
405 | /* Raw registers */ | |
406 | u32 dclr0; /* DRAM Configuration Low DCT0 reg */ | |
407 | u32 dclr1; /* DRAM Configuration Low DCT1 reg */ | |
408 | u32 dchr0; /* DRAM Configuration High DCT0 reg */ | |
409 | u32 dchr1; /* DRAM Configuration High DCT1 reg */ | |
410 | u32 nbcap; /* North Bridge Capabilities */ | |
411 | u32 nbcfg; /* F10 North Bridge Configuration */ | |
412 | u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ | |
413 | u32 dhar; /* DRAM Hoist reg */ | |
414 | u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ | |
415 | u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ | |
416 | ||
417 | /* DRAM CS Base Address Registers F2x[1,0][5C:40] */ | |
9d858bb1 BP |
418 | u32 dcsb0[MAX_CS_COUNT]; |
419 | u32 dcsb1[MAX_CS_COUNT]; | |
cfe40fdb DT |
420 | |
421 | /* DRAM CS Mask Registers F2x[1,0][6C:60] */ | |
9d858bb1 BP |
422 | u32 dcsm0[MAX_CS_COUNT]; |
423 | u32 dcsm1[MAX_CS_COUNT]; | |
cfe40fdb DT |
424 | |
425 | /* | |
426 | * Decoded parts of DRAM BASE and LIMIT Registers | |
427 | * F1x[78,70,68,60,58,50,48,40] | |
428 | */ | |
429 | u64 dram_base[DRAM_REG_COUNT]; | |
430 | u64 dram_limit[DRAM_REG_COUNT]; | |
431 | u8 dram_IntlvSel[DRAM_REG_COUNT]; | |
432 | u8 dram_IntlvEn[DRAM_REG_COUNT]; | |
433 | u8 dram_DstNode[DRAM_REG_COUNT]; | |
434 | u8 dram_rw_en[DRAM_REG_COUNT]; | |
435 | ||
436 | /* | |
437 | * The following fields are set at (load) run time, after CPU revision | |
438 | * has been determined, since the dct_base and dct_mask registers vary | |
439 | * based on revision | |
440 | */ | |
441 | u32 dcsb_base; /* DCSB base bits */ | |
442 | u32 dcsm_mask; /* DCSM mask bits */ | |
9d858bb1 | 443 | u32 cs_count; /* num chip selects (== num DCSB registers) */ |
cfe40fdb DT |
444 | u32 num_dcsm; /* Number of DCSM registers */ |
445 | u32 dcs_mask_notused; /* DCSM notused mask bits */ | |
446 | u32 dcs_shift; /* DCSB and DCSM shift value */ | |
447 | ||
448 | u64 top_mem; /* top of memory below 4GB */ | |
449 | u64 top_mem2; /* top of memory above 4GB */ | |
450 | ||
451 | u32 dram_ctl_select_low; /* DRAM Controller Select Low Reg */ | |
452 | u32 dram_ctl_select_high; /* DRAM Controller Select High Reg */ | |
453 | u32 online_spare; /* On-Line spare Reg */ | |
454 | ||
ad6a32e9 BP |
455 | /* x4 or x8 syndromes in use */ |
456 | u8 syn_type; | |
457 | ||
cfe40fdb | 458 | /* temp storage for when input is received from sysfs */ |
ef44cc4c | 459 | struct err_regs ctl_error_info; |
cfe40fdb DT |
460 | |
461 | /* place to store error injection parameters prior to issue */ | |
462 | struct error_injection injection; | |
463 | ||
464 | /* Save old hw registers' values before we modified them */ | |
465 | u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */ | |
466 | u32 old_nbctl; | |
cfe40fdb | 467 | |
395ae783 BP |
468 | /* DCT per-family scrubrate setting */ |
469 | u32 min_scrubrate; | |
470 | ||
0092b20d BP |
471 | /* family name this instance is running on */ |
472 | const char *ctl_name; | |
473 | ||
cfe40fdb DT |
474 | /* misc settings */ |
475 | struct flags { | |
d95cf4de BP |
476 | unsigned long nb_mce_enable:1; |
477 | unsigned long nb_ecc_prev:1; | |
cfe40fdb DT |
478 | } flags; |
479 | }; | |
480 | ||
481 | struct scrubrate { | |
482 | u32 scrubval; /* bit pattern for scrub rate */ | |
483 | u32 bandwidth; /* bandwidth consumed (bytes/sec) */ | |
484 | }; | |
485 | ||
486 | extern struct scrubrate scrubrates[23]; | |
cfe40fdb DT |
487 | extern const char *tt_msgs[4]; |
488 | extern const char *ll_msgs[4]; | |
489 | extern const char *rrrr_msgs[16]; | |
490 | extern const char *to_msgs[2]; | |
491 | extern const char *pp_msgs[4]; | |
492 | extern const char *ii_msgs[4]; | |
cfe40fdb DT |
493 | extern const char *htlink_msgs[8]; |
494 | ||
7d6034d3 | 495 | #ifdef CONFIG_EDAC_DEBUG |
9cdeb404 | 496 | #define NUM_DBG_ATTRS 5 |
7d6034d3 DT |
497 | #else |
498 | #define NUM_DBG_ATTRS 0 | |
499 | #endif | |
500 | ||
501 | #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION | |
502 | #define NUM_INJ_ATTRS 5 | |
503 | #else | |
504 | #define NUM_INJ_ATTRS 0 | |
505 | #endif | |
506 | ||
507 | extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS], | |
508 | amd64_inj_attrs[NUM_INJ_ATTRS]; | |
509 | ||
cfe40fdb DT |
510 | /* |
511 | * Each of the PCI Device IDs types have their own set of hardware accessor | |
512 | * functions and per device encoding/decoding logic. | |
513 | */ | |
514 | struct low_ops { | |
1433eb99 BP |
515 | int (*early_channel_count) (struct amd64_pvt *pvt); |
516 | ||
517 | u64 (*get_error_address) (struct mem_ctl_info *mci, | |
518 | struct err_regs *info); | |
519 | void (*read_dram_base_limit) (struct amd64_pvt *pvt, int dram); | |
520 | void (*read_dram_ctl_register) (struct amd64_pvt *pvt); | |
521 | void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, | |
522 | struct err_regs *info, u64 SystemAddr); | |
523 | int (*dbam_to_cs) (struct amd64_pvt *pvt, int cs_mode); | |
cfe40fdb DT |
524 | }; |
525 | ||
526 | struct amd64_family_type { | |
527 | const char *ctl_name; | |
8d5b5d9c | 528 | u16 f1_id, f3_id; |
cfe40fdb DT |
529 | struct low_ops ops; |
530 | }; | |
531 | ||
6ba5dcdc BP |
532 | static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, |
533 | u32 *val, const char *func) | |
534 | { | |
535 | int err = 0; | |
536 | ||
537 | err = pci_read_config_dword(pdev, offset, val); | |
538 | if (err) | |
24f9a7fe BP |
539 | amd64_warn("%s: error reading F%dx%x.\n", |
540 | func, PCI_FUNC(pdev->devfn), offset); | |
6ba5dcdc BP |
541 | |
542 | return err; | |
543 | } | |
544 | ||
545 | #define amd64_read_pci_cfg(pdev, offset, val) \ | |
546 | amd64_read_pci_cfg_dword(pdev, offset, val, __func__) | |
547 | ||
cfe40fdb DT |
548 | /* |
549 | * For future CPU versions, verify the following as new 'slow' rates appear and | |
550 | * modify the necessary skip values for the supported CPU. | |
551 | */ | |
552 | #define K8_MIN_SCRUB_RATE_BITS 0x0 | |
553 | #define F10_MIN_SCRUB_RATE_BITS 0x5 | |
cfe40fdb | 554 | |
cfe40fdb DT |
555 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, |
556 | u64 *hole_offset, u64 *hole_size); |