[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / amd64_edac.h

/*
 * AMD64 class Memory Controller kernel module
 *
 * Copyright (c) 2009 SoftwareBitMaker.
 * Copyright (c) 2009 Advanced Micro Devices, Inc.
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 *	Originally Written by Thayne Harbaugh
 *
 *      Changes by Douglas "norsk" Thompson  <dougthompson@xmission.com>:
 *		- K8 CPU Revision D and greater support
 *
 *      Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
 *		- Module largely rewritten, with new (and hopefully correct)
 *		code for dealing with node and chip select interleaving,
 *		various code cleanup, and bug fixes
 *		- Added support for memory hoisting using DRAM hole address
 *		register
 *
 *	Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
 *		-K8 Rev (1207) revision support added, required Revision
 *		specific mini-driver code to support Rev F as well as
 *		prior revisions
 *
 *	Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
 *		-Family 10h revision support added. New PCI Device IDs,
 *		indicating new changes. Actual registers modified
 *		were slight, less than the Rev E to Rev F transition
 *		but changing the PCI Device ID was the proper thing to
 *		do, as it provides for almost automactic family
 *		detection. The mods to Rev F required more family
 *		information detection.
 *
 *	Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>:
 *		- misc fixes and code cleanups
 *
 * This module is based on the following documents
 * (available from http://www.amd.com/):
 *
 *	Title:	BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
 *		Opteron Processors
 *	AMD publication #: 26094
 *`	Revision: 3.26
 *
 *	Title:	BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
 *		Processors
 *	AMD publication #: 32559
 *	Revision: 3.00
 *	Issue Date: May 2006
 *
 *	Title:	BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
 *		Processors
 *	AMD publication #: 31116
 *	Revision: 3.00
 *	Issue Date: September 07, 2007
 *
 * Sections in the first 2 documents are no longer in sync with each other.
 * The Family 10h BKDG was totally re-written from scratch with a new
 * presentation model.
 * Therefore, comments that refer to a Document section might be off.
 */

#include <linux/module.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/mmzone.h>
#include <linux/edac.h>
#include <asm/msr.h>
#include "edac_core.h"
#include "mce_amd.h"

#define amd64_debug(fmt, arg...) \
	edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)

#define amd64_info(fmt, arg...) \
	edac_printk(KERN_INFO, "amd64", fmt, ##arg)

#define amd64_notice(fmt, arg...) \
	edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)

#define amd64_warn(fmt, arg...) \
	edac_printk(KERN_WARNING, "amd64", fmt, ##arg)

#define amd64_err(fmt, arg...) \
	edac_printk(KERN_ERR, "amd64", fmt, ##arg)

#define amd64_mc_warn(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)

#define amd64_mc_err(mci, fmt, arg...) \
	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)

/*
 * Throughout the comments in this code, the following terms are used:
 *
 *	SysAddr, DramAddr, and InputAddr
 *
 *  These terms come directly from the amd64 documentation
 * (AMD publication #26094).  They are defined as follows:
 *
 *     SysAddr:
 *         This is a physical address generated by a CPU core or a device
 *         doing DMA.  If generated by a CPU core, a SysAddr is the result of
 *         a virtual to physical address translation by the CPU core's address
 *         translation mechanism (MMU).
 *
 *     DramAddr:
 *         A DramAddr is derived from a SysAddr by subtracting an offset that
 *         depends on which node the SysAddr maps to and whether the SysAddr
 *         is within a range affected by memory hoisting.  The DRAM Base
 *         (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
 *         determine which node a SysAddr maps to.
 *
 *         If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
 *         is within the range of addresses specified by this register, then
 *         a value x from the DHAR is subtracted from the SysAddr to produce a
 *         DramAddr.  Here, x represents the base address for the node that
 *         the SysAddr maps to plus an offset due to memory hoisting.  See
 *         section 3.4.8 and the comments in amd64_get_dram_hole_info() and
 *         sys_addr_to_dram_addr() below for more information.
 *
 *         If the SysAddr is not affected by the DHAR then a value y is
 *         subtracted from the SysAddr to produce a DramAddr.  Here, y is the
 *         base address for the node that the SysAddr maps to.  See section
 *         3.4.4 and the comments in sys_addr_to_dram_addr() below for more
 *         information.
 *
 *     InputAddr:
 *         A DramAddr is translated to an InputAddr before being passed to the
 *         memory controller for the node that the DramAddr is associated
 *         with.  The memory controller then maps the InputAddr to a csrow.
 *         If node interleaving is not in use, then the InputAddr has the same
 *         value as the DramAddr.  Otherwise, the InputAddr is produced by
 *         discarding the bits used for node interleaving from the DramAddr.
 *         See section 3.4.4 for more information.
 *
 *         The memory controller for a given node uses its DRAM CS Base and
 *         DRAM CS Mask registers to map an InputAddr to a csrow.  See
 *         sections 3.5.4 and 3.5.5 for more information.
 */

#define EDAC_AMD64_VERSION		"v3.3.0"
#define EDAC_MOD_STR			"amd64_edac"

/* Extended Model from CPUID, for CPU Revision numbers */
#define K8_REV_D			1
#define K8_REV_E			2
#define K8_REV_F			4

/* Hardware limit on ChipSelect rows per MC and processors per system */
#define NUM_CHIPSELECTS			8
#define DRAM_RANGES			8

#define ON true
#define OFF false

/*
 * Create a contiguous bitmask starting at bit position @lo and ending at
 * position @hi. For example
 *
 * GENMASK(21, 39) gives us the 64bit vector 0x000000ffffe00000.
 */
#define GENMASK(lo, hi)			(((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))

/*
 * PCI-defined configuration space registers
 */


/*
 * Function 1 - Address Map
 */
#define DRAM_BASE_LO			0x40
#define DRAM_LIMIT_LO			0x44

#define dram_intlv_en(pvt, i)		((pvt->ranges[i].base.lo >> 8) & 0x7)
#define dram_rw(pvt, i)			(pvt->ranges[i].base.lo & 0x3)
#define dram_intlv_sel(pvt, i)		((pvt->ranges[i].lim.lo >> 8) & 0x7)
#define dram_dst_node(pvt, i)		(pvt->ranges[i].lim.lo & 0x7)

#define DHAR				0xf0
#define dhar_valid(pvt)			((pvt)->dhar & BIT(0))
#define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))
#define dhar_base(pvt)			((pvt)->dhar & 0xff000000)
#define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)

					/* NOTE: Extra mask bit vs K8 */
#define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)

#define DCT_CFG_SEL			0x10C

#define DRAM_BASE_HI			0x140
#define DRAM_LIMIT_HI			0x144


/*
 * Function 2 - DRAM controller
 */
#define DCSB0				0x40
#define DCSB1				0x140
#define DCSB_CS_ENABLE			BIT(0)

#define DCSM0				0x60
#define DCSM1				0x160

#define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)

#define DBAM0				0x80
#define DBAM1				0x180

/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
#define DBAM_DIMM(i, reg)		((((reg) >> (4*i))) & 0xF)

#define DBAM_MAX_VALUE			11

#define DCLR0				0x90
#define DCLR1				0x190
#define REVE_WIDTH_128			BIT(16)
#define F10_WIDTH_128			BIT(11)

#define DCHR0				0x94
#define DCHR1				0x194
#define DDR3_MODE			BIT(8)

#define DCT_SEL_LO			0x110
#define dct_sel_baseaddr(pvt)		((pvt)->dct_sel_lo & 0xFFFFF800)
#define dct_sel_interleave_addr(pvt)	(((pvt)->dct_sel_lo >> 6) & 0x3)
#define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))
#define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))

#define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))

#define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))
#define dct_dram_enabled(pvt)		((pvt)->dct_sel_lo & BIT(8))
#define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))

#define DCT_SEL_HI			0x114

/*
 * Function 3 - Misc Control
 */
#define NBCTL				0x40

#define NBCFG				0x44
#define NBCFG_CHIPKILL			BIT(23)
#define NBCFG_ECC_ENABLE		BIT(22)

/* F3x48: NBSL */
#define F10_NBSL_EXT_ERR_ECC		0x8
#define NBSL_PP_OBS			0x2

#define SCRCTRL				0x58

#define F10_ONLINE_SPARE		0xB0
#define F10_ONLINE_SPARE_SWAPDONE0(x)	((x) & BIT(1))
#define F10_ONLINE_SPARE_SWAPDONE1(x)	((x) & BIT(3))
#define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007)
#define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007)

#define F10_NB_ARRAY_ADDR		0xB8
#define F10_NB_ARRAY_DRAM_ECC		BIT(31)

/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline  */
#define SET_NB_ARRAY_ADDRESS(section)	(((section) & 0x3) << 1)

#define F10_NB_ARRAY_DATA		0xBC
#define SET_NB_DRAM_INJECTION_WRITE(word, bits)  \
					(BIT(((word) & 0xF) + 20) | \
					BIT(17) | bits)
#define SET_NB_DRAM_INJECTION_READ(word, bits)  \
					(BIT(((word) & 0xF) + 20) | \
					BIT(16) |  bits)

#define NBCAP				0xE8
#define NBCAP_CHIPKILL			BIT(4)
#define NBCAP_SECDED			BIT(3)
#define NBCAP_DCT_DUAL			BIT(0)

#define EXT_NB_MCA_CFG			0x180

/* MSRs */
#define MSR_MCGCTL_NBE			BIT(4)

/* AMD sets the first MC device at device ID 0x18. */
static inline int get_node_id(struct pci_dev *pdev)
{
	return PCI_SLOT(pdev->devfn) - 0x18;
}

enum amd_families {
	K8_CPUS = 0,
	F10_CPUS,
	F15_CPUS,
	NUM_FAMILIES,
};

/* Error injection control structure */
struct error_injection {
	u32	section;
	u32	word;
	u32	bit_map;
};

/* low and high part of PCI config space regs */
struct reg_pair {
	u32 lo, hi;
};

/*
 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
 */
struct dram_range {
	struct reg_pair base;
	struct reg_pair lim;
};

/* A DCT chip selects collection */
struct chip_select {
	u32 csbases[NUM_CHIPSELECTS];
	u8 b_cnt;

	u32 csmasks[NUM_CHIPSELECTS];
	u8 m_cnt;
};

struct amd64_pvt {
	struct low_ops *ops;

	/* pci_device handles which we utilize */
	struct pci_dev *F1, *F2, *F3;

	int mc_node_id;		/* MC index of this MC node */
	int ext_model;		/* extended model value of this node */
	int channel_count;

	/* Raw registers */
	u32 dclr0;		/* DRAM Configuration Low DCT0 reg */
	u32 dclr1;		/* DRAM Configuration Low DCT1 reg */
	u32 dchr0;		/* DRAM Configuration High DCT0 reg */
	u32 dchr1;		/* DRAM Configuration High DCT1 reg */
	u32 nbcap;		/* North Bridge Capabilities */
	u32 nbcfg;		/* F10 North Bridge Configuration */
	u32 ext_nbcfg;		/* Extended F10 North Bridge Configuration */
	u32 dhar;		/* DRAM Hoist reg */
	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */

	/* one for each DCT */
	struct chip_select csels[2];

	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
	struct dram_range ranges[DRAM_RANGES];

	u64 top_mem;		/* top of memory below 4GB */
	u64 top_mem2;		/* top of memory above 4GB */

	u32 dct_sel_lo;		/* DRAM Controller Select Low */
	u32 dct_sel_hi;		/* DRAM Controller Select High */
	u32 online_spare;	/* On-Line spare Reg */

	/* x4 or x8 syndromes in use */
	u8 syn_type;

	/* place to store error injection parameters prior to issue */
	struct error_injection injection;

	/* DCT per-family scrubrate setting */
	u32 min_scrubrate;

	/* family name this instance is running on */
	const char *ctl_name;

};

static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)
{
	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;

	if (boot_cpu_data.x86 == 0xf)
		return addr;

	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
}

static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i)
{
	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;

	if (boot_cpu_data.x86 == 0xf)
		return lim;

	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
}

static inline u16 extract_syndrome(u64 status)
{
	return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
}

/*
 * per-node ECC settings descriptor
 */
struct ecc_settings {
	u32 old_nbctl;
	bool nbctl_valid;

	struct flags {
		unsigned long nb_mce_enable:1;
		unsigned long nb_ecc_prev:1;
	} flags;
};

extern const char *tt_msgs[4];
extern const char *ll_msgs[4];
extern const char *rrrr_msgs[16];
extern const char *to_msgs[2];
extern const char *pp_msgs[4];
extern const char *ii_msgs[4];
extern const char *htlink_msgs[8];

#ifdef CONFIG_EDAC_DEBUG
#define NUM_DBG_ATTRS 5
#else
#define NUM_DBG_ATTRS 0
#endif

#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
#define NUM_INJ_ATTRS 5
#else
#define NUM_INJ_ATTRS 0
#endif

extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
				     amd64_inj_attrs[NUM_INJ_ATTRS];

/*
 * Each of the PCI Device IDs types have their own set of hardware accessor
 * functions and per device encoding/decoding logic.
 */
struct low_ops {
	int (*early_channel_count)	(struct amd64_pvt *pvt);
	void (*read_dram_ctl_register)	(struct amd64_pvt *pvt);
	void (*map_sysaddr_to_csrow)	(struct mem_ctl_info *mci, u64 sys_addr,
					 u16 syndrome);
	int (*dbam_to_cs)		(struct amd64_pvt *pvt, int cs_mode);
	int (*read_dct_pci_cfg)		(struct amd64_pvt *pvt, int offset,
					 u32 *val, const char *func);
};

struct amd64_family_type {
	const char *ctl_name;
	u16 f1_id, f3_id;
	struct low_ops ops;
};

int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
				u32 val, const char *func);

#define amd64_read_pci_cfg(pdev, offset, val)	\
	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)

#define amd64_write_pci_cfg(pdev, offset, val)	\
	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)

#define amd64_read_dct_pci_cfg(pvt, offset, val) \
	pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)

/*
 * For future CPU versions, verify the following as new 'slow' rates appear and
 * modify the necessary skip values for the supported CPU.
 */
#define K8_MIN_SCRUB_RATE_BITS	0x0
#define F10_MIN_SCRUB_RATE_BITS	0x5

int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
			     u64 *hole_offset, u64 *hole_size);
Commit	Line	Data
cfe40fdb DT	1	/*
	2	* AMD64 class Memory Controller kernel module
	3	*
	4	* Copyright (c) 2009 SoftwareBitMaker.
	5	* Copyright (c) 2009 Advanced Micro Devices, Inc.
	6	*
	7	* This file may be distributed under the terms of the
	8	* GNU General Public License.
	9	*
	10	* Originally Written by Thayne Harbaugh
	11	*
	12	* Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
	13	* - K8 CPU Revision D and greater support
	14	*
	15	* Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
	16	* - Module largely rewritten, with new (and hopefully correct)
	17	* code for dealing with node and chip select interleaving,
	18	* various code cleanup, and bug fixes
	19	* - Added support for memory hoisting using DRAM hole address
	20	* register
	21	*
	22	* Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
	23	* -K8 Rev (1207) revision support added, required Revision
	24	* specific mini-driver code to support Rev F as well as
	25	* prior revisions
	26	*
	27	* Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
	28	* -Family 10h revision support added. New PCI Device IDs,
	29	* indicating new changes. Actual registers modified
	30	* were slight, less than the Rev E to Rev F transition
	31	* but changing the PCI Device ID was the proper thing to
	32	* do, as it provides for almost automactic family
	33	* detection. The mods to Rev F required more family
	34	* information detection.
	35	*
	36	* Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>:
	37	* - misc fixes and code cleanups
	38	*
	39	* This module is based on the following documents
	40	* (available from http://www.amd.com/):
	41	*
	42	* Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
	43	* Opteron Processors
	44	* AMD publication #: 26094
	45	*` Revision: 3.26
	46	*
	47	* Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
	48	* Processors
	49	* AMD publication #: 32559
	50	* Revision: 3.00
	51	* Issue Date: May 2006
	52	*
	53	* Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
	54	* Processors
	55	* AMD publication #: 31116
	56	* Revision: 3.00
	57	* Issue Date: September 07, 2007
	58	*
	59	* Sections in the first 2 documents are no longer in sync with each other.
	60	* The Family 10h BKDG was totally re-written from scratch with a new
	61	* presentation model.
	62	* Therefore, comments that refer to a Document section might be off.
	63	*/
	64
65	#include <linux/module.h>
66	#include <linux/ctype.h>
67	#include <linux/init.h>
68	#include <linux/pci.h>
69	#include <linux/pci_ids.h>
70	#include <linux/slab.h>
71	#include <linux/mmzone.h>
72	#include <linux/edac.h>
f9431992	73	#include <asm/msr.h>
cfe40fdb	74	#include "edac_core.h"
47ca08a4	75	#include "mce_amd.h"
cfe40fdb	76
24f9a7fe BP	77	#define amd64_debug(fmt, arg...) \
24f9a7fe BP	78	edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
cfe40fdb	79
24f9a7fe BP	80	#define amd64_info(fmt, arg...) \
	81	edac_printk(KERN_INFO, "amd64", fmt, ##arg)
	82
	83	#define amd64_notice(fmt, arg...) \
	84	edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
	85
	86	#define amd64_warn(fmt, arg...) \
	87	edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
	88
	89	#define amd64_err(fmt, arg...) \
	90	edac_printk(KERN_ERR, "amd64", fmt, ##arg)
	91
	92	#define amd64_mc_warn(mci, fmt, arg...) \
	93	edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
	94
	95	#define amd64_mc_err(mci, fmt, arg...) \
	96	edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
cfe40fdb DT	97
	98	/*
	99	* Throughout the comments in this code, the following terms are used:
	100	*
	101	* SysAddr, DramAddr, and InputAddr
	102	*
	103	* These terms come directly from the amd64 documentation
	104	* (AMD publication #26094). They are defined as follows:
	105	*
	106	* SysAddr:
	107	* This is a physical address generated by a CPU core or a device
	108	* doing DMA. If generated by a CPU core, a SysAddr is the result of
	109	* a virtual to physical address translation by the CPU core's address
	110	* translation mechanism (MMU).
	111	*
	112	* DramAddr:
	113	* A DramAddr is derived from a SysAddr by subtracting an offset that
	114	* depends on which node the SysAddr maps to and whether the SysAddr
	115	* is within a range affected by memory hoisting. The DRAM Base
	116	* (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
	117	* determine which node a SysAddr maps to.
	118	*
	119	* If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
	120	* is within the range of addresses specified by this register, then
	121	* a value x from the DHAR is subtracted from the SysAddr to produce a
	122	* DramAddr. Here, x represents the base address for the node that
	123	* the SysAddr maps to plus an offset due to memory hoisting. See
	124	* section 3.4.8 and the comments in amd64_get_dram_hole_info() and
	125	* sys_addr_to_dram_addr() below for more information.
	126	*
	127	* If the SysAddr is not affected by the DHAR then a value y is
	128	* subtracted from the SysAddr to produce a DramAddr. Here, y is the
	129	* base address for the node that the SysAddr maps to. See section
	130	* 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
	131	* information.
	132	*
	133	* InputAddr:
	134	* A DramAddr is translated to an InputAddr before being passed to the
	135	* memory controller for the node that the DramAddr is associated
	136	* with. The memory controller then maps the InputAddr to a csrow.
	137	* If node interleaving is not in use, then the InputAddr has the same
	138	* value as the DramAddr. Otherwise, the InputAddr is produced by
	139	* discarding the bits used for node interleaving from the DramAddr.
	140	* See section 3.4.4 for more information.
	141	*
	142	* The memory controller for a given node uses its DRAM CS Base and
	143	* DRAM CS Mask registers to map an InputAddr to a csrow. See
	144	* sections 3.5.4 and 3.5.5 for more information.
	145	*/
	146
24f9a7fe	147	#define EDAC_AMD64_VERSION "v3.3.0"
cfe40fdb DT	148	#define EDAC_MOD_STR "amd64_edac"
	149
	150	/* Extended Model from CPUID, for CPU Revision numbers */
1433eb99 BP	151	#define K8_REV_D 1
	152	#define K8_REV_E 2
	153	#define K8_REV_F 4
cfe40fdb DT	154
cfe40fdb DT	155	/* Hardware limit on ChipSelect rows per MC and processors per system */
7f19bf75 BP	156	#define NUM_CHIPSELECTS 8
7f19bf75 BP	157	#define DRAM_RANGES 8
cfe40fdb	158
f6d6ae96 BP	159	#define ON true
f6d6ae96 BP	160	#define OFF false
cfe40fdb	161
11c75ead BP	162	/*
	163	* Create a contiguous bitmask starting at bit position @lo and ending at
	164	* position @hi. For example
	165	*
	166	* GENMASK(21, 39) gives us the 64bit vector 0x000000ffffe00000.
	167	*/
	168	#define GENMASK(lo, hi) (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))
	169
cfe40fdb DT	170	/*
	171	* PCI-defined configuration space registers
	172	*/
	173
	174
	175	/*
	176	* Function 1 - Address Map
	177	*/
7f19bf75 BP	178	#define DRAM_BASE_LO 0x40
	179	#define DRAM_LIMIT_LO 0x44
	180
	181	#define dram_intlv_en(pvt, i) ((pvt->ranges[i].base.lo >> 8) & 0x7)
	182	#define dram_rw(pvt, i) (pvt->ranges[i].base.lo & 0x3)
	183	#define dram_intlv_sel(pvt, i) ((pvt->ranges[i].lim.lo >> 8) & 0x7)
	184	#define dram_dst_node(pvt, i) (pvt->ranges[i].lim.lo & 0x7)
	185
bc21fa57	186	#define DHAR 0xf0
c8e518d5 BP	187	#define dhar_valid(pvt) ((pvt)->dhar & BIT(0))
	188	#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
	189	#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
	190	#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
cfe40fdb	191
cfe40fdb	192	/* NOTE: Extra mask bit vs K8 */
c8e518d5	193	#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
cfe40fdb	194
b2b0c605	195	#define DCT_CFG_SEL 0x10C
cfe40fdb	196
7f19bf75 BP	197	#define DRAM_BASE_HI 0x140
7f19bf75 BP	198	#define DRAM_LIMIT_HI 0x144
cfe40fdb DT	199
	200
	201	/*
	202	* Function 2 - DRAM controller
	203	*/
11c75ead BP	204	#define DCSB0 0x40
	205	#define DCSB1 0x140
	206	#define DCSB_CS_ENABLE BIT(0)
cfe40fdb	207
11c75ead BP	208	#define DCSM0 0x60
11c75ead BP	209	#define DCSM1 0x160
cfe40fdb	210
11c75ead	211	#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
cfe40fdb DT	212
	213	#define DBAM0 0x80
	214	#define DBAM1 0x180
	215
	216	/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
	217	#define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF)
	218
	219	#define DBAM_MAX_VALUE 11
	220
cb328507 BP	221	#define DCLR0 0x90
cb328507 BP	222	#define DCLR1 0x190
cfe40fdb DT	223	#define REVE_WIDTH_128 BIT(16)
	224	#define F10_WIDTH_128 BIT(11)
	225
cb328507 BP	226	#define DCHR0 0x94
cb328507 BP	227	#define DCHR1 0x194
1433eb99	228	#define DDR3_MODE BIT(8)
cfe40fdb	229
78da121e BP	230	#define DCT_SEL_LO 0x110
	231	#define dct_sel_baseaddr(pvt) ((pvt)->dct_sel_lo & 0xFFFFF800)
	232	#define dct_sel_interleave_addr(pvt) (((pvt)->dct_sel_lo >> 6) & 0x3)
	233	#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
	234	#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
cb328507	235
78da121e	236	#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
cb328507	237
78da121e BP	238	#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
	239	#define dct_dram_enabled(pvt) ((pvt)->dct_sel_lo & BIT(8))
	240	#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
cfe40fdb	241
78da121e	242	#define DCT_SEL_HI 0x114
cfe40fdb	243
cfe40fdb DT	244	/*
	245	* Function 3 - Misc Control
	246	*/
c9f4f26e	247	#define NBCTL 0x40
cfe40fdb	248
a97fa68e BP	249	#define NBCFG 0x44
	250	#define NBCFG_CHIPKILL BIT(23)
	251	#define NBCFG_ECC_ENABLE BIT(22)
cfe40fdb	252
5980bb9c	253	/* F3x48: NBSL */
cfe40fdb	254	#define F10_NBSL_EXT_ERR_ECC 0x8
5980bb9c	255	#define NBSL_PP_OBS 0x2
cfe40fdb	256
5980bb9c	257	#define SCRCTRL 0x58
cfe40fdb DT	258
	259	#define F10_ONLINE_SPARE 0xB0
	260	#define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1))
	261	#define F10_ONLINE_SPARE_SWAPDONE1(x) ((x) & BIT(3))
	262	#define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007)
	263	#define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007)
	264
	265	#define F10_NB_ARRAY_ADDR 0xB8
5980bb9c	266	#define F10_NB_ARRAY_DRAM_ECC BIT(31)
cfe40fdb DT	267
	268	/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
	269	#define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1)
	270
	271	#define F10_NB_ARRAY_DATA 0xBC
cfe40fdb DT	272	#define SET_NB_DRAM_INJECTION_WRITE(word, bits) \
cfe40fdb DT	273	(BIT(((word) & 0xF) + 20) \| \
94baaee4	274	BIT(17) \| bits)
cfe40fdb DT	275	#define SET_NB_DRAM_INJECTION_READ(word, bits) \
cfe40fdb DT	276	(BIT(((word) & 0xF) + 20) \| \
94baaee4	277	BIT(16) \| bits)
cfe40fdb	278
5980bb9c BP	279	#define NBCAP 0xE8
	280	#define NBCAP_CHIPKILL BIT(4)
	281	#define NBCAP_SECDED BIT(3)
	282	#define NBCAP_DCT_DUAL BIT(0)
cfe40fdb	283
ad6a32e9 BP	284	#define EXT_NB_MCA_CFG 0x180
ad6a32e9 BP	285
f6d6ae96	286	/* MSRs */
5980bb9c	287	#define MSR_MCGCTL_NBE BIT(4)
cfe40fdb DT	288
cfe40fdb DT	289	/* AMD sets the first MC device at device ID 0x18. */
37da0450	290	static inline int get_node_id(struct pci_dev *pdev)
cfe40fdb DT	291	{
	292	return PCI_SLOT(pdev->devfn) - 0x18;
	293	}
	294
b2b0c605	295	enum amd_families {
cfe40fdb DT	296	K8_CPUS = 0,
cfe40fdb DT	297	F10_CPUS,
b2b0c605 BP	298	F15_CPUS,
b2b0c605 BP	299	NUM_FAMILIES,
cfe40fdb DT	300	};
cfe40fdb DT	301
cfe40fdb DT	302	/* Error injection control structure */
	303	struct error_injection {
	304	u32 section;
	305	u32 word;
	306	u32 bit_map;
	307	};
	308
7f19bf75 BP	309	/* low and high part of PCI config space regs */
	310	struct reg_pair {
	311	u32 lo, hi;
	312	};
	313
	314	/*
	315	* See F1x[1, 0][7C:40] DRAM Base/Limit Registers
	316	*/
	317	struct dram_range {
	318	struct reg_pair base;
	319	struct reg_pair lim;
	320	};
	321
11c75ead BP	322	/* A DCT chip selects collection */
	323	struct chip_select {
	324	u32 csbases[NUM_CHIPSELECTS];
	325	u8 b_cnt;
	326
	327	u32 csmasks[NUM_CHIPSELECTS];
	328	u8 m_cnt;
	329	};
	330
cfe40fdb	331	struct amd64_pvt {
b8cfa02f BP	332	struct low_ops *ops;
b8cfa02f BP	333
cfe40fdb	334	/* pci_device handles which we utilize */
8d5b5d9c	335	struct pci_dev F1, F2, *F3;
cfe40fdb DT	336
	337	int mc_node_id; /* MC index of this MC node */
	338	int ext_model; /* extended model value of this node */
cfe40fdb DT	339	int channel_count;
	340
	341	/* Raw registers */
	342	u32 dclr0; /* DRAM Configuration Low DCT0 reg */
	343	u32 dclr1; /* DRAM Configuration Low DCT1 reg */
	344	u32 dchr0; /* DRAM Configuration High DCT0 reg */
	345	u32 dchr1; /* DRAM Configuration High DCT1 reg */
	346	u32 nbcap; /* North Bridge Capabilities */
	347	u32 nbcfg; /* F10 North Bridge Configuration */
	348	u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
	349	u32 dhar; /* DRAM Hoist reg */
	350	u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
	351	u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
	352
11c75ead BP	353	/* one for each DCT */
11c75ead BP	354	struct chip_select csels[2];
cfe40fdb	355
7f19bf75 BP	356	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
7f19bf75 BP	357	struct dram_range ranges[DRAM_RANGES];
cfe40fdb	358
cfe40fdb DT	359	u64 top_mem; /* top of memory below 4GB */
	360	u64 top_mem2; /* top of memory above 4GB */
	361
78da121e BP	362	u32 dct_sel_lo; /* DRAM Controller Select Low */
78da121e BP	363	u32 dct_sel_hi; /* DRAM Controller Select High */
b2b0c605	364	u32 online_spare; /* On-Line spare Reg */
cfe40fdb	365
ad6a32e9 BP	366	/* x4 or x8 syndromes in use */
	367	u8 syn_type;
	368
cfe40fdb DT	369	/* place to store error injection parameters prior to issue */
	370	struct error_injection injection;
	371
395ae783 BP	372	/* DCT per-family scrubrate setting */
	373	u32 min_scrubrate;
	374
0092b20d BP	375	/* family name this instance is running on */
	376	const char *ctl_name;
	377
ae7bb7c6 BP	378	};
ae7bb7c6 BP	379
7f19bf75 BP	380	static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)
	381	{
	382	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
	383
	384	if (boot_cpu_data.x86 == 0xf)
	385	return addr;
	386
	387	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) \| addr;
	388	}
	389
	390	static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i)
	391	{
	392	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) \| 0x00ffffff;
	393
	394	if (boot_cpu_data.x86 == 0xf)
	395	return lim;
	396
	397	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) \| lim;
	398	}
	399
f192c7b1 BP	400	static inline u16 extract_syndrome(u64 status)
	401	{
	402	return ((status >> 47) & 0xff) \| ((status >> 16) & 0xff00);
	403	}
	404
ae7bb7c6 BP	405	/*
	406	* per-node ECC settings descriptor
	407	*/
	408	struct ecc_settings {
	409	u32 old_nbctl;
	410	bool nbctl_valid;
	411
cfe40fdb	412	struct flags {
d95cf4de BP	413	unsigned long nb_mce_enable:1;
d95cf4de BP	414	unsigned long nb_ecc_prev:1;
cfe40fdb DT	415	} flags;
	416	};
	417
cfe40fdb DT	418	extern const char *tt_msgs[4];
	419	extern const char *ll_msgs[4];
	420	extern const char *rrrr_msgs[16];
	421	extern const char *to_msgs[2];
	422	extern const char *pp_msgs[4];
	423	extern const char *ii_msgs[4];
cfe40fdb DT	424	extern const char *htlink_msgs[8];
cfe40fdb DT	425
7d6034d3	426	#ifdef CONFIG_EDAC_DEBUG
9cdeb404	427	#define NUM_DBG_ATTRS 5
7d6034d3 DT	428	#else
	429	#define NUM_DBG_ATTRS 0
	430	#endif
	431
	432	#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
	433	#define NUM_INJ_ATTRS 5
	434	#else
	435	#define NUM_INJ_ATTRS 0
	436	#endif
	437
	438	extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
	439	amd64_inj_attrs[NUM_INJ_ATTRS];
	440
cfe40fdb DT	441	/*
	442	* Each of the PCI Device IDs types have their own set of hardware accessor
	443	* functions and per device encoding/decoding logic.
	444	*/
	445	struct low_ops {
1433eb99	446	int (early_channel_count) (struct amd64_pvt pvt);
1433eb99	447	void (read_dram_ctl_register) (struct amd64_pvt pvt);
f192c7b1 BP	448	void (map_sysaddr_to_csrow) (struct mem_ctl_info mci, u64 sys_addr,
f192c7b1 BP	449	u16 syndrome);
1433eb99	450	int (dbam_to_cs) (struct amd64_pvt pvt, int cs_mode);
b2b0c605 BP	451	int (read_dct_pci_cfg) (struct amd64_pvt pvt, int offset,
b2b0c605 BP	452	u32 val, const char func);
cfe40fdb DT	453	};
	454
	455	struct amd64_family_type {
	456	const char *ctl_name;
8d5b5d9c	457	u16 f1_id, f3_id;
cfe40fdb DT	458	struct low_ops ops;
	459	};
	460
b2b0c605 BP	461	int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
b2b0c605 BP	462	u32 val, const char *func);
6ba5dcdc	463
b2b0c605 BP	464	#define amd64_read_pci_cfg(pdev, offset, val) \
b2b0c605 BP	465	__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	466
b2b0c605 BP	467	#define amd64_write_pci_cfg(pdev, offset, val) \
b2b0c605 BP	468	__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
6ba5dcdc	469
b2b0c605 BP	470	#define amd64_read_dct_pci_cfg(pvt, offset, val) \
b2b0c605 BP	471	pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)
6ba5dcdc	472
cfe40fdb DT	473	/*
	474	* For future CPU versions, verify the following as new 'slow' rates appear and
	475	* modify the necessary skip values for the supported CPU.
	476	*/
	477	#define K8_MIN_SCRUB_RATE_BITS 0x0
	478	#define F10_MIN_SCRUB_RATE_BITS 0x5
cfe40fdb	479
cfe40fdb DT	480	int amd64_get_dram_hole_info(struct mem_ctl_info mci, u64 hole_base,
cfe40fdb DT	481	u64 hole_offset, u64 hole_size);