[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / ste_dma40_ll.c

/*
 * Copyright (C) ST-Ericsson SA 2007-2010
 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 */

#include <linux/kernel.h>
#include <linux/platform_data/dma-ste-dma40.h>

#include "ste_dma40_ll.h"

/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
void d40_log_cfg(struct stedma40_chan_cfg *cfg,
		 u32 *lcsp1, u32 *lcsp3)
{
	u32 l3 = 0; /* dst */
	u32 l1 = 0; /* src */

	/* src is mem? -> increase address pos */
	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
		l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;

	/* dst is mem? -> increase address pos */
	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
		l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;

	/* src is hw? -> master port 1 */
	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
		l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;

	/* dst is hw? -> master port 1 */
	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
		l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;

	l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
	l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
	l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;

	l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
	l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
	l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;

	*lcsp1 = l1;
	*lcsp3 = l3;

}

/* Sets up SRC and DST CFG register for both logical and physical channels */
void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
		 u32 *src_cfg, u32 *dst_cfg, bool is_log)
{
	u32 src = 0;
	u32 dst = 0;

	if (!is_log) {
		/* Physical channel */
		if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
			/* Set master port to 1 */
			src |= 1 << D40_SREG_CFG_MST_POS;
			src |= D40_TYPE_TO_EVENT(cfg->src_dev_type);

			if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
				src |= 1 << D40_SREG_CFG_PHY_TM_POS;
			else
				src |= 3 << D40_SREG_CFG_PHY_TM_POS;
		}
		if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
			/* Set master port to 1 */
			dst |= 1 << D40_SREG_CFG_MST_POS;
			dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type);

			if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
				dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
			else
				dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
		}
		/* Interrupt on end of transfer for destination */
		dst |= 1 << D40_SREG_CFG_TIM_POS;

		/* Generate interrupt on error */
		src |= 1 << D40_SREG_CFG_EIM_POS;
		dst |= 1 << D40_SREG_CFG_EIM_POS;

		/* PSIZE */
		if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
			src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
			src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
		}
		if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
			dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
			dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
		}

		/* Element size */
		src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
		dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;

		/* Set the priority bit to high for the physical channel */
		if (cfg->high_priority) {
			src |= 1 << D40_SREG_CFG_PRI_POS;
			dst |= 1 << D40_SREG_CFG_PRI_POS;
		}

	} else {
		/* Logical channel */
		dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
		src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
	}

	if (cfg->src_info.big_endian)
		src |= 1 << D40_SREG_CFG_LBE_POS;
	if (cfg->dst_info.big_endian)
		dst |= 1 << D40_SREG_CFG_LBE_POS;

	*src_cfg = src;
	*dst_cfg = dst;
}

static int d40_phy_fill_lli(struct d40_phy_lli *lli,
			    dma_addr_t data,
			    u32 data_size,
			    dma_addr_t next_lli,
			    u32 reg_cfg,
			    struct stedma40_half_channel_info *info,
			    unsigned int flags)
{
	bool addr_inc = flags & LLI_ADDR_INC;
	bool term_int = flags & LLI_TERM_INT;
	unsigned int data_width = info->data_width;
	int psize = info->psize;
	int num_elems;

	if (psize == STEDMA40_PSIZE_PHY_1)
		num_elems = 1;
	else
		num_elems = 2 << psize;

	/* Must be aligned */
	if (!IS_ALIGNED(data, 0x1 << data_width))
		return -EINVAL;

	/* Transfer size can't be smaller than (num_elms * elem_size) */
	if (data_size < num_elems * (0x1 << data_width))
		return -EINVAL;

	/* The number of elements. IE now many chunks */
	lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;

	/*
	 * Distance to next element sized entry.
	 * Usually the size of the element unless you want gaps.
	 */
	if (addr_inc)
		lli->reg_elt |= (0x1 << data_width) <<
			D40_SREG_ELEM_PHY_EIDX_POS;

	/* Where the data is */
	lli->reg_ptr = data;
	lli->reg_cfg = reg_cfg;

	/* If this scatter list entry is the last one, no next link */
	if (next_lli == 0)
		lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
	else
		lli->reg_lnk = next_lli;

	/* Set/clear interrupt generation on this link item.*/
	if (term_int)
		lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
	else
		lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);

	/* Post link */
	lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;

	return 0;
}

static int d40_seg_size(int size, int data_width1, int data_width2)
{
	u32 max_w = max(data_width1, data_width2);
	u32 min_w = min(data_width1, data_width2);
	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);

	if (seg_max > STEDMA40_MAX_SEG_SIZE)
		seg_max -= (1 << max_w);

	if (size <= seg_max)
		return size;

	if (size <= 2 * seg_max)
		return ALIGN(size / 2, 1 << max_w);

	return seg_max;
}

static struct d40_phy_lli *
d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
		   dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
		   struct stedma40_half_channel_info *info,
		   struct stedma40_half_channel_info *otherinfo,
		   unsigned long flags)
{
	bool lastlink = flags & LLI_LAST_LINK;
	bool addr_inc = flags & LLI_ADDR_INC;
	bool term_int = flags & LLI_TERM_INT;
	bool cyclic = flags & LLI_CYCLIC;
	int err;
	dma_addr_t next = lli_phys;
	int size_rest = size;
	int size_seg = 0;

	/*
	 * This piece may be split up based on d40_seg_size(); we only want the
	 * term int on the last part.
	 */
	if (term_int)
		flags &= ~LLI_TERM_INT;

	do {
		size_seg = d40_seg_size(size_rest, info->data_width,
					otherinfo->data_width);
		size_rest -= size_seg;

		if (size_rest == 0 && term_int)
			flags |= LLI_TERM_INT;

		if (size_rest == 0 && lastlink)
			next = cyclic ? first_phys : 0;
		else
			next = ALIGN(next + sizeof(struct d40_phy_lli),
				     D40_LLI_ALIGN);

		err = d40_phy_fill_lli(lli, addr, size_seg, next,
				       reg_cfg, info, flags);

		if (err)
			goto err;

		lli++;
		if (addr_inc)
			addr += size_seg;
	} while (size_rest);

	return lli;

err:
	return NULL;
}

int d40_phy_sg_to_lli(struct scatterlist *sg,
		      int sg_len,
		      dma_addr_t target,
		      struct d40_phy_lli *lli_sg,
		      dma_addr_t lli_phys,
		      u32 reg_cfg,
		      struct stedma40_half_channel_info *info,
		      struct stedma40_half_channel_info *otherinfo,
		      unsigned long flags)
{
	int total_size = 0;
	int i;
	struct scatterlist *current_sg = sg;
	struct d40_phy_lli *lli = lli_sg;
	dma_addr_t l_phys = lli_phys;

	if (!target)
		flags |= LLI_ADDR_INC;

	for_each_sg(sg, current_sg, sg_len, i) {
		dma_addr_t sg_addr = sg_dma_address(current_sg);
		unsigned int len = sg_dma_len(current_sg);
		dma_addr_t dst = target ?: sg_addr;

		total_size += sg_dma_len(current_sg);

		if (i == sg_len - 1)
			flags |= LLI_TERM_INT | LLI_LAST_LINK;

		l_phys = ALIGN(lli_phys + (lli - lli_sg) *
			       sizeof(struct d40_phy_lli), D40_LLI_ALIGN);

		lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
					 reg_cfg, info, otherinfo, flags);

		if (lli == NULL)
			return -EINVAL;
	}

	return total_size;
}


/* DMA logical lli operations */

static void d40_log_lli_link(struct d40_log_lli *lli_dst,
			     struct d40_log_lli *lli_src,
			     int next, unsigned int flags)
{
	bool interrupt = flags & LLI_TERM_INT;
	u32 slos = 0;
	u32 dlos = 0;

	if (next != -EINVAL) {
		slos = next * 2;
		dlos = next * 2 + 1;
	}

	if (interrupt) {
		lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
		lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
	}

	lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
		(slos << D40_MEM_LCSP1_SLOS_POS);

	lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
		(dlos << D40_MEM_LCSP1_SLOS_POS);
}

void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
			   struct d40_log_lli *lli_dst,
			   struct d40_log_lli *lli_src,
			   int next, unsigned int flags)
{
	d40_log_lli_link(lli_dst, lli_src, next, flags);

	writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
	writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
	writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
	writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
}

void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
			   struct d40_log_lli *lli_dst,
			   struct d40_log_lli *lli_src,
			   int next, unsigned int flags)
{
	d40_log_lli_link(lli_dst, lli_src, next, flags);

	writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
	writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
	writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
	writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
}

static void d40_log_fill_lli(struct d40_log_lli *lli,
			     dma_addr_t data, u32 data_size,
			     u32 reg_cfg,
			     u32 data_width,
			     unsigned int flags)
{
	bool addr_inc = flags & LLI_ADDR_INC;

	lli->lcsp13 = reg_cfg;

	/* The number of elements to transfer */
	lli->lcsp02 = ((data_size >> data_width) <<
		       D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;

	BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);

	/* 16 LSBs address of the current element */
	lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
	/* 16 MSBs address of the current element */
	lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;

	if (addr_inc)
		lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;

}

static struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
				       dma_addr_t addr,
				       int size,
				       u32 lcsp13, /* src or dst*/
				       u32 data_width1,
				       u32 data_width2,
				       unsigned int flags)
{
	bool addr_inc = flags & LLI_ADDR_INC;
	struct d40_log_lli *lli = lli_sg;
	int size_rest = size;
	int size_seg = 0;

	do {
		size_seg = d40_seg_size(size_rest, data_width1, data_width2);
		size_rest -= size_seg;

		d40_log_fill_lli(lli,
				 addr,
				 size_seg,
				 lcsp13, data_width1,
				 flags);
		if (addr_inc)
			addr += size_seg;
		lli++;
	} while (size_rest);

	return lli;
}

int d40_log_sg_to_lli(struct scatterlist *sg,
		      int sg_len,
		      dma_addr_t dev_addr,
		      struct d40_log_lli *lli_sg,
		      u32 lcsp13, /* src or dst*/
		      u32 data_width1, u32 data_width2)
{
	int total_size = 0;
	struct scatterlist *current_sg = sg;
	int i;
	struct d40_log_lli *lli = lli_sg;
	unsigned long flags = 0;

	if (!dev_addr)
		flags |= LLI_ADDR_INC;

	for_each_sg(sg, current_sg, sg_len, i) {
		dma_addr_t sg_addr = sg_dma_address(current_sg);
		unsigned int len = sg_dma_len(current_sg);
		dma_addr_t addr = dev_addr ?: sg_addr;

		total_size += sg_dma_len(current_sg);

		lli = d40_log_buf_to_lli(lli, addr, len,
					 lcsp13,
					 data_width1,
					 data_width2,
					 flags);
	}

	return total_size;
}
Commit	Line	Data
8d318a50	1	/*
767a9675	2	* Copyright (C) ST-Ericsson SA 2007-2010
d49278e3	3	* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675	4	* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50	5	* License terms: GNU General Public License (GPL) version 2
8d318a50 LW	6	*/
	7
	8	#include <linux/kernel.h>
865fab60	9	#include <linux/platform_data/dma-ste-dma40.h>
8d318a50 LW	10
	11	#include "ste_dma40_ll.h"
	12
	13	/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
	14	void d40_log_cfg(struct stedma40_chan_cfg *cfg,
	15	u32 lcsp1, u32 lcsp3)
	16	{
	17	u32 l3 = 0; /* dst */
	18	u32 l1 = 0; /* src */
	19
	20	/* src is mem? -> increase address pos */
	21	if (cfg->dir == STEDMA40_MEM_TO_PERIPH \|\|
	22	cfg->dir == STEDMA40_MEM_TO_MEM)
	23	l1 \|= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
	24
	25	/* dst is mem? -> increase address pos */
	26	if (cfg->dir == STEDMA40_PERIPH_TO_MEM \|\|
	27	cfg->dir == STEDMA40_MEM_TO_MEM)
	28	l3 \|= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
	29
	30	/* src is hw? -> master port 1 */
	31	if (cfg->dir == STEDMA40_PERIPH_TO_MEM \|\|
	32	cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
	33	l1 \|= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
	34
	35	/* dst is hw? -> master port 1 */
	36	if (cfg->dir == STEDMA40_MEM_TO_PERIPH \|\|
	37	cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
	38	l3 \|= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
	39
8d318a50 LW	40	l3 \|= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
	41	l3 \|= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
	42	l3 \|= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
8d318a50 LW	43
	44	l1 \|= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
	45	l1 \|= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
	46	l1 \|= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
8d318a50 LW	47
	48	*lcsp1 = l1;
	49	*lcsp3 = l3;
	50
	51	}
	52
	53	/* Sets up SRC and DST CFG register for both logical and physical channels */
	54	void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
	55	u32 src_cfg, u32 dst_cfg, bool is_log)
	56	{
	57	u32 src = 0;
	58	u32 dst = 0;
	59
	60	if (!is_log) {
	61	/* Physical channel */
	62	if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) \|\|
	63	(cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
	64	/* Set master port to 1 */
	65	src \|= 1 << D40_SREG_CFG_MST_POS;
	66	src \|= D40_TYPE_TO_EVENT(cfg->src_dev_type);
	67
	68	if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
	69	src \|= 1 << D40_SREG_CFG_PHY_TM_POS;
	70	else
	71	src \|= 3 << D40_SREG_CFG_PHY_TM_POS;
	72	}
	73	if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) \|\|
	74	(cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
	75	/* Set master port to 1 */
	76	dst \|= 1 << D40_SREG_CFG_MST_POS;
	77	dst \|= D40_TYPE_TO_EVENT(cfg->dst_dev_type);
	78
	79	if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
	80	dst \|= 1 << D40_SREG_CFG_PHY_TM_POS;
	81	else
	82	dst \|= 3 << D40_SREG_CFG_PHY_TM_POS;
	83	}
	84	/* Interrupt on end of transfer for destination */
	85	dst \|= 1 << D40_SREG_CFG_TIM_POS;
	86
	87	/* Generate interrupt on error */
	88	src \|= 1 << D40_SREG_CFG_EIM_POS;
	89	dst \|= 1 << D40_SREG_CFG_EIM_POS;
	90
	91	/* PSIZE */
	92	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
	93	src \|= 1 << D40_SREG_CFG_PHY_PEN_POS;
	94	src \|= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
	95	}
	96	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
	97	dst \|= 1 << D40_SREG_CFG_PHY_PEN_POS;
	98	dst \|= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
	99	}
	100
	101	/* Element size */
	102	src \|= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
	103	dst \|= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
	104
0fd60223 N	105	/* Set the priority bit to high for the physical channel */
	106	if (cfg->high_priority) {
	107	src \|= 1 << D40_SREG_CFG_PRI_POS;
	108	dst \|= 1 << D40_SREG_CFG_PRI_POS;
	109	}
	110
8d318a50 LW	111	} else {
	112	/* Logical channel */
	113	dst \|= 1 << D40_SREG_CFG_LOG_GIM_POS;
	114	src \|= 1 << D40_SREG_CFG_LOG_GIM_POS;
	115	}
	116
51f5d744 RV	117	if (cfg->src_info.big_endian)
	118	src \|= 1 << D40_SREG_CFG_LBE_POS;
	119	if (cfg->dst_info.big_endian)
	120	dst \|= 1 << D40_SREG_CFG_LBE_POS;
8d318a50 LW	121
	122	*src_cfg = src;
	123	*dst_cfg = dst;
	124	}
	125
d49278e3 PF	126	static int d40_phy_fill_lli(struct d40_phy_lli *lli,
	127	dma_addr_t data,
	128	u32 data_size,
d49278e3 PF	129	dma_addr_t next_lli,
d49278e3 PF	130	u32 reg_cfg,
7f933bed RV	131	struct stedma40_half_channel_info *info,
7f933bed RV	132	unsigned int flags)
8d318a50	133	{
7f933bed RV	134	bool addr_inc = flags & LLI_ADDR_INC;
7f933bed RV	135	bool term_int = flags & LLI_TERM_INT;
cc31b6f7 RV	136	unsigned int data_width = info->data_width;
cc31b6f7 RV	137	int psize = info->psize;
8d318a50 LW	138	int num_elems;
	139
	140	if (psize == STEDMA40_PSIZE_PHY_1)
	141	num_elems = 1;
	142	else
	143	num_elems = 2 << psize;
	144
8d318a50 LW	145	/* Must be aligned */
	146	if (!IS_ALIGNED(data, 0x1 << data_width))
	147	return -EINVAL;
	148
	149	/* Transfer size can't be smaller than (num_elms * elem_size) */
	150	if (data_size < num_elems * (0x1 << data_width))
	151	return -EINVAL;
	152
	153	/* The number of elements. IE now many chunks */
	154	lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
	155
	156	/*
	157	* Distance to next element sized entry.
	158	* Usually the size of the element unless you want gaps.
	159	*/
7f933bed	160	if (addr_inc)
8d318a50 LW	161	lli->reg_elt \|= (0x1 << data_width) <<
	162	D40_SREG_ELEM_PHY_EIDX_POS;
	163
	164	/* Where the data is */
	165	lli->reg_ptr = data;
	166	lli->reg_cfg = reg_cfg;
	167
	168	/* If this scatter list entry is the last one, no next link */
	169	if (next_lli == 0)
	170	lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
	171	else
	172	lli->reg_lnk = next_lli;
	173
	174	/* Set/clear interrupt generation on this link item.*/
	175	if (term_int)
	176	lli->reg_cfg \|= 0x1 << D40_SREG_CFG_TIM_POS;
	177	else
	178	lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
	179
	180	/* Post link */
	181	lli->reg_lnk \|= 0 << D40_SREG_LNK_PHY_PRE_POS;
	182
	183	return 0;
	184	}
	185
d49278e3 PF	186	static int d40_seg_size(int size, int data_width1, int data_width2)
	187	{
	188	u32 max_w = max(data_width1, data_width2);
	189	u32 min_w = min(data_width1, data_width2);
	190	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
	191
	192	if (seg_max > STEDMA40_MAX_SEG_SIZE)
	193	seg_max -= (1 << max_w);
	194
	195	if (size <= seg_max)
	196	return size;
	197
	198	if (size <= 2 * seg_max)
	199	return ALIGN(size / 2, 1 << max_w);
	200
	201	return seg_max;
	202	}
	203
cc31b6f7 RV	204	static struct d40_phy_lli *
cc31b6f7 RV	205	d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
0c842b55	206	dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
7f933bed RV	207	struct stedma40_half_channel_info *info,
	208	struct stedma40_half_channel_info *otherinfo,
	209	unsigned long flags)
d49278e3	210	{
0c842b55	211	bool lastlink = flags & LLI_LAST_LINK;
7f933bed RV	212	bool addr_inc = flags & LLI_ADDR_INC;
7f933bed RV	213	bool term_int = flags & LLI_TERM_INT;
0c842b55	214	bool cyclic = flags & LLI_CYCLIC;
d49278e3 PF	215	int err;
	216	dma_addr_t next = lli_phys;
	217	int size_rest = size;
	218	int size_seg = 0;
	219
7f933bed RV	220	/*
	221	* This piece may be split up based on d40_seg_size(); we only want the
	222	* term int on the last part.
	223	*/
	224	if (term_int)
	225	flags &= ~LLI_TERM_INT;
	226
d49278e3	227	do {
cc31b6f7 RV	228	size_seg = d40_seg_size(size_rest, info->data_width,
cc31b6f7 RV	229	otherinfo->data_width);
d49278e3 PF	230	size_rest -= size_seg;
d49278e3 PF	231
0c842b55	232	if (size_rest == 0 && term_int)
7f933bed	233	flags \|= LLI_TERM_INT;
0c842b55 RV	234
	235	if (size_rest == 0 && lastlink)
	236	next = cyclic ? first_phys : 0;
	237	else
d49278e3 PF	238	next = ALIGN(next + sizeof(struct d40_phy_lli),
	239	D40_LLI_ALIGN);
	240
7f933bed RV	241	err = d40_phy_fill_lli(lli, addr, size_seg, next,
7f933bed RV	242	reg_cfg, info, flags);
d49278e3 PF	243
	244	if (err)
	245	goto err;
	246
	247	lli++;
7f933bed	248	if (addr_inc)
d49278e3 PF	249	addr += size_seg;
	250	} while (size_rest);
	251
	252	return lli;
	253
f26e03ad	254	err:
d49278e3 PF	255	return NULL;
	256	}
	257
8d318a50 LW	258	int d40_phy_sg_to_lli(struct scatterlist *sg,
	259	int sg_len,
	260	dma_addr_t target,
d49278e3	261	struct d40_phy_lli *lli_sg,
8d318a50 LW	262	dma_addr_t lli_phys,
8d318a50 LW	263	u32 reg_cfg,
cc31b6f7	264	struct stedma40_half_channel_info *info,
0c842b55 RV	265	struct stedma40_half_channel_info *otherinfo,
0c842b55 RV	266	unsigned long flags)
8d318a50 LW	267	{
	268	int total_size = 0;
	269	int i;
	270	struct scatterlist *current_sg = sg;
d49278e3 PF	271	struct d40_phy_lli *lli = lli_sg;
d49278e3 PF	272	dma_addr_t l_phys = lli_phys;
7f933bed RV	273
	274	if (!target)
	275	flags \|= LLI_ADDR_INC;
8d318a50 LW	276
8d318a50 LW	277	for_each_sg(sg, current_sg, sg_len, i) {
7f933bed RV	278	dma_addr_t sg_addr = sg_dma_address(current_sg);
	279	unsigned int len = sg_dma_len(current_sg);
	280	dma_addr_t dst = target ?: sg_addr;
8d318a50 LW	281
	282	total_size += sg_dma_len(current_sg);
	283
7f933bed	284	if (i == sg_len - 1)
0c842b55	285	flags \|= LLI_TERM_INT \| LLI_LAST_LINK;
8d318a50	286
d49278e3 PF	287	l_phys = ALIGN(lli_phys + (lli - lli_sg) *
	288	sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
	289
0c842b55	290	lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
7f933bed RV	291	reg_cfg, info, otherinfo, flags);
7f933bed RV	292
d49278e3 PF	293	if (lli == NULL)
d49278e3 PF	294	return -EINVAL;
8d318a50 LW	295	}
	296
	297	return total_size;
8d318a50 LW	298	}
	299
	300
8d318a50 LW	301	/* DMA logical lli operations */
8d318a50 LW	302
698e4732 JA	303	static void d40_log_lli_link(struct d40_log_lli *lli_dst,
698e4732 JA	304	struct d40_log_lli *lli_src,
0c842b55	305	int next, unsigned int flags)
698e4732	306	{
0c842b55	307	bool interrupt = flags & LLI_TERM_INT;
698e4732 JA	308	u32 slos = 0;
	309	u32 dlos = 0;
	310
	311	if (next != -EINVAL) {
	312	slos = next * 2;
	313	dlos = next * 2 + 1;
0c842b55 RV	314	}
	315
	316	if (interrupt) {
698e4732 JA	317	lli_dst->lcsp13 \|= D40_MEM_LCSP1_SCFG_TIM_MASK;
	318	lli_dst->lcsp13 \|= D40_MEM_LCSP3_DTCP_MASK;
	319	}
	320
	321	lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) \|
	322	(slos << D40_MEM_LCSP1_SLOS_POS);
	323
	324	lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) \|
	325	(dlos << D40_MEM_LCSP1_SLOS_POS);
	326	}
	327
	328	void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
	329	struct d40_log_lli *lli_dst,
	330	struct d40_log_lli *lli_src,
0c842b55	331	int next, unsigned int flags)
698e4732	332	{
0c842b55	333	d40_log_lli_link(lli_dst, lli_src, next, flags);
698e4732	334
8a5d2039 PF	335	writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
	336	writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
	337	writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
	338	writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
698e4732 JA	339	}
	340
	341	void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
	342	struct d40_log_lli *lli_dst,
	343	struct d40_log_lli *lli_src,
0c842b55	344	int next, unsigned int flags)
698e4732	345	{
0c842b55	346	d40_log_lli_link(lli_dst, lli_src, next, flags);
698e4732	347
8a5d2039 PF	348	writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
	349	writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
	350	writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
	351	writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
698e4732 JA	352	}
698e4732 JA	353
d49278e3 PF	354	static void d40_log_fill_lli(struct d40_log_lli *lli,
	355	dma_addr_t data, u32 data_size,
	356	u32 reg_cfg,
	357	u32 data_width,
7f933bed	358	unsigned int flags)
8d318a50	359	{
7f933bed RV	360	bool addr_inc = flags & LLI_ADDR_INC;
7f933bed RV	361
8d318a50 LW	362	lli->lcsp13 = reg_cfg;
	363
	364	/* The number of elements to transfer */
	365	lli->lcsp02 = ((data_size >> data_width) <<
	366	D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
d49278e3 PF	367
	368	BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);
	369
8d318a50 LW	370	/* 16 LSBs address of the current element */
	371	lli->lcsp02 \|= data & D40_MEM_LCSP0_SPTR_MASK;
	372	/* 16 MSBs address of the current element */
	373	lli->lcsp13 \|= data & D40_MEM_LCSP1_SPTR_MASK;
	374
	375	if (addr_inc)
	376	lli->lcsp13 \|= D40_MEM_LCSP1_SCFG_INCR_MASK;
	377
8d318a50 LW	378	}
8d318a50 LW	379
1f7622ca	380	static struct d40_log_lli d40_log_buf_to_lli(struct d40_log_lli lli_sg,
d49278e3 PF	381	dma_addr_t addr,
	382	int size,
	383	u32 lcsp13, /* src or dst*/
	384	u32 data_width1,
	385	u32 data_width2,
7f933bed	386	unsigned int flags)
d49278e3	387	{
7f933bed	388	bool addr_inc = flags & LLI_ADDR_INC;
d49278e3 PF	389	struct d40_log_lli *lli = lli_sg;
	390	int size_rest = size;
	391	int size_seg = 0;
	392
	393	do {
	394	size_seg = d40_seg_size(size_rest, data_width1, data_width2);
	395	size_rest -= size_seg;
	396
	397	d40_log_fill_lli(lli,
	398	addr,
	399	size_seg,
	400	lcsp13, data_width1,
7f933bed	401	flags);
d49278e3 PF	402	if (addr_inc)
	403	addr += size_seg;
	404	lli++;
	405	} while (size_rest);
	406
	407	return lli;
	408	}
	409
698e4732	410	int d40_log_sg_to_lli(struct scatterlist *sg,
8d318a50	411	int sg_len,
5ed04b85	412	dma_addr_t dev_addr,
8d318a50 LW	413	struct d40_log_lli *lli_sg,
8d318a50 LW	414	u32 lcsp13, /* src or dst*/
d49278e3	415	u32 data_width1, u32 data_width2)
8d318a50 LW	416	{
	417	int total_size = 0;
	418	struct scatterlist *current_sg = sg;
	419	int i;
d49278e3	420	struct d40_log_lli *lli = lli_sg;
7f933bed RV	421	unsigned long flags = 0;
	422
	423	if (!dev_addr)
	424	flags \|= LLI_ADDR_INC;
8d318a50 LW	425
8d318a50 LW	426	for_each_sg(sg, current_sg, sg_len, i) {
5ed04b85 RV	427	dma_addr_t sg_addr = sg_dma_address(current_sg);
	428	unsigned int len = sg_dma_len(current_sg);
	429	dma_addr_t addr = dev_addr ?: sg_addr;
	430
8d318a50	431	total_size += sg_dma_len(current_sg);
5ed04b85 RV	432
5ed04b85 RV	433	lli = d40_log_buf_to_lli(lli, addr, len,
d49278e3	434	lcsp13,
5ed04b85 RV	435	data_width1,
5ed04b85 RV	436	data_width2,
7f933bed	437	flags);
8d318a50	438	}
5ed04b85	439
8d318a50 LW	440	return total_size;
8d318a50 LW	441	}