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b3040e40 JB |
1 | /* linux/drivers/dma/pl330.c |
2 | * | |
3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
4 | * Jaswinder Singh <jassi.brar@samsung.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/io.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/amba/bus.h> | |
19 | #include <linux/amba/pl330.h> | |
a2f5203f | 20 | #include <linux/pm_runtime.h> |
1b9bb715 | 21 | #include <linux/scatterlist.h> |
93ed5544 | 22 | #include <linux/of.h> |
b3040e40 | 23 | |
d2ebfb33 RKAL |
24 | #include "dmaengine.h" |
25 | ||
b3040e40 JB |
26 | #define NR_DEFAULT_DESC 16 |
27 | ||
28 | enum desc_status { | |
29 | /* In the DMAC pool */ | |
30 | FREE, | |
31 | /* | |
32 | * Allocted to some channel during prep_xxx | |
33 | * Also may be sitting on the work_list. | |
34 | */ | |
35 | PREP, | |
36 | /* | |
37 | * Sitting on the work_list and already submitted | |
38 | * to the PL330 core. Not more than two descriptors | |
39 | * of a channel can be BUSY at any time. | |
40 | */ | |
41 | BUSY, | |
42 | /* | |
43 | * Sitting on the channel work_list but xfer done | |
44 | * by PL330 core | |
45 | */ | |
46 | DONE, | |
47 | }; | |
48 | ||
49 | struct dma_pl330_chan { | |
50 | /* Schedule desc completion */ | |
51 | struct tasklet_struct task; | |
52 | ||
53 | /* DMA-Engine Channel */ | |
54 | struct dma_chan chan; | |
55 | ||
b3040e40 JB |
56 | /* List of to be xfered descriptors */ |
57 | struct list_head work_list; | |
58 | ||
59 | /* Pointer to the DMAC that manages this channel, | |
60 | * NULL if the channel is available to be acquired. | |
61 | * As the parent, this DMAC also provides descriptors | |
62 | * to the channel. | |
63 | */ | |
64 | struct dma_pl330_dmac *dmac; | |
65 | ||
66 | /* To protect channel manipulation */ | |
67 | spinlock_t lock; | |
68 | ||
69 | /* Token of a hardware channel thread of PL330 DMAC | |
70 | * NULL if the channel is available to be acquired. | |
71 | */ | |
72 | void *pl330_chid; | |
1b9bb715 BK |
73 | |
74 | /* For D-to-M and M-to-D channels */ | |
75 | int burst_sz; /* the peripheral fifo width */ | |
1d0c1d60 | 76 | int burst_len; /* the number of burst */ |
1b9bb715 | 77 | dma_addr_t fifo_addr; |
42bc9cf4 BK |
78 | |
79 | /* for cyclic capability */ | |
80 | bool cyclic; | |
b3040e40 JB |
81 | }; |
82 | ||
83 | struct dma_pl330_dmac { | |
84 | struct pl330_info pif; | |
85 | ||
86 | /* DMA-Engine Device */ | |
87 | struct dma_device ddma; | |
88 | ||
89 | /* Pool of descriptors available for the DMAC's channels */ | |
90 | struct list_head desc_pool; | |
91 | /* To protect desc_pool manipulation */ | |
92 | spinlock_t pool_lock; | |
93 | ||
94 | /* Peripheral channels connected to this DMAC */ | |
4e0e6109 | 95 | struct dma_pl330_chan *peripherals; /* keep at end */ |
a2f5203f BK |
96 | |
97 | struct clk *clk; | |
b3040e40 JB |
98 | }; |
99 | ||
100 | struct dma_pl330_desc { | |
101 | /* To attach to a queue as child */ | |
102 | struct list_head node; | |
103 | ||
104 | /* Descriptor for the DMA Engine API */ | |
105 | struct dma_async_tx_descriptor txd; | |
106 | ||
107 | /* Xfer for PL330 core */ | |
108 | struct pl330_xfer px; | |
109 | ||
110 | struct pl330_reqcfg rqcfg; | |
111 | struct pl330_req req; | |
112 | ||
113 | enum desc_status status; | |
114 | ||
115 | /* The channel which currently holds this desc */ | |
116 | struct dma_pl330_chan *pchan; | |
117 | }; | |
118 | ||
3e2ec13a TA |
119 | /* forward declaration */ |
120 | static struct amba_driver pl330_driver; | |
121 | ||
b3040e40 JB |
122 | static inline struct dma_pl330_chan * |
123 | to_pchan(struct dma_chan *ch) | |
124 | { | |
125 | if (!ch) | |
126 | return NULL; | |
127 | ||
128 | return container_of(ch, struct dma_pl330_chan, chan); | |
129 | } | |
130 | ||
131 | static inline struct dma_pl330_desc * | |
132 | to_desc(struct dma_async_tx_descriptor *tx) | |
133 | { | |
134 | return container_of(tx, struct dma_pl330_desc, txd); | |
135 | } | |
136 | ||
137 | static inline void free_desc_list(struct list_head *list) | |
138 | { | |
139 | struct dma_pl330_dmac *pdmac; | |
140 | struct dma_pl330_desc *desc; | |
141 | struct dma_pl330_chan *pch; | |
142 | unsigned long flags; | |
143 | ||
144 | if (list_empty(list)) | |
145 | return; | |
146 | ||
147 | /* Finish off the work list */ | |
148 | list_for_each_entry(desc, list, node) { | |
149 | dma_async_tx_callback callback; | |
150 | void *param; | |
151 | ||
152 | /* All desc in a list belong to same channel */ | |
153 | pch = desc->pchan; | |
154 | callback = desc->txd.callback; | |
155 | param = desc->txd.callback_param; | |
156 | ||
157 | if (callback) | |
158 | callback(param); | |
159 | ||
160 | desc->pchan = NULL; | |
161 | } | |
162 | ||
163 | pdmac = pch->dmac; | |
164 | ||
165 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
166 | list_splice_tail_init(list, &pdmac->desc_pool); | |
167 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
168 | } | |
169 | ||
42bc9cf4 BK |
170 | static inline void handle_cyclic_desc_list(struct list_head *list) |
171 | { | |
172 | struct dma_pl330_desc *desc; | |
173 | struct dma_pl330_chan *pch; | |
174 | unsigned long flags; | |
175 | ||
176 | if (list_empty(list)) | |
177 | return; | |
178 | ||
179 | list_for_each_entry(desc, list, node) { | |
180 | dma_async_tx_callback callback; | |
181 | ||
182 | /* Change status to reload it */ | |
183 | desc->status = PREP; | |
184 | pch = desc->pchan; | |
185 | callback = desc->txd.callback; | |
186 | if (callback) | |
187 | callback(desc->txd.callback_param); | |
188 | } | |
189 | ||
190 | spin_lock_irqsave(&pch->lock, flags); | |
191 | list_splice_tail_init(list, &pch->work_list); | |
192 | spin_unlock_irqrestore(&pch->lock, flags); | |
193 | } | |
194 | ||
b3040e40 JB |
195 | static inline void fill_queue(struct dma_pl330_chan *pch) |
196 | { | |
197 | struct dma_pl330_desc *desc; | |
198 | int ret; | |
199 | ||
200 | list_for_each_entry(desc, &pch->work_list, node) { | |
201 | ||
202 | /* If already submitted */ | |
203 | if (desc->status == BUSY) | |
204 | break; | |
205 | ||
206 | ret = pl330_submit_req(pch->pl330_chid, | |
207 | &desc->req); | |
208 | if (!ret) { | |
209 | desc->status = BUSY; | |
210 | break; | |
211 | } else if (ret == -EAGAIN) { | |
212 | /* QFull or DMAC Dying */ | |
213 | break; | |
214 | } else { | |
215 | /* Unacceptable request */ | |
216 | desc->status = DONE; | |
217 | dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n", | |
218 | __func__, __LINE__, desc->txd.cookie); | |
219 | tasklet_schedule(&pch->task); | |
220 | } | |
221 | } | |
222 | } | |
223 | ||
224 | static void pl330_tasklet(unsigned long data) | |
225 | { | |
226 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; | |
227 | struct dma_pl330_desc *desc, *_dt; | |
228 | unsigned long flags; | |
229 | LIST_HEAD(list); | |
230 | ||
231 | spin_lock_irqsave(&pch->lock, flags); | |
232 | ||
233 | /* Pick up ripe tomatoes */ | |
234 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) | |
235 | if (desc->status == DONE) { | |
f7fbce07 | 236 | dma_cookie_complete(&desc->txd); |
b3040e40 JB |
237 | list_move_tail(&desc->node, &list); |
238 | } | |
239 | ||
240 | /* Try to submit a req imm. next to the last completed cookie */ | |
241 | fill_queue(pch); | |
242 | ||
243 | /* Make sure the PL330 Channel thread is active */ | |
244 | pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START); | |
245 | ||
246 | spin_unlock_irqrestore(&pch->lock, flags); | |
247 | ||
42bc9cf4 BK |
248 | if (pch->cyclic) |
249 | handle_cyclic_desc_list(&list); | |
250 | else | |
251 | free_desc_list(&list); | |
b3040e40 JB |
252 | } |
253 | ||
254 | static void dma_pl330_rqcb(void *token, enum pl330_op_err err) | |
255 | { | |
256 | struct dma_pl330_desc *desc = token; | |
257 | struct dma_pl330_chan *pch = desc->pchan; | |
258 | unsigned long flags; | |
259 | ||
260 | /* If desc aborted */ | |
261 | if (!pch) | |
262 | return; | |
263 | ||
264 | spin_lock_irqsave(&pch->lock, flags); | |
265 | ||
266 | desc->status = DONE; | |
267 | ||
268 | spin_unlock_irqrestore(&pch->lock, flags); | |
269 | ||
270 | tasklet_schedule(&pch->task); | |
271 | } | |
272 | ||
3e2ec13a TA |
273 | bool pl330_filter(struct dma_chan *chan, void *param) |
274 | { | |
cd072515 | 275 | u8 *peri_id; |
3e2ec13a TA |
276 | |
277 | if (chan->device->dev->driver != &pl330_driver.drv) | |
278 | return false; | |
279 | ||
93ed5544 TA |
280 | #ifdef CONFIG_OF |
281 | if (chan->device->dev->of_node) { | |
282 | const __be32 *prop_value; | |
283 | phandle phandle; | |
284 | struct device_node *node; | |
285 | ||
286 | prop_value = ((struct property *)param)->value; | |
287 | phandle = be32_to_cpup(prop_value++); | |
288 | node = of_find_node_by_phandle(phandle); | |
289 | return ((chan->private == node) && | |
290 | (chan->chan_id == be32_to_cpup(prop_value))); | |
291 | } | |
292 | #endif | |
293 | ||
cd072515 TA |
294 | peri_id = chan->private; |
295 | return *peri_id == (unsigned)param; | |
3e2ec13a TA |
296 | } |
297 | EXPORT_SYMBOL(pl330_filter); | |
298 | ||
b3040e40 JB |
299 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
300 | { | |
301 | struct dma_pl330_chan *pch = to_pchan(chan); | |
302 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
303 | unsigned long flags; | |
304 | ||
305 | spin_lock_irqsave(&pch->lock, flags); | |
306 | ||
4d4e58de | 307 | chan->completed_cookie = chan->cookie = 1; |
42bc9cf4 | 308 | pch->cyclic = false; |
b3040e40 JB |
309 | |
310 | pch->pl330_chid = pl330_request_channel(&pdmac->pif); | |
311 | if (!pch->pl330_chid) { | |
312 | spin_unlock_irqrestore(&pch->lock, flags); | |
313 | return 0; | |
314 | } | |
315 | ||
316 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); | |
317 | ||
318 | spin_unlock_irqrestore(&pch->lock, flags); | |
319 | ||
320 | return 1; | |
321 | } | |
322 | ||
323 | static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg) | |
324 | { | |
325 | struct dma_pl330_chan *pch = to_pchan(chan); | |
ae43b886 | 326 | struct dma_pl330_desc *desc, *_dt; |
b3040e40 | 327 | unsigned long flags; |
1d0c1d60 BK |
328 | struct dma_pl330_dmac *pdmac = pch->dmac; |
329 | struct dma_slave_config *slave_config; | |
ae43b886 | 330 | LIST_HEAD(list); |
b3040e40 | 331 | |
1d0c1d60 BK |
332 | switch (cmd) { |
333 | case DMA_TERMINATE_ALL: | |
334 | spin_lock_irqsave(&pch->lock, flags); | |
b3040e40 | 335 | |
1d0c1d60 BK |
336 | /* FLUSH the PL330 Channel thread */ |
337 | pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH); | |
b3040e40 | 338 | |
1d0c1d60 | 339 | /* Mark all desc done */ |
ae43b886 | 340 | list_for_each_entry_safe(desc, _dt, &pch->work_list , node) { |
1d0c1d60 | 341 | desc->status = DONE; |
ae43b886 BK |
342 | pch->completed = desc->txd.cookie; |
343 | list_move_tail(&desc->node, &list); | |
344 | } | |
b3040e40 | 345 | |
ae43b886 | 346 | list_splice_tail_init(&list, &pdmac->desc_pool); |
1d0c1d60 | 347 | spin_unlock_irqrestore(&pch->lock, flags); |
1d0c1d60 BK |
348 | break; |
349 | case DMA_SLAVE_CONFIG: | |
350 | slave_config = (struct dma_slave_config *)arg; | |
351 | ||
db8196df | 352 | if (slave_config->direction == DMA_MEM_TO_DEV) { |
1d0c1d60 BK |
353 | if (slave_config->dst_addr) |
354 | pch->fifo_addr = slave_config->dst_addr; | |
355 | if (slave_config->dst_addr_width) | |
356 | pch->burst_sz = __ffs(slave_config->dst_addr_width); | |
357 | if (slave_config->dst_maxburst) | |
358 | pch->burst_len = slave_config->dst_maxburst; | |
db8196df | 359 | } else if (slave_config->direction == DMA_DEV_TO_MEM) { |
1d0c1d60 BK |
360 | if (slave_config->src_addr) |
361 | pch->fifo_addr = slave_config->src_addr; | |
362 | if (slave_config->src_addr_width) | |
363 | pch->burst_sz = __ffs(slave_config->src_addr_width); | |
364 | if (slave_config->src_maxburst) | |
365 | pch->burst_len = slave_config->src_maxburst; | |
366 | } | |
367 | break; | |
368 | default: | |
369 | dev_err(pch->dmac->pif.dev, "Not supported command.\n"); | |
370 | return -ENXIO; | |
371 | } | |
b3040e40 JB |
372 | |
373 | return 0; | |
374 | } | |
375 | ||
376 | static void pl330_free_chan_resources(struct dma_chan *chan) | |
377 | { | |
378 | struct dma_pl330_chan *pch = to_pchan(chan); | |
379 | unsigned long flags; | |
380 | ||
381 | spin_lock_irqsave(&pch->lock, flags); | |
382 | ||
383 | tasklet_kill(&pch->task); | |
384 | ||
385 | pl330_release_channel(pch->pl330_chid); | |
386 | pch->pl330_chid = NULL; | |
387 | ||
42bc9cf4 BK |
388 | if (pch->cyclic) |
389 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); | |
390 | ||
b3040e40 JB |
391 | spin_unlock_irqrestore(&pch->lock, flags); |
392 | } | |
393 | ||
394 | static enum dma_status | |
395 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
396 | struct dma_tx_state *txstate) | |
397 | { | |
398 | struct dma_pl330_chan *pch = to_pchan(chan); | |
399 | dma_cookie_t last_done, last_used; | |
400 | int ret; | |
401 | ||
4d4e58de | 402 | last_done = chan->completed_cookie; |
b3040e40 JB |
403 | last_used = chan->cookie; |
404 | ||
405 | ret = dma_async_is_complete(cookie, last_done, last_used); | |
406 | ||
407 | dma_set_tx_state(txstate, last_done, last_used, 0); | |
408 | ||
409 | return ret; | |
410 | } | |
411 | ||
412 | static void pl330_issue_pending(struct dma_chan *chan) | |
413 | { | |
414 | pl330_tasklet((unsigned long) to_pchan(chan)); | |
415 | } | |
416 | ||
417 | /* | |
418 | * We returned the last one of the circular list of descriptor(s) | |
419 | * from prep_xxx, so the argument to submit corresponds to the last | |
420 | * descriptor of the list. | |
421 | */ | |
422 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) | |
423 | { | |
424 | struct dma_pl330_desc *desc, *last = to_desc(tx); | |
425 | struct dma_pl330_chan *pch = to_pchan(tx->chan); | |
426 | dma_cookie_t cookie; | |
427 | unsigned long flags; | |
428 | ||
429 | spin_lock_irqsave(&pch->lock, flags); | |
430 | ||
431 | /* Assign cookies to all nodes */ | |
b3040e40 JB |
432 | while (!list_empty(&last->node)) { |
433 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); | |
434 | ||
884485e1 | 435 | dma_cookie_assign(&desc->txd); |
b3040e40 JB |
436 | |
437 | list_move_tail(&desc->node, &pch->work_list); | |
438 | } | |
439 | ||
884485e1 | 440 | cookie = dma_cookie_assign(&last->txd); |
b3040e40 | 441 | list_add_tail(&last->node, &pch->work_list); |
b3040e40 JB |
442 | spin_unlock_irqrestore(&pch->lock, flags); |
443 | ||
444 | return cookie; | |
445 | } | |
446 | ||
447 | static inline void _init_desc(struct dma_pl330_desc *desc) | |
448 | { | |
449 | desc->pchan = NULL; | |
450 | desc->req.x = &desc->px; | |
451 | desc->req.token = desc; | |
452 | desc->rqcfg.swap = SWAP_NO; | |
453 | desc->rqcfg.privileged = 0; | |
454 | desc->rqcfg.insnaccess = 0; | |
455 | desc->rqcfg.scctl = SCCTRL0; | |
456 | desc->rqcfg.dcctl = DCCTRL0; | |
457 | desc->req.cfg = &desc->rqcfg; | |
458 | desc->req.xfer_cb = dma_pl330_rqcb; | |
459 | desc->txd.tx_submit = pl330_tx_submit; | |
460 | ||
461 | INIT_LIST_HEAD(&desc->node); | |
462 | } | |
463 | ||
464 | /* Returns the number of descriptors added to the DMAC pool */ | |
465 | int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count) | |
466 | { | |
467 | struct dma_pl330_desc *desc; | |
468 | unsigned long flags; | |
469 | int i; | |
470 | ||
471 | if (!pdmac) | |
472 | return 0; | |
473 | ||
474 | desc = kmalloc(count * sizeof(*desc), flg); | |
475 | if (!desc) | |
476 | return 0; | |
477 | ||
478 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
479 | ||
480 | for (i = 0; i < count; i++) { | |
481 | _init_desc(&desc[i]); | |
482 | list_add_tail(&desc[i].node, &pdmac->desc_pool); | |
483 | } | |
484 | ||
485 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
486 | ||
487 | return count; | |
488 | } | |
489 | ||
490 | static struct dma_pl330_desc * | |
491 | pluck_desc(struct dma_pl330_dmac *pdmac) | |
492 | { | |
493 | struct dma_pl330_desc *desc = NULL; | |
494 | unsigned long flags; | |
495 | ||
496 | if (!pdmac) | |
497 | return NULL; | |
498 | ||
499 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
500 | ||
501 | if (!list_empty(&pdmac->desc_pool)) { | |
502 | desc = list_entry(pdmac->desc_pool.next, | |
503 | struct dma_pl330_desc, node); | |
504 | ||
505 | list_del_init(&desc->node); | |
506 | ||
507 | desc->status = PREP; | |
508 | desc->txd.callback = NULL; | |
509 | } | |
510 | ||
511 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
512 | ||
513 | return desc; | |
514 | } | |
515 | ||
516 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) | |
517 | { | |
518 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
cd072515 | 519 | u8 *peri_id = pch->chan.private; |
b3040e40 JB |
520 | struct dma_pl330_desc *desc; |
521 | ||
522 | /* Pluck one desc from the pool of DMAC */ | |
523 | desc = pluck_desc(pdmac); | |
524 | ||
525 | /* If the DMAC pool is empty, alloc new */ | |
526 | if (!desc) { | |
527 | if (!add_desc(pdmac, GFP_ATOMIC, 1)) | |
528 | return NULL; | |
529 | ||
530 | /* Try again */ | |
531 | desc = pluck_desc(pdmac); | |
532 | if (!desc) { | |
533 | dev_err(pch->dmac->pif.dev, | |
534 | "%s:%d ALERT!\n", __func__, __LINE__); | |
535 | return NULL; | |
536 | } | |
537 | } | |
538 | ||
539 | /* Initialize the descriptor */ | |
540 | desc->pchan = pch; | |
541 | desc->txd.cookie = 0; | |
542 | async_tx_ack(&desc->txd); | |
543 | ||
cd072515 | 544 | desc->req.peri = peri_id ? pch->chan.chan_id : 0; |
b3040e40 JB |
545 | |
546 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); | |
547 | ||
548 | return desc; | |
549 | } | |
550 | ||
551 | static inline void fill_px(struct pl330_xfer *px, | |
552 | dma_addr_t dst, dma_addr_t src, size_t len) | |
553 | { | |
554 | px->next = NULL; | |
555 | px->bytes = len; | |
556 | px->dst_addr = dst; | |
557 | px->src_addr = src; | |
558 | } | |
559 | ||
560 | static struct dma_pl330_desc * | |
561 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, | |
562 | dma_addr_t src, size_t len) | |
563 | { | |
564 | struct dma_pl330_desc *desc = pl330_get_desc(pch); | |
565 | ||
566 | if (!desc) { | |
567 | dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", | |
568 | __func__, __LINE__); | |
569 | return NULL; | |
570 | } | |
571 | ||
572 | /* | |
573 | * Ideally we should lookout for reqs bigger than | |
574 | * those that can be programmed with 256 bytes of | |
575 | * MC buffer, but considering a req size is seldom | |
576 | * going to be word-unaligned and more than 200MB, | |
577 | * we take it easy. | |
578 | * Also, should the limit is reached we'd rather | |
579 | * have the platform increase MC buffer size than | |
580 | * complicating this API driver. | |
581 | */ | |
582 | fill_px(&desc->px, dst, src, len); | |
583 | ||
584 | return desc; | |
585 | } | |
586 | ||
587 | /* Call after fixing burst size */ | |
588 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) | |
589 | { | |
590 | struct dma_pl330_chan *pch = desc->pchan; | |
591 | struct pl330_info *pi = &pch->dmac->pif; | |
592 | int burst_len; | |
593 | ||
594 | burst_len = pi->pcfg.data_bus_width / 8; | |
595 | burst_len *= pi->pcfg.data_buf_dep; | |
596 | burst_len >>= desc->rqcfg.brst_size; | |
597 | ||
598 | /* src/dst_burst_len can't be more than 16 */ | |
599 | if (burst_len > 16) | |
600 | burst_len = 16; | |
601 | ||
602 | while (burst_len > 1) { | |
603 | if (!(len % (burst_len << desc->rqcfg.brst_size))) | |
604 | break; | |
605 | burst_len--; | |
606 | } | |
607 | ||
608 | return burst_len; | |
609 | } | |
610 | ||
42bc9cf4 BK |
611 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
612 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, | |
db8196df | 613 | size_t period_len, enum dma_transfer_direction direction) |
42bc9cf4 BK |
614 | { |
615 | struct dma_pl330_desc *desc; | |
616 | struct dma_pl330_chan *pch = to_pchan(chan); | |
617 | dma_addr_t dst; | |
618 | dma_addr_t src; | |
619 | ||
620 | desc = pl330_get_desc(pch); | |
621 | if (!desc) { | |
622 | dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", | |
623 | __func__, __LINE__); | |
624 | return NULL; | |
625 | } | |
626 | ||
627 | switch (direction) { | |
db8196df | 628 | case DMA_MEM_TO_DEV: |
42bc9cf4 BK |
629 | desc->rqcfg.src_inc = 1; |
630 | desc->rqcfg.dst_inc = 0; | |
cd072515 | 631 | desc->req.rqtype = MEMTODEV; |
42bc9cf4 BK |
632 | src = dma_addr; |
633 | dst = pch->fifo_addr; | |
634 | break; | |
db8196df | 635 | case DMA_DEV_TO_MEM: |
42bc9cf4 BK |
636 | desc->rqcfg.src_inc = 0; |
637 | desc->rqcfg.dst_inc = 1; | |
cd072515 | 638 | desc->req.rqtype = DEVTOMEM; |
42bc9cf4 BK |
639 | src = pch->fifo_addr; |
640 | dst = dma_addr; | |
641 | break; | |
642 | default: | |
643 | dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n", | |
644 | __func__, __LINE__); | |
645 | return NULL; | |
646 | } | |
647 | ||
648 | desc->rqcfg.brst_size = pch->burst_sz; | |
649 | desc->rqcfg.brst_len = 1; | |
650 | ||
651 | pch->cyclic = true; | |
652 | ||
653 | fill_px(&desc->px, dst, src, period_len); | |
654 | ||
655 | return &desc->txd; | |
656 | } | |
657 | ||
b3040e40 JB |
658 | static struct dma_async_tx_descriptor * |
659 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, | |
660 | dma_addr_t src, size_t len, unsigned long flags) | |
661 | { | |
662 | struct dma_pl330_desc *desc; | |
663 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 JB |
664 | struct pl330_info *pi; |
665 | int burst; | |
666 | ||
4e0e6109 | 667 | if (unlikely(!pch || !len)) |
b3040e40 JB |
668 | return NULL; |
669 | ||
b3040e40 JB |
670 | pi = &pch->dmac->pif; |
671 | ||
672 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); | |
673 | if (!desc) | |
674 | return NULL; | |
675 | ||
676 | desc->rqcfg.src_inc = 1; | |
677 | desc->rqcfg.dst_inc = 1; | |
cd072515 | 678 | desc->req.rqtype = MEMTOMEM; |
b3040e40 JB |
679 | |
680 | /* Select max possible burst size */ | |
681 | burst = pi->pcfg.data_bus_width / 8; | |
682 | ||
683 | while (burst > 1) { | |
684 | if (!(len % burst)) | |
685 | break; | |
686 | burst /= 2; | |
687 | } | |
688 | ||
689 | desc->rqcfg.brst_size = 0; | |
690 | while (burst != (1 << desc->rqcfg.brst_size)) | |
691 | desc->rqcfg.brst_size++; | |
692 | ||
693 | desc->rqcfg.brst_len = get_burst_len(desc, len); | |
694 | ||
695 | desc->txd.flags = flags; | |
696 | ||
697 | return &desc->txd; | |
698 | } | |
699 | ||
700 | static struct dma_async_tx_descriptor * | |
701 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 702 | unsigned int sg_len, enum dma_transfer_direction direction, |
b3040e40 JB |
703 | unsigned long flg) |
704 | { | |
705 | struct dma_pl330_desc *first, *desc = NULL; | |
706 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 JB |
707 | struct scatterlist *sg; |
708 | unsigned long flags; | |
1b9bb715 | 709 | int i; |
b3040e40 JB |
710 | dma_addr_t addr; |
711 | ||
cd072515 | 712 | if (unlikely(!pch || !sgl || !sg_len)) |
b3040e40 JB |
713 | return NULL; |
714 | ||
1b9bb715 | 715 | addr = pch->fifo_addr; |
b3040e40 JB |
716 | |
717 | first = NULL; | |
718 | ||
719 | for_each_sg(sgl, sg, sg_len, i) { | |
720 | ||
721 | desc = pl330_get_desc(pch); | |
722 | if (!desc) { | |
723 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
724 | ||
725 | dev_err(pch->dmac->pif.dev, | |
726 | "%s:%d Unable to fetch desc\n", | |
727 | __func__, __LINE__); | |
728 | if (!first) | |
729 | return NULL; | |
730 | ||
731 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
732 | ||
733 | while (!list_empty(&first->node)) { | |
734 | desc = list_entry(first->node.next, | |
735 | struct dma_pl330_desc, node); | |
736 | list_move_tail(&desc->node, &pdmac->desc_pool); | |
737 | } | |
738 | ||
739 | list_move_tail(&first->node, &pdmac->desc_pool); | |
740 | ||
741 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
742 | ||
743 | return NULL; | |
744 | } | |
745 | ||
746 | if (!first) | |
747 | first = desc; | |
748 | else | |
749 | list_add_tail(&desc->node, &first->node); | |
750 | ||
db8196df | 751 | if (direction == DMA_MEM_TO_DEV) { |
b3040e40 JB |
752 | desc->rqcfg.src_inc = 1; |
753 | desc->rqcfg.dst_inc = 0; | |
cd072515 | 754 | desc->req.rqtype = MEMTODEV; |
b3040e40 JB |
755 | fill_px(&desc->px, |
756 | addr, sg_dma_address(sg), sg_dma_len(sg)); | |
757 | } else { | |
758 | desc->rqcfg.src_inc = 0; | |
759 | desc->rqcfg.dst_inc = 1; | |
cd072515 | 760 | desc->req.rqtype = DEVTOMEM; |
b3040e40 JB |
761 | fill_px(&desc->px, |
762 | sg_dma_address(sg), addr, sg_dma_len(sg)); | |
763 | } | |
764 | ||
1b9bb715 | 765 | desc->rqcfg.brst_size = pch->burst_sz; |
b3040e40 JB |
766 | desc->rqcfg.brst_len = 1; |
767 | } | |
768 | ||
769 | /* Return the last desc in the chain */ | |
770 | desc->txd.flags = flg; | |
771 | return &desc->txd; | |
772 | } | |
773 | ||
774 | static irqreturn_t pl330_irq_handler(int irq, void *data) | |
775 | { | |
776 | if (pl330_update(data)) | |
777 | return IRQ_HANDLED; | |
778 | else | |
779 | return IRQ_NONE; | |
780 | } | |
781 | ||
782 | static int __devinit | |
aa25afad | 783 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
b3040e40 JB |
784 | { |
785 | struct dma_pl330_platdata *pdat; | |
786 | struct dma_pl330_dmac *pdmac; | |
787 | struct dma_pl330_chan *pch; | |
788 | struct pl330_info *pi; | |
789 | struct dma_device *pd; | |
790 | struct resource *res; | |
791 | int i, ret, irq; | |
4e0e6109 | 792 | int num_chan; |
b3040e40 JB |
793 | |
794 | pdat = adev->dev.platform_data; | |
795 | ||
b3040e40 | 796 | /* Allocate a new DMAC and its Channels */ |
4e0e6109 | 797 | pdmac = kzalloc(sizeof(*pdmac), GFP_KERNEL); |
b3040e40 JB |
798 | if (!pdmac) { |
799 | dev_err(&adev->dev, "unable to allocate mem\n"); | |
800 | return -ENOMEM; | |
801 | } | |
802 | ||
803 | pi = &pdmac->pif; | |
804 | pi->dev = &adev->dev; | |
805 | pi->pl330_data = NULL; | |
4e0e6109 | 806 | pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0; |
b3040e40 JB |
807 | |
808 | res = &adev->res; | |
809 | request_mem_region(res->start, resource_size(res), "dma-pl330"); | |
810 | ||
811 | pi->base = ioremap(res->start, resource_size(res)); | |
812 | if (!pi->base) { | |
813 | ret = -ENXIO; | |
814 | goto probe_err1; | |
815 | } | |
816 | ||
a2f5203f BK |
817 | pdmac->clk = clk_get(&adev->dev, "dma"); |
818 | if (IS_ERR(pdmac->clk)) { | |
819 | dev_err(&adev->dev, "Cannot get operation clock.\n"); | |
820 | ret = -EINVAL; | |
7bec78e0 | 821 | goto probe_err2; |
a2f5203f BK |
822 | } |
823 | ||
824 | amba_set_drvdata(adev, pdmac); | |
825 | ||
3506c0d5 | 826 | #ifndef CONFIG_PM_RUNTIME |
a2f5203f BK |
827 | /* enable dma clk */ |
828 | clk_enable(pdmac->clk); | |
829 | #endif | |
830 | ||
b3040e40 JB |
831 | irq = adev->irq[0]; |
832 | ret = request_irq(irq, pl330_irq_handler, 0, | |
833 | dev_name(&adev->dev), pi); | |
834 | if (ret) | |
7bec78e0 | 835 | goto probe_err3; |
b3040e40 JB |
836 | |
837 | ret = pl330_add(pi); | |
838 | if (ret) | |
7bec78e0 | 839 | goto probe_err4; |
b3040e40 JB |
840 | |
841 | INIT_LIST_HEAD(&pdmac->desc_pool); | |
842 | spin_lock_init(&pdmac->pool_lock); | |
843 | ||
844 | /* Create a descriptor pool of default size */ | |
845 | if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC)) | |
846 | dev_warn(&adev->dev, "unable to allocate desc\n"); | |
847 | ||
848 | pd = &pdmac->ddma; | |
849 | INIT_LIST_HEAD(&pd->channels); | |
850 | ||
851 | /* Initialize channel parameters */ | |
93ed5544 TA |
852 | num_chan = max(pdat ? pdat->nr_valid_peri : (u8)pi->pcfg.num_peri, |
853 | (u8)pi->pcfg.num_chan); | |
4e0e6109 | 854 | pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); |
b3040e40 | 855 | |
4e0e6109 RH |
856 | for (i = 0; i < num_chan; i++) { |
857 | pch = &pdmac->peripherals[i]; | |
93ed5544 TA |
858 | if (!adev->dev.of_node) |
859 | pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; | |
860 | else | |
861 | pch->chan.private = adev->dev.of_node; | |
b3040e40 JB |
862 | |
863 | INIT_LIST_HEAD(&pch->work_list); | |
864 | spin_lock_init(&pch->lock); | |
865 | pch->pl330_chid = NULL; | |
b3040e40 | 866 | pch->chan.device = pd; |
b3040e40 JB |
867 | pch->dmac = pdmac; |
868 | ||
869 | /* Add the channel to the DMAC list */ | |
b3040e40 JB |
870 | list_add_tail(&pch->chan.device_node, &pd->channels); |
871 | } | |
872 | ||
873 | pd->dev = &adev->dev; | |
93ed5544 | 874 | if (pdat) { |
cd072515 | 875 | pd->cap_mask = pdat->cap_mask; |
93ed5544 | 876 | } else { |
cd072515 | 877 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); |
93ed5544 TA |
878 | if (pi->pcfg.num_peri) { |
879 | dma_cap_set(DMA_SLAVE, pd->cap_mask); | |
880 | dma_cap_set(DMA_CYCLIC, pd->cap_mask); | |
881 | } | |
882 | } | |
b3040e40 JB |
883 | |
884 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; | |
885 | pd->device_free_chan_resources = pl330_free_chan_resources; | |
886 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; | |
42bc9cf4 | 887 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
b3040e40 JB |
888 | pd->device_tx_status = pl330_tx_status; |
889 | pd->device_prep_slave_sg = pl330_prep_slave_sg; | |
890 | pd->device_control = pl330_control; | |
891 | pd->device_issue_pending = pl330_issue_pending; | |
892 | ||
893 | ret = dma_async_device_register(pd); | |
894 | if (ret) { | |
895 | dev_err(&adev->dev, "unable to register DMAC\n"); | |
7bec78e0 | 896 | goto probe_err5; |
b3040e40 JB |
897 | } |
898 | ||
b3040e40 JB |
899 | dev_info(&adev->dev, |
900 | "Loaded driver for PL330 DMAC-%d\n", adev->periphid); | |
901 | dev_info(&adev->dev, | |
902 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | |
903 | pi->pcfg.data_buf_dep, | |
904 | pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan, | |
905 | pi->pcfg.num_peri, pi->pcfg.num_events); | |
906 | ||
907 | return 0; | |
908 | ||
7bec78e0 | 909 | probe_err5: |
b3040e40 | 910 | pl330_del(pi); |
7bec78e0 | 911 | probe_err4: |
b3040e40 | 912 | free_irq(irq, pi); |
7bec78e0 JL |
913 | probe_err3: |
914 | #ifndef CONFIG_PM_RUNTIME | |
915 | clk_disable(pdmac->clk); | |
916 | #endif | |
917 | clk_put(pdmac->clk); | |
b3040e40 JB |
918 | probe_err2: |
919 | iounmap(pi->base); | |
920 | probe_err1: | |
921 | release_mem_region(res->start, resource_size(res)); | |
922 | kfree(pdmac); | |
923 | ||
924 | return ret; | |
925 | } | |
926 | ||
927 | static int __devexit pl330_remove(struct amba_device *adev) | |
928 | { | |
929 | struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev); | |
930 | struct dma_pl330_chan *pch, *_p; | |
931 | struct pl330_info *pi; | |
932 | struct resource *res; | |
933 | int irq; | |
934 | ||
935 | if (!pdmac) | |
936 | return 0; | |
937 | ||
938 | amba_set_drvdata(adev, NULL); | |
939 | ||
940 | /* Idle the DMAC */ | |
941 | list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels, | |
942 | chan.device_node) { | |
943 | ||
944 | /* Remove the channel */ | |
945 | list_del(&pch->chan.device_node); | |
946 | ||
947 | /* Flush the channel */ | |
948 | pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); | |
949 | pl330_free_chan_resources(&pch->chan); | |
950 | } | |
951 | ||
952 | pi = &pdmac->pif; | |
953 | ||
954 | pl330_del(pi); | |
955 | ||
956 | irq = adev->irq[0]; | |
957 | free_irq(irq, pi); | |
958 | ||
959 | iounmap(pi->base); | |
960 | ||
961 | res = &adev->res; | |
962 | release_mem_region(res->start, resource_size(res)); | |
963 | ||
3506c0d5 | 964 | #ifndef CONFIG_PM_RUNTIME |
a2f5203f BK |
965 | clk_disable(pdmac->clk); |
966 | #endif | |
967 | ||
b3040e40 JB |
968 | kfree(pdmac); |
969 | ||
970 | return 0; | |
971 | } | |
972 | ||
973 | static struct amba_id pl330_ids[] = { | |
974 | { | |
975 | .id = 0x00041330, | |
976 | .mask = 0x000fffff, | |
977 | }, | |
978 | { 0, 0 }, | |
979 | }; | |
980 | ||
e8fa516a DM |
981 | MODULE_DEVICE_TABLE(amba, pl330_ids); |
982 | ||
a2f5203f BK |
983 | #ifdef CONFIG_PM_RUNTIME |
984 | static int pl330_runtime_suspend(struct device *dev) | |
985 | { | |
986 | struct dma_pl330_dmac *pdmac = dev_get_drvdata(dev); | |
987 | ||
988 | if (!pdmac) { | |
989 | dev_err(dev, "failed to get dmac\n"); | |
990 | return -ENODEV; | |
991 | } | |
992 | ||
993 | clk_disable(pdmac->clk); | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
998 | static int pl330_runtime_resume(struct device *dev) | |
999 | { | |
1000 | struct dma_pl330_dmac *pdmac = dev_get_drvdata(dev); | |
1001 | ||
1002 | if (!pdmac) { | |
1003 | dev_err(dev, "failed to get dmac\n"); | |
1004 | return -ENODEV; | |
1005 | } | |
1006 | ||
1007 | clk_enable(pdmac->clk); | |
1008 | ||
1009 | return 0; | |
1010 | } | |
1011 | #else | |
1012 | #define pl330_runtime_suspend NULL | |
1013 | #define pl330_runtime_resume NULL | |
1014 | #endif /* CONFIG_PM_RUNTIME */ | |
1015 | ||
1016 | static const struct dev_pm_ops pl330_pm_ops = { | |
1017 | .runtime_suspend = pl330_runtime_suspend, | |
1018 | .runtime_resume = pl330_runtime_resume, | |
1019 | }; | |
1020 | ||
b3040e40 JB |
1021 | static struct amba_driver pl330_driver = { |
1022 | .drv = { | |
1023 | .owner = THIS_MODULE, | |
1024 | .name = "dma-pl330", | |
a2f5203f | 1025 | .pm = &pl330_pm_ops, |
b3040e40 JB |
1026 | }, |
1027 | .id_table = pl330_ids, | |
1028 | .probe = pl330_probe, | |
1029 | .remove = pl330_remove, | |
1030 | }; | |
1031 | ||
1032 | static int __init pl330_init(void) | |
1033 | { | |
1034 | return amba_driver_register(&pl330_driver); | |
1035 | } | |
1036 | module_init(pl330_init); | |
1037 | ||
1038 | static void __exit pl330_exit(void) | |
1039 | { | |
1040 | amba_driver_unregister(&pl330_driver); | |
1041 | return; | |
1042 | } | |
1043 | module_exit(pl330_exit); | |
1044 | ||
1045 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
1046 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); | |
1047 | MODULE_LICENSE("GPL"); |