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b3040e40 JB |
1 | /* linux/drivers/dma/pl330.c |
2 | * | |
3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
4 | * Jaswinder Singh <jassi.brar@samsung.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/io.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/amba/bus.h> | |
19 | #include <linux/amba/pl330.h> | |
a2f5203f | 20 | #include <linux/pm_runtime.h> |
1b9bb715 | 21 | #include <linux/scatterlist.h> |
b3040e40 JB |
22 | |
23 | #define NR_DEFAULT_DESC 16 | |
24 | ||
25 | enum desc_status { | |
26 | /* In the DMAC pool */ | |
27 | FREE, | |
28 | /* | |
29 | * Allocted to some channel during prep_xxx | |
30 | * Also may be sitting on the work_list. | |
31 | */ | |
32 | PREP, | |
33 | /* | |
34 | * Sitting on the work_list and already submitted | |
35 | * to the PL330 core. Not more than two descriptors | |
36 | * of a channel can be BUSY at any time. | |
37 | */ | |
38 | BUSY, | |
39 | /* | |
40 | * Sitting on the channel work_list but xfer done | |
41 | * by PL330 core | |
42 | */ | |
43 | DONE, | |
44 | }; | |
45 | ||
46 | struct dma_pl330_chan { | |
47 | /* Schedule desc completion */ | |
48 | struct tasklet_struct task; | |
49 | ||
50 | /* DMA-Engine Channel */ | |
51 | struct dma_chan chan; | |
52 | ||
53 | /* Last completed cookie */ | |
54 | dma_cookie_t completed; | |
55 | ||
56 | /* List of to be xfered descriptors */ | |
57 | struct list_head work_list; | |
58 | ||
59 | /* Pointer to the DMAC that manages this channel, | |
60 | * NULL if the channel is available to be acquired. | |
61 | * As the parent, this DMAC also provides descriptors | |
62 | * to the channel. | |
63 | */ | |
64 | struct dma_pl330_dmac *dmac; | |
65 | ||
66 | /* To protect channel manipulation */ | |
67 | spinlock_t lock; | |
68 | ||
69 | /* Token of a hardware channel thread of PL330 DMAC | |
70 | * NULL if the channel is available to be acquired. | |
71 | */ | |
72 | void *pl330_chid; | |
1b9bb715 BK |
73 | |
74 | /* For D-to-M and M-to-D channels */ | |
75 | int burst_sz; /* the peripheral fifo width */ | |
1d0c1d60 | 76 | int burst_len; /* the number of burst */ |
1b9bb715 | 77 | dma_addr_t fifo_addr; |
42bc9cf4 BK |
78 | |
79 | /* for cyclic capability */ | |
80 | bool cyclic; | |
b3040e40 JB |
81 | }; |
82 | ||
83 | struct dma_pl330_dmac { | |
84 | struct pl330_info pif; | |
85 | ||
86 | /* DMA-Engine Device */ | |
87 | struct dma_device ddma; | |
88 | ||
89 | /* Pool of descriptors available for the DMAC's channels */ | |
90 | struct list_head desc_pool; | |
91 | /* To protect desc_pool manipulation */ | |
92 | spinlock_t pool_lock; | |
93 | ||
94 | /* Peripheral channels connected to this DMAC */ | |
4e0e6109 | 95 | struct dma_pl330_chan *peripherals; /* keep at end */ |
a2f5203f BK |
96 | |
97 | struct clk *clk; | |
b3040e40 JB |
98 | }; |
99 | ||
100 | struct dma_pl330_desc { | |
101 | /* To attach to a queue as child */ | |
102 | struct list_head node; | |
103 | ||
104 | /* Descriptor for the DMA Engine API */ | |
105 | struct dma_async_tx_descriptor txd; | |
106 | ||
107 | /* Xfer for PL330 core */ | |
108 | struct pl330_xfer px; | |
109 | ||
110 | struct pl330_reqcfg rqcfg; | |
111 | struct pl330_req req; | |
112 | ||
113 | enum desc_status status; | |
114 | ||
115 | /* The channel which currently holds this desc */ | |
116 | struct dma_pl330_chan *pchan; | |
117 | }; | |
118 | ||
3e2ec13a TA |
119 | /* forward declaration */ |
120 | static struct amba_driver pl330_driver; | |
121 | ||
b3040e40 JB |
122 | static inline struct dma_pl330_chan * |
123 | to_pchan(struct dma_chan *ch) | |
124 | { | |
125 | if (!ch) | |
126 | return NULL; | |
127 | ||
128 | return container_of(ch, struct dma_pl330_chan, chan); | |
129 | } | |
130 | ||
131 | static inline struct dma_pl330_desc * | |
132 | to_desc(struct dma_async_tx_descriptor *tx) | |
133 | { | |
134 | return container_of(tx, struct dma_pl330_desc, txd); | |
135 | } | |
136 | ||
137 | static inline void free_desc_list(struct list_head *list) | |
138 | { | |
139 | struct dma_pl330_dmac *pdmac; | |
140 | struct dma_pl330_desc *desc; | |
141 | struct dma_pl330_chan *pch; | |
142 | unsigned long flags; | |
143 | ||
144 | if (list_empty(list)) | |
145 | return; | |
146 | ||
147 | /* Finish off the work list */ | |
148 | list_for_each_entry(desc, list, node) { | |
149 | dma_async_tx_callback callback; | |
150 | void *param; | |
151 | ||
152 | /* All desc in a list belong to same channel */ | |
153 | pch = desc->pchan; | |
154 | callback = desc->txd.callback; | |
155 | param = desc->txd.callback_param; | |
156 | ||
157 | if (callback) | |
158 | callback(param); | |
159 | ||
160 | desc->pchan = NULL; | |
161 | } | |
162 | ||
163 | pdmac = pch->dmac; | |
164 | ||
165 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
166 | list_splice_tail_init(list, &pdmac->desc_pool); | |
167 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
168 | } | |
169 | ||
42bc9cf4 BK |
170 | static inline void handle_cyclic_desc_list(struct list_head *list) |
171 | { | |
172 | struct dma_pl330_desc *desc; | |
173 | struct dma_pl330_chan *pch; | |
174 | unsigned long flags; | |
175 | ||
176 | if (list_empty(list)) | |
177 | return; | |
178 | ||
179 | list_for_each_entry(desc, list, node) { | |
180 | dma_async_tx_callback callback; | |
181 | ||
182 | /* Change status to reload it */ | |
183 | desc->status = PREP; | |
184 | pch = desc->pchan; | |
185 | callback = desc->txd.callback; | |
186 | if (callback) | |
187 | callback(desc->txd.callback_param); | |
188 | } | |
189 | ||
190 | spin_lock_irqsave(&pch->lock, flags); | |
191 | list_splice_tail_init(list, &pch->work_list); | |
192 | spin_unlock_irqrestore(&pch->lock, flags); | |
193 | } | |
194 | ||
b3040e40 JB |
195 | static inline void fill_queue(struct dma_pl330_chan *pch) |
196 | { | |
197 | struct dma_pl330_desc *desc; | |
198 | int ret; | |
199 | ||
200 | list_for_each_entry(desc, &pch->work_list, node) { | |
201 | ||
202 | /* If already submitted */ | |
203 | if (desc->status == BUSY) | |
204 | break; | |
205 | ||
206 | ret = pl330_submit_req(pch->pl330_chid, | |
207 | &desc->req); | |
208 | if (!ret) { | |
209 | desc->status = BUSY; | |
210 | break; | |
211 | } else if (ret == -EAGAIN) { | |
212 | /* QFull or DMAC Dying */ | |
213 | break; | |
214 | } else { | |
215 | /* Unacceptable request */ | |
216 | desc->status = DONE; | |
217 | dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n", | |
218 | __func__, __LINE__, desc->txd.cookie); | |
219 | tasklet_schedule(&pch->task); | |
220 | } | |
221 | } | |
222 | } | |
223 | ||
224 | static void pl330_tasklet(unsigned long data) | |
225 | { | |
226 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; | |
227 | struct dma_pl330_desc *desc, *_dt; | |
228 | unsigned long flags; | |
229 | LIST_HEAD(list); | |
230 | ||
231 | spin_lock_irqsave(&pch->lock, flags); | |
232 | ||
233 | /* Pick up ripe tomatoes */ | |
234 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) | |
235 | if (desc->status == DONE) { | |
236 | pch->completed = desc->txd.cookie; | |
237 | list_move_tail(&desc->node, &list); | |
238 | } | |
239 | ||
240 | /* Try to submit a req imm. next to the last completed cookie */ | |
241 | fill_queue(pch); | |
242 | ||
243 | /* Make sure the PL330 Channel thread is active */ | |
244 | pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START); | |
245 | ||
246 | spin_unlock_irqrestore(&pch->lock, flags); | |
247 | ||
42bc9cf4 BK |
248 | if (pch->cyclic) |
249 | handle_cyclic_desc_list(&list); | |
250 | else | |
251 | free_desc_list(&list); | |
b3040e40 JB |
252 | } |
253 | ||
254 | static void dma_pl330_rqcb(void *token, enum pl330_op_err err) | |
255 | { | |
256 | struct dma_pl330_desc *desc = token; | |
257 | struct dma_pl330_chan *pch = desc->pchan; | |
258 | unsigned long flags; | |
259 | ||
260 | /* If desc aborted */ | |
261 | if (!pch) | |
262 | return; | |
263 | ||
264 | spin_lock_irqsave(&pch->lock, flags); | |
265 | ||
266 | desc->status = DONE; | |
267 | ||
268 | spin_unlock_irqrestore(&pch->lock, flags); | |
269 | ||
270 | tasklet_schedule(&pch->task); | |
271 | } | |
272 | ||
3e2ec13a TA |
273 | bool pl330_filter(struct dma_chan *chan, void *param) |
274 | { | |
cd072515 | 275 | u8 *peri_id; |
3e2ec13a TA |
276 | |
277 | if (chan->device->dev->driver != &pl330_driver.drv) | |
278 | return false; | |
279 | ||
cd072515 TA |
280 | peri_id = chan->private; |
281 | return *peri_id == (unsigned)param; | |
3e2ec13a TA |
282 | } |
283 | EXPORT_SYMBOL(pl330_filter); | |
284 | ||
b3040e40 JB |
285 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
286 | { | |
287 | struct dma_pl330_chan *pch = to_pchan(chan); | |
288 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
289 | unsigned long flags; | |
290 | ||
291 | spin_lock_irqsave(&pch->lock, flags); | |
292 | ||
293 | pch->completed = chan->cookie = 1; | |
42bc9cf4 | 294 | pch->cyclic = false; |
b3040e40 JB |
295 | |
296 | pch->pl330_chid = pl330_request_channel(&pdmac->pif); | |
297 | if (!pch->pl330_chid) { | |
298 | spin_unlock_irqrestore(&pch->lock, flags); | |
299 | return 0; | |
300 | } | |
301 | ||
302 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); | |
303 | ||
304 | spin_unlock_irqrestore(&pch->lock, flags); | |
305 | ||
306 | return 1; | |
307 | } | |
308 | ||
309 | static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg) | |
310 | { | |
311 | struct dma_pl330_chan *pch = to_pchan(chan); | |
ae43b886 | 312 | struct dma_pl330_desc *desc, *_dt; |
b3040e40 | 313 | unsigned long flags; |
1d0c1d60 BK |
314 | struct dma_pl330_dmac *pdmac = pch->dmac; |
315 | struct dma_slave_config *slave_config; | |
ae43b886 | 316 | LIST_HEAD(list); |
b3040e40 | 317 | |
1d0c1d60 BK |
318 | switch (cmd) { |
319 | case DMA_TERMINATE_ALL: | |
320 | spin_lock_irqsave(&pch->lock, flags); | |
b3040e40 | 321 | |
1d0c1d60 BK |
322 | /* FLUSH the PL330 Channel thread */ |
323 | pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH); | |
b3040e40 | 324 | |
1d0c1d60 | 325 | /* Mark all desc done */ |
ae43b886 | 326 | list_for_each_entry_safe(desc, _dt, &pch->work_list , node) { |
1d0c1d60 | 327 | desc->status = DONE; |
ae43b886 BK |
328 | pch->completed = desc->txd.cookie; |
329 | list_move_tail(&desc->node, &list); | |
330 | } | |
b3040e40 | 331 | |
ae43b886 | 332 | list_splice_tail_init(&list, &pdmac->desc_pool); |
1d0c1d60 | 333 | spin_unlock_irqrestore(&pch->lock, flags); |
1d0c1d60 BK |
334 | break; |
335 | case DMA_SLAVE_CONFIG: | |
336 | slave_config = (struct dma_slave_config *)arg; | |
337 | ||
338 | if (slave_config->direction == DMA_TO_DEVICE) { | |
339 | if (slave_config->dst_addr) | |
340 | pch->fifo_addr = slave_config->dst_addr; | |
341 | if (slave_config->dst_addr_width) | |
342 | pch->burst_sz = __ffs(slave_config->dst_addr_width); | |
343 | if (slave_config->dst_maxburst) | |
344 | pch->burst_len = slave_config->dst_maxburst; | |
345 | } else if (slave_config->direction == DMA_FROM_DEVICE) { | |
346 | if (slave_config->src_addr) | |
347 | pch->fifo_addr = slave_config->src_addr; | |
348 | if (slave_config->src_addr_width) | |
349 | pch->burst_sz = __ffs(slave_config->src_addr_width); | |
350 | if (slave_config->src_maxburst) | |
351 | pch->burst_len = slave_config->src_maxburst; | |
352 | } | |
353 | break; | |
354 | default: | |
355 | dev_err(pch->dmac->pif.dev, "Not supported command.\n"); | |
356 | return -ENXIO; | |
357 | } | |
b3040e40 JB |
358 | |
359 | return 0; | |
360 | } | |
361 | ||
362 | static void pl330_free_chan_resources(struct dma_chan *chan) | |
363 | { | |
364 | struct dma_pl330_chan *pch = to_pchan(chan); | |
365 | unsigned long flags; | |
366 | ||
367 | spin_lock_irqsave(&pch->lock, flags); | |
368 | ||
369 | tasklet_kill(&pch->task); | |
370 | ||
371 | pl330_release_channel(pch->pl330_chid); | |
372 | pch->pl330_chid = NULL; | |
373 | ||
42bc9cf4 BK |
374 | if (pch->cyclic) |
375 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); | |
376 | ||
b3040e40 JB |
377 | spin_unlock_irqrestore(&pch->lock, flags); |
378 | } | |
379 | ||
380 | static enum dma_status | |
381 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
382 | struct dma_tx_state *txstate) | |
383 | { | |
384 | struct dma_pl330_chan *pch = to_pchan(chan); | |
385 | dma_cookie_t last_done, last_used; | |
386 | int ret; | |
387 | ||
388 | last_done = pch->completed; | |
389 | last_used = chan->cookie; | |
390 | ||
391 | ret = dma_async_is_complete(cookie, last_done, last_used); | |
392 | ||
393 | dma_set_tx_state(txstate, last_done, last_used, 0); | |
394 | ||
395 | return ret; | |
396 | } | |
397 | ||
398 | static void pl330_issue_pending(struct dma_chan *chan) | |
399 | { | |
400 | pl330_tasklet((unsigned long) to_pchan(chan)); | |
401 | } | |
402 | ||
403 | /* | |
404 | * We returned the last one of the circular list of descriptor(s) | |
405 | * from prep_xxx, so the argument to submit corresponds to the last | |
406 | * descriptor of the list. | |
407 | */ | |
408 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) | |
409 | { | |
410 | struct dma_pl330_desc *desc, *last = to_desc(tx); | |
411 | struct dma_pl330_chan *pch = to_pchan(tx->chan); | |
412 | dma_cookie_t cookie; | |
413 | unsigned long flags; | |
414 | ||
415 | spin_lock_irqsave(&pch->lock, flags); | |
416 | ||
417 | /* Assign cookies to all nodes */ | |
418 | cookie = tx->chan->cookie; | |
419 | ||
420 | while (!list_empty(&last->node)) { | |
421 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); | |
422 | ||
423 | if (++cookie < 0) | |
424 | cookie = 1; | |
425 | desc->txd.cookie = cookie; | |
426 | ||
427 | list_move_tail(&desc->node, &pch->work_list); | |
428 | } | |
429 | ||
430 | if (++cookie < 0) | |
431 | cookie = 1; | |
432 | last->txd.cookie = cookie; | |
433 | ||
434 | list_add_tail(&last->node, &pch->work_list); | |
435 | ||
436 | tx->chan->cookie = cookie; | |
437 | ||
438 | spin_unlock_irqrestore(&pch->lock, flags); | |
439 | ||
440 | return cookie; | |
441 | } | |
442 | ||
443 | static inline void _init_desc(struct dma_pl330_desc *desc) | |
444 | { | |
445 | desc->pchan = NULL; | |
446 | desc->req.x = &desc->px; | |
447 | desc->req.token = desc; | |
448 | desc->rqcfg.swap = SWAP_NO; | |
449 | desc->rqcfg.privileged = 0; | |
450 | desc->rqcfg.insnaccess = 0; | |
451 | desc->rqcfg.scctl = SCCTRL0; | |
452 | desc->rqcfg.dcctl = DCCTRL0; | |
453 | desc->req.cfg = &desc->rqcfg; | |
454 | desc->req.xfer_cb = dma_pl330_rqcb; | |
455 | desc->txd.tx_submit = pl330_tx_submit; | |
456 | ||
457 | INIT_LIST_HEAD(&desc->node); | |
458 | } | |
459 | ||
460 | /* Returns the number of descriptors added to the DMAC pool */ | |
461 | int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count) | |
462 | { | |
463 | struct dma_pl330_desc *desc; | |
464 | unsigned long flags; | |
465 | int i; | |
466 | ||
467 | if (!pdmac) | |
468 | return 0; | |
469 | ||
470 | desc = kmalloc(count * sizeof(*desc), flg); | |
471 | if (!desc) | |
472 | return 0; | |
473 | ||
474 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
475 | ||
476 | for (i = 0; i < count; i++) { | |
477 | _init_desc(&desc[i]); | |
478 | list_add_tail(&desc[i].node, &pdmac->desc_pool); | |
479 | } | |
480 | ||
481 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
482 | ||
483 | return count; | |
484 | } | |
485 | ||
486 | static struct dma_pl330_desc * | |
487 | pluck_desc(struct dma_pl330_dmac *pdmac) | |
488 | { | |
489 | struct dma_pl330_desc *desc = NULL; | |
490 | unsigned long flags; | |
491 | ||
492 | if (!pdmac) | |
493 | return NULL; | |
494 | ||
495 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
496 | ||
497 | if (!list_empty(&pdmac->desc_pool)) { | |
498 | desc = list_entry(pdmac->desc_pool.next, | |
499 | struct dma_pl330_desc, node); | |
500 | ||
501 | list_del_init(&desc->node); | |
502 | ||
503 | desc->status = PREP; | |
504 | desc->txd.callback = NULL; | |
505 | } | |
506 | ||
507 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
508 | ||
509 | return desc; | |
510 | } | |
511 | ||
512 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) | |
513 | { | |
514 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
cd072515 | 515 | u8 *peri_id = pch->chan.private; |
b3040e40 JB |
516 | struct dma_pl330_desc *desc; |
517 | ||
518 | /* Pluck one desc from the pool of DMAC */ | |
519 | desc = pluck_desc(pdmac); | |
520 | ||
521 | /* If the DMAC pool is empty, alloc new */ | |
522 | if (!desc) { | |
523 | if (!add_desc(pdmac, GFP_ATOMIC, 1)) | |
524 | return NULL; | |
525 | ||
526 | /* Try again */ | |
527 | desc = pluck_desc(pdmac); | |
528 | if (!desc) { | |
529 | dev_err(pch->dmac->pif.dev, | |
530 | "%s:%d ALERT!\n", __func__, __LINE__); | |
531 | return NULL; | |
532 | } | |
533 | } | |
534 | ||
535 | /* Initialize the descriptor */ | |
536 | desc->pchan = pch; | |
537 | desc->txd.cookie = 0; | |
538 | async_tx_ack(&desc->txd); | |
539 | ||
cd072515 | 540 | desc->req.peri = peri_id ? pch->chan.chan_id : 0; |
b3040e40 JB |
541 | |
542 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); | |
543 | ||
544 | return desc; | |
545 | } | |
546 | ||
547 | static inline void fill_px(struct pl330_xfer *px, | |
548 | dma_addr_t dst, dma_addr_t src, size_t len) | |
549 | { | |
550 | px->next = NULL; | |
551 | px->bytes = len; | |
552 | px->dst_addr = dst; | |
553 | px->src_addr = src; | |
554 | } | |
555 | ||
556 | static struct dma_pl330_desc * | |
557 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, | |
558 | dma_addr_t src, size_t len) | |
559 | { | |
560 | struct dma_pl330_desc *desc = pl330_get_desc(pch); | |
561 | ||
562 | if (!desc) { | |
563 | dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", | |
564 | __func__, __LINE__); | |
565 | return NULL; | |
566 | } | |
567 | ||
568 | /* | |
569 | * Ideally we should lookout for reqs bigger than | |
570 | * those that can be programmed with 256 bytes of | |
571 | * MC buffer, but considering a req size is seldom | |
572 | * going to be word-unaligned and more than 200MB, | |
573 | * we take it easy. | |
574 | * Also, should the limit is reached we'd rather | |
575 | * have the platform increase MC buffer size than | |
576 | * complicating this API driver. | |
577 | */ | |
578 | fill_px(&desc->px, dst, src, len); | |
579 | ||
580 | return desc; | |
581 | } | |
582 | ||
583 | /* Call after fixing burst size */ | |
584 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) | |
585 | { | |
586 | struct dma_pl330_chan *pch = desc->pchan; | |
587 | struct pl330_info *pi = &pch->dmac->pif; | |
588 | int burst_len; | |
589 | ||
590 | burst_len = pi->pcfg.data_bus_width / 8; | |
591 | burst_len *= pi->pcfg.data_buf_dep; | |
592 | burst_len >>= desc->rqcfg.brst_size; | |
593 | ||
594 | /* src/dst_burst_len can't be more than 16 */ | |
595 | if (burst_len > 16) | |
596 | burst_len = 16; | |
597 | ||
598 | while (burst_len > 1) { | |
599 | if (!(len % (burst_len << desc->rqcfg.brst_size))) | |
600 | break; | |
601 | burst_len--; | |
602 | } | |
603 | ||
604 | return burst_len; | |
605 | } | |
606 | ||
42bc9cf4 BK |
607 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
608 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, | |
609 | size_t period_len, enum dma_data_direction direction) | |
610 | { | |
611 | struct dma_pl330_desc *desc; | |
612 | struct dma_pl330_chan *pch = to_pchan(chan); | |
613 | dma_addr_t dst; | |
614 | dma_addr_t src; | |
615 | ||
616 | desc = pl330_get_desc(pch); | |
617 | if (!desc) { | |
618 | dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", | |
619 | __func__, __LINE__); | |
620 | return NULL; | |
621 | } | |
622 | ||
623 | switch (direction) { | |
624 | case DMA_TO_DEVICE: | |
625 | desc->rqcfg.src_inc = 1; | |
626 | desc->rqcfg.dst_inc = 0; | |
cd072515 | 627 | desc->req.rqtype = MEMTODEV; |
42bc9cf4 BK |
628 | src = dma_addr; |
629 | dst = pch->fifo_addr; | |
630 | break; | |
631 | case DMA_FROM_DEVICE: | |
632 | desc->rqcfg.src_inc = 0; | |
633 | desc->rqcfg.dst_inc = 1; | |
cd072515 | 634 | desc->req.rqtype = DEVTOMEM; |
42bc9cf4 BK |
635 | src = pch->fifo_addr; |
636 | dst = dma_addr; | |
637 | break; | |
638 | default: | |
639 | dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n", | |
640 | __func__, __LINE__); | |
641 | return NULL; | |
642 | } | |
643 | ||
644 | desc->rqcfg.brst_size = pch->burst_sz; | |
645 | desc->rqcfg.brst_len = 1; | |
646 | ||
647 | pch->cyclic = true; | |
648 | ||
649 | fill_px(&desc->px, dst, src, period_len); | |
650 | ||
651 | return &desc->txd; | |
652 | } | |
653 | ||
b3040e40 JB |
654 | static struct dma_async_tx_descriptor * |
655 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, | |
656 | dma_addr_t src, size_t len, unsigned long flags) | |
657 | { | |
658 | struct dma_pl330_desc *desc; | |
659 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 JB |
660 | struct pl330_info *pi; |
661 | int burst; | |
662 | ||
4e0e6109 | 663 | if (unlikely(!pch || !len)) |
b3040e40 JB |
664 | return NULL; |
665 | ||
b3040e40 JB |
666 | pi = &pch->dmac->pif; |
667 | ||
668 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); | |
669 | if (!desc) | |
670 | return NULL; | |
671 | ||
672 | desc->rqcfg.src_inc = 1; | |
673 | desc->rqcfg.dst_inc = 1; | |
cd072515 | 674 | desc->req.rqtype = MEMTOMEM; |
b3040e40 JB |
675 | |
676 | /* Select max possible burst size */ | |
677 | burst = pi->pcfg.data_bus_width / 8; | |
678 | ||
679 | while (burst > 1) { | |
680 | if (!(len % burst)) | |
681 | break; | |
682 | burst /= 2; | |
683 | } | |
684 | ||
685 | desc->rqcfg.brst_size = 0; | |
686 | while (burst != (1 << desc->rqcfg.brst_size)) | |
687 | desc->rqcfg.brst_size++; | |
688 | ||
689 | desc->rqcfg.brst_len = get_burst_len(desc, len); | |
690 | ||
691 | desc->txd.flags = flags; | |
692 | ||
693 | return &desc->txd; | |
694 | } | |
695 | ||
696 | static struct dma_async_tx_descriptor * | |
697 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
698 | unsigned int sg_len, enum dma_data_direction direction, | |
699 | unsigned long flg) | |
700 | { | |
701 | struct dma_pl330_desc *first, *desc = NULL; | |
702 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 JB |
703 | struct scatterlist *sg; |
704 | unsigned long flags; | |
1b9bb715 | 705 | int i; |
b3040e40 JB |
706 | dma_addr_t addr; |
707 | ||
cd072515 | 708 | if (unlikely(!pch || !sgl || !sg_len)) |
b3040e40 | 709 | return NULL; |
b3040e40 | 710 | |
1b9bb715 | 711 | addr = pch->fifo_addr; |
b3040e40 JB |
712 | |
713 | first = NULL; | |
714 | ||
715 | for_each_sg(sgl, sg, sg_len, i) { | |
716 | ||
717 | desc = pl330_get_desc(pch); | |
718 | if (!desc) { | |
719 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
720 | ||
721 | dev_err(pch->dmac->pif.dev, | |
722 | "%s:%d Unable to fetch desc\n", | |
723 | __func__, __LINE__); | |
724 | if (!first) | |
725 | return NULL; | |
726 | ||
727 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
728 | ||
729 | while (!list_empty(&first->node)) { | |
730 | desc = list_entry(first->node.next, | |
731 | struct dma_pl330_desc, node); | |
732 | list_move_tail(&desc->node, &pdmac->desc_pool); | |
733 | } | |
734 | ||
735 | list_move_tail(&first->node, &pdmac->desc_pool); | |
736 | ||
737 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
738 | ||
739 | return NULL; | |
740 | } | |
741 | ||
742 | if (!first) | |
743 | first = desc; | |
744 | else | |
745 | list_add_tail(&desc->node, &first->node); | |
746 | ||
747 | if (direction == DMA_TO_DEVICE) { | |
748 | desc->rqcfg.src_inc = 1; | |
749 | desc->rqcfg.dst_inc = 0; | |
cd072515 | 750 | desc->req.rqtype = MEMTODEV; |
b3040e40 JB |
751 | fill_px(&desc->px, |
752 | addr, sg_dma_address(sg), sg_dma_len(sg)); | |
753 | } else { | |
754 | desc->rqcfg.src_inc = 0; | |
755 | desc->rqcfg.dst_inc = 1; | |
cd072515 | 756 | desc->req.rqtype = DEVTOMEM; |
b3040e40 JB |
757 | fill_px(&desc->px, |
758 | sg_dma_address(sg), addr, sg_dma_len(sg)); | |
759 | } | |
760 | ||
1b9bb715 | 761 | desc->rqcfg.brst_size = pch->burst_sz; |
b3040e40 JB |
762 | desc->rqcfg.brst_len = 1; |
763 | } | |
764 | ||
765 | /* Return the last desc in the chain */ | |
766 | desc->txd.flags = flg; | |
767 | return &desc->txd; | |
768 | } | |
769 | ||
770 | static irqreturn_t pl330_irq_handler(int irq, void *data) | |
771 | { | |
772 | if (pl330_update(data)) | |
773 | return IRQ_HANDLED; | |
774 | else | |
775 | return IRQ_NONE; | |
776 | } | |
777 | ||
778 | static int __devinit | |
aa25afad | 779 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
b3040e40 JB |
780 | { |
781 | struct dma_pl330_platdata *pdat; | |
782 | struct dma_pl330_dmac *pdmac; | |
783 | struct dma_pl330_chan *pch; | |
784 | struct pl330_info *pi; | |
785 | struct dma_device *pd; | |
786 | struct resource *res; | |
787 | int i, ret, irq; | |
4e0e6109 | 788 | int num_chan; |
b3040e40 JB |
789 | |
790 | pdat = adev->dev.platform_data; | |
791 | ||
b3040e40 | 792 | /* Allocate a new DMAC and its Channels */ |
4e0e6109 | 793 | pdmac = kzalloc(sizeof(*pdmac), GFP_KERNEL); |
b3040e40 JB |
794 | if (!pdmac) { |
795 | dev_err(&adev->dev, "unable to allocate mem\n"); | |
796 | return -ENOMEM; | |
797 | } | |
798 | ||
799 | pi = &pdmac->pif; | |
800 | pi->dev = &adev->dev; | |
801 | pi->pl330_data = NULL; | |
4e0e6109 | 802 | pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0; |
b3040e40 JB |
803 | |
804 | res = &adev->res; | |
805 | request_mem_region(res->start, resource_size(res), "dma-pl330"); | |
806 | ||
807 | pi->base = ioremap(res->start, resource_size(res)); | |
808 | if (!pi->base) { | |
809 | ret = -ENXIO; | |
810 | goto probe_err1; | |
811 | } | |
812 | ||
a2f5203f BK |
813 | pdmac->clk = clk_get(&adev->dev, "dma"); |
814 | if (IS_ERR(pdmac->clk)) { | |
815 | dev_err(&adev->dev, "Cannot get operation clock.\n"); | |
816 | ret = -EINVAL; | |
817 | goto probe_err1; | |
818 | } | |
819 | ||
820 | amba_set_drvdata(adev, pdmac); | |
821 | ||
822 | #ifdef CONFIG_PM_RUNTIME | |
823 | /* to use the runtime PM helper functions */ | |
824 | pm_runtime_enable(&adev->dev); | |
825 | ||
826 | /* enable the power domain */ | |
827 | if (pm_runtime_get_sync(&adev->dev)) { | |
828 | dev_err(&adev->dev, "failed to get runtime pm\n"); | |
829 | ret = -ENODEV; | |
830 | goto probe_err1; | |
831 | } | |
832 | #else | |
833 | /* enable dma clk */ | |
834 | clk_enable(pdmac->clk); | |
835 | #endif | |
836 | ||
b3040e40 JB |
837 | irq = adev->irq[0]; |
838 | ret = request_irq(irq, pl330_irq_handler, 0, | |
839 | dev_name(&adev->dev), pi); | |
840 | if (ret) | |
841 | goto probe_err2; | |
842 | ||
843 | ret = pl330_add(pi); | |
844 | if (ret) | |
845 | goto probe_err3; | |
846 | ||
847 | INIT_LIST_HEAD(&pdmac->desc_pool); | |
848 | spin_lock_init(&pdmac->pool_lock); | |
849 | ||
850 | /* Create a descriptor pool of default size */ | |
851 | if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC)) | |
852 | dev_warn(&adev->dev, "unable to allocate desc\n"); | |
853 | ||
854 | pd = &pdmac->ddma; | |
855 | INIT_LIST_HEAD(&pd->channels); | |
856 | ||
857 | /* Initialize channel parameters */ | |
4e0e6109 RH |
858 | num_chan = max(pdat ? pdat->nr_valid_peri : 0, (u8)pi->pcfg.num_chan); |
859 | pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); | |
b3040e40 | 860 | |
4e0e6109 RH |
861 | for (i = 0; i < num_chan; i++) { |
862 | pch = &pdmac->peripherals[i]; | |
cd072515 | 863 | pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; |
b3040e40 JB |
864 | INIT_LIST_HEAD(&pch->work_list); |
865 | spin_lock_init(&pch->lock); | |
866 | pch->pl330_chid = NULL; | |
b3040e40 | 867 | pch->chan.device = pd; |
b3040e40 JB |
868 | pch->dmac = pdmac; |
869 | ||
870 | /* Add the channel to the DMAC list */ | |
b3040e40 JB |
871 | list_add_tail(&pch->chan.device_node, &pd->channels); |
872 | } | |
873 | ||
874 | pd->dev = &adev->dev; | |
cd072515 TA |
875 | if (pdat) |
876 | pd->cap_mask = pdat->cap_mask; | |
877 | else | |
878 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); | |
b3040e40 JB |
879 | |
880 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; | |
881 | pd->device_free_chan_resources = pl330_free_chan_resources; | |
882 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; | |
42bc9cf4 | 883 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
b3040e40 JB |
884 | pd->device_tx_status = pl330_tx_status; |
885 | pd->device_prep_slave_sg = pl330_prep_slave_sg; | |
886 | pd->device_control = pl330_control; | |
887 | pd->device_issue_pending = pl330_issue_pending; | |
888 | ||
889 | ret = dma_async_device_register(pd); | |
890 | if (ret) { | |
891 | dev_err(&adev->dev, "unable to register DMAC\n"); | |
892 | goto probe_err4; | |
893 | } | |
894 | ||
b3040e40 JB |
895 | dev_info(&adev->dev, |
896 | "Loaded driver for PL330 DMAC-%d\n", adev->periphid); | |
897 | dev_info(&adev->dev, | |
898 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | |
899 | pi->pcfg.data_buf_dep, | |
900 | pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan, | |
901 | pi->pcfg.num_peri, pi->pcfg.num_events); | |
902 | ||
903 | return 0; | |
904 | ||
905 | probe_err4: | |
906 | pl330_del(pi); | |
907 | probe_err3: | |
908 | free_irq(irq, pi); | |
909 | probe_err2: | |
910 | iounmap(pi->base); | |
911 | probe_err1: | |
912 | release_mem_region(res->start, resource_size(res)); | |
913 | kfree(pdmac); | |
914 | ||
915 | return ret; | |
916 | } | |
917 | ||
918 | static int __devexit pl330_remove(struct amba_device *adev) | |
919 | { | |
920 | struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev); | |
921 | struct dma_pl330_chan *pch, *_p; | |
922 | struct pl330_info *pi; | |
923 | struct resource *res; | |
924 | int irq; | |
925 | ||
926 | if (!pdmac) | |
927 | return 0; | |
928 | ||
929 | amba_set_drvdata(adev, NULL); | |
930 | ||
931 | /* Idle the DMAC */ | |
932 | list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels, | |
933 | chan.device_node) { | |
934 | ||
935 | /* Remove the channel */ | |
936 | list_del(&pch->chan.device_node); | |
937 | ||
938 | /* Flush the channel */ | |
939 | pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); | |
940 | pl330_free_chan_resources(&pch->chan); | |
941 | } | |
942 | ||
943 | pi = &pdmac->pif; | |
944 | ||
945 | pl330_del(pi); | |
946 | ||
947 | irq = adev->irq[0]; | |
948 | free_irq(irq, pi); | |
949 | ||
950 | iounmap(pi->base); | |
951 | ||
952 | res = &adev->res; | |
953 | release_mem_region(res->start, resource_size(res)); | |
954 | ||
a2f5203f BK |
955 | #ifdef CONFIG_PM_RUNTIME |
956 | pm_runtime_put(&adev->dev); | |
957 | pm_runtime_disable(&adev->dev); | |
958 | #else | |
959 | clk_disable(pdmac->clk); | |
960 | #endif | |
961 | ||
b3040e40 JB |
962 | kfree(pdmac); |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
967 | static struct amba_id pl330_ids[] = { | |
968 | { | |
969 | .id = 0x00041330, | |
970 | .mask = 0x000fffff, | |
971 | }, | |
972 | { 0, 0 }, | |
973 | }; | |
974 | ||
a2f5203f BK |
975 | #ifdef CONFIG_PM_RUNTIME |
976 | static int pl330_runtime_suspend(struct device *dev) | |
977 | { | |
978 | struct dma_pl330_dmac *pdmac = dev_get_drvdata(dev); | |
979 | ||
980 | if (!pdmac) { | |
981 | dev_err(dev, "failed to get dmac\n"); | |
982 | return -ENODEV; | |
983 | } | |
984 | ||
985 | clk_disable(pdmac->clk); | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
990 | static int pl330_runtime_resume(struct device *dev) | |
991 | { | |
992 | struct dma_pl330_dmac *pdmac = dev_get_drvdata(dev); | |
993 | ||
994 | if (!pdmac) { | |
995 | dev_err(dev, "failed to get dmac\n"); | |
996 | return -ENODEV; | |
997 | } | |
998 | ||
999 | clk_enable(pdmac->clk); | |
1000 | ||
1001 | return 0; | |
1002 | } | |
1003 | #else | |
1004 | #define pl330_runtime_suspend NULL | |
1005 | #define pl330_runtime_resume NULL | |
1006 | #endif /* CONFIG_PM_RUNTIME */ | |
1007 | ||
1008 | static const struct dev_pm_ops pl330_pm_ops = { | |
1009 | .runtime_suspend = pl330_runtime_suspend, | |
1010 | .runtime_resume = pl330_runtime_resume, | |
1011 | }; | |
1012 | ||
b3040e40 JB |
1013 | static struct amba_driver pl330_driver = { |
1014 | .drv = { | |
1015 | .owner = THIS_MODULE, | |
1016 | .name = "dma-pl330", | |
a2f5203f | 1017 | .pm = &pl330_pm_ops, |
b3040e40 JB |
1018 | }, |
1019 | .id_table = pl330_ids, | |
1020 | .probe = pl330_probe, | |
1021 | .remove = pl330_remove, | |
1022 | }; | |
1023 | ||
1024 | static int __init pl330_init(void) | |
1025 | { | |
1026 | return amba_driver_register(&pl330_driver); | |
1027 | } | |
1028 | module_init(pl330_init); | |
1029 | ||
1030 | static void __exit pl330_exit(void) | |
1031 | { | |
1032 | amba_driver_unregister(&pl330_driver); | |
1033 | return; | |
1034 | } | |
1035 | module_exit(pl330_exit); | |
1036 | ||
1037 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
1038 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); | |
1039 | MODULE_LICENSE("GPL"); |