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dmaengine: consolidate assignment of DMA cookies
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / intel_mid_dma.c
CommitLineData
b3c567e4
VK		 1/*
2 * intel_mid_dma.c - Intel Langwell DMA Drivers
3 *
4 * Copyright (C) 2008-10 Intel Corp
5 * Author: Vinod Koul <vinod.koul@intel.com>
6 * The driver design is based on dw_dmac driver
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 *
22 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
23 *
24 *
25 */
26#include <linux/pci.h>
27#include <linux/interrupt.h>
53a61bad 28#include <linux/pm_runtime.h>
b3c567e4 29#include <linux/intel_mid_dma.h>
7c52d551 30#include <linux/module.h>
b3c567e4 31
d2ebfb33
RKAL		 32#include "dmaengine.h"
33
b3c567e4
VK		 34#define MAX_CHAN 4 /*max ch across controllers*/
35#include "intel_mid_dma_regs.h"
36
37#define INTEL_MID_DMAC1_ID 0x0814
38#define INTEL_MID_DMAC2_ID 0x0813
39#define INTEL_MID_GP_DMAC2_ID 0x0827
40#define INTEL_MFLD_DMAC1_ID 0x0830
41#define LNW_PERIPHRAL_MASK_BASE 0xFFAE8008
42#define LNW_PERIPHRAL_MASK_SIZE 0x10
43#define LNW_PERIPHRAL_STATUS 0x0
44#define LNW_PERIPHRAL_MASK 0x8
45
46struct intel_mid_dma_probe_info {
47 u8 max_chan;
48 u8 ch_base;
49 u16 block_size;
50 u32 pimr_mask;
51};
52
53#define INFO(_max_chan, _ch_base, _block_size, _pimr_mask) \
54 ((kernel_ulong_t)&(struct intel_mid_dma_probe_info) { \
55 .max_chan = (_max_chan), \
56 .ch_base = (_ch_base), \
57 .block_size = (_block_size), \
58 .pimr_mask = (_pimr_mask), \
59 })
60
61/*****************************************************************************
62Utility Functions*/
63/**
64 * get_ch_index - convert status to channel
65 * @status: status mask
66 * @base: dma ch base value
67 *
68 * Modify the status mask and return the channel index needing
69 * attention (or -1 if neither)
70 */
71static int get_ch_index(int *status, unsigned int base)
72{
73 int i;
74 for (i = 0; i < MAX_CHAN; i++) {
75 if (*status & (1 << (i + base))) {
76 *status = *status & ~(1 << (i + base));
77 pr_debug("MDMA: index %d New status %x\n", i, *status);
78 return i;
79 }
80 }
81 return -1;
82}
83
84/**
85 * get_block_ts - calculates dma transaction length
86 * @len: dma transfer length
87 * @tx_width: dma transfer src width
88 * @block_size: dma controller max block size
89 *
90 * Based on src width calculate the DMA trsaction length in data items
91 * return data items or FFFF if exceeds max length for block
92 */
93static int get_block_ts(int len, int tx_width, int block_size)
94{
95 int byte_width = 0, block_ts = 0;
96
97 switch (tx_width) {
20dd6390 98 case DMA_SLAVE_BUSWIDTH_1_BYTE:
b3c567e4
VK		 99 byte_width = 1;
100 break;
20dd6390 101 case DMA_SLAVE_BUSWIDTH_2_BYTES:
b3c567e4
VK		 102 byte_width = 2;
103 break;
20dd6390 104 case DMA_SLAVE_BUSWIDTH_4_BYTES:
b3c567e4
VK		 105 default:
106 byte_width = 4;
107 break;
108 }
109
110 block_ts = len/byte_width;
111 if (block_ts > block_size)
112 block_ts = 0xFFFF;
113 return block_ts;
114}
115
116/*****************************************************************************
117DMAC1 interrupt Functions*/
118
119/**
120 * dmac1_mask_periphral_intr - mask the periphral interrupt
4598fc2c 121 * @mid: dma device for which masking is required
b3c567e4
VK		 122 *
123 * Masks the DMA periphral interrupt
124 * this is valid for DMAC1 family controllers only
125 * This controller should have periphral mask registers already mapped
126 */
4598fc2c 127static void dmac1_mask_periphral_intr(struct middma_device *mid)
b3c567e4
VK		 128{
129 u32 pimr;
b3c567e4
VK		 130
131 if (mid->pimr_mask) {
132 pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK);
133 pimr |= mid->pimr_mask;
134 writel(pimr, mid->mask_reg + LNW_PERIPHRAL_MASK);
135 }
136 return;
137}
138
139/**
140 * dmac1_unmask_periphral_intr - unmask the periphral interrupt
141 * @midc: dma channel for which masking is required
142 *
143 * UnMasks the DMA periphral interrupt,
144 * this is valid for DMAC1 family controllers only
145 * This controller should have periphral mask registers already mapped
146 */
147static void dmac1_unmask_periphral_intr(struct intel_mid_dma_chan *midc)
148{
149 u32 pimr;
150 struct middma_device *mid = to_middma_device(midc->chan.device);
151
152 if (mid->pimr_mask) {
153 pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK);
154 pimr &= ~mid->pimr_mask;
155 writel(pimr, mid->mask_reg + LNW_PERIPHRAL_MASK);
156 }
157 return;
158}
159
160/**
161 * enable_dma_interrupt - enable the periphral interrupt
162 * @midc: dma channel for which enable interrupt is required
163 *
164 * Enable the DMA periphral interrupt,
165 * this is valid for DMAC1 family controllers only
166 * This controller should have periphral mask registers already mapped
167 */
168static void enable_dma_interrupt(struct intel_mid_dma_chan *midc)
169{
170 dmac1_unmask_periphral_intr(midc);
171
172 /*en ch interrupts*/
173 iowrite32(UNMASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR);
174 iowrite32(UNMASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR);
175 return;
176}
177
178/**
179 * disable_dma_interrupt - disable the periphral interrupt
180 * @midc: dma channel for which disable interrupt is required
181 *
182 * Disable the DMA periphral interrupt,
183 * this is valid for DMAC1 family controllers only
184 * This controller should have periphral mask registers already mapped
185 */
186static void disable_dma_interrupt(struct intel_mid_dma_chan *midc)
187{
188 /*Check LPE PISR, make sure fwd is disabled*/
b3c567e4
VK		 189 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_BLOCK);
190 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR);
191 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR);
192 return;
193}
194
195/*****************************************************************************
196DMA channel helper Functions*/
197/**
198 * mid_desc_get - get a descriptor
199 * @midc: dma channel for which descriptor is required
200 *
201 * Obtain a descriptor for the channel. Returns NULL if none are free.
202 * Once the descriptor is returned it is private until put on another
203 * list or freed
204 */
205static struct intel_mid_dma_desc *midc_desc_get(struct intel_mid_dma_chan *midc)
206{
207 struct intel_mid_dma_desc *desc, *_desc;
208 struct intel_mid_dma_desc *ret = NULL;
209
210 spin_lock_bh(&midc->lock);
211 list_for_each_entry_safe(desc, _desc, &midc->free_list, desc_node) {
212 if (async_tx_test_ack(&desc->txd)) {
213 list_del(&desc->desc_node);
214 ret = desc;
215 break;
216 }
217 }
218 spin_unlock_bh(&midc->lock);
219 return ret;
220}
221
222/**
223 * mid_desc_put - put a descriptor
224 * @midc: dma channel for which descriptor is required
225 * @desc: descriptor to put
226 *
227 * Return a descriptor from lwn_desc_get back to the free pool
228 */
229static void midc_desc_put(struct intel_mid_dma_chan *midc,
230 struct intel_mid_dma_desc *desc)
231{
232 if (desc) {
233 spin_lock_bh(&midc->lock);
234 list_add_tail(&desc->desc_node, &midc->free_list);
235 spin_unlock_bh(&midc->lock);
236 }
237}
238/**
239 * midc_dostart - begin a DMA transaction
240 * @midc: channel for which txn is to be started
241 * @first: first descriptor of series
242 *
243 * Load a transaction into the engine. This must be called with midc->lock
244 * held and bh disabled.
245 */
246static void midc_dostart(struct intel_mid_dma_chan *midc,
247 struct intel_mid_dma_desc *first)
248{
249 struct middma_device *mid = to_middma_device(midc->chan.device);
250
251 /* channel is idle */
53a61bad 252 if (midc->busy && test_ch_en(midc->dma_base, midc->ch_id)) {
b3c567e4
VK		 253 /*error*/
254 pr_err("ERR_MDMA: channel is busy in start\n");
255 /* The tasklet will hopefully advance the queue... */
256 return;
257 }
53a61bad 258 midc->busy = true;
b3c567e4
VK		 259 /*write registers and en*/
260 iowrite32(first->sar, midc->ch_regs + SAR);
261 iowrite32(first->dar, midc->ch_regs + DAR);
576e3c39 262 iowrite32(first->lli_phys, midc->ch_regs + LLP);
b3c567e4
VK		 263 iowrite32(first->cfg_hi, midc->ch_regs + CFG_HIGH);
264 iowrite32(first->cfg_lo, midc->ch_regs + CFG_LOW);
265 iowrite32(first->ctl_lo, midc->ch_regs + CTL_LOW);
266 iowrite32(first->ctl_hi, midc->ch_regs + CTL_HIGH);
267 pr_debug("MDMA:TX SAR %x,DAR %x,CFGL %x,CFGH %x,CTLH %x, CTLL %x\n",
268 (int)first->sar, (int)first->dar, first->cfg_hi,
269 first->cfg_lo, first->ctl_hi, first->ctl_lo);
576e3c39 270 first->status = DMA_IN_PROGRESS;
b3c567e4
VK		 271
272 iowrite32(ENABLE_CHANNEL(midc->ch_id), mid->dma_base + DMA_CHAN_EN);
b3c567e4
VK		 273}
274
275/**
276 * midc_descriptor_complete - process completed descriptor
277 * @midc: channel owning the descriptor
278 * @desc: the descriptor itself
279 *
280 * Process a completed descriptor and perform any callbacks upon
281 * the completion. The completion handling drops the lock during the
282 * callbacks but must be called with the lock held.
283 */
284static void midc_descriptor_complete(struct intel_mid_dma_chan *midc,
1fded075
AH		 285 struct intel_mid_dma_desc *desc)
286 __releases(&midc->lock) __acquires(&midc->lock)
b3c567e4
VK		 287{
288 struct dma_async_tx_descriptor *txd = &desc->txd;
289 dma_async_tx_callback callback_txd = NULL;
576e3c39 290 struct intel_mid_dma_lli *llitem;
b3c567e4
VK		 291 void *param_txd = NULL;
292
4d4e58de 293 midc->chan.completed_cookie = txd->cookie;
b3c567e4
VK		 294 callback_txd = txd->callback;
295 param_txd = txd->callback_param;
296
576e3c39
RB		 297 if (desc->lli != NULL) {
298 /*clear the DONE bit of completed LLI in memory*/
299 llitem = desc->lli + desc->current_lli;
300 llitem->ctl_hi &= CLEAR_DONE;
301 if (desc->current_lli < desc->lli_length-1)
302 (desc->current_lli)++;
303 else
304 desc->current_lli = 0;
305 }
b3c567e4
VK		 306 spin_unlock_bh(&midc->lock);
307 if (callback_txd) {
308 pr_debug("MDMA: TXD callback set ... calling\n");
309 callback_txd(param_txd);
576e3c39
RB		 310 }
311 if (midc->raw_tfr) {
312 desc->status = DMA_SUCCESS;
313 if (desc->lli != NULL) {
314 pci_pool_free(desc->lli_pool, desc->lli,
315 desc->lli_phys);
316 pci_pool_destroy(desc->lli_pool);
1fded075 317 desc->lli = NULL;
576e3c39
RB		 318 }
319 list_move(&desc->desc_node, &midc->free_list);
320 midc->busy = false;
b3c567e4
VK		 321 }
322 spin_lock_bh(&midc->lock);
323
324}
325/**
326 * midc_scan_descriptors - check the descriptors in channel
327 * mark completed when tx is completete
328 * @mid: device
329 * @midc: channel to scan
330 *
331 * Walk the descriptor chain for the device and process any entries
332 * that are complete.
333 */
334static void midc_scan_descriptors(struct middma_device *mid,
335 struct intel_mid_dma_chan *midc)
336{
337 struct intel_mid_dma_desc *desc = NULL, *_desc = NULL;
338
339 /*tx is complete*/
340 list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
576e3c39 341 if (desc->status == DMA_IN_PROGRESS)
b3c567e4 342 midc_descriptor_complete(midc, desc);
b3c567e4
VK		 343 }
344 return;
576e3c39
RB		 345 }
346/**
347 * midc_lli_fill_sg - Helper function to convert
348 * SG list to Linked List Items.
349 *@midc: Channel
350 *@desc: DMA descriptor
351 *@sglist: Pointer to SG list
352 *@sglen: SG list length
353 *@flags: DMA transaction flags
354 *
355 * Walk through the SG list and convert the SG list into Linked
356 * List Items (LLI).
357 */
358static int midc_lli_fill_sg(struct intel_mid_dma_chan *midc,
359 struct intel_mid_dma_desc *desc,
360 struct scatterlist *sglist,
361 unsigned int sglen,
362 unsigned int flags)
363{
364 struct intel_mid_dma_slave *mids;
365 struct scatterlist *sg;
366 dma_addr_t lli_next, sg_phy_addr;
367 struct intel_mid_dma_lli *lli_bloc_desc;
368 union intel_mid_dma_ctl_lo ctl_lo;
369 union intel_mid_dma_ctl_hi ctl_hi;
370 int i;
371
372 pr_debug("MDMA: Entered midc_lli_fill_sg\n");
20dd6390 373 mids = midc->mid_slave;
576e3c39
RB		 374
375 lli_bloc_desc = desc->lli;
376 lli_next = desc->lli_phys;
b3c567e4 377
576e3c39
RB		 378 ctl_lo.ctl_lo = desc->ctl_lo;
379 ctl_hi.ctl_hi = desc->ctl_hi;
380 for_each_sg(sglist, sg, sglen, i) {
381 /*Populate CTL_LOW and LLI values*/
382 if (i != sglen - 1) {
383 lli_next = lli_next +
384 sizeof(struct intel_mid_dma_lli);
385 } else {
386 /*Check for circular list, otherwise terminate LLI to ZERO*/
387 if (flags & DMA_PREP_CIRCULAR_LIST) {
388 pr_debug("MDMA: LLI is configured in circular mode\n");
389 lli_next = desc->lli_phys;
390 } else {
391 lli_next = 0;
392 ctl_lo.ctlx.llp_dst_en = 0;
393 ctl_lo.ctlx.llp_src_en = 0;
394 }
395 }
396 /*Populate CTL_HI values*/
397 ctl_hi.ctlx.block_ts = get_block_ts(sg->length,
398 desc->width,
399 midc->dma->block_size);
400 /*Populate SAR and DAR values*/
401 sg_phy_addr = sg_phys(sg);
db8196df 402 if (desc->dirn == DMA_MEM_TO_DEV) {
576e3c39 403 lli_bloc_desc->sar = sg_phy_addr;
20dd6390 404 lli_bloc_desc->dar = mids->dma_slave.dst_addr;
db8196df 405 } else if (desc->dirn == DMA_DEV_TO_MEM) {
20dd6390 406 lli_bloc_desc->sar = mids->dma_slave.src_addr;
576e3c39
RB		 407 lli_bloc_desc->dar = sg_phy_addr;
408 }
409 /*Copy values into block descriptor in system memroy*/
410 lli_bloc_desc->llp = lli_next;
411 lli_bloc_desc->ctl_lo = ctl_lo.ctl_lo;
412 lli_bloc_desc->ctl_hi = ctl_hi.ctl_hi;
413
414 lli_bloc_desc++;
415 }
416 /*Copy very first LLI values to descriptor*/
417 desc->ctl_lo = desc->lli->ctl_lo;
418 desc->ctl_hi = desc->lli->ctl_hi;
419 desc->sar = desc->lli->sar;
420 desc->dar = desc->lli->dar;
421
422 return 0;
423}
b3c567e4
VK		 424/*****************************************************************************
425DMA engine callback Functions*/
426/**
427 * intel_mid_dma_tx_submit - callback to submit DMA transaction
428 * @tx: dma engine descriptor
429 *
430 * Submit the DMA trasaction for this descriptor, start if ch idle
431 */
432static dma_cookie_t intel_mid_dma_tx_submit(struct dma_async_tx_descriptor *tx)
433{
434 struct intel_mid_dma_desc *desc = to_intel_mid_dma_desc(tx);
435 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(tx->chan);
436 dma_cookie_t cookie;
437
438 spin_lock_bh(&midc->lock);
884485e1 439 cookie = dma_cookie_assign(tx);
b3c567e4 440
576e3c39 441 if (list_empty(&midc->active_list))
b3c567e4 442 list_add_tail(&desc->desc_node, &midc->active_list);
576e3c39 443 else
b3c567e4 444 list_add_tail(&desc->desc_node, &midc->queue);
576e3c39
RB		 445
446 midc_dostart(midc, desc);
b3c567e4
VK		 447 spin_unlock_bh(&midc->lock);
448
449 return cookie;
450}
451
452/**
453 * intel_mid_dma_issue_pending - callback to issue pending txn
454 * @chan: chan where pending trascation needs to be checked and submitted
455 *
456 * Call for scan to issue pending descriptors
457 */
458static void intel_mid_dma_issue_pending(struct dma_chan *chan)
459{
460 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
461
462 spin_lock_bh(&midc->lock);
463 if (!list_empty(&midc->queue))
464 midc_scan_descriptors(to_middma_device(chan->device), midc);
465 spin_unlock_bh(&midc->lock);
466}
467
468/**
469 * intel_mid_dma_tx_status - Return status of txn
470 * @chan: chan for where status needs to be checked
471 * @cookie: cookie for txn
472 * @txstate: DMA txn state
473 *
474 * Return status of DMA txn
475 */
476static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
477 dma_cookie_t cookie,
478 struct dma_tx_state *txstate)
479{
b3c567e4
VK		 480 dma_cookie_t last_used;
481 dma_cookie_t last_complete;
482 int ret;
483
4d4e58de 484 last_complete = chan->completed_cookie;
b3c567e4
VK		 485 last_used = chan->cookie;
486
487 ret = dma_async_is_complete(cookie, last_complete, last_used);
488 if (ret != DMA_SUCCESS) {
1fded075 489 spin_lock_bh(&midc->lock);
b3c567e4 490 midc_scan_descriptors(to_middma_device(chan->device), midc);
1fded075 491 spin_unlock_bh(&midc->lock);
b3c567e4 492
4d4e58de 493 last_complete = chan->completed_cookie;
b3c567e4
VK		 494 last_used = chan->cookie;
495
496 ret = dma_async_is_complete(cookie, last_complete, last_used);
497 }
498
499 if (txstate) {
500 txstate->last = last_complete;
501 txstate->used = last_used;
502 txstate->residue = 0;
503 }
504 return ret;
505}
506
20dd6390
KV		 507static int dma_slave_control(struct dma_chan *chan, unsigned long arg)
508{
509 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
510 struct dma_slave_config *slave = (struct dma_slave_config *)arg;
511 struct intel_mid_dma_slave *mid_slave;
512
513 BUG_ON(!midc);
514 BUG_ON(!slave);
515 pr_debug("MDMA: slave control called\n");
516
517 mid_slave = to_intel_mid_dma_slave(slave);
518
519 BUG_ON(!mid_slave);
520
521 midc->mid_slave = mid_slave;
522 return 0;
523}
b3c567e4
VK		 524/**
525 * intel_mid_dma_device_control - DMA device control
526 * @chan: chan for DMA control
527 * @cmd: control cmd
528 * @arg: cmd arg value
529 *
530 * Perform DMA control command
531 */
532static int intel_mid_dma_device_control(struct dma_chan *chan,
533 enum dma_ctrl_cmd cmd, unsigned long arg)
534{
535 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
536 struct middma_device *mid = to_middma_device(chan->device);
537 struct intel_mid_dma_desc *desc, *_desc;
576e3c39 538 union intel_mid_dma_cfg_lo cfg_lo;
b3c567e4 539
20dd6390
KV		 540 if (cmd == DMA_SLAVE_CONFIG)
541 return dma_slave_control(chan, arg);
542
b3c567e4
VK		 543 if (cmd != DMA_TERMINATE_ALL)
544 return -ENXIO;
545
546 spin_lock_bh(&midc->lock);
53a61bad 547 if (midc->busy == false) {
b3c567e4
VK		 548 spin_unlock_bh(&midc->lock);
549 return 0;
550 }
576e3c39
RB		 551 /*Suspend and disable the channel*/
552 cfg_lo.cfg_lo = ioread32(midc->ch_regs + CFG_LOW);
553 cfg_lo.cfgx.ch_susp = 1;
554 iowrite32(cfg_lo.cfg_lo, midc->ch_regs + CFG_LOW);
555 iowrite32(DISABLE_CHANNEL(midc->ch_id), mid->dma_base + DMA_CHAN_EN);
556 midc->busy = false;
b3c567e4
VK		 557 /* Disable interrupts */
558 disable_dma_interrupt(midc);
576e3c39 559 midc->descs_allocated = 0;
b3c567e4
VK		 560
561 spin_unlock_bh(&midc->lock);
576e3c39
RB		 562 list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
563 if (desc->lli != NULL) {
564 pci_pool_free(desc->lli_pool, desc->lli,
565 desc->lli_phys);
566 pci_pool_destroy(desc->lli_pool);
1fded075 567 desc->lli = NULL;
576e3c39
RB		 568 }
569 list_move(&desc->desc_node, &midc->free_list);
b3c567e4
VK		 570 }
571 return 0;
572}
573
b3c567e4
VK		 574
575/**
576 * intel_mid_dma_prep_memcpy - Prep memcpy txn
577 * @chan: chan for DMA transfer
578 * @dest: destn address
579 * @src: src address
580 * @len: DMA transfer len
581 * @flags: DMA flags
582 *
583 * Perform a DMA memcpy. Note we support slave periphral DMA transfers only
584 * The periphral txn details should be filled in slave structure properly
585 * Returns the descriptor for this txn
586 */
587static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
588 struct dma_chan *chan, dma_addr_t dest,
589 dma_addr_t src, size_t len, unsigned long flags)
590{
591 struct intel_mid_dma_chan *midc;
592 struct intel_mid_dma_desc *desc = NULL;
593 struct intel_mid_dma_slave *mids;
594 union intel_mid_dma_ctl_lo ctl_lo;
595 union intel_mid_dma_ctl_hi ctl_hi;
596 union intel_mid_dma_cfg_lo cfg_lo;
597 union intel_mid_dma_cfg_hi cfg_hi;
20dd6390 598 enum dma_slave_buswidth width;
b3c567e4
VK		 599
600 pr_debug("MDMA: Prep for memcpy\n");
8b649223 601 BUG_ON(!chan);
b3c567e4
VK		 602 if (!len)
603 return NULL;
604
b3c567e4 605 midc = to_intel_mid_dma_chan(chan);
8b649223 606 BUG_ON(!midc);
b3c567e4 607
20dd6390
KV		 608 mids = midc->mid_slave;
609 BUG_ON(!mids);
610
b3c567e4
VK		 611 pr_debug("MDMA:called for DMA %x CH %d Length %zu\n",
612 midc->dma->pci_id, midc->ch_id, len);
613 pr_debug("MDMA:Cfg passed Mode %x, Dirn %x, HS %x, Width %x\n",
20dd6390
KV		 614 mids->cfg_mode, mids->dma_slave.direction,
615 mids->hs_mode, mids->dma_slave.src_addr_width);
b3c567e4
VK		 616
617 /*calculate CFG_LO*/
618 if (mids->hs_mode == LNW_DMA_SW_HS) {
619 cfg_lo.cfg_lo = 0;
620 cfg_lo.cfgx.hs_sel_dst = 1;
621 cfg_lo.cfgx.hs_sel_src = 1;
622 } else if (mids->hs_mode == LNW_DMA_HW_HS)
623 cfg_lo.cfg_lo = 0x00000;
624
625 /*calculate CFG_HI*/
626 if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) {
627 /*SW HS only*/
628 cfg_hi.cfg_hi = 0;
629 } else {
630 cfg_hi.cfg_hi = 0;
631 if (midc->dma->pimr_mask) {
632 cfg_hi.cfgx.protctl = 0x0; /*default value*/
633 cfg_hi.cfgx.fifo_mode = 1;
db8196df 634 if (mids->dma_slave.direction == DMA_MEM_TO_DEV) {
b3c567e4
VK		 635 cfg_hi.cfgx.src_per = 0;
636 if (mids->device_instance == 0)
637 cfg_hi.cfgx.dst_per = 3;
638 if (mids->device_instance == 1)
639 cfg_hi.cfgx.dst_per = 1;
db8196df 640 } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) {
b3c567e4
VK		 641 if (mids->device_instance == 0)
642 cfg_hi.cfgx.src_per = 2;
643 if (mids->device_instance == 1)
644 cfg_hi.cfgx.src_per = 0;
645 cfg_hi.cfgx.dst_per = 0;
646 }
647 } else {
648 cfg_hi.cfgx.protctl = 0x1; /*default value*/
649 cfg_hi.cfgx.src_per = cfg_hi.cfgx.dst_per =
650 midc->ch_id - midc->dma->chan_base;
651 }
652 }
653
654 /*calculate CTL_HI*/
655 ctl_hi.ctlx.reser = 0;
576e3c39 656 ctl_hi.ctlx.done = 0;
20dd6390 657 width = mids->dma_slave.src_addr_width;
b3c567e4
VK		 658
659 ctl_hi.ctlx.block_ts = get_block_ts(len, width, midc->dma->block_size);
660 pr_debug("MDMA:calc len %d for block size %d\n",
661 ctl_hi.ctlx.block_ts, midc->dma->block_size);
662 /*calculate CTL_LO*/
663 ctl_lo.ctl_lo = 0;
664 ctl_lo.ctlx.int_en = 1;
20dd6390
KV		 665 ctl_lo.ctlx.dst_msize = mids->dma_slave.src_maxburst;
666 ctl_lo.ctlx.src_msize = mids->dma_slave.dst_maxburst;
b3c567e4 667
0be035f3
FT		 668 /*
669 * Here we need some translation from "enum dma_slave_buswidth"
670 * to the format for our dma controller
671 * standard intel_mid_dmac's format
672 * 1 Byte 0b000
673 * 2 Bytes 0b001
674 * 4 Bytes 0b010
675 */
676 ctl_lo.ctlx.dst_tr_width = mids->dma_slave.dst_addr_width / 2;
677 ctl_lo.ctlx.src_tr_width = mids->dma_slave.src_addr_width / 2;
678
b3c567e4
VK		 679 if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) {
680 ctl_lo.ctlx.tt_fc = 0;
681 ctl_lo.ctlx.sinc = 0;
682 ctl_lo.ctlx.dinc = 0;
683 } else {
db8196df 684 if (mids->dma_slave.direction == DMA_MEM_TO_DEV) {
b3c567e4
VK		 685 ctl_lo.ctlx.sinc = 0;
686 ctl_lo.ctlx.dinc = 2;
687 ctl_lo.ctlx.tt_fc = 1;
db8196df 688 } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) {
b3c567e4
VK		 689 ctl_lo.ctlx.sinc = 2;
690 ctl_lo.ctlx.dinc = 0;
691 ctl_lo.ctlx.tt_fc = 2;
692 }
693 }
694
695 pr_debug("MDMA:Calc CTL LO %x, CTL HI %x, CFG LO %x, CFG HI %x\n",
696 ctl_lo.ctl_lo, ctl_hi.ctl_hi, cfg_lo.cfg_lo, cfg_hi.cfg_hi);
697
698 enable_dma_interrupt(midc);
699
700 desc = midc_desc_get(midc);
701 if (desc == NULL)
702 goto err_desc_get;
703 desc->sar = src;
704 desc->dar = dest ;
705 desc->len = len;
706 desc->cfg_hi = cfg_hi.cfg_hi;
707 desc->cfg_lo = cfg_lo.cfg_lo;
708 desc->ctl_lo = ctl_lo.ctl_lo;
709 desc->ctl_hi = ctl_hi.ctl_hi;
710 desc->width = width;
20dd6390 711 desc->dirn = mids->dma_slave.direction;
576e3c39
RB		 712 desc->lli_phys = 0;
713 desc->lli = NULL;
714 desc->lli_pool = NULL;
b3c567e4
VK		 715 return &desc->txd;
716
717err_desc_get:
718 pr_err("ERR_MDMA: Failed to get desc\n");
719 midc_desc_put(midc, desc);
720 return NULL;
721}
576e3c39
RB		 722/**
723 * intel_mid_dma_prep_slave_sg - Prep slave sg txn
724 * @chan: chan for DMA transfer
725 * @sgl: scatter gather list
726 * @sg_len: length of sg txn
727 * @direction: DMA transfer dirtn
728 * @flags: DMA flags
729 *
730 * Prepares LLI based periphral transfer
731 */
732static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
733 struct dma_chan *chan, struct scatterlist *sgl,
db8196df 734 unsigned int sg_len, enum dma_transfer_direction direction,
576e3c39
RB		 735 unsigned long flags)
736{
737 struct intel_mid_dma_chan *midc = NULL;
738 struct intel_mid_dma_slave *mids = NULL;
739 struct intel_mid_dma_desc *desc = NULL;
740 struct dma_async_tx_descriptor *txd = NULL;
741 union intel_mid_dma_ctl_lo ctl_lo;
742
743 pr_debug("MDMA: Prep for slave SG\n");
744
745 if (!sg_len) {
746 pr_err("MDMA: Invalid SG length\n");
747 return NULL;
748 }
749 midc = to_intel_mid_dma_chan(chan);
750 BUG_ON(!midc);
751
20dd6390 752 mids = midc->mid_slave;
576e3c39
RB		 753 BUG_ON(!mids);
754
755 if (!midc->dma->pimr_mask) {
0be035f3
FT		 756 /* We can still handle sg list with only one item */
757 if (sg_len == 1) {
758 txd = intel_mid_dma_prep_memcpy(chan,
759 mids->dma_slave.dst_addr,
760 mids->dma_slave.src_addr,
761 sgl->length,
762 flags);
763 return txd;
764 } else {
765 pr_warn("MDMA: SG list is not supported by this controller\n");
766 return NULL;
767 }
576e3c39
RB		 768 }
769
770 pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n",
771 sg_len, direction, flags);
772
773 txd = intel_mid_dma_prep_memcpy(chan, 0, 0, sgl->length, flags);
774 if (NULL == txd) {
775 pr_err("MDMA: Prep memcpy failed\n");
776 return NULL;
777 }
0be035f3 778
576e3c39
RB		 779 desc = to_intel_mid_dma_desc(txd);
780 desc->dirn = direction;
781 ctl_lo.ctl_lo = desc->ctl_lo;
782 ctl_lo.ctlx.llp_dst_en = 1;
783 ctl_lo.ctlx.llp_src_en = 1;
784 desc->ctl_lo = ctl_lo.ctl_lo;
785 desc->lli_length = sg_len;
786 desc->current_lli = 0;
787 /* DMA coherent memory pool for LLI descriptors*/
788 desc->lli_pool = pci_pool_create("intel_mid_dma_lli_pool",
789 midc->dma->pdev,
790 (sizeof(struct intel_mid_dma_lli)*sg_len),
791 32, 0);
792 if (NULL == desc->lli_pool) {
793 pr_err("MID_DMA:LLI pool create failed\n");
794 return NULL;
795 }
796
797 desc->lli = pci_pool_alloc(desc->lli_pool, GFP_KERNEL, &desc->lli_phys);
798 if (!desc->lli) {
799 pr_err("MID_DMA: LLI alloc failed\n");
800 pci_pool_destroy(desc->lli_pool);
801 return NULL;
802 }
803
804 midc_lli_fill_sg(midc, desc, sgl, sg_len, flags);
805 if (flags & DMA_PREP_INTERRUPT) {
806 iowrite32(UNMASK_INTR_REG(midc->ch_id),
807 midc->dma_base + MASK_BLOCK);
808 pr_debug("MDMA:Enabled Block interrupt\n");
809 }
810 return &desc->txd;
811}
b3c567e4
VK		 812
813/**
814 * intel_mid_dma_free_chan_resources - Frees dma resources
815 * @chan: chan requiring attention
816 *
817 * Frees the allocated resources on this DMA chan
818 */
819static void intel_mid_dma_free_chan_resources(struct dma_chan *chan)
820{
821 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
822 struct middma_device *mid = to_middma_device(chan->device);
823 struct intel_mid_dma_desc *desc, *_desc;
824
53a61bad 825 if (true == midc->busy) {
b3c567e4
VK		 826 /*trying to free ch in use!!!!!*/
827 pr_err("ERR_MDMA: trying to free ch in use\n");
828 }
b3c567e4
VK		 829 spin_lock_bh(&midc->lock);
830 midc->descs_allocated = 0;
831 list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
832 list_del(&desc->desc_node);
833 pci_pool_free(mid->dma_pool, desc, desc->txd.phys);
834 }
835 list_for_each_entry_safe(desc, _desc, &midc->free_list, desc_node) {
836 list_del(&desc->desc_node);
837 pci_pool_free(mid->dma_pool, desc, desc->txd.phys);
838 }
839 list_for_each_entry_safe(desc, _desc, &midc->queue, desc_node) {
840 list_del(&desc->desc_node);
841 pci_pool_free(mid->dma_pool, desc, desc->txd.phys);
842 }
843 spin_unlock_bh(&midc->lock);
844 midc->in_use = false;
53a61bad 845 midc->busy = false;
b3c567e4
VK		 846 /* Disable CH interrupts */
847 iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_BLOCK);
848 iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_ERR);
91c1c9e3 849 pm_runtime_put(&mid->pdev->dev);
b3c567e4
VK		 850}
851
852/**
853 * intel_mid_dma_alloc_chan_resources - Allocate dma resources
854 * @chan: chan requiring attention
855 *
856 * Allocates DMA resources on this chan
857 * Return the descriptors allocated
858 */
859static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
860{
861 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
862 struct middma_device *mid = to_middma_device(chan->device);
863 struct intel_mid_dma_desc *desc;
864 dma_addr_t phys;
865 int i = 0;
866
53a61bad
KV		 867 pm_runtime_get_sync(&mid->pdev->dev);
868
869 if (mid->state == SUSPENDED) {
8730790b 870 if (dma_resume(&mid->pdev->dev)) {
53a61bad
KV		 871 pr_err("ERR_MDMA: resume failed");
872 return -EFAULT;
873 }
874 }
b3c567e4
VK		 875
876 /* ASSERT: channel is idle */
877 if (test_ch_en(mid->dma_base, midc->ch_id)) {
878 /*ch is not idle*/
879 pr_err("ERR_MDMA: ch not idle\n");
53a61bad 880 pm_runtime_put(&mid->pdev->dev);
b3c567e4
VK		 881 return -EIO;
882 }
4d4e58de 883 chan->completed_cookie = chan->cookie = 1;
b3c567e4
VK		 884
885 spin_lock_bh(&midc->lock);
886 while (midc->descs_allocated < DESCS_PER_CHANNEL) {
887 spin_unlock_bh(&midc->lock);
888 desc = pci_pool_alloc(mid->dma_pool, GFP_KERNEL, &phys);
889 if (!desc) {
890 pr_err("ERR_MDMA: desc failed\n");
53a61bad 891 pm_runtime_put(&mid->pdev->dev);
b3c567e4
VK		 892 return -ENOMEM;
893 /*check*/
894 }
895 dma_async_tx_descriptor_init(&desc->txd, chan);
896 desc->txd.tx_submit = intel_mid_dma_tx_submit;
897 desc->txd.flags = DMA_CTRL_ACK;
898 desc->txd.phys = phys;
899 spin_lock_bh(&midc->lock);
900 i = ++midc->descs_allocated;
901 list_add_tail(&desc->desc_node, &midc->free_list);
902 }
903 spin_unlock_bh(&midc->lock);
53a61bad
KV		 904 midc->in_use = true;
905 midc->busy = false;
b3c567e4
VK		 906 pr_debug("MID_DMA: Desc alloc done ret: %d desc\n", i);
907 return i;
908}
909
910/**
911 * midc_handle_error - Handle DMA txn error
25985edc
LDM		 912 * @mid: controller where error occurred
913 * @midc: chan where error occurred
b3c567e4
VK		 914 *
915 * Scan the descriptor for error
916 */
917static void midc_handle_error(struct middma_device *mid,
918 struct intel_mid_dma_chan *midc)
919{
920 midc_scan_descriptors(mid, midc);
921}
922
923/**
924 * dma_tasklet - DMA interrupt tasklet
925 * @data: tasklet arg (the controller structure)
926 *
927 * Scan the controller for interrupts for completion/error
928 * Clear the interrupt and call for handling completion/error
929 */
930static void dma_tasklet(unsigned long data)
931{
932 struct middma_device *mid = NULL;
933 struct intel_mid_dma_chan *midc = NULL;
576e3c39 934 u32 status, raw_tfr, raw_block;
b3c567e4
VK		 935 int i;
936
937 mid = (struct middma_device *)data;
938 if (mid == NULL) {
939 pr_err("ERR_MDMA: tasklet Null param\n");
940 return;
941 }
942 pr_debug("MDMA: in tasklet for device %x\n", mid->pci_id);
576e3c39
RB		 943 raw_tfr = ioread32(mid->dma_base + RAW_TFR);
944 raw_block = ioread32(mid->dma_base + RAW_BLOCK);
945 status = raw_tfr | raw_block;
b3c567e4
VK		 946 status &= mid->intr_mask;
947 while (status) {
948 /*txn interrupt*/
949 i = get_ch_index(&status, mid->chan_base);
950 if (i < 0) {
951 pr_err("ERR_MDMA:Invalid ch index %x\n", i);
952 return;
953 }
954 midc = &mid->ch[i];
955 if (midc == NULL) {
956 pr_err("ERR_MDMA:Null param midc\n");
957 return;
958 }
959 pr_debug("MDMA:Tx complete interrupt %x, Ch No %d Index %d\n",
960 status, midc->ch_id, i);
576e3c39
RB		 961 midc->raw_tfr = raw_tfr;
962 midc->raw_block = raw_block;
963 spin_lock_bh(&midc->lock);
b3c567e4
VK		 964 /*clearing this interrupts first*/
965 iowrite32((1 << midc->ch_id), mid->dma_base + CLEAR_TFR);
576e3c39
RB		 966 if (raw_block) {
967 iowrite32((1 << midc->ch_id),
968 mid->dma_base + CLEAR_BLOCK);
969 }
b3c567e4
VK		 970 midc_scan_descriptors(mid, midc);
971 pr_debug("MDMA:Scan of desc... complete, unmasking\n");
972 iowrite32(UNMASK_INTR_REG(midc->ch_id),
973 mid->dma_base + MASK_TFR);
576e3c39
RB		 974 if (raw_block) {
975 iowrite32(UNMASK_INTR_REG(midc->ch_id),
976 mid->dma_base + MASK_BLOCK);
977 }
b3c567e4
VK		 978 spin_unlock_bh(&midc->lock);
979 }
980
981 status = ioread32(mid->dma_base + RAW_ERR);
982 status &= mid->intr_mask;
983 while (status) {
984 /*err interrupt*/
985 i = get_ch_index(&status, mid->chan_base);
986 if (i < 0) {
987 pr_err("ERR_MDMA:Invalid ch index %x\n", i);
988 return;
989 }
990 midc = &mid->ch[i];
991 if (midc == NULL) {
992 pr_err("ERR_MDMA:Null param midc\n");
993 return;
994 }
995 pr_debug("MDMA:Tx complete interrupt %x, Ch No %d Index %d\n",
996 status, midc->ch_id, i);
997
998 iowrite32((1 << midc->ch_id), mid->dma_base + CLEAR_ERR);
999 spin_lock_bh(&midc->lock);
1000 midc_handle_error(mid, midc);
1001 iowrite32(UNMASK_INTR_REG(midc->ch_id),
1002 mid->dma_base + MASK_ERR);
1003 spin_unlock_bh(&midc->lock);
1004 }
1005 pr_debug("MDMA:Exiting takslet...\n");
1006 return;
1007}
1008
1009static void dma_tasklet1(unsigned long data)
1010{
1011 pr_debug("MDMA:in takslet1...\n");
1012 return dma_tasklet(data);
1013}
1014
1015static void dma_tasklet2(unsigned long data)
1016{
1017 pr_debug("MDMA:in takslet2...\n");
1018 return dma_tasklet(data);
1019}
1020
1021/**
1022 * intel_mid_dma_interrupt - DMA ISR
1023 * @irq: IRQ where interrupt occurred
1024 * @data: ISR cllback data (the controller structure)
1025 *
1026 * See if this is our interrupt if so then schedule the tasklet
1027 * otherwise ignore
1028 */
1029static irqreturn_t intel_mid_dma_interrupt(int irq, void *data)
1030{
1031 struct middma_device *mid = data;
b306df5e 1032 u32 tfr_status, err_status;
b3c567e4
VK		 1033 int call_tasklet = 0;
1034
b306df5e
YW		 1035 tfr_status = ioread32(mid->dma_base + RAW_TFR);
1036 err_status = ioread32(mid->dma_base + RAW_ERR);
1037 if (!tfr_status && !err_status)
1038 return IRQ_NONE;
1039
b3c567e4
VK		 1040 /*DMA Interrupt*/
1041 pr_debug("MDMA:Got an interrupt on irq %d\n", irq);
b306df5e
YW		 1042 pr_debug("MDMA: Status %x, Mask %x\n", tfr_status, mid->intr_mask);
1043 tfr_status &= mid->intr_mask;
1044 if (tfr_status) {
b3c567e4 1045 /*need to disable intr*/
576e3c39
RB		 1046 iowrite32((tfr_status << INT_MASK_WE), mid->dma_base + MASK_TFR);
1047 iowrite32((tfr_status << INT_MASK_WE), mid->dma_base + MASK_BLOCK);
b306df5e 1048 pr_debug("MDMA: Calling tasklet %x\n", tfr_status);
b3c567e4
VK		 1049 call_tasklet = 1;
1050 }
b306df5e
YW		 1051 err_status &= mid->intr_mask;
1052 if (err_status) {
7f99a421
AH		 1053 iowrite32((err_status << INT_MASK_WE),
1054 mid->dma_base + MASK_ERR);
b3c567e4
VK		 1055 call_tasklet = 1;
1056 }
1057 if (call_tasklet)
1058 tasklet_schedule(&mid->tasklet);
1059
1060 return IRQ_HANDLED;
1061}
1062
1063static irqreturn_t intel_mid_dma_interrupt1(int irq, void *data)
1064{
1065 return intel_mid_dma_interrupt(irq, data);
1066}
1067
1068static irqreturn_t intel_mid_dma_interrupt2(int irq, void *data)
1069{
1070 return intel_mid_dma_interrupt(irq, data);
1071}
1072
1073/**
1074 * mid_setup_dma - Setup the DMA controller
1075 * @pdev: Controller PCI device structure
1076 *
b595076a
UKK		 1077 * Initialize the DMA controller, channels, registers with DMA engine,
1078 * ISR. Initialize DMA controller channels.
b3c567e4
VK		 1079 */
1080static int mid_setup_dma(struct pci_dev *pdev)
1081{
1082 struct middma_device *dma = pci_get_drvdata(pdev);
1083 int err, i;
b3c567e4
VK		 1084
1085 /* DMA coherent memory pool for DMA descriptor allocations */
1086 dma->dma_pool = pci_pool_create("intel_mid_dma_desc_pool", pdev,
1087 sizeof(struct intel_mid_dma_desc),
1088 32, 0);
1089 if (NULL == dma->dma_pool) {
1090 pr_err("ERR_MDMA:pci_pool_create failed\n");
1091 err = -ENOMEM;
b3c567e4
VK		 1092 goto err_dma_pool;
1093 }
1094
1095 INIT_LIST_HEAD(&dma->common.channels);
1096 dma->pci_id = pdev->device;
1097 if (dma->pimr_mask) {
1098 dma->mask_reg = ioremap(LNW_PERIPHRAL_MASK_BASE,
1099 LNW_PERIPHRAL_MASK_SIZE);
1100 if (dma->mask_reg == NULL) {
25985edc 1101 pr_err("ERR_MDMA:Can't map periphral intr space !!\n");
2a0ff7a6
AH		 1102 err = -ENOMEM;
1103 goto err_ioremap;
b3c567e4
VK		 1104 }
1105 } else
1106 dma->mask_reg = NULL;
1107
1108 pr_debug("MDMA:Adding %d channel for this controller\n", dma->max_chan);
1109 /*init CH structures*/
1110 dma->intr_mask = 0;
53a61bad 1111 dma->state = RUNNING;
b3c567e4
VK		 1112 for (i = 0; i < dma->max_chan; i++) {
1113 struct intel_mid_dma_chan *midch = &dma->ch[i];
1114
1115 midch->chan.device = &dma->common;
1116 midch->chan.cookie = 1;
b3c567e4
VK		 1117 midch->ch_id = dma->chan_base + i;
1118 pr_debug("MDMA:Init CH %d, ID %d\n", i, midch->ch_id);
1119
1120 midch->dma_base = dma->dma_base;
1121 midch->ch_regs = dma->dma_base + DMA_CH_SIZE * midch->ch_id;
1122 midch->dma = dma;
1123 dma->intr_mask |= 1 << (dma->chan_base + i);
1124 spin_lock_init(&midch->lock);
1125
1126 INIT_LIST_HEAD(&midch->active_list);
1127 INIT_LIST_HEAD(&midch->queue);
1128 INIT_LIST_HEAD(&midch->free_list);
1129 /*mask interrupts*/
1130 iowrite32(MASK_INTR_REG(midch->ch_id),
1131 dma->dma_base + MASK_BLOCK);
1132 iowrite32(MASK_INTR_REG(midch->ch_id),
1133 dma->dma_base + MASK_SRC_TRAN);
1134 iowrite32(MASK_INTR_REG(midch->ch_id),
1135 dma->dma_base + MASK_DST_TRAN);
1136 iowrite32(MASK_INTR_REG(midch->ch_id),
1137 dma->dma_base + MASK_ERR);
1138 iowrite32(MASK_INTR_REG(midch->ch_id),
1139 dma->dma_base + MASK_TFR);
1140
1141 disable_dma_interrupt(midch);
1142 list_add_tail(&midch->chan.device_node, &dma->common.channels);
1143 }
1144 pr_debug("MDMA: Calc Mask as %x for this controller\n", dma->intr_mask);
1145
1146 /*init dma structure*/
1147 dma_cap_zero(dma->common.cap_mask);
1148 dma_cap_set(DMA_MEMCPY, dma->common.cap_mask);
1149 dma_cap_set(DMA_SLAVE, dma->common.cap_mask);
1150 dma_cap_set(DMA_PRIVATE, dma->common.cap_mask);
1151 dma->common.dev = &pdev->dev;
b3c567e4
VK		 1152
1153 dma->common.device_alloc_chan_resources =
1154 intel_mid_dma_alloc_chan_resources;
1155 dma->common.device_free_chan_resources =
1156 intel_mid_dma_free_chan_resources;
1157
1158 dma->common.device_tx_status = intel_mid_dma_tx_status;
1159 dma->common.device_prep_dma_memcpy = intel_mid_dma_prep_memcpy;
1160 dma->common.device_issue_pending = intel_mid_dma_issue_pending;
1161 dma->common.device_prep_slave_sg = intel_mid_dma_prep_slave_sg;
1162 dma->common.device_control = intel_mid_dma_device_control;
1163
1164 /*enable dma cntrl*/
1165 iowrite32(REG_BIT0, dma->dma_base + DMA_CFG);
1166
1167 /*register irq */
1168 if (dma->pimr_mask) {
b3c567e4
VK		 1169 pr_debug("MDMA:Requesting irq shared for DMAC1\n");
1170 err = request_irq(pdev->irq, intel_mid_dma_interrupt1,
1171 IRQF_SHARED, "INTEL_MID_DMAC1", dma);
1172 if (0 != err)
1173 goto err_irq;
1174 } else {
1175 dma->intr_mask = 0x03;
b3c567e4
VK		 1176 pr_debug("MDMA:Requesting irq for DMAC2\n");
1177 err = request_irq(pdev->irq, intel_mid_dma_interrupt2,
03b96dca 1178 IRQF_SHARED, "INTEL_MID_DMAC2", dma);
b3c567e4
VK		 1179 if (0 != err)
1180 goto err_irq;
1181 }
1182 /*register device w/ engine*/
1183 err = dma_async_device_register(&dma->common);
1184 if (0 != err) {
1185 pr_err("ERR_MDMA:device_register failed: %d\n", err);
1186 goto err_engine;
1187 }
1188 if (dma->pimr_mask) {
1189 pr_debug("setting up tasklet1 for DMAC1\n");
1190 tasklet_init(&dma->tasklet, dma_tasklet1, (unsigned long)dma);
1191 } else {
1192 pr_debug("setting up tasklet2 for DMAC2\n");
1193 tasklet_init(&dma->tasklet, dma_tasklet2, (unsigned long)dma);
1194 }
1195 return 0;
1196
1197err_engine:
1198 free_irq(pdev->irq, dma);
1199err_irq:
2a0ff7a6
AH		 1200 if (dma->mask_reg)
1201 iounmap(dma->mask_reg);
1202err_ioremap:
b3c567e4 1203 pci_pool_destroy(dma->dma_pool);
b3c567e4
VK		 1204err_dma_pool:
1205 pr_err("ERR_MDMA:setup_dma failed: %d\n", err);
1206 return err;
1207
1208}
1209
1210/**
1211 * middma_shutdown - Shutdown the DMA controller
1212 * @pdev: Controller PCI device structure
1213 *
1214 * Called by remove
1215 * Unregister DMa controller, clear all structures and free interrupt
1216 */
1217static void middma_shutdown(struct pci_dev *pdev)
1218{
1219 struct middma_device *device = pci_get_drvdata(pdev);
1220
1221 dma_async_device_unregister(&device->common);
1222 pci_pool_destroy(device->dma_pool);
1223 if (device->mask_reg)
1224 iounmap(device->mask_reg);
1225 if (device->dma_base)
1226 iounmap(device->dma_base);
1227 free_irq(pdev->irq, device);
1228 return;
1229}
1230
1231/**
1232 * intel_mid_dma_probe - PCI Probe
1233 * @pdev: Controller PCI device structure
1234 * @id: pci device id structure
1235 *
b595076a 1236 * Initialize the PCI device, map BARs, query driver data.
b3c567e4
VK		 1237 * Call setup_dma to complete contoller and chan initilzation
1238 */
1239static int __devinit intel_mid_dma_probe(struct pci_dev *pdev,
1240 const struct pci_device_id *id)
1241{
1242 struct middma_device *device;
1243 u32 base_addr, bar_size;
1244 struct intel_mid_dma_probe_info *info;
1245 int err;
1246
1247 pr_debug("MDMA: probe for %x\n", pdev->device);
1248 info = (void *)id->driver_data;
1249 pr_debug("MDMA: CH %d, base %d, block len %d, Periphral mask %x\n",
1250 info->max_chan, info->ch_base,
1251 info->block_size, info->pimr_mask);
1252
1253 err = pci_enable_device(pdev);
1254 if (err)
1255 goto err_enable_device;
1256
1257 err = pci_request_regions(pdev, "intel_mid_dmac");
1258 if (err)
1259 goto err_request_regions;
1260
1261 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1262 if (err)
1263 goto err_set_dma_mask;
1264
1265 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1266 if (err)
1267 goto err_set_dma_mask;
1268
1269 device = kzalloc(sizeof(*device), GFP_KERNEL);
1270 if (!device) {
1271 pr_err("ERR_MDMA:kzalloc failed probe\n");
1272 err = -ENOMEM;
1273 goto err_kzalloc;
1274 }
1275 device->pdev = pci_dev_get(pdev);
1276
1277 base_addr = pci_resource_start(pdev, 0);
1278 bar_size = pci_resource_len(pdev, 0);
1279 device->dma_base = ioremap_nocache(base_addr, DMA_REG_SIZE);
1280 if (!device->dma_base) {
1281 pr_err("ERR_MDMA:ioremap failed\n");
1282 err = -ENOMEM;
1283 goto err_ioremap;
1284 }
1285 pci_set_drvdata(pdev, device);
1286 pci_set_master(pdev);
1287 device->max_chan = info->max_chan;
1288 device->chan_base = info->ch_base;
1289 device->block_size = info->block_size;
1290 device->pimr_mask = info->pimr_mask;
1291
1292 err = mid_setup_dma(pdev);
1293 if (err)
1294 goto err_dma;
1295
e2142df7 1296 pm_runtime_put_noidle(&pdev->dev);
53a61bad 1297 pm_runtime_allow(&pdev->dev);
b3c567e4
VK		 1298 return 0;
1299
1300err_dma:
1301 iounmap(device->dma_base);
1302err_ioremap:
1303 pci_dev_put(pdev);
1304 kfree(device);
1305err_kzalloc:
1306err_set_dma_mask:
1307 pci_release_regions(pdev);
1308 pci_disable_device(pdev);
1309err_request_regions:
1310err_enable_device:
1311 pr_err("ERR_MDMA:Probe failed %d\n", err);
1312 return err;
1313}
1314
1315/**
1316 * intel_mid_dma_remove - PCI remove
1317 * @pdev: Controller PCI device structure
1318 *
1319 * Free up all resources and data
1320 * Call shutdown_dma to complete contoller and chan cleanup
1321 */
1322static void __devexit intel_mid_dma_remove(struct pci_dev *pdev)
1323{
1324 struct middma_device *device = pci_get_drvdata(pdev);
e2142df7
KCA		 1325
1326 pm_runtime_get_noresume(&pdev->dev);
1327 pm_runtime_forbid(&pdev->dev);
b3c567e4
VK		 1328 middma_shutdown(pdev);
1329 pci_dev_put(pdev);
1330 kfree(device);
1331 pci_release_regions(pdev);
1332 pci_disable_device(pdev);
1333}
1334
53a61bad
KV		 1335/* Power Management */
1336/*
1337* dma_suspend - PCI suspend function
1338*
1339* @pci: PCI device structure
1340* @state: PM message
1341*
1342* This function is called by OS when a power event occurs
1343*/
8730790b 1344static int dma_suspend(struct device *dev)
53a61bad 1345{
8730790b 1346 struct pci_dev *pci = to_pci_dev(dev);
53a61bad
KV		 1347 int i;
1348 struct middma_device *device = pci_get_drvdata(pci);
1349 pr_debug("MDMA: dma_suspend called\n");
1350
1351 for (i = 0; i < device->max_chan; i++) {
1352 if (device->ch[i].in_use)
1353 return -EAGAIN;
1354 }
4598fc2c 1355 dmac1_mask_periphral_intr(device);
53a61bad 1356 device->state = SUSPENDED;
53a61bad
KV		 1357 pci_save_state(pci);
1358 pci_disable_device(pci);
1359 pci_set_power_state(pci, PCI_D3hot);
1360 return 0;
1361}
1362
1363/**
1364* dma_resume - PCI resume function
1365*
1366* @pci: PCI device structure
1367*
1368* This function is called by OS when a power event occurs
1369*/
8730790b 1370int dma_resume(struct device *dev)
53a61bad 1371{
8730790b 1372 struct pci_dev *pci = to_pci_dev(dev);
53a61bad
KV		 1373 int ret;
1374 struct middma_device *device = pci_get_drvdata(pci);
1375
1376 pr_debug("MDMA: dma_resume called\n");
1377 pci_set_power_state(pci, PCI_D0);
1378 pci_restore_state(pci);
1379 ret = pci_enable_device(pci);
1380 if (ret) {
25985edc 1381 pr_err("MDMA: device can't be enabled for %x\n", pci->device);
53a61bad
KV		 1382 return ret;
1383 }
1384 device->state = RUNNING;
1385 iowrite32(REG_BIT0, device->dma_base + DMA_CFG);
53a61bad
KV		 1386 return 0;
1387}
1388
1389static int dma_runtime_suspend(struct device *dev)
1390{
1391 struct pci_dev *pci_dev = to_pci_dev(dev);
e2142df7
KCA		 1392 struct middma_device *device = pci_get_drvdata(pci_dev);
1393
1394 device->state = SUSPENDED;
1395 return 0;
53a61bad
KV		 1396}
1397
1398static int dma_runtime_resume(struct device *dev)
1399{
1400 struct pci_dev *pci_dev = to_pci_dev(dev);
e2142df7
KCA		 1401 struct middma_device *device = pci_get_drvdata(pci_dev);
1402
1403 device->state = RUNNING;
1404 iowrite32(REG_BIT0, device->dma_base + DMA_CFG);
1405 return 0;
53a61bad
KV		 1406}
1407
1408static int dma_runtime_idle(struct device *dev)
1409{
1410 struct pci_dev *pdev = to_pci_dev(dev);
1411 struct middma_device *device = pci_get_drvdata(pdev);
1412 int i;
1413
1414 for (i = 0; i < device->max_chan; i++) {
1415 if (device->ch[i].in_use)
1416 return -EAGAIN;
1417 }
1418
1419 return pm_schedule_suspend(dev, 0);
1420}
1421
b3c567e4
VK		 1422/******************************************************************************
1423* PCI stuff
1424*/
1425static struct pci_device_id intel_mid_dma_ids[] = {
1426 { PCI_VDEVICE(INTEL, INTEL_MID_DMAC1_ID), INFO(2, 6, 4095, 0x200020)},
1427 { PCI_VDEVICE(INTEL, INTEL_MID_DMAC2_ID), INFO(2, 0, 2047, 0)},
1428 { PCI_VDEVICE(INTEL, INTEL_MID_GP_DMAC2_ID), INFO(2, 0, 2047, 0)},
1429 { PCI_VDEVICE(INTEL, INTEL_MFLD_DMAC1_ID), INFO(4, 0, 4095, 0x400040)},
1430 { 0, }
1431};
1432MODULE_DEVICE_TABLE(pci, intel_mid_dma_ids);
1433
53a61bad
KV		 1434static const struct dev_pm_ops intel_mid_dma_pm = {
1435 .runtime_suspend = dma_runtime_suspend,
1436 .runtime_resume = dma_runtime_resume,
1437 .runtime_idle = dma_runtime_idle,
8730790b
KCA		 1438 .suspend = dma_suspend,
1439 .resume = dma_resume,
53a61bad
KV		 1440};
1441
cf2f9c59 1442static struct pci_driver intel_mid_dma_pci_driver = {
b3c567e4
VK		 1443 .name = "Intel MID DMA",
1444 .id_table = intel_mid_dma_ids,
1445 .probe = intel_mid_dma_probe,
1446 .remove = __devexit_p(intel_mid_dma_remove),
53a61bad 1447#ifdef CONFIG_PM
53a61bad
KV		 1448 .driver = {
1449 .pm = &intel_mid_dma_pm,
1450 },
1451#endif
b3c567e4
VK		 1452};
1453
1454static int __init intel_mid_dma_init(void)
1455{
1456 pr_debug("INFO_MDMA: LNW DMA Driver Version %s\n",
1457 INTEL_MID_DMA_DRIVER_VERSION);
cf2f9c59 1458 return pci_register_driver(&intel_mid_dma_pci_driver);
b3c567e4
VK		 1459}
1460fs_initcall(intel_mid_dma_init);
1461
1462static void __exit intel_mid_dma_exit(void)
1463{
cf2f9c59 1464 pci_unregister_driver(&intel_mid_dma_pci_driver);
b3c567e4
VK		 1465}
1466module_exit(intel_mid_dma_exit);
1467
1468MODULE_AUTHOR("Vinod Koul <vinod.koul@intel.com>");
1469MODULE_DESCRIPTION("Intel (R) MID DMAC Driver");
1470MODULE_LICENSE("GPL v2");
1471MODULE_VERSION(INTEL_MID_DMA_DRIVER_VERSION);
kernel source for telekom puls (alcatel/mediatek)