Commit | Line | Data |
---|---|---|
173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
e2c8e425 | 4 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. |
173acc7c ZW |
5 | * |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
c2e07b3a | 13 | * The support for MPC8349 DMA controller is also added. |
173acc7c | 14 | * |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
173acc7c ZW |
31 | #include <linux/interrupt.h> |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/dmapool.h> | |
36 | #include <linux/of_platform.h> | |
37 | ||
38 | #include "fsldma.h" | |
39 | ||
c1433041 IS |
40 | static const char msg_ld_oom[] = "No free memory for link descriptor\n"; |
41 | ||
a1c03319 | 42 | static void dma_init(struct fsldma_chan *chan) |
173acc7c ZW |
43 | { |
44 | /* Reset the channel */ | |
a1c03319 | 45 | DMA_OUT(chan, &chan->regs->mr, 0, 32); |
173acc7c | 46 | |
a1c03319 | 47 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c ZW |
48 | case FSL_DMA_IP_85XX: |
49 | /* Set the channel to below modes: | |
50 | * EIE - Error interrupt enable | |
51 | * EOSIE - End of segments interrupt enable (basic mode) | |
52 | * EOLNIE - End of links interrupt enable | |
f3c677b9 | 53 | * BWC - Bandwidth sharing among channels |
173acc7c | 54 | */ |
f3c677b9 FS |
55 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC |
56 | | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE | |
57 | | FSL_DMA_MR_EOSIE, 32); | |
173acc7c ZW |
58 | break; |
59 | case FSL_DMA_IP_83XX: | |
60 | /* Set the channel to below modes: | |
61 | * EOTIE - End-of-transfer interrupt enable | |
a7aea373 | 62 | * PRC_RM - PCI read multiple |
173acc7c | 63 | */ |
a1c03319 | 64 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE |
a7aea373 | 65 | | FSL_DMA_MR_PRC_RM, 32); |
173acc7c ZW |
66 | break; |
67 | } | |
173acc7c ZW |
68 | } |
69 | ||
a1c03319 | 70 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 71 | { |
a1c03319 | 72 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
73 | } |
74 | ||
a1c03319 | 75 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 76 | { |
a1c03319 | 77 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
78 | } |
79 | ||
a1c03319 | 80 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
81 | struct fsl_dma_ld_hw *hw, u32 count) |
82 | { | |
a1c03319 | 83 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
84 | } |
85 | ||
a1c03319 | 86 | static void set_desc_src(struct fsldma_chan *chan, |
173acc7c ZW |
87 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
88 | { | |
89 | u64 snoop_bits; | |
90 | ||
a1c03319 | 91 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 92 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 93 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
94 | } |
95 | ||
a1c03319 | 96 | static void set_desc_dst(struct fsldma_chan *chan, |
738f5f7e | 97 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
98 | { |
99 | u64 snoop_bits; | |
100 | ||
a1c03319 | 101 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 102 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 103 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
104 | } |
105 | ||
a1c03319 | 106 | static void set_desc_next(struct fsldma_chan *chan, |
173acc7c ZW |
107 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
108 | { | |
109 | u64 snoop_bits; | |
110 | ||
a1c03319 | 111 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 112 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 113 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
114 | } |
115 | ||
a1c03319 | 116 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
173acc7c | 117 | { |
a1c03319 | 118 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); |
173acc7c ZW |
119 | } |
120 | ||
a1c03319 | 121 | static dma_addr_t get_cdar(struct fsldma_chan *chan) |
173acc7c | 122 | { |
a1c03319 | 123 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; |
173acc7c ZW |
124 | } |
125 | ||
a1c03319 | 126 | static dma_addr_t get_ndar(struct fsldma_chan *chan) |
173acc7c | 127 | { |
a1c03319 | 128 | return DMA_IN(chan, &chan->regs->ndar, 64); |
173acc7c ZW |
129 | } |
130 | ||
a1c03319 | 131 | static u32 get_bcr(struct fsldma_chan *chan) |
f79abb62 | 132 | { |
a1c03319 | 133 | return DMA_IN(chan, &chan->regs->bcr, 32); |
f79abb62 ZW |
134 | } |
135 | ||
a1c03319 | 136 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 137 | { |
a1c03319 | 138 | u32 sr = get_sr(chan); |
173acc7c ZW |
139 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
140 | } | |
141 | ||
a1c03319 | 142 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 143 | { |
272ca655 IS |
144 | u32 mode; |
145 | ||
a1c03319 | 146 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 147 | |
a1c03319 IS |
148 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { |
149 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { | |
150 | DMA_OUT(chan, &chan->regs->bcr, 0, 32); | |
272ca655 IS |
151 | mode |= FSL_DMA_MR_EMP_EN; |
152 | } else { | |
153 | mode &= ~FSL_DMA_MR_EMP_EN; | |
154 | } | |
43a1a3ed | 155 | } |
173acc7c | 156 | |
a1c03319 | 157 | if (chan->feature & FSL_DMA_CHAN_START_EXT) |
272ca655 | 158 | mode |= FSL_DMA_MR_EMS_EN; |
173acc7c | 159 | else |
272ca655 | 160 | mode |= FSL_DMA_MR_CS; |
173acc7c | 161 | |
a1c03319 | 162 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
163 | } |
164 | ||
a1c03319 | 165 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 166 | { |
272ca655 | 167 | u32 mode; |
900325a6 DW |
168 | int i; |
169 | ||
a1c03319 | 170 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 171 | mode |= FSL_DMA_MR_CA; |
a1c03319 | 172 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
272ca655 IS |
173 | |
174 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); | |
a1c03319 | 175 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c | 176 | |
900325a6 | 177 | for (i = 0; i < 100; i++) { |
a1c03319 | 178 | if (dma_is_idle(chan)) |
9c3a50b7 IS |
179 | return; |
180 | ||
173acc7c | 181 | udelay(10); |
900325a6 | 182 | } |
272ca655 | 183 | |
9c3a50b7 | 184 | if (!dma_is_idle(chan)) |
a1c03319 | 185 | dev_err(chan->dev, "DMA halt timeout!\n"); |
173acc7c ZW |
186 | } |
187 | ||
a1c03319 | 188 | static void set_ld_eol(struct fsldma_chan *chan, |
173acc7c ZW |
189 | struct fsl_desc_sw *desc) |
190 | { | |
776c8943 IS |
191 | u64 snoop_bits; |
192 | ||
a1c03319 | 193 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
776c8943 IS |
194 | ? FSL_DMA_SNEN : 0; |
195 | ||
a1c03319 IS |
196 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
197 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
776c8943 | 198 | | snoop_bits, 64); |
173acc7c ZW |
199 | } |
200 | ||
173acc7c ZW |
201 | /** |
202 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 203 | * @chan : Freescale DMA channel |
173acc7c ZW |
204 | * @size : Address loop size, 0 for disable loop |
205 | * | |
206 | * The set source address hold transfer size. The source | |
207 | * address hold or loop transfer size is when the DMA transfer | |
208 | * data from source address (SA), if the loop size is 4, the DMA will | |
209 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
210 | * SA + 1 ... and so on. | |
211 | */ | |
a1c03319 | 212 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 213 | { |
272ca655 IS |
214 | u32 mode; |
215 | ||
a1c03319 | 216 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 217 | |
173acc7c ZW |
218 | switch (size) { |
219 | case 0: | |
272ca655 | 220 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
221 | break; |
222 | case 1: | |
223 | case 2: | |
224 | case 4: | |
225 | case 8: | |
272ca655 | 226 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
227 | break; |
228 | } | |
272ca655 | 229 | |
a1c03319 | 230 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
231 | } |
232 | ||
233 | /** | |
738f5f7e | 234 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 235 | * @chan : Freescale DMA channel |
173acc7c ZW |
236 | * @size : Address loop size, 0 for disable loop |
237 | * | |
238 | * The set destination address hold transfer size. The destination | |
239 | * address hold or loop transfer size is when the DMA transfer | |
240 | * data to destination address (TA), if the loop size is 4, the DMA will | |
241 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
242 | * TA + 1 ... and so on. | |
243 | */ | |
a1c03319 | 244 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 245 | { |
272ca655 IS |
246 | u32 mode; |
247 | ||
a1c03319 | 248 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 249 | |
173acc7c ZW |
250 | switch (size) { |
251 | case 0: | |
272ca655 | 252 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
253 | break; |
254 | case 1: | |
255 | case 2: | |
256 | case 4: | |
257 | case 8: | |
272ca655 | 258 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
259 | break; |
260 | } | |
272ca655 | 261 | |
a1c03319 | 262 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
263 | } |
264 | ||
265 | /** | |
e6c7ecb6 | 266 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 267 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
268 | * @size : Number of bytes to transfer in a single request |
269 | * | |
270 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
271 | * The DMA request count is how many bytes are allowed to transfer before | |
272 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
273 | * operation. | |
173acc7c | 274 | * |
e6c7ecb6 | 275 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 276 | */ |
a1c03319 | 277 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 278 | { |
272ca655 IS |
279 | u32 mode; |
280 | ||
e6c7ecb6 | 281 | BUG_ON(size > 1024); |
272ca655 | 282 | |
a1c03319 | 283 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 IS |
284 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
285 | ||
a1c03319 | 286 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
e6c7ecb6 | 287 | } |
173acc7c | 288 | |
e6c7ecb6 IS |
289 | /** |
290 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 291 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
292 | * @enable : 0 is disabled, 1 is enabled. |
293 | * | |
294 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
295 | * The DMA Request Count feature should be used in addition to this feature | |
296 | * to set the number of bytes to transfer before pausing the channel. | |
297 | */ | |
a1c03319 | 298 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
299 | { |
300 | if (enable) | |
a1c03319 | 301 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 302 | else |
a1c03319 | 303 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
304 | } |
305 | ||
306 | /** | |
307 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 308 | * @chan : Freescale DMA channel |
173acc7c ZW |
309 | * @enable : 0 is disabled, 1 is enabled. |
310 | * | |
311 | * If enable the external start, the channel can be started by an | |
312 | * external DMA start pin. So the dma_start() does not start the | |
313 | * transfer immediately. The DMA channel will wait for the | |
314 | * control pin asserted. | |
315 | */ | |
a1c03319 | 316 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
317 | { |
318 | if (enable) | |
a1c03319 | 319 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 320 | else |
a1c03319 | 321 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
322 | } |
323 | ||
9c3a50b7 IS |
324 | static void append_ld_queue(struct fsldma_chan *chan, |
325 | struct fsl_desc_sw *desc) | |
326 | { | |
327 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); | |
328 | ||
329 | if (list_empty(&chan->ld_pending)) | |
330 | goto out_splice; | |
331 | ||
332 | /* | |
333 | * Add the hardware descriptor to the chain of hardware descriptors | |
334 | * that already exists in memory. | |
335 | * | |
336 | * This will un-set the EOL bit of the existing transaction, and the | |
337 | * last link in this transaction will become the EOL descriptor. | |
338 | */ | |
339 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); | |
340 | ||
341 | /* | |
342 | * Add the software descriptor and all children to the list | |
343 | * of pending transactions | |
344 | */ | |
345 | out_splice: | |
346 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
347 | } | |
348 | ||
173acc7c ZW |
349 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
350 | { | |
a1c03319 | 351 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
352 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
353 | struct fsl_desc_sw *child; | |
173acc7c ZW |
354 | unsigned long flags; |
355 | dma_cookie_t cookie; | |
356 | ||
a1c03319 | 357 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 358 | |
9c3a50b7 IS |
359 | /* |
360 | * assign cookies to all of the software descriptors | |
361 | * that make up this transaction | |
362 | */ | |
a1c03319 | 363 | cookie = chan->common.cookie; |
eda34234 | 364 | list_for_each_entry(child, &desc->tx_list, node) { |
bcfb7465 IS |
365 | cookie++; |
366 | if (cookie < 0) | |
367 | cookie = 1; | |
368 | ||
6ca3a7a9 | 369 | child->async_tx.cookie = cookie; |
bcfb7465 IS |
370 | } |
371 | ||
a1c03319 | 372 | chan->common.cookie = cookie; |
9c3a50b7 IS |
373 | |
374 | /* put this transaction onto the tail of the pending queue */ | |
a1c03319 | 375 | append_ld_queue(chan, desc); |
173acc7c | 376 | |
a1c03319 | 377 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
378 | |
379 | return cookie; | |
380 | } | |
381 | ||
382 | /** | |
383 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 384 | * @chan : Freescale DMA channel |
173acc7c ZW |
385 | * |
386 | * Return - The descriptor allocated. NULL for failed. | |
387 | */ | |
388 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor( | |
a1c03319 | 389 | struct fsldma_chan *chan) |
173acc7c | 390 | { |
9c3a50b7 | 391 | struct fsl_desc_sw *desc; |
173acc7c | 392 | dma_addr_t pdesc; |
9c3a50b7 IS |
393 | |
394 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); | |
395 | if (!desc) { | |
396 | dev_dbg(chan->dev, "out of memory for link desc\n"); | |
397 | return NULL; | |
173acc7c ZW |
398 | } |
399 | ||
9c3a50b7 IS |
400 | memset(desc, 0, sizeof(*desc)); |
401 | INIT_LIST_HEAD(&desc->tx_list); | |
402 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); | |
403 | desc->async_tx.tx_submit = fsl_dma_tx_submit; | |
404 | desc->async_tx.phys = pdesc; | |
405 | ||
406 | return desc; | |
173acc7c ZW |
407 | } |
408 | ||
409 | ||
410 | /** | |
411 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 412 | * @chan : Freescale DMA channel |
173acc7c ZW |
413 | * |
414 | * This function will create a dma pool for descriptor allocation. | |
415 | * | |
416 | * Return - The number of descriptors allocated. | |
417 | */ | |
a1c03319 | 418 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 419 | { |
a1c03319 | 420 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
421 | |
422 | /* Has this channel already been allocated? */ | |
a1c03319 | 423 | if (chan->desc_pool) |
77cd62e8 | 424 | return 1; |
173acc7c | 425 | |
9c3a50b7 IS |
426 | /* |
427 | * We need the descriptor to be aligned to 32bytes | |
173acc7c ZW |
428 | * for meeting FSL DMA specification requirement. |
429 | */ | |
a1c03319 | 430 | chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", |
9c3a50b7 IS |
431 | chan->dev, |
432 | sizeof(struct fsl_desc_sw), | |
433 | __alignof__(struct fsl_desc_sw), 0); | |
a1c03319 | 434 | if (!chan->desc_pool) { |
9c3a50b7 IS |
435 | dev_err(chan->dev, "unable to allocate channel %d " |
436 | "descriptor pool\n", chan->id); | |
437 | return -ENOMEM; | |
173acc7c ZW |
438 | } |
439 | ||
9c3a50b7 | 440 | /* there is at least one descriptor free to be allocated */ |
173acc7c ZW |
441 | return 1; |
442 | } | |
443 | ||
9c3a50b7 IS |
444 | /** |
445 | * fsldma_free_desc_list - Free all descriptors in a queue | |
446 | * @chan: Freescae DMA channel | |
447 | * @list: the list to free | |
448 | * | |
449 | * LOCKING: must hold chan->desc_lock | |
450 | */ | |
451 | static void fsldma_free_desc_list(struct fsldma_chan *chan, | |
452 | struct list_head *list) | |
453 | { | |
454 | struct fsl_desc_sw *desc, *_desc; | |
455 | ||
456 | list_for_each_entry_safe(desc, _desc, list, node) { | |
457 | list_del(&desc->node); | |
458 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
459 | } | |
460 | } | |
461 | ||
462 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, | |
463 | struct list_head *list) | |
464 | { | |
465 | struct fsl_desc_sw *desc, *_desc; | |
466 | ||
467 | list_for_each_entry_safe_reverse(desc, _desc, list, node) { | |
468 | list_del(&desc->node); | |
469 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
470 | } | |
471 | } | |
472 | ||
173acc7c ZW |
473 | /** |
474 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 475 | * @chan : Freescale DMA channel |
173acc7c | 476 | */ |
a1c03319 | 477 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 478 | { |
a1c03319 | 479 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
480 | unsigned long flags; |
481 | ||
a1c03319 IS |
482 | dev_dbg(chan->dev, "Free all channel resources.\n"); |
483 | spin_lock_irqsave(&chan->desc_lock, flags); | |
9c3a50b7 IS |
484 | fsldma_free_desc_list(chan, &chan->ld_pending); |
485 | fsldma_free_desc_list(chan, &chan->ld_running); | |
a1c03319 | 486 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
77cd62e8 | 487 | |
9c3a50b7 | 488 | dma_pool_destroy(chan->desc_pool); |
a1c03319 | 489 | chan->desc_pool = NULL; |
173acc7c ZW |
490 | } |
491 | ||
2187c269 | 492 | static struct dma_async_tx_descriptor * |
a1c03319 | 493 | fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) |
2187c269 | 494 | { |
a1c03319 | 495 | struct fsldma_chan *chan; |
2187c269 ZW |
496 | struct fsl_desc_sw *new; |
497 | ||
a1c03319 | 498 | if (!dchan) |
2187c269 ZW |
499 | return NULL; |
500 | ||
a1c03319 | 501 | chan = to_fsl_chan(dchan); |
2187c269 | 502 | |
a1c03319 | 503 | new = fsl_dma_alloc_descriptor(chan); |
2187c269 | 504 | if (!new) { |
c1433041 | 505 | dev_err(chan->dev, msg_ld_oom); |
2187c269 ZW |
506 | return NULL; |
507 | } | |
508 | ||
509 | new->async_tx.cookie = -EBUSY; | |
636bdeaa | 510 | new->async_tx.flags = flags; |
2187c269 | 511 | |
f79abb62 | 512 | /* Insert the link descriptor to the LD ring */ |
eda34234 | 513 | list_add_tail(&new->node, &new->tx_list); |
f79abb62 | 514 | |
2187c269 | 515 | /* Set End-of-link to the last link descriptor of new list*/ |
a1c03319 | 516 | set_ld_eol(chan, new); |
2187c269 ZW |
517 | |
518 | return &new->async_tx; | |
519 | } | |
520 | ||
173acc7c | 521 | static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( |
a1c03319 | 522 | struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, |
173acc7c ZW |
523 | size_t len, unsigned long flags) |
524 | { | |
a1c03319 | 525 | struct fsldma_chan *chan; |
173acc7c ZW |
526 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
527 | size_t copy; | |
173acc7c | 528 | |
a1c03319 | 529 | if (!dchan) |
173acc7c ZW |
530 | return NULL; |
531 | ||
532 | if (!len) | |
533 | return NULL; | |
534 | ||
a1c03319 | 535 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
536 | |
537 | do { | |
538 | ||
539 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 540 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 541 | if (!new) { |
c1433041 | 542 | dev_err(chan->dev, msg_ld_oom); |
2e077f8e | 543 | goto fail; |
173acc7c ZW |
544 | } |
545 | #ifdef FSL_DMA_LD_DEBUG | |
a1c03319 | 546 | dev_dbg(chan->dev, "new link desc alloc %p\n", new); |
173acc7c ZW |
547 | #endif |
548 | ||
56822843 | 549 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 550 | |
a1c03319 IS |
551 | set_desc_cnt(chan, &new->hw, copy); |
552 | set_desc_src(chan, &new->hw, dma_src); | |
553 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
554 | |
555 | if (!first) | |
556 | first = new; | |
557 | else | |
a1c03319 | 558 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
559 | |
560 | new->async_tx.cookie = 0; | |
636bdeaa | 561 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
562 | |
563 | prev = new; | |
564 | len -= copy; | |
565 | dma_src += copy; | |
738f5f7e | 566 | dma_dst += copy; |
173acc7c ZW |
567 | |
568 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 569 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
570 | } while (len); |
571 | ||
636bdeaa | 572 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
573 | new->async_tx.cookie = -EBUSY; |
574 | ||
575 | /* Set End-of-link to the last link descriptor of new list*/ | |
a1c03319 | 576 | set_ld_eol(chan, new); |
173acc7c | 577 | |
2e077f8e IS |
578 | return &first->async_tx; |
579 | ||
580 | fail: | |
581 | if (!first) | |
582 | return NULL; | |
583 | ||
9c3a50b7 | 584 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
2e077f8e | 585 | return NULL; |
173acc7c ZW |
586 | } |
587 | ||
c1433041 IS |
588 | static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan, |
589 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
590 | struct scatterlist *src_sg, unsigned int src_nents, | |
591 | unsigned long flags) | |
592 | { | |
593 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; | |
594 | struct fsldma_chan *chan = to_fsl_chan(dchan); | |
595 | size_t dst_avail, src_avail; | |
596 | dma_addr_t dst, src; | |
597 | size_t len; | |
598 | ||
599 | /* basic sanity checks */ | |
600 | if (dst_nents == 0 || src_nents == 0) | |
601 | return NULL; | |
602 | ||
603 | if (dst_sg == NULL || src_sg == NULL) | |
604 | return NULL; | |
605 | ||
606 | /* | |
607 | * TODO: should we check that both scatterlists have the same | |
608 | * TODO: number of bytes in total? Is that really an error? | |
609 | */ | |
610 | ||
611 | /* get prepared for the loop */ | |
612 | dst_avail = sg_dma_len(dst_sg); | |
613 | src_avail = sg_dma_len(src_sg); | |
614 | ||
615 | /* run until we are out of scatterlist entries */ | |
616 | while (true) { | |
617 | ||
618 | /* create the largest transaction possible */ | |
619 | len = min_t(size_t, src_avail, dst_avail); | |
620 | len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT); | |
621 | if (len == 0) | |
622 | goto fetch; | |
623 | ||
624 | dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; | |
625 | src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; | |
626 | ||
627 | /* allocate and populate the descriptor */ | |
628 | new = fsl_dma_alloc_descriptor(chan); | |
629 | if (!new) { | |
630 | dev_err(chan->dev, msg_ld_oom); | |
631 | goto fail; | |
632 | } | |
633 | #ifdef FSL_DMA_LD_DEBUG | |
634 | dev_dbg(chan->dev, "new link desc alloc %p\n", new); | |
635 | #endif | |
636 | ||
637 | set_desc_cnt(chan, &new->hw, len); | |
638 | set_desc_src(chan, &new->hw, src); | |
639 | set_desc_dst(chan, &new->hw, dst); | |
640 | ||
641 | if (!first) | |
642 | first = new; | |
643 | else | |
644 | set_desc_next(chan, &prev->hw, new->async_tx.phys); | |
645 | ||
646 | new->async_tx.cookie = 0; | |
647 | async_tx_ack(&new->async_tx); | |
648 | prev = new; | |
649 | ||
650 | /* Insert the link descriptor to the LD ring */ | |
651 | list_add_tail(&new->node, &first->tx_list); | |
652 | ||
653 | /* update metadata */ | |
654 | dst_avail -= len; | |
655 | src_avail -= len; | |
656 | ||
657 | fetch: | |
658 | /* fetch the next dst scatterlist entry */ | |
659 | if (dst_avail == 0) { | |
660 | ||
661 | /* no more entries: we're done */ | |
662 | if (dst_nents == 0) | |
663 | break; | |
664 | ||
665 | /* fetch the next entry: if there are no more: done */ | |
666 | dst_sg = sg_next(dst_sg); | |
667 | if (dst_sg == NULL) | |
668 | break; | |
669 | ||
670 | dst_nents--; | |
671 | dst_avail = sg_dma_len(dst_sg); | |
672 | } | |
673 | ||
674 | /* fetch the next src scatterlist entry */ | |
675 | if (src_avail == 0) { | |
676 | ||
677 | /* no more entries: we're done */ | |
678 | if (src_nents == 0) | |
679 | break; | |
680 | ||
681 | /* fetch the next entry: if there are no more: done */ | |
682 | src_sg = sg_next(src_sg); | |
683 | if (src_sg == NULL) | |
684 | break; | |
685 | ||
686 | src_nents--; | |
687 | src_avail = sg_dma_len(src_sg); | |
688 | } | |
689 | } | |
690 | ||
691 | new->async_tx.flags = flags; /* client is in control of this ack */ | |
692 | new->async_tx.cookie = -EBUSY; | |
693 | ||
694 | /* Set End-of-link to the last link descriptor of new list */ | |
695 | set_ld_eol(chan, new); | |
696 | ||
697 | return &first->async_tx; | |
698 | ||
699 | fail: | |
700 | if (!first) | |
701 | return NULL; | |
702 | ||
703 | fsldma_free_desc_list_reverse(chan, &first->tx_list); | |
704 | return NULL; | |
705 | } | |
706 | ||
bbea0b6e IS |
707 | /** |
708 | * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
709 | * @chan: DMA channel | |
710 | * @sgl: scatterlist to transfer to/from | |
711 | * @sg_len: number of entries in @scatterlist | |
712 | * @direction: DMA direction | |
713 | * @flags: DMAEngine flags | |
714 | * | |
715 | * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the | |
716 | * DMA_SLAVE API, this gets the device-specific information from the | |
717 | * chan->private variable. | |
718 | */ | |
719 | static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( | |
a1c03319 | 720 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
bbea0b6e IS |
721 | enum dma_data_direction direction, unsigned long flags) |
722 | { | |
bbea0b6e | 723 | /* |
968f19ae | 724 | * This operation is not supported on the Freescale DMA controller |
bbea0b6e | 725 | * |
968f19ae IS |
726 | * However, we need to provide the function pointer to allow the |
727 | * device_control() method to work. | |
bbea0b6e | 728 | */ |
bbea0b6e IS |
729 | return NULL; |
730 | } | |
731 | ||
c3635c78 | 732 | static int fsl_dma_device_control(struct dma_chan *dchan, |
05827630 | 733 | enum dma_ctrl_cmd cmd, unsigned long arg) |
bbea0b6e | 734 | { |
968f19ae | 735 | struct dma_slave_config *config; |
a1c03319 | 736 | struct fsldma_chan *chan; |
bbea0b6e | 737 | unsigned long flags; |
968f19ae | 738 | int size; |
c3635c78 | 739 | |
a1c03319 | 740 | if (!dchan) |
c3635c78 | 741 | return -EINVAL; |
bbea0b6e | 742 | |
a1c03319 | 743 | chan = to_fsl_chan(dchan); |
bbea0b6e | 744 | |
968f19ae IS |
745 | switch (cmd) { |
746 | case DMA_TERMINATE_ALL: | |
747 | /* Halt the DMA engine */ | |
748 | dma_halt(chan); | |
bbea0b6e | 749 | |
968f19ae | 750 | spin_lock_irqsave(&chan->desc_lock, flags); |
bbea0b6e | 751 | |
968f19ae IS |
752 | /* Remove and free all of the descriptors in the LD queue */ |
753 | fsldma_free_desc_list(chan, &chan->ld_pending); | |
754 | fsldma_free_desc_list(chan, &chan->ld_running); | |
bbea0b6e | 755 | |
968f19ae IS |
756 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
757 | return 0; | |
758 | ||
759 | case DMA_SLAVE_CONFIG: | |
760 | config = (struct dma_slave_config *)arg; | |
761 | ||
762 | /* make sure the channel supports setting burst size */ | |
763 | if (!chan->set_request_count) | |
764 | return -ENXIO; | |
765 | ||
766 | /* we set the controller burst size depending on direction */ | |
767 | if (config->direction == DMA_TO_DEVICE) | |
768 | size = config->dst_addr_width * config->dst_maxburst; | |
769 | else | |
770 | size = config->src_addr_width * config->src_maxburst; | |
771 | ||
772 | chan->set_request_count(chan, size); | |
773 | return 0; | |
774 | ||
775 | case FSLDMA_EXTERNAL_START: | |
776 | ||
777 | /* make sure the channel supports external start */ | |
778 | if (!chan->toggle_ext_start) | |
779 | return -ENXIO; | |
780 | ||
781 | chan->toggle_ext_start(chan, arg); | |
782 | return 0; | |
783 | ||
784 | default: | |
785 | return -ENXIO; | |
786 | } | |
c3635c78 LW |
787 | |
788 | return 0; | |
bbea0b6e IS |
789 | } |
790 | ||
173acc7c ZW |
791 | /** |
792 | * fsl_dma_update_completed_cookie - Update the completed cookie. | |
a1c03319 | 793 | * @chan : Freescale DMA channel |
9c3a50b7 IS |
794 | * |
795 | * CONTEXT: hardirq | |
173acc7c | 796 | */ |
a1c03319 | 797 | static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) |
173acc7c | 798 | { |
9c3a50b7 IS |
799 | struct fsl_desc_sw *desc; |
800 | unsigned long flags; | |
801 | dma_cookie_t cookie; | |
173acc7c | 802 | |
9c3a50b7 | 803 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 804 | |
9c3a50b7 IS |
805 | if (list_empty(&chan->ld_running)) { |
806 | dev_dbg(chan->dev, "no running descriptors\n"); | |
807 | goto out_unlock; | |
173acc7c | 808 | } |
9c3a50b7 IS |
809 | |
810 | /* Get the last descriptor, update the cookie to that */ | |
811 | desc = to_fsl_desc(chan->ld_running.prev); | |
812 | if (dma_is_idle(chan)) | |
813 | cookie = desc->async_tx.cookie; | |
76bd061f | 814 | else { |
9c3a50b7 | 815 | cookie = desc->async_tx.cookie - 1; |
76bd061f SM |
816 | if (unlikely(cookie < DMA_MIN_COOKIE)) |
817 | cookie = DMA_MAX_COOKIE; | |
818 | } | |
9c3a50b7 IS |
819 | |
820 | chan->completed_cookie = cookie; | |
821 | ||
822 | out_unlock: | |
823 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
824 | } | |
825 | ||
826 | /** | |
827 | * fsldma_desc_status - Check the status of a descriptor | |
828 | * @chan: Freescale DMA channel | |
829 | * @desc: DMA SW descriptor | |
830 | * | |
831 | * This function will return the status of the given descriptor | |
832 | */ | |
833 | static enum dma_status fsldma_desc_status(struct fsldma_chan *chan, | |
834 | struct fsl_desc_sw *desc) | |
835 | { | |
836 | return dma_async_is_complete(desc->async_tx.cookie, | |
837 | chan->completed_cookie, | |
838 | chan->common.cookie); | |
173acc7c ZW |
839 | } |
840 | ||
841 | /** | |
842 | * fsl_chan_ld_cleanup - Clean up link descriptors | |
a1c03319 | 843 | * @chan : Freescale DMA channel |
173acc7c ZW |
844 | * |
845 | * This function clean up the ld_queue of DMA channel. | |
173acc7c | 846 | */ |
a1c03319 | 847 | static void fsl_chan_ld_cleanup(struct fsldma_chan *chan) |
173acc7c ZW |
848 | { |
849 | struct fsl_desc_sw *desc, *_desc; | |
850 | unsigned long flags; | |
851 | ||
a1c03319 | 852 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 853 | |
9c3a50b7 IS |
854 | dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie); |
855 | list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { | |
173acc7c ZW |
856 | dma_async_tx_callback callback; |
857 | void *callback_param; | |
858 | ||
9c3a50b7 | 859 | if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS) |
173acc7c ZW |
860 | break; |
861 | ||
9c3a50b7 | 862 | /* Remove from the list of running transactions */ |
173acc7c ZW |
863 | list_del(&desc->node); |
864 | ||
173acc7c | 865 | /* Run the link descriptor callback function */ |
9c3a50b7 IS |
866 | callback = desc->async_tx.callback; |
867 | callback_param = desc->async_tx.callback_param; | |
173acc7c | 868 | if (callback) { |
a1c03319 | 869 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
9c3a50b7 | 870 | dev_dbg(chan->dev, "LD %p callback\n", desc); |
173acc7c | 871 | callback(callback_param); |
a1c03319 | 872 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 873 | } |
9c3a50b7 IS |
874 | |
875 | /* Run any dependencies, then free the descriptor */ | |
876 | dma_run_dependencies(&desc->async_tx); | |
877 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
173acc7c | 878 | } |
9c3a50b7 | 879 | |
a1c03319 | 880 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
881 | } |
882 | ||
883 | /** | |
9c3a50b7 | 884 | * fsl_chan_xfer_ld_queue - transfer any pending transactions |
a1c03319 | 885 | * @chan : Freescale DMA channel |
9c3a50b7 IS |
886 | * |
887 | * This will make sure that any pending transactions will be run. | |
888 | * If the DMA controller is idle, it will be started. Otherwise, | |
889 | * the DMA controller's interrupt handler will start any pending | |
890 | * transactions when it becomes idle. | |
173acc7c | 891 | */ |
a1c03319 | 892 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) |
173acc7c | 893 | { |
9c3a50b7 | 894 | struct fsl_desc_sw *desc; |
173acc7c ZW |
895 | unsigned long flags; |
896 | ||
a1c03319 | 897 | spin_lock_irqsave(&chan->desc_lock, flags); |
138ef018 | 898 | |
9c3a50b7 IS |
899 | /* |
900 | * If the list of pending descriptors is empty, then we | |
901 | * don't need to do any work at all | |
902 | */ | |
903 | if (list_empty(&chan->ld_pending)) { | |
904 | dev_dbg(chan->dev, "no pending LDs\n"); | |
138ef018 | 905 | goto out_unlock; |
9c3a50b7 | 906 | } |
173acc7c | 907 | |
9c3a50b7 IS |
908 | /* |
909 | * The DMA controller is not idle, which means the interrupt | |
910 | * handler will start any queued transactions when it runs | |
911 | * at the end of the current transaction | |
912 | */ | |
913 | if (!dma_is_idle(chan)) { | |
914 | dev_dbg(chan->dev, "DMA controller still busy\n"); | |
915 | goto out_unlock; | |
916 | } | |
917 | ||
918 | /* | |
919 | * TODO: | |
920 | * make sure the dma_halt() function really un-wedges the | |
921 | * controller as much as possible | |
922 | */ | |
a1c03319 | 923 | dma_halt(chan); |
173acc7c | 924 | |
9c3a50b7 IS |
925 | /* |
926 | * If there are some link descriptors which have not been | |
927 | * transferred, we need to start the controller | |
173acc7c | 928 | */ |
173acc7c | 929 | |
9c3a50b7 IS |
930 | /* |
931 | * Move all elements from the queue of pending transactions | |
932 | * onto the list of running transactions | |
933 | */ | |
934 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); | |
935 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); | |
936 | ||
937 | /* | |
938 | * Program the descriptor's address into the DMA controller, | |
939 | * then start the DMA transaction | |
940 | */ | |
941 | set_cdar(chan, desc->async_tx.phys); | |
942 | dma_start(chan); | |
138ef018 IS |
943 | |
944 | out_unlock: | |
a1c03319 | 945 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
946 | } |
947 | ||
948 | /** | |
949 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 950 | * @chan : Freescale DMA channel |
173acc7c | 951 | */ |
a1c03319 | 952 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 953 | { |
a1c03319 | 954 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
a1c03319 | 955 | fsl_chan_xfer_ld_queue(chan); |
173acc7c ZW |
956 | } |
957 | ||
173acc7c | 958 | /** |
07934481 | 959 | * fsl_tx_status - Determine the DMA status |
a1c03319 | 960 | * @chan : Freescale DMA channel |
173acc7c | 961 | */ |
07934481 | 962 | static enum dma_status fsl_tx_status(struct dma_chan *dchan, |
173acc7c | 963 | dma_cookie_t cookie, |
07934481 | 964 | struct dma_tx_state *txstate) |
173acc7c | 965 | { |
a1c03319 | 966 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
967 | dma_cookie_t last_used; |
968 | dma_cookie_t last_complete; | |
969 | ||
a1c03319 | 970 | fsl_chan_ld_cleanup(chan); |
173acc7c | 971 | |
a1c03319 IS |
972 | last_used = dchan->cookie; |
973 | last_complete = chan->completed_cookie; | |
173acc7c | 974 | |
bca34692 | 975 | dma_set_tx_state(txstate, last_complete, last_used, 0); |
173acc7c ZW |
976 | |
977 | return dma_async_is_complete(cookie, last_complete, last_used); | |
978 | } | |
979 | ||
d3f620b2 IS |
980 | /*----------------------------------------------------------------------------*/ |
981 | /* Interrupt Handling */ | |
982 | /*----------------------------------------------------------------------------*/ | |
983 | ||
e7a29151 | 984 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 985 | { |
a1c03319 | 986 | struct fsldma_chan *chan = data; |
1c62979e ZW |
987 | int update_cookie = 0; |
988 | int xfer_ld_q = 0; | |
a1c03319 | 989 | u32 stat; |
173acc7c | 990 | |
9c3a50b7 | 991 | /* save and clear the status register */ |
a1c03319 | 992 | stat = get_sr(chan); |
9c3a50b7 IS |
993 | set_sr(chan, stat); |
994 | dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat); | |
173acc7c ZW |
995 | |
996 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); | |
997 | if (!stat) | |
998 | return IRQ_NONE; | |
999 | ||
1000 | if (stat & FSL_DMA_SR_TE) | |
a1c03319 | 1001 | dev_err(chan->dev, "Transfer Error!\n"); |
173acc7c | 1002 | |
9c3a50b7 IS |
1003 | /* |
1004 | * Programming Error | |
f79abb62 ZW |
1005 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
1006 | * triger a PE interrupt. | |
1007 | */ | |
1008 | if (stat & FSL_DMA_SR_PE) { | |
9c3a50b7 | 1009 | dev_dbg(chan->dev, "irq: Programming Error INT\n"); |
a1c03319 | 1010 | if (get_bcr(chan) == 0) { |
f79abb62 ZW |
1011 | /* BCR register is 0, this is a DMA_INTERRUPT async_tx. |
1012 | * Now, update the completed cookie, and continue the | |
1013 | * next uncompleted transfer. | |
1014 | */ | |
1c62979e ZW |
1015 | update_cookie = 1; |
1016 | xfer_ld_q = 1; | |
f79abb62 ZW |
1017 | } |
1018 | stat &= ~FSL_DMA_SR_PE; | |
1019 | } | |
1020 | ||
9c3a50b7 IS |
1021 | /* |
1022 | * If the link descriptor segment transfer finishes, | |
173acc7c ZW |
1023 | * we will recycle the used descriptor. |
1024 | */ | |
1025 | if (stat & FSL_DMA_SR_EOSI) { | |
9c3a50b7 IS |
1026 | dev_dbg(chan->dev, "irq: End-of-segments INT\n"); |
1027 | dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n", | |
a1c03319 IS |
1028 | (unsigned long long)get_cdar(chan), |
1029 | (unsigned long long)get_ndar(chan)); | |
173acc7c | 1030 | stat &= ~FSL_DMA_SR_EOSI; |
1c62979e ZW |
1031 | update_cookie = 1; |
1032 | } | |
1033 | ||
9c3a50b7 IS |
1034 | /* |
1035 | * For MPC8349, EOCDI event need to update cookie | |
1c62979e ZW |
1036 | * and start the next transfer if it exist. |
1037 | */ | |
1038 | if (stat & FSL_DMA_SR_EOCDI) { | |
9c3a50b7 | 1039 | dev_dbg(chan->dev, "irq: End-of-Chain link INT\n"); |
1c62979e ZW |
1040 | stat &= ~FSL_DMA_SR_EOCDI; |
1041 | update_cookie = 1; | |
1042 | xfer_ld_q = 1; | |
173acc7c ZW |
1043 | } |
1044 | ||
9c3a50b7 IS |
1045 | /* |
1046 | * If it current transfer is the end-of-transfer, | |
173acc7c ZW |
1047 | * we should clear the Channel Start bit for |
1048 | * prepare next transfer. | |
1049 | */ | |
1c62979e | 1050 | if (stat & FSL_DMA_SR_EOLNI) { |
9c3a50b7 | 1051 | dev_dbg(chan->dev, "irq: End-of-link INT\n"); |
173acc7c | 1052 | stat &= ~FSL_DMA_SR_EOLNI; |
1c62979e | 1053 | xfer_ld_q = 1; |
173acc7c ZW |
1054 | } |
1055 | ||
1c62979e | 1056 | if (update_cookie) |
a1c03319 | 1057 | fsl_dma_update_completed_cookie(chan); |
1c62979e | 1058 | if (xfer_ld_q) |
a1c03319 | 1059 | fsl_chan_xfer_ld_queue(chan); |
173acc7c | 1060 | if (stat) |
9c3a50b7 | 1061 | dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat); |
173acc7c | 1062 | |
9c3a50b7 | 1063 | dev_dbg(chan->dev, "irq: Exit\n"); |
a1c03319 | 1064 | tasklet_schedule(&chan->tasklet); |
173acc7c ZW |
1065 | return IRQ_HANDLED; |
1066 | } | |
1067 | ||
d3f620b2 IS |
1068 | static void dma_do_tasklet(unsigned long data) |
1069 | { | |
a1c03319 IS |
1070 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
1071 | fsl_chan_ld_cleanup(chan); | |
d3f620b2 IS |
1072 | } |
1073 | ||
1074 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1075 | { |
a4f56d4b | 1076 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1077 | struct fsldma_chan *chan; |
1078 | unsigned int handled = 0; | |
1079 | u32 gsr, mask; | |
1080 | int i; | |
173acc7c | 1081 | |
e7a29151 | 1082 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1083 | : in_le32(fdev->regs); |
1084 | mask = 0xff000000; | |
1085 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1086 | |
d3f620b2 IS |
1087 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1088 | chan = fdev->chan[i]; | |
1089 | if (!chan) | |
1090 | continue; | |
1091 | ||
1092 | if (gsr & mask) { | |
1093 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1094 | fsldma_chan_irq(irq, chan); | |
1095 | handled++; | |
1096 | } | |
1097 | ||
1098 | gsr &= ~mask; | |
1099 | mask >>= 8; | |
1100 | } | |
1101 | ||
1102 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1103 | } |
1104 | ||
d3f620b2 | 1105 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1106 | { |
d3f620b2 IS |
1107 | struct fsldma_chan *chan; |
1108 | int i; | |
1109 | ||
1110 | if (fdev->irq != NO_IRQ) { | |
1111 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); | |
1112 | free_irq(fdev->irq, fdev); | |
1113 | return; | |
1114 | } | |
1115 | ||
1116 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1117 | chan = fdev->chan[i]; | |
1118 | if (chan && chan->irq != NO_IRQ) { | |
1119 | dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id); | |
1120 | free_irq(chan->irq, chan); | |
1121 | } | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1126 | { | |
1127 | struct fsldma_chan *chan; | |
1128 | int ret; | |
1129 | int i; | |
1130 | ||
1131 | /* if we have a per-controller IRQ, use that */ | |
1132 | if (fdev->irq != NO_IRQ) { | |
1133 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); | |
1134 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1135 | "fsldma-controller", fdev); | |
1136 | return ret; | |
1137 | } | |
1138 | ||
1139 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1140 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1141 | chan = fdev->chan[i]; | |
1142 | if (!chan) | |
1143 | continue; | |
1144 | ||
1145 | if (chan->irq == NO_IRQ) { | |
1146 | dev_err(fdev->dev, "no interrupts property defined for " | |
1147 | "DMA channel %d. Please fix your " | |
1148 | "device tree\n", chan->id); | |
1149 | ret = -ENODEV; | |
1150 | goto out_unwind; | |
1151 | } | |
1152 | ||
1153 | dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id); | |
1154 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, | |
1155 | "fsldma-chan", chan); | |
1156 | if (ret) { | |
1157 | dev_err(fdev->dev, "unable to request IRQ for DMA " | |
1158 | "channel %d\n", chan->id); | |
1159 | goto out_unwind; | |
1160 | } | |
1161 | } | |
1162 | ||
1163 | return 0; | |
1164 | ||
1165 | out_unwind: | |
1166 | for (/* none */; i >= 0; i--) { | |
1167 | chan = fdev->chan[i]; | |
1168 | if (!chan) | |
1169 | continue; | |
1170 | ||
1171 | if (chan->irq == NO_IRQ) | |
1172 | continue; | |
1173 | ||
1174 | free_irq(chan->irq, chan); | |
1175 | } | |
1176 | ||
1177 | return ret; | |
173acc7c ZW |
1178 | } |
1179 | ||
a4f56d4b IS |
1180 | /*----------------------------------------------------------------------------*/ |
1181 | /* OpenFirmware Subsystem */ | |
1182 | /*----------------------------------------------------------------------------*/ | |
1183 | ||
1184 | static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, | |
77cd62e8 | 1185 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1186 | { |
a1c03319 | 1187 | struct fsldma_chan *chan; |
4ce0e953 | 1188 | struct resource res; |
173acc7c ZW |
1189 | int err; |
1190 | ||
173acc7c | 1191 | /* alloc channel */ |
a1c03319 IS |
1192 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1193 | if (!chan) { | |
e7a29151 IS |
1194 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
1195 | err = -ENOMEM; | |
1196 | goto out_return; | |
1197 | } | |
1198 | ||
1199 | /* ioremap registers for use */ | |
a1c03319 IS |
1200 | chan->regs = of_iomap(node, 0); |
1201 | if (!chan->regs) { | |
e7a29151 IS |
1202 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1203 | err = -ENOMEM; | |
a1c03319 | 1204 | goto out_free_chan; |
173acc7c ZW |
1205 | } |
1206 | ||
4ce0e953 | 1207 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1208 | if (err) { |
e7a29151 IS |
1209 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1210 | goto out_iounmap_regs; | |
173acc7c ZW |
1211 | } |
1212 | ||
a1c03319 | 1213 | chan->feature = feature; |
173acc7c | 1214 | if (!fdev->feature) |
a1c03319 | 1215 | fdev->feature = chan->feature; |
173acc7c | 1216 | |
e7a29151 IS |
1217 | /* |
1218 | * If the DMA device's feature is different than the feature | |
1219 | * of its channels, report the bug | |
173acc7c | 1220 | */ |
a1c03319 | 1221 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1222 | |
a1c03319 IS |
1223 | chan->dev = fdev->dev; |
1224 | chan->id = ((res.start - 0x100) & 0xfff) >> 7; | |
1225 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { | |
e7a29151 | 1226 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1227 | err = -EINVAL; |
e7a29151 | 1228 | goto out_iounmap_regs; |
173acc7c | 1229 | } |
173acc7c | 1230 | |
a1c03319 IS |
1231 | fdev->chan[chan->id] = chan; |
1232 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
e7a29151 IS |
1233 | |
1234 | /* Initialize the channel */ | |
a1c03319 | 1235 | dma_init(chan); |
173acc7c ZW |
1236 | |
1237 | /* Clear cdar registers */ | |
a1c03319 | 1238 | set_cdar(chan, 0); |
173acc7c | 1239 | |
a1c03319 | 1240 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1241 | case FSL_DMA_IP_85XX: |
a1c03319 | 1242 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1243 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1244 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1245 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1246 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1247 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1248 | } |
1249 | ||
a1c03319 | 1250 | spin_lock_init(&chan->desc_lock); |
9c3a50b7 IS |
1251 | INIT_LIST_HEAD(&chan->ld_pending); |
1252 | INIT_LIST_HEAD(&chan->ld_running); | |
173acc7c | 1253 | |
a1c03319 | 1254 | chan->common.device = &fdev->common; |
173acc7c | 1255 | |
d3f620b2 | 1256 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1257 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1258 | |
173acc7c | 1259 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1260 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c ZW |
1261 | fdev->common.chancnt++; |
1262 | ||
a1c03319 IS |
1263 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
1264 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); | |
173acc7c ZW |
1265 | |
1266 | return 0; | |
51ee87f2 | 1267 | |
e7a29151 | 1268 | out_iounmap_regs: |
a1c03319 IS |
1269 | iounmap(chan->regs); |
1270 | out_free_chan: | |
1271 | kfree(chan); | |
e7a29151 | 1272 | out_return: |
173acc7c ZW |
1273 | return err; |
1274 | } | |
1275 | ||
a1c03319 | 1276 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1277 | { |
a1c03319 IS |
1278 | irq_dispose_mapping(chan->irq); |
1279 | list_del(&chan->common.device_node); | |
1280 | iounmap(chan->regs); | |
1281 | kfree(chan); | |
173acc7c ZW |
1282 | } |
1283 | ||
00006124 | 1284 | static int __devinit fsldma_of_probe(struct platform_device *op) |
173acc7c | 1285 | { |
a4f56d4b | 1286 | struct fsldma_device *fdev; |
77cd62e8 | 1287 | struct device_node *child; |
e7a29151 | 1288 | int err; |
173acc7c | 1289 | |
a4f56d4b | 1290 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1291 | if (!fdev) { |
e7a29151 IS |
1292 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
1293 | err = -ENOMEM; | |
1294 | goto out_return; | |
173acc7c | 1295 | } |
e7a29151 IS |
1296 | |
1297 | fdev->dev = &op->dev; | |
173acc7c ZW |
1298 | INIT_LIST_HEAD(&fdev->common.channels); |
1299 | ||
e7a29151 | 1300 | /* ioremap the registers for use */ |
61c7a080 | 1301 | fdev->regs = of_iomap(op->dev.of_node, 0); |
e7a29151 IS |
1302 | if (!fdev->regs) { |
1303 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1304 | err = -ENOMEM; | |
1305 | goto out_free_fdev; | |
173acc7c ZW |
1306 | } |
1307 | ||
d3f620b2 | 1308 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
61c7a080 | 1309 | fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
d3f620b2 | 1310 | |
173acc7c ZW |
1311 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
1312 | dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); | |
c1433041 | 1313 | dma_cap_set(DMA_SG, fdev->common.cap_mask); |
bbea0b6e | 1314 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1315 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1316 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
2187c269 | 1317 | fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; |
173acc7c | 1318 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; |
c1433041 | 1319 | fdev->common.device_prep_dma_sg = fsl_dma_prep_sg; |
07934481 | 1320 | fdev->common.device_tx_status = fsl_tx_status; |
173acc7c | 1321 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; |
bbea0b6e | 1322 | fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; |
c3635c78 | 1323 | fdev->common.device_control = fsl_dma_device_control; |
e7a29151 | 1324 | fdev->common.dev = &op->dev; |
173acc7c | 1325 | |
e2c8e425 LY |
1326 | dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); |
1327 | ||
e7a29151 | 1328 | dev_set_drvdata(&op->dev, fdev); |
77cd62e8 | 1329 | |
e7a29151 IS |
1330 | /* |
1331 | * We cannot use of_platform_bus_probe() because there is no | |
1332 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1333 | * channel object. |
1334 | */ | |
61c7a080 | 1335 | for_each_child_of_node(op->dev.of_node, child) { |
e7a29151 | 1336 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { |
77cd62e8 TT |
1337 | fsl_dma_chan_probe(fdev, child, |
1338 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1339 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1340 | } |
1341 | ||
1342 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1343 | fsl_dma_chan_probe(fdev, child, |
1344 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1345 | "fsl,elo-dma-channel"); | |
e7a29151 | 1346 | } |
77cd62e8 | 1347 | } |
173acc7c | 1348 | |
d3f620b2 IS |
1349 | /* |
1350 | * Hookup the IRQ handler(s) | |
1351 | * | |
1352 | * If we have a per-controller interrupt, we prefer that to the | |
1353 | * per-channel interrupts to reduce the number of shared interrupt | |
1354 | * handlers on the same IRQ line | |
1355 | */ | |
1356 | err = fsldma_request_irqs(fdev); | |
1357 | if (err) { | |
1358 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1359 | goto out_free_fdev; | |
1360 | } | |
1361 | ||
173acc7c ZW |
1362 | dma_async_device_register(&fdev->common); |
1363 | return 0; | |
1364 | ||
e7a29151 | 1365 | out_free_fdev: |
d3f620b2 | 1366 | irq_dispose_mapping(fdev->irq); |
173acc7c | 1367 | kfree(fdev); |
e7a29151 | 1368 | out_return: |
173acc7c ZW |
1369 | return err; |
1370 | } | |
1371 | ||
2dc11581 | 1372 | static int fsldma_of_remove(struct platform_device *op) |
77cd62e8 | 1373 | { |
a4f56d4b | 1374 | struct fsldma_device *fdev; |
77cd62e8 TT |
1375 | unsigned int i; |
1376 | ||
e7a29151 | 1377 | fdev = dev_get_drvdata(&op->dev); |
77cd62e8 TT |
1378 | dma_async_device_unregister(&fdev->common); |
1379 | ||
d3f620b2 IS |
1380 | fsldma_free_irqs(fdev); |
1381 | ||
e7a29151 | 1382 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1383 | if (fdev->chan[i]) |
1384 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1385 | } |
77cd62e8 | 1386 | |
e7a29151 IS |
1387 | iounmap(fdev->regs); |
1388 | dev_set_drvdata(&op->dev, NULL); | |
77cd62e8 | 1389 | kfree(fdev); |
77cd62e8 TT |
1390 | |
1391 | return 0; | |
1392 | } | |
1393 | ||
4b1cf1fa | 1394 | static const struct of_device_id fsldma_of_ids[] = { |
049c9d45 KG |
1395 | { .compatible = "fsl,eloplus-dma", }, |
1396 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1397 | {} |
1398 | }; | |
1399 | ||
a4f56d4b | 1400 | static struct of_platform_driver fsldma_of_driver = { |
4018294b GL |
1401 | .driver = { |
1402 | .name = "fsl-elo-dma", | |
1403 | .owner = THIS_MODULE, | |
1404 | .of_match_table = fsldma_of_ids, | |
1405 | }, | |
1406 | .probe = fsldma_of_probe, | |
1407 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1408 | }; |
1409 | ||
a4f56d4b IS |
1410 | /*----------------------------------------------------------------------------*/ |
1411 | /* Module Init / Exit */ | |
1412 | /*----------------------------------------------------------------------------*/ | |
1413 | ||
1414 | static __init int fsldma_init(void) | |
173acc7c | 1415 | { |
77cd62e8 | 1416 | pr_info("Freescale Elo / Elo Plus DMA driver\n"); |
00006124 | 1417 | return platform_driver_register(&fsldma_of_driver); |
77cd62e8 TT |
1418 | } |
1419 | ||
a4f56d4b | 1420 | static void __exit fsldma_exit(void) |
77cd62e8 | 1421 | { |
00006124 | 1422 | platform_driver_unregister(&fsldma_of_driver); |
173acc7c ZW |
1423 | } |
1424 | ||
a4f56d4b IS |
1425 | subsys_initcall(fsldma_init); |
1426 | module_exit(fsldma_exit); | |
77cd62e8 TT |
1427 | |
1428 | MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); | |
1429 | MODULE_LICENSE("GPL"); |