[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / dw_dmac_regs.h

/*
 * Driver for the Synopsys DesignWare AHB DMA Controller
 *
 * Copyright (C) 2005-2007 Atmel Corporation
 * Copyright (C) 2010-2011 ST Microelectronics
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/dw_dmac.h>

#define DW_DMA_MAX_NR_CHANNELS	8

/* flow controller */
enum dw_dma_fc {
	DW_DMA_FC_D_M2M,
	DW_DMA_FC_D_M2P,
	DW_DMA_FC_D_P2M,
	DW_DMA_FC_D_P2P,
	DW_DMA_FC_P_P2M,
	DW_DMA_FC_SP_P2P,
	DW_DMA_FC_P_M2P,
	DW_DMA_FC_DP_P2P,
};

/*
 * Redefine this macro to handle differences between 32- and 64-bit
 * addressing, big vs. little endian, etc.
 */
#define DW_REG(name)		u32 name; u32 __pad_##name

/* Hardware register definitions. */
struct dw_dma_chan_regs {
	DW_REG(SAR);		/* Source Address Register */
	DW_REG(DAR);		/* Destination Address Register */
	DW_REG(LLP);		/* Linked List Pointer */
	u32	CTL_LO;		/* Control Register Low */
	u32	CTL_HI;		/* Control Register High */
	DW_REG(SSTAT);
	DW_REG(DSTAT);
	DW_REG(SSTATAR);
	DW_REG(DSTATAR);
	u32	CFG_LO;		/* Configuration Register Low */
	u32	CFG_HI;		/* Configuration Register High */
	DW_REG(SGR);
	DW_REG(DSR);
};

struct dw_dma_irq_regs {
	DW_REG(XFER);
	DW_REG(BLOCK);
	DW_REG(SRC_TRAN);
	DW_REG(DST_TRAN);
	DW_REG(ERROR);
};

struct dw_dma_regs {
	/* per-channel registers */
	struct dw_dma_chan_regs	CHAN[DW_DMA_MAX_NR_CHANNELS];

	/* irq handling */
	struct dw_dma_irq_regs	RAW;		/* r */
	struct dw_dma_irq_regs	STATUS;		/* r (raw & mask) */
	struct dw_dma_irq_regs	MASK;		/* rw (set = irq enabled) */
	struct dw_dma_irq_regs	CLEAR;		/* w (ack, affects "raw") */

	DW_REG(STATUS_INT);			/* r */

	/* software handshaking */
	DW_REG(REQ_SRC);
	DW_REG(REQ_DST);
	DW_REG(SGL_REQ_SRC);
	DW_REG(SGL_REQ_DST);
	DW_REG(LAST_SRC);
	DW_REG(LAST_DST);

	/* miscellaneous */
	DW_REG(CFG);
	DW_REG(CH_EN);
	DW_REG(ID);
	DW_REG(TEST);

	/* reserved */
	DW_REG(__reserved0);
	DW_REG(__reserved1);

	/* optional encoded params, 0x3c8..0x3f7 */
	u32	__reserved;

	/* per-channel configuration registers */
	u32	DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
	u32	MULTI_BLK_TYPE;
	u32	MAX_BLK_SIZE;

	/* top-level parameters */
	u32	DW_PARAMS;
};

/* To access the registers in early stage of probe */
#define dma_read_byaddr(addr, name) \
	readl((addr) + offsetof(struct dw_dma_regs, name))

/* Bitfields in DW_PARAMS */
#define DW_PARAMS_NR_CHAN	8		/* number of channels */
#define DW_PARAMS_NR_MASTER	11		/* number of AHB masters */
#define DW_PARAMS_DATA_WIDTH(n)	(15 + 2 * (n))
#define DW_PARAMS_DATA_WIDTH1	15		/* master 1 data width */
#define DW_PARAMS_DATA_WIDTH2	17		/* master 2 data width */
#define DW_PARAMS_DATA_WIDTH3	19		/* master 3 data width */
#define DW_PARAMS_DATA_WIDTH4	21		/* master 4 data width */
#define DW_PARAMS_EN		28		/* encoded parameters */

/* Bitfields in DWC_PARAMS */
#define DWC_PARAMS_MBLK_EN	11		/* multi block transfer */

/* Bitfields in CTL_LO */
#define DWC_CTLL_INT_EN		(1 << 0)	/* irqs enabled? */
#define DWC_CTLL_DST_WIDTH(n)	((n)<<1)	/* bytes per element */
#define DWC_CTLL_SRC_WIDTH(n)	((n)<<4)
#define DWC_CTLL_DST_INC	(0<<7)		/* DAR update/not */
#define DWC_CTLL_DST_DEC	(1<<7)
#define DWC_CTLL_DST_FIX	(2<<7)
#define DWC_CTLL_SRC_INC	(0<<7)		/* SAR update/not */
#define DWC_CTLL_SRC_DEC	(1<<9)
#define DWC_CTLL_SRC_FIX	(2<<9)
#define DWC_CTLL_DST_MSIZE(n)	((n)<<11)	/* burst, #elements */
#define DWC_CTLL_SRC_MSIZE(n)	((n)<<14)
#define DWC_CTLL_S_GATH_EN	(1 << 17)	/* src gather, !FIX */
#define DWC_CTLL_D_SCAT_EN	(1 << 18)	/* dst scatter, !FIX */
#define DWC_CTLL_FC(n)		((n) << 20)
#define DWC_CTLL_FC_M2M		(0 << 20)	/* mem-to-mem */
#define DWC_CTLL_FC_M2P		(1 << 20)	/* mem-to-periph */
#define DWC_CTLL_FC_P2M		(2 << 20)	/* periph-to-mem */
#define DWC_CTLL_FC_P2P		(3 << 20)	/* periph-to-periph */
/* plus 4 transfer types for peripheral-as-flow-controller */
#define DWC_CTLL_DMS(n)		((n)<<23)	/* dst master select */
#define DWC_CTLL_SMS(n)		((n)<<25)	/* src master select */
#define DWC_CTLL_LLP_D_EN	(1 << 27)	/* dest block chain */
#define DWC_CTLL_LLP_S_EN	(1 << 28)	/* src block chain */

/* Bitfields in CTL_HI */
#define DWC_CTLH_DONE		0x00001000
#define DWC_CTLH_BLOCK_TS_MASK	0x00000fff

/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
#define DWC_CFGL_CH_PRIOR_MASK	(0x7 << 5)	/* priority mask */
#define DWC_CFGL_CH_PRIOR(x)	((x) << 5)	/* priority */
#define DWC_CFGL_CH_SUSP	(1 << 8)	/* pause xfer */
#define DWC_CFGL_FIFO_EMPTY	(1 << 9)	/* pause xfer */
#define DWC_CFGL_HS_DST		(1 << 10)	/* handshake w/dst */
#define DWC_CFGL_HS_SRC		(1 << 11)	/* handshake w/src */
#define DWC_CFGL_MAX_BURST(x)	((x) << 20)
#define DWC_CFGL_RELOAD_SAR	(1 << 30)
#define DWC_CFGL_RELOAD_DAR	(1 << 31)

/* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
#define DWC_CFGH_DS_UPD_EN	(1 << 5)
#define DWC_CFGH_SS_UPD_EN	(1 << 6)

/* Bitfields in SGR */
#define DWC_SGR_SGI(x)		((x) << 0)
#define DWC_SGR_SGC(x)		((x) << 20)

/* Bitfields in DSR */
#define DWC_DSR_DSI(x)		((x) << 0)
#define DWC_DSR_DSC(x)		((x) << 20)

/* Bitfields in CFG */
#define DW_CFG_DMA_EN		(1 << 0)

enum dw_dmac_flags {
	DW_DMA_IS_CYCLIC = 0,
	DW_DMA_IS_SOFT_LLP = 1,
};

struct dw_dma_chan {
	struct dma_chan		chan;
	void __iomem		*ch_regs;
	u8			mask;
	u8			priority;
	bool			paused;
	bool			initialized;

	/* software emulation of the LLP transfers */
	struct list_head	*tx_list;
	struct list_head	*tx_node_active;

	spinlock_t		lock;

	/* these other elements are all protected by lock */
	unsigned long		flags;
	struct list_head	active_list;
	struct list_head	queue;
	struct list_head	free_list;
	struct dw_cyclic_desc	*cdesc;

	unsigned int		descs_allocated;

	/* hardware configuration */
	unsigned int		block_size;
	bool			nollp;

	/* configuration passed via DMA_SLAVE_CONFIG */
	struct dma_slave_config dma_sconfig;

	/* backlink to dw_dma */
	struct dw_dma		*dw;
};

static inline struct dw_dma_chan_regs __iomem *
__dwc_regs(struct dw_dma_chan *dwc)
{
	return dwc->ch_regs;
}

#define channel_readl(dwc, name) \
	readl(&(__dwc_regs(dwc)->name))
#define channel_writel(dwc, name, val) \
	writel((val), &(__dwc_regs(dwc)->name))

static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct dw_dma_chan, chan);
}

struct dw_dma {
	struct dma_device	dma;
	void __iomem		*regs;
	struct tasklet_struct	tasklet;
	struct clk		*clk;

	u8			all_chan_mask;

	/* hardware configuration */
	unsigned char		nr_masters;
	unsigned char		data_width[4];

	struct dw_dma_chan	chan[0];
};

static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
{
	return dw->regs;
}

#define dma_readl(dw, name) \
	readl(&(__dw_regs(dw)->name))
#define dma_writel(dw, name, val) \
	writel((val), &(__dw_regs(dw)->name))

#define channel_set_bit(dw, reg, mask) \
	dma_writel(dw, reg, ((mask) << 8) | (mask))
#define channel_clear_bit(dw, reg, mask) \
	dma_writel(dw, reg, ((mask) << 8) | 0)

static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
{
	return container_of(ddev, struct dw_dma, dma);
}

/* LLI == Linked List Item; a.k.a. DMA block descriptor */
struct dw_lli {
	/* values that are not changed by hardware */
	u32		sar;
	u32		dar;
	u32		llp;		/* chain to next lli */
	u32		ctllo;
	/* values that may get written back: */
	u32		ctlhi;
	/* sstat and dstat can snapshot peripheral register state.
	 * silicon config may discard either or both...
	 */
	u32		sstat;
	u32		dstat;
};

struct dw_desc {
	/* FIRST values the hardware uses */
	struct dw_lli			lli;

	/* THEN values for driver housekeeping */
	struct list_head		desc_node;
	struct list_head		tx_list;
	struct dma_async_tx_descriptor	txd;
	size_t				len;
};

static inline struct dw_desc *
txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
{
	return container_of(txd, struct dw_desc, txd);
}
Commit	Line	Data
3bfb1d20 HS	1	/*
	2	* Driver for the Synopsys DesignWare AHB DMA Controller
	3	*
	4	* Copyright (C) 2005-2007 Atmel Corporation
aecb7b64	5	* Copyright (C) 2010-2011 ST Microelectronics
3bfb1d20 HS	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/dw_dmac.h>
	13
	14	#define DW_DMA_MAX_NR_CHANNELS 8
	15
a1c46016 VK	16	/* flow controller */
	17	enum dw_dma_fc {
	18	DW_DMA_FC_D_M2M,
	19	DW_DMA_FC_D_M2P,
	20	DW_DMA_FC_D_P2M,
	21	DW_DMA_FC_D_P2P,
	22	DW_DMA_FC_P_P2M,
	23	DW_DMA_FC_SP_P2P,
	24	DW_DMA_FC_P_M2P,
	25	DW_DMA_FC_DP_P2P,
	26	};
	27
3bfb1d20 HS	28	/*
	29	* Redefine this macro to handle differences between 32- and 64-bit
	30	* addressing, big vs. little endian, etc.
	31	*/
	32	#define DW_REG(name) u32 name; u32 __pad_##name
	33
	34	/* Hardware register definitions. */
	35	struct dw_dma_chan_regs {
	36	DW_REG(SAR); /* Source Address Register */
	37	DW_REG(DAR); /* Destination Address Register */
	38	DW_REG(LLP); /* Linked List Pointer */
	39	u32 CTL_LO; /* Control Register Low */
	40	u32 CTL_HI; /* Control Register High */
	41	DW_REG(SSTAT);
	42	DW_REG(DSTAT);
	43	DW_REG(SSTATAR);
	44	DW_REG(DSTATAR);
	45	u32 CFG_LO; /* Configuration Register Low */
	46	u32 CFG_HI; /* Configuration Register High */
	47	DW_REG(SGR);
	48	DW_REG(DSR);
	49	};
	50
	51	struct dw_dma_irq_regs {
	52	DW_REG(XFER);
	53	DW_REG(BLOCK);
	54	DW_REG(SRC_TRAN);
	55	DW_REG(DST_TRAN);
	56	DW_REG(ERROR);
	57	};
	58
	59	struct dw_dma_regs {
	60	/* per-channel registers */
	61	struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
	62
	63	/* irq handling */
	64	struct dw_dma_irq_regs RAW; /* r */
	65	struct dw_dma_irq_regs STATUS; /* r (raw & mask) */
	66	struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */
	67	struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
	68
	69	DW_REG(STATUS_INT); /* r */
	70
	71	/* software handshaking */
	72	DW_REG(REQ_SRC);
	73	DW_REG(REQ_DST);
	74	DW_REG(SGL_REQ_SRC);
	75	DW_REG(SGL_REQ_DST);
	76	DW_REG(LAST_SRC);
	77	DW_REG(LAST_DST);
	78
	79	/* miscellaneous */
	80	DW_REG(CFG);
	81	DW_REG(CH_EN);
	82	DW_REG(ID);
	83	DW_REG(TEST);
	84
2a9fe9ae AS	85	/* reserved */
	86	DW_REG(__reserved0);
	87	DW_REG(__reserved1);
	88
745664eb	89	/* optional encoded params, 0x3c8..0x3f7 */
2a9fe9ae AS	90	u32 __reserved;
	91
	92	/* per-channel configuration registers */
	93	u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
	94	u32 MULTI_BLK_TYPE;
	95	u32 MAX_BLK_SIZE;
	96
	97	/* top-level parameters */
	98	u32 DW_PARAMS;
3bfb1d20 HS	99	};
3bfb1d20 HS	100
2a9fe9ae AS	101	/* To access the registers in early stage of probe */
	102	#define dma_read_byaddr(addr, name) \
	103	readl((addr) + offsetof(struct dw_dma_regs, name))
	104
	105	/* Bitfields in DW_PARAMS */
	106	#define DW_PARAMS_NR_CHAN 8 /* number of channels */
	107	#define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */
	108	#define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
	109	#define DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */
	110	#define DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */
	111	#define DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */
	112	#define DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */
	113	#define DW_PARAMS_EN 28 /* encoded parameters */
	114
	115	/* Bitfields in DWC_PARAMS */
	116	#define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */
	117
3bfb1d20 HS	118	/* Bitfields in CTL_LO */
	119	#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
	120	#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
	121	#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
	122	#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
	123	#define DWC_CTLL_DST_DEC (1<<7)
	124	#define DWC_CTLL_DST_FIX (2<<7)
	125	#define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */
	126	#define DWC_CTLL_SRC_DEC (1<<9)
	127	#define DWC_CTLL_SRC_FIX (2<<9)
	128	#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
	129	#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
	130	#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
	131	#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
ee66509d	132	#define DWC_CTLL_FC(n) ((n) << 20)
3bfb1d20 HS	133	#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
	134	#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
	135	#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
	136	#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */
	137	/* plus 4 transfer types for peripheral-as-flow-controller */
	138	#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */
	139	#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */
	140	#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
	141	#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
	142
	143	/* Bitfields in CTL_HI */
	144	#define DWC_CTLH_DONE 0x00001000
	145	#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
	146
	147	/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
93317e8e VK	148	#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
93317e8e VK	149	#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
3bfb1d20 HS	150	#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
	151	#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
	152	#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
	153	#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */
	154	#define DWC_CFGL_MAX_BURST(x) ((x) << 20)
	155	#define DWC_CFGL_RELOAD_SAR (1 << 30)
	156	#define DWC_CFGL_RELOAD_DAR (1 << 31)
	157
	158	/* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
	159	#define DWC_CFGH_DS_UPD_EN (1 << 5)
	160	#define DWC_CFGH_SS_UPD_EN (1 << 6)
	161
	162	/* Bitfields in SGR */
	163	#define DWC_SGR_SGI(x) ((x) << 0)
	164	#define DWC_SGR_SGC(x) ((x) << 20)
	165
	166	/* Bitfields in DSR */
	167	#define DWC_DSR_DSI(x) ((x) << 0)
	168	#define DWC_DSR_DSC(x) ((x) << 20)
	169
	170	/* Bitfields in CFG */
	171	#define DW_CFG_DMA_EN (1 << 0)
	172
d9de4519 HCE	173	enum dw_dmac_flags {
d9de4519 HCE	174	DW_DMA_IS_CYCLIC = 0,
fed2574b	175	DW_DMA_IS_SOFT_LLP = 1,
d9de4519 HCE	176	};
d9de4519 HCE	177
3bfb1d20 HS	178	struct dw_dma_chan {
	179	struct dma_chan chan;
	180	void __iomem *ch_regs;
	181	u8 mask;
93317e8e	182	u8 priority;
a7c57cf7	183	bool paused;
61e183f8	184	bool initialized;
3bfb1d20	185
fed2574b AS	186	/* software emulation of the LLP transfers */
	187	struct list_head *tx_list;
	188	struct list_head *tx_node_active;
	189
3bfb1d20 HS	190	spinlock_t lock;
	191
	192	/* these other elements are all protected by lock */
d9de4519	193	unsigned long flags;
3bfb1d20 HS	194	struct list_head active_list;
	195	struct list_head queue;
	196	struct list_head free_list;
d9de4519	197	struct dw_cyclic_desc *cdesc;
3bfb1d20	198
3bfb1d20	199	unsigned int descs_allocated;
327e6970	200
4a63a8b3 AS	201	/* hardware configuration */
4a63a8b3 AS	202	unsigned int block_size;
fed2574b	203	bool nollp;
4a63a8b3	204
327e6970 VK	205	/* configuration passed via DMA_SLAVE_CONFIG */
327e6970 VK	206	struct dma_slave_config dma_sconfig;
a0982004 AS	207
	208	/* backlink to dw_dma */
	209	struct dw_dma *dw;
3bfb1d20 HS	210	};
	211
	212	static inline struct dw_dma_chan_regs __iomem *
	213	__dwc_regs(struct dw_dma_chan *dwc)
	214	{
	215	return dwc->ch_regs;
	216	}
	217
	218	#define channel_readl(dwc, name) \
29782da5	219	readl(&(__dwc_regs(dwc)->name))
3bfb1d20	220	#define channel_writel(dwc, name, val) \
29782da5	221	writel((val), &(__dwc_regs(dwc)->name))
3bfb1d20 HS	222
	223	static inline struct dw_dma_chan to_dw_dma_chan(struct dma_chan chan)
	224	{
	225	return container_of(chan, struct dw_dma_chan, chan);
	226	}
	227
3bfb1d20 HS	228	struct dw_dma {
	229	struct dma_device dma;
	230	void __iomem *regs;
	231	struct tasklet_struct tasklet;
	232	struct clk *clk;
	233
	234	u8 all_chan_mask;
	235
a0982004 AS	236	/* hardware configuration */
	237	unsigned char nr_masters;
	238	unsigned char data_width[4];
	239
3bfb1d20 HS	240	struct dw_dma_chan chan[0];
	241	};
	242
	243	static inline struct dw_dma_regs __iomem __dw_regs(struct dw_dma dw)
	244	{
	245	return dw->regs;
	246	}
	247
	248	#define dma_readl(dw, name) \
29782da5	249	readl(&(__dw_regs(dw)->name))
3bfb1d20	250	#define dma_writel(dw, name, val) \
29782da5	251	writel((val), &(__dw_regs(dw)->name))
3bfb1d20 HS	252
	253	#define channel_set_bit(dw, reg, mask) \
	254	dma_writel(dw, reg, ((mask) << 8) \| (mask))
	255	#define channel_clear_bit(dw, reg, mask) \
	256	dma_writel(dw, reg, ((mask) << 8) \| 0)
	257
	258	static inline struct dw_dma to_dw_dma(struct dma_device ddev)
	259	{
	260	return container_of(ddev, struct dw_dma, dma);
	261	}
	262
	263	/* LLI == Linked List Item; a.k.a. DMA block descriptor */
	264	struct dw_lli {
	265	/* values that are not changed by hardware */
f8609c2b AS	266	u32 sar;
	267	u32 dar;
	268	u32 llp; /* chain to next lli */
3bfb1d20 HS	269	u32 ctllo;
	270	/* values that may get written back: */
	271	u32 ctlhi;
	272	/* sstat and dstat can snapshot peripheral register state.
	273	* silicon config may discard either or both...
	274	*/
	275	u32 sstat;
	276	u32 dstat;
	277	};
	278
	279	struct dw_desc {
	280	/* FIRST values the hardware uses */
	281	struct dw_lli lli;
	282
	283	/* THEN values for driver housekeeping */
	284	struct list_head desc_node;
e0bd0f8c	285	struct list_head tx_list;
3bfb1d20 HS	286	struct dma_async_tx_descriptor txd;
	287	size_t len;
	288	};
	289
	290	static inline struct dw_desc *
	291	txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
	292	{
	293	return container_of(txd, struct dw_desc, txd);
	294	}