[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / dma / dw_dmac_regs.h

/*
 * Driver for the Synopsys DesignWare AHB DMA Controller
 *
 * Copyright (C) 2005-2007 Atmel Corporation
 * Copyright (C) 2010-2011 ST Microelectronics
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/dw_dmac.h>

#define DW_DMA_MAX_NR_CHANNELS	8

/* flow controller */
enum dw_dma_fc {
	DW_DMA_FC_D_M2M,
	DW_DMA_FC_D_M2P,
	DW_DMA_FC_D_P2M,
	DW_DMA_FC_D_P2P,
	DW_DMA_FC_P_P2M,
	DW_DMA_FC_SP_P2P,
	DW_DMA_FC_P_M2P,
	DW_DMA_FC_DP_P2P,
};

/*
 * Redefine this macro to handle differences between 32- and 64-bit
 * addressing, big vs. little endian, etc.
 */
#define DW_REG(name)		u32 name; u32 __pad_##name

/* Hardware register definitions. */
struct dw_dma_chan_regs {
	DW_REG(SAR);		/* Source Address Register */
	DW_REG(DAR);		/* Destination Address Register */
	DW_REG(LLP);		/* Linked List Pointer */
	u32	CTL_LO;		/* Control Register Low */
	u32	CTL_HI;		/* Control Register High */
	DW_REG(SSTAT);
	DW_REG(DSTAT);
	DW_REG(SSTATAR);
	DW_REG(DSTATAR);
	u32	CFG_LO;		/* Configuration Register Low */
	u32	CFG_HI;		/* Configuration Register High */
	DW_REG(SGR);
	DW_REG(DSR);
};

struct dw_dma_irq_regs {
	DW_REG(XFER);
	DW_REG(BLOCK);
	DW_REG(SRC_TRAN);
	DW_REG(DST_TRAN);
	DW_REG(ERROR);
};

struct dw_dma_regs {
	/* per-channel registers */
	struct dw_dma_chan_regs	CHAN[DW_DMA_MAX_NR_CHANNELS];

	/* irq handling */
	struct dw_dma_irq_regs	RAW;		/* r */
	struct dw_dma_irq_regs	STATUS;		/* r (raw & mask) */
	struct dw_dma_irq_regs	MASK;		/* rw (set = irq enabled) */
	struct dw_dma_irq_regs	CLEAR;		/* w (ack, affects "raw") */

	DW_REG(STATUS_INT);			/* r */

	/* software handshaking */
	DW_REG(REQ_SRC);
	DW_REG(REQ_DST);
	DW_REG(SGL_REQ_SRC);
	DW_REG(SGL_REQ_DST);
	DW_REG(LAST_SRC);
	DW_REG(LAST_DST);

	/* miscellaneous */
	DW_REG(CFG);
	DW_REG(CH_EN);
	DW_REG(ID);
	DW_REG(TEST);

	/* optional encoded params, 0x3c8..0x3 */
};

/* Bitfields in CTL_LO */
#define DWC_CTLL_INT_EN		(1 << 0)	/* irqs enabled? */
#define DWC_CTLL_DST_WIDTH(n)	((n)<<1)	/* bytes per element */
#define DWC_CTLL_SRC_WIDTH(n)	((n)<<4)
#define DWC_CTLL_DST_INC	(0<<7)		/* DAR update/not */
#define DWC_CTLL_DST_DEC	(1<<7)
#define DWC_CTLL_DST_FIX	(2<<7)
#define DWC_CTLL_SRC_INC	(0<<7)		/* SAR update/not */
#define DWC_CTLL_SRC_DEC	(1<<9)
#define DWC_CTLL_SRC_FIX	(2<<9)
#define DWC_CTLL_DST_MSIZE(n)	((n)<<11)	/* burst, #elements */
#define DWC_CTLL_SRC_MSIZE(n)	((n)<<14)
#define DWC_CTLL_S_GATH_EN	(1 << 17)	/* src gather, !FIX */
#define DWC_CTLL_D_SCAT_EN	(1 << 18)	/* dst scatter, !FIX */
#define DWC_CTLL_FC(n)		((n) << 20)
#define DWC_CTLL_FC_M2M		(0 << 20)	/* mem-to-mem */
#define DWC_CTLL_FC_M2P		(1 << 20)	/* mem-to-periph */
#define DWC_CTLL_FC_P2M		(2 << 20)	/* periph-to-mem */
#define DWC_CTLL_FC_P2P		(3 << 20)	/* periph-to-periph */
/* plus 4 transfer types for peripheral-as-flow-controller */
#define DWC_CTLL_DMS(n)		((n)<<23)	/* dst master select */
#define DWC_CTLL_SMS(n)		((n)<<25)	/* src master select */
#define DWC_CTLL_LLP_D_EN	(1 << 27)	/* dest block chain */
#define DWC_CTLL_LLP_S_EN	(1 << 28)	/* src block chain */

/* Bitfields in CTL_HI */
#define DWC_CTLH_DONE		0x00001000
#define DWC_CTLH_BLOCK_TS_MASK	0x00000fff

/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
#define DWC_CFGL_CH_PRIOR_MASK	(0x7 << 5)	/* priority mask */
#define DWC_CFGL_CH_PRIOR(x)	((x) << 5)	/* priority */
#define DWC_CFGL_CH_SUSP	(1 << 8)	/* pause xfer */
#define DWC_CFGL_FIFO_EMPTY	(1 << 9)	/* pause xfer */
#define DWC_CFGL_HS_DST		(1 << 10)	/* handshake w/dst */
#define DWC_CFGL_HS_SRC		(1 << 11)	/* handshake w/src */
#define DWC_CFGL_MAX_BURST(x)	((x) << 20)
#define DWC_CFGL_RELOAD_SAR	(1 << 30)
#define DWC_CFGL_RELOAD_DAR	(1 << 31)

/* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
#define DWC_CFGH_DS_UPD_EN	(1 << 5)
#define DWC_CFGH_SS_UPD_EN	(1 << 6)

/* Bitfields in SGR */
#define DWC_SGR_SGI(x)		((x) << 0)
#define DWC_SGR_SGC(x)		((x) << 20)

/* Bitfields in DSR */
#define DWC_DSR_DSI(x)		((x) << 0)
#define DWC_DSR_DSC(x)		((x) << 20)

/* Bitfields in CFG */
#define DW_CFG_DMA_EN		(1 << 0)

#define DW_REGLEN		0x400

enum dw_dmac_flags {
	DW_DMA_IS_CYCLIC = 0,
};

struct dw_dma_chan {
	struct dma_chan		chan;
	void __iomem		*ch_regs;
	u8			mask;
	u8			priority;
	bool			paused;
	bool			initialized;

	spinlock_t		lock;

	/* these other elements are all protected by lock */
	unsigned long		flags;
	struct list_head	active_list;
	struct list_head	queue;
	struct list_head	free_list;
	struct dw_cyclic_desc	*cdesc;

	unsigned int		descs_allocated;

	/* configuration passed via DMA_SLAVE_CONFIG */
	struct dma_slave_config dma_sconfig;
};

static inline struct dw_dma_chan_regs __iomem *
__dwc_regs(struct dw_dma_chan *dwc)
{
	return dwc->ch_regs;
}

#define channel_readl(dwc, name) \
	readl(&(__dwc_regs(dwc)->name))
#define channel_writel(dwc, name, val) \
	writel((val), &(__dwc_regs(dwc)->name))

static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct dw_dma_chan, chan);
}

struct dw_dma {
	struct dma_device	dma;
	void __iomem		*regs;
	struct tasklet_struct	tasklet;
	struct clk		*clk;

	u8			all_chan_mask;

	struct dw_dma_chan	chan[0];
};

static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
{
	return dw->regs;
}

#define dma_readl(dw, name) \
	readl(&(__dw_regs(dw)->name))
#define dma_writel(dw, name, val) \
	writel((val), &(__dw_regs(dw)->name))

#define channel_set_bit(dw, reg, mask) \
	dma_writel(dw, reg, ((mask) << 8) | (mask))
#define channel_clear_bit(dw, reg, mask) \
	dma_writel(dw, reg, ((mask) << 8) | 0)

static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
{
	return container_of(ddev, struct dw_dma, dma);
}

/* LLI == Linked List Item; a.k.a. DMA block descriptor */
struct dw_lli {
	/* values that are not changed by hardware */
	dma_addr_t	sar;
	dma_addr_t	dar;
	dma_addr_t	llp;		/* chain to next lli */
	u32		ctllo;
	/* values that may get written back: */
	u32		ctlhi;
	/* sstat and dstat can snapshot peripheral register state.
	 * silicon config may discard either or both...
	 */
	u32		sstat;
	u32		dstat;
};

struct dw_desc {
	/* FIRST values the hardware uses */
	struct dw_lli			lli;

	/* THEN values for driver housekeeping */
	struct list_head		desc_node;
	struct list_head		tx_list;
	struct dma_async_tx_descriptor	txd;
	size_t				len;
};

static inline struct dw_desc *
txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
{
	return container_of(txd, struct dw_desc, txd);
}
Commit	Line	Data
3bfb1d20 HS	1	/*
	2	* Driver for the Synopsys DesignWare AHB DMA Controller
	3	*
	4	* Copyright (C) 2005-2007 Atmel Corporation
aecb7b64	5	* Copyright (C) 2010-2011 ST Microelectronics
3bfb1d20 HS	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/dw_dmac.h>
	13
	14	#define DW_DMA_MAX_NR_CHANNELS 8
	15
a1c46016 VK	16	/* flow controller */
	17	enum dw_dma_fc {
	18	DW_DMA_FC_D_M2M,
	19	DW_DMA_FC_D_M2P,
	20	DW_DMA_FC_D_P2M,
	21	DW_DMA_FC_D_P2P,
	22	DW_DMA_FC_P_P2M,
	23	DW_DMA_FC_SP_P2P,
	24	DW_DMA_FC_P_M2P,
	25	DW_DMA_FC_DP_P2P,
	26	};
	27
3bfb1d20 HS	28	/*
	29	* Redefine this macro to handle differences between 32- and 64-bit
	30	* addressing, big vs. little endian, etc.
	31	*/
	32	#define DW_REG(name) u32 name; u32 __pad_##name
	33
	34	/* Hardware register definitions. */
	35	struct dw_dma_chan_regs {
	36	DW_REG(SAR); /* Source Address Register */
	37	DW_REG(DAR); /* Destination Address Register */
	38	DW_REG(LLP); /* Linked List Pointer */
	39	u32 CTL_LO; /* Control Register Low */
	40	u32 CTL_HI; /* Control Register High */
	41	DW_REG(SSTAT);
	42	DW_REG(DSTAT);
	43	DW_REG(SSTATAR);
	44	DW_REG(DSTATAR);
	45	u32 CFG_LO; /* Configuration Register Low */
	46	u32 CFG_HI; /* Configuration Register High */
	47	DW_REG(SGR);
	48	DW_REG(DSR);
	49	};
	50
	51	struct dw_dma_irq_regs {
	52	DW_REG(XFER);
	53	DW_REG(BLOCK);
	54	DW_REG(SRC_TRAN);
	55	DW_REG(DST_TRAN);
	56	DW_REG(ERROR);
	57	};
	58
	59	struct dw_dma_regs {
	60	/* per-channel registers */
	61	struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
	62
	63	/* irq handling */
	64	struct dw_dma_irq_regs RAW; /* r */
	65	struct dw_dma_irq_regs STATUS; /* r (raw & mask) */
	66	struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */
	67	struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
	68
	69	DW_REG(STATUS_INT); /* r */
	70
	71	/* software handshaking */
	72	DW_REG(REQ_SRC);
	73	DW_REG(REQ_DST);
	74	DW_REG(SGL_REQ_SRC);
	75	DW_REG(SGL_REQ_DST);
	76	DW_REG(LAST_SRC);
	77	DW_REG(LAST_DST);
	78
	79	/* miscellaneous */
	80	DW_REG(CFG);
	81	DW_REG(CH_EN);
	82	DW_REG(ID);
	83	DW_REG(TEST);
	84
	85	/* optional encoded params, 0x3c8..0x3 */
	86	};
	87
	88	/* Bitfields in CTL_LO */
	89	#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
	90	#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
	91	#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
92	#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
93	#define DWC_CTLL_DST_DEC (1<<7)
94	#define DWC_CTLL_DST_FIX (2<<7)
95	#define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */
96	#define DWC_CTLL_SRC_DEC (1<<9)
97	#define DWC_CTLL_SRC_FIX (2<<9)
98	#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
99	#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
100	#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
101	#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
ee66509d	102	#define DWC_CTLL_FC(n) ((n) << 20)
3bfb1d20 HS	103	#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
	104	#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
	105	#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
	106	#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */
	107	/* plus 4 transfer types for peripheral-as-flow-controller */
	108	#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */
	109	#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */
	110	#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
	111	#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
	112
	113	/* Bitfields in CTL_HI */
	114	#define DWC_CTLH_DONE 0x00001000
	115	#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
	116
	117	/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
93317e8e VK	118	#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
93317e8e VK	119	#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
3bfb1d20 HS	120	#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
	121	#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
	122	#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
	123	#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */
	124	#define DWC_CFGL_MAX_BURST(x) ((x) << 20)
	125	#define DWC_CFGL_RELOAD_SAR (1 << 30)
	126	#define DWC_CFGL_RELOAD_DAR (1 << 31)
	127
	128	/* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
	129	#define DWC_CFGH_DS_UPD_EN (1 << 5)
	130	#define DWC_CFGH_SS_UPD_EN (1 << 6)
	131
	132	/* Bitfields in SGR */
	133	#define DWC_SGR_SGI(x) ((x) << 0)
	134	#define DWC_SGR_SGC(x) ((x) << 20)
	135
	136	/* Bitfields in DSR */
	137	#define DWC_DSR_DSI(x) ((x) << 0)
	138	#define DWC_DSR_DSC(x) ((x) << 20)
	139
	140	/* Bitfields in CFG */
	141	#define DW_CFG_DMA_EN (1 << 0)
	142
	143	#define DW_REGLEN 0x400
	144
d9de4519 HCE	145	enum dw_dmac_flags {
	146	DW_DMA_IS_CYCLIC = 0,
	147	};
	148
3bfb1d20 HS	149	struct dw_dma_chan {
	150	struct dma_chan chan;
	151	void __iomem *ch_regs;
	152	u8 mask;
93317e8e	153	u8 priority;
a7c57cf7	154	bool paused;
61e183f8	155	bool initialized;
3bfb1d20 HS	156
	157	spinlock_t lock;
	158
	159	/* these other elements are all protected by lock */
d9de4519	160	unsigned long flags;
3bfb1d20 HS	161	struct list_head active_list;
	162	struct list_head queue;
	163	struct list_head free_list;
d9de4519	164	struct dw_cyclic_desc *cdesc;
3bfb1d20	165
3bfb1d20	166	unsigned int descs_allocated;
327e6970 VK	167
	168	/* configuration passed via DMA_SLAVE_CONFIG */
	169	struct dma_slave_config dma_sconfig;
3bfb1d20 HS	170	};
	171
	172	static inline struct dw_dma_chan_regs __iomem *
	173	__dwc_regs(struct dw_dma_chan *dwc)
	174	{
	175	return dwc->ch_regs;
	176	}
	177
	178	#define channel_readl(dwc, name) \
29782da5	179	readl(&(__dwc_regs(dwc)->name))
3bfb1d20	180	#define channel_writel(dwc, name, val) \
29782da5	181	writel((val), &(__dwc_regs(dwc)->name))
3bfb1d20 HS	182
	183	static inline struct dw_dma_chan to_dw_dma_chan(struct dma_chan chan)
	184	{
	185	return container_of(chan, struct dw_dma_chan, chan);
	186	}
	187
3bfb1d20 HS	188	struct dw_dma {
	189	struct dma_device dma;
	190	void __iomem *regs;
	191	struct tasklet_struct tasklet;
	192	struct clk *clk;
	193
	194	u8 all_chan_mask;
	195
	196	struct dw_dma_chan chan[0];
	197	};
	198
	199	static inline struct dw_dma_regs __iomem __dw_regs(struct dw_dma dw)
	200	{
	201	return dw->regs;
	202	}
	203
	204	#define dma_readl(dw, name) \
29782da5	205	readl(&(__dw_regs(dw)->name))
3bfb1d20	206	#define dma_writel(dw, name, val) \
29782da5	207	writel((val), &(__dw_regs(dw)->name))
3bfb1d20 HS	208
	209	#define channel_set_bit(dw, reg, mask) \
	210	dma_writel(dw, reg, ((mask) << 8) \| (mask))
	211	#define channel_clear_bit(dw, reg, mask) \
	212	dma_writel(dw, reg, ((mask) << 8) \| 0)
	213
	214	static inline struct dw_dma to_dw_dma(struct dma_device ddev)
	215	{
	216	return container_of(ddev, struct dw_dma, dma);
	217	}
	218
	219	/* LLI == Linked List Item; a.k.a. DMA block descriptor */
	220	struct dw_lli {
	221	/* values that are not changed by hardware */
	222	dma_addr_t sar;
	223	dma_addr_t dar;
	224	dma_addr_t llp; /* chain to next lli */
	225	u32 ctllo;
	226	/* values that may get written back: */
	227	u32 ctlhi;
	228	/* sstat and dstat can snapshot peripheral register state.
	229	* silicon config may discard either or both...
	230	*/
	231	u32 sstat;
	232	u32 dstat;
	233	};
	234
	235	struct dw_desc {
	236	/* FIRST values the hardware uses */
	237	struct dw_lli lli;
	238
	239	/* THEN values for driver housekeeping */
	240	struct list_head desc_node;
e0bd0f8c	241	struct list_head tx_list;
3bfb1d20 HS	242	struct dma_async_tx_descriptor txd;
	243	size_t len;
	244	};
	245
	246	static inline struct dw_desc *
	247	txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
	248	{
	249	return container_of(txd, struct dw_desc, txd);
	250	}