[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / crypto / talitos.h

/*
 * Freescale SEC (talitos) device register and descriptor header defines
 *
 * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/*
 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
 */

/* global register offset addresses */
#define TALITOS_MCR			0x1030  /* master control register */
#define TALITOS_MCR_LO			0x1038
#define   TALITOS_MCR_SWR		0x1     /* s/w reset */
#define TALITOS_IMR			0x1008  /* interrupt mask register */
#define   TALITOS_IMR_INIT		0x100ff /* enable channel IRQs */
#define   TALITOS_IMR_DONE		0x00055 /* done IRQs */
#define TALITOS_IMR_LO			0x100C
#define   TALITOS_IMR_LO_INIT		0x20000 /* allow RNGU error IRQs */
#define TALITOS_ISR			0x1010  /* interrupt status register */
#define   TALITOS_ISR_CHERR		0xaa    /* channel errors mask */
#define   TALITOS_ISR_CHDONE		0x55    /* channel done mask */
#define TALITOS_ISR_LO			0x1014
#define TALITOS_ICR			0x1018  /* interrupt clear register */
#define TALITOS_ICR_LO			0x101C

/* channel register address stride */
#define TALITOS_CH_BASE_OFFSET		0x1000	/* default channel map base */
#define TALITOS_CH_STRIDE		0x100

/* channel configuration register  */
#define TALITOS_CCCR			0x8
#define   TALITOS_CCCR_CONT		0x2    /* channel continue */
#define   TALITOS_CCCR_RESET		0x1    /* channel reset */
#define TALITOS_CCCR_LO			0xc
#define   TALITOS_CCCR_LO_IWSE		0x80   /* chan. ICCR writeback enab. */
#define   TALITOS_CCCR_LO_EAE		0x20   /* extended address enable */
#define   TALITOS_CCCR_LO_CDWE		0x10   /* chan. done writeback enab. */
#define   TALITOS_CCCR_LO_NT		0x4    /* notification type */
#define   TALITOS_CCCR_LO_CDIE		0x2    /* channel done IRQ enable */

/* CCPSR: channel pointer status register */
#define TALITOS_CCPSR			0x10
#define TALITOS_CCPSR_LO		0x14
#define   TALITOS_CCPSR_LO_DOF		0x8000 /* double FF write oflow error */
#define   TALITOS_CCPSR_LO_SOF		0x4000 /* single FF write oflow error */
#define   TALITOS_CCPSR_LO_MDTE		0x2000 /* master data transfer error */
#define   TALITOS_CCPSR_LO_SGDLZ	0x1000 /* s/g data len zero error */
#define   TALITOS_CCPSR_LO_FPZ		0x0800 /* fetch ptr zero error */
#define   TALITOS_CCPSR_LO_IDH		0x0400 /* illegal desc hdr error */
#define   TALITOS_CCPSR_LO_IEU		0x0200 /* invalid EU error */
#define   TALITOS_CCPSR_LO_EU		0x0100 /* EU error detected */
#define   TALITOS_CCPSR_LO_GB		0x0080 /* gather boundary error */
#define   TALITOS_CCPSR_LO_GRL		0x0040 /* gather return/length error */
#define   TALITOS_CCPSR_LO_SB		0x0020 /* scatter boundary error */
#define   TALITOS_CCPSR_LO_SRL		0x0010 /* scatter return/length error */

/* channel fetch fifo register */
#define TALITOS_FF			0x48
#define TALITOS_FF_LO			0x4c

/* current descriptor pointer register */
#define TALITOS_CDPR			0x40
#define TALITOS_CDPR_LO			0x44

/* descriptor buffer register */
#define TALITOS_DESCBUF			0x80
#define TALITOS_DESCBUF_LO		0x84

/* gather link table */
#define TALITOS_GATHER			0xc0
#define TALITOS_GATHER_LO		0xc4

/* scatter link table */
#define TALITOS_SCATTER			0xe0
#define TALITOS_SCATTER_LO		0xe4

/* execution unit interrupt status registers */
#define TALITOS_DEUISR			0x2030 /* DES unit */
#define TALITOS_DEUISR_LO		0x2034
#define TALITOS_AESUISR			0x4030 /* AES unit */
#define TALITOS_AESUISR_LO		0x4034
#define TALITOS_MDEUISR			0x6030 /* message digest unit */
#define TALITOS_MDEUISR_LO		0x6034
#define TALITOS_MDEUICR			0x6038 /* interrupt control */
#define TALITOS_MDEUICR_LO		0x603c
#define   TALITOS_MDEUICR_LO_ICE	0x4000 /* integrity check IRQ enable */
#define TALITOS_AFEUISR			0x8030 /* arc4 unit */
#define TALITOS_AFEUISR_LO		0x8034
#define TALITOS_RNGUISR			0xa030 /* random number unit */
#define TALITOS_RNGUISR_LO		0xa034
#define TALITOS_RNGUSR			0xa028 /* rng status */
#define TALITOS_RNGUSR_LO		0xa02c
#define   TALITOS_RNGUSR_LO_RD		0x1	/* reset done */
#define   TALITOS_RNGUSR_LO_OFL		0xff0000/* output FIFO length */
#define TALITOS_RNGUDSR			0xa010	/* data size */
#define TALITOS_RNGUDSR_LO		0xa014
#define TALITOS_RNGU_FIFO		0xa800	/* output FIFO */
#define TALITOS_RNGU_FIFO_LO		0xa804	/* output FIFO */
#define TALITOS_RNGURCR			0xa018	/* reset control */
#define TALITOS_RNGURCR_LO		0xa01c
#define   TALITOS_RNGURCR_LO_SR		0x1	/* software reset */
#define TALITOS_PKEUISR			0xc030 /* public key unit */
#define TALITOS_PKEUISR_LO		0xc034
#define TALITOS_KEUISR			0xe030 /* kasumi unit */
#define TALITOS_KEUISR_LO		0xe034
#define TALITOS_CRCUISR			0xf030 /* cyclic redundancy check unit*/
#define TALITOS_CRCUISR_LO		0xf034

#define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256	0x28
#define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512		0x48

/*
 * talitos descriptor header (hdr) bits
 */

/* written back when done */
#define DESC_HDR_DONE			cpu_to_be32(0xff000000)
#define DESC_HDR_LO_ICCR1_MASK		cpu_to_be32(0x00180000)
#define DESC_HDR_LO_ICCR1_PASS		cpu_to_be32(0x00080000)
#define DESC_HDR_LO_ICCR1_FAIL		cpu_to_be32(0x00100000)

/* primary execution unit select */
#define	DESC_HDR_SEL0_MASK		cpu_to_be32(0xf0000000)
#define	DESC_HDR_SEL0_AFEU		cpu_to_be32(0x10000000)
#define	DESC_HDR_SEL0_DEU		cpu_to_be32(0x20000000)
#define	DESC_HDR_SEL0_MDEUA		cpu_to_be32(0x30000000)
#define	DESC_HDR_SEL0_MDEUB		cpu_to_be32(0xb0000000)
#define	DESC_HDR_SEL0_RNG		cpu_to_be32(0x40000000)
#define	DESC_HDR_SEL0_PKEU		cpu_to_be32(0x50000000)
#define	DESC_HDR_SEL0_AESU		cpu_to_be32(0x60000000)
#define	DESC_HDR_SEL0_KEU		cpu_to_be32(0x70000000)
#define	DESC_HDR_SEL0_CRCU		cpu_to_be32(0x80000000)

/* primary execution unit mode (MODE0) and derivatives */
#define	DESC_HDR_MODE0_ENCRYPT		cpu_to_be32(0x00100000)
#define	DESC_HDR_MODE0_AESU_CBC		cpu_to_be32(0x00200000)
#define	DESC_HDR_MODE0_DEU_CBC		cpu_to_be32(0x00400000)
#define	DESC_HDR_MODE0_DEU_3DES		cpu_to_be32(0x00200000)
#define	DESC_HDR_MODE0_MDEU_CONT	cpu_to_be32(0x08000000)
#define	DESC_HDR_MODE0_MDEU_INIT	cpu_to_be32(0x01000000)
#define	DESC_HDR_MODE0_MDEU_HMAC	cpu_to_be32(0x00800000)
#define	DESC_HDR_MODE0_MDEU_PAD		cpu_to_be32(0x00400000)
#define	DESC_HDR_MODE0_MDEU_SHA224	cpu_to_be32(0x00300000)
#define	DESC_HDR_MODE0_MDEU_MD5		cpu_to_be32(0x00200000)
#define	DESC_HDR_MODE0_MDEU_SHA256	cpu_to_be32(0x00100000)
#define	DESC_HDR_MODE0_MDEU_SHA1	cpu_to_be32(0x00000000)
#define	DESC_HDR_MODE0_MDEUB_SHA384	cpu_to_be32(0x00000000)
#define	DESC_HDR_MODE0_MDEUB_SHA512	cpu_to_be32(0x00200000)
#define	DESC_HDR_MODE0_MDEU_MD5_HMAC	(DESC_HDR_MODE0_MDEU_MD5 | \
					 DESC_HDR_MODE0_MDEU_HMAC)
#define	DESC_HDR_MODE0_MDEU_SHA256_HMAC	(DESC_HDR_MODE0_MDEU_SHA256 | \
					 DESC_HDR_MODE0_MDEU_HMAC)
#define	DESC_HDR_MODE0_MDEU_SHA1_HMAC	(DESC_HDR_MODE0_MDEU_SHA1 | \
					 DESC_HDR_MODE0_MDEU_HMAC)

/* secondary execution unit select (SEL1) */
#define	DESC_HDR_SEL1_MASK		cpu_to_be32(0x000f0000)
#define	DESC_HDR_SEL1_MDEUA		cpu_to_be32(0x00030000)
#define	DESC_HDR_SEL1_MDEUB		cpu_to_be32(0x000b0000)
#define	DESC_HDR_SEL1_CRCU		cpu_to_be32(0x00080000)

/* secondary execution unit mode (MODE1) and derivatives */
#define	DESC_HDR_MODE1_MDEU_CICV	cpu_to_be32(0x00004000)
#define	DESC_HDR_MODE1_MDEU_INIT	cpu_to_be32(0x00001000)
#define	DESC_HDR_MODE1_MDEU_HMAC	cpu_to_be32(0x00000800)
#define	DESC_HDR_MODE1_MDEU_PAD		cpu_to_be32(0x00000400)
#define	DESC_HDR_MODE1_MDEU_SHA224	cpu_to_be32(0x00000300)
#define	DESC_HDR_MODE1_MDEU_MD5		cpu_to_be32(0x00000200)
#define	DESC_HDR_MODE1_MDEU_SHA256	cpu_to_be32(0x00000100)
#define	DESC_HDR_MODE1_MDEU_SHA1	cpu_to_be32(0x00000000)
#define	DESC_HDR_MODE1_MDEUB_SHA384	cpu_to_be32(0x00000000)
#define	DESC_HDR_MODE1_MDEUB_SHA512	cpu_to_be32(0x00000200)
#define	DESC_HDR_MODE1_MDEU_MD5_HMAC	(DESC_HDR_MODE1_MDEU_MD5 | \
					 DESC_HDR_MODE1_MDEU_HMAC)
#define	DESC_HDR_MODE1_MDEU_SHA256_HMAC	(DESC_HDR_MODE1_MDEU_SHA256 | \
					 DESC_HDR_MODE1_MDEU_HMAC)
#define	DESC_HDR_MODE1_MDEU_SHA1_HMAC	(DESC_HDR_MODE1_MDEU_SHA1 | \
					 DESC_HDR_MODE1_MDEU_HMAC)

/* direction of overall data flow (DIR) */
#define	DESC_HDR_DIR_INBOUND		cpu_to_be32(0x00000002)

/* request done notification (DN) */
#define	DESC_HDR_DONE_NOTIFY		cpu_to_be32(0x00000001)

/* descriptor types */
#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP		cpu_to_be32(0 << 3)
#define DESC_HDR_TYPE_IPSEC_ESP			cpu_to_be32(1 << 3)
#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU	cpu_to_be32(2 << 3)
#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU	cpu_to_be32(4 << 3)

/* link table extent field bits */
#define DESC_PTR_LNKTBL_JUMP			0x80
#define DESC_PTR_LNKTBL_RETURN			0x02
#define DESC_PTR_LNKTBL_NEXT			0x01
Commit	Line	Data
9c4a7965 KP	1	/*
	2	* Freescale SEC (talitos) device register and descriptor header defines
	3	*
ad42d5fc	4	* Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
9c4a7965 KP	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* 1. Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* 2. Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in the
	14	* documentation and/or other materials provided with the distribution.
	15	* 3. The name of the author may not be used to endorse or promote products
	16	* derived from this software without specific prior written permission.
	17	*
	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	28	*
	29	*/
	30
	31	/*
	32	* TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
	33	*/
	34
	35	/* global register offset addresses */
	36	#define TALITOS_MCR 0x1030 /* master control register */
	37	#define TALITOS_MCR_LO 0x1038
	38	#define TALITOS_MCR_SWR 0x1 /* s/w reset */
	39	#define TALITOS_IMR 0x1008 /* interrupt mask register */
1c2e8811 LN	40	#define TALITOS_IMR_INIT 0x100ff /* enable channel IRQs */
1c2e8811 LN	41	#define TALITOS_IMR_DONE 0x00055 /* done IRQs */
9c4a7965 KP	42	#define TALITOS_IMR_LO 0x100C
	43	#define TALITOS_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
	44	#define TALITOS_ISR 0x1010 /* interrupt status register */
	45	#define TALITOS_ISR_CHERR 0xaa /* channel errors mask */
	46	#define TALITOS_ISR_CHDONE 0x55 /* channel done mask */
	47	#define TALITOS_ISR_LO 0x1014
	48	#define TALITOS_ICR 0x1018 /* interrupt clear register */
	49	#define TALITOS_ICR_LO 0x101C
	50
	51	/* channel register address stride */
ad42d5fc	52	#define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */
9c4a7965 KP	53	#define TALITOS_CH_STRIDE 0x100
	54
	55	/* channel configuration register */
ad42d5fc	56	#define TALITOS_CCCR 0x8
9c4a7965 KP	57	#define TALITOS_CCCR_CONT 0x2 /* channel continue */
9c4a7965 KP	58	#define TALITOS_CCCR_RESET 0x1 /* channel reset */
ad42d5fc	59	#define TALITOS_CCCR_LO 0xc
fe5720e2	60	#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
81eb024c	61	#define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
9c4a7965 KP	62	#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
	63	#define TALITOS_CCCR_LO_NT 0x4 /* notification type */
	64	#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
	65
	66	/* CCPSR: channel pointer status register */
ad42d5fc KP	67	#define TALITOS_CCPSR 0x10
ad42d5fc KP	68	#define TALITOS_CCPSR_LO 0x14
9c4a7965 KP	69	#define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
	70	#define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
	71	#define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
	72	#define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
	73	#define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
	74	#define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
	75	#define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
	76	#define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
	77	#define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
	78	#define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
	79	#define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
	80	#define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
	81
	82	/* channel fetch fifo register */
ad42d5fc KP	83	#define TALITOS_FF 0x48
ad42d5fc KP	84	#define TALITOS_FF_LO 0x4c
9c4a7965 KP	85
9c4a7965 KP	86	/* current descriptor pointer register */
ad42d5fc KP	87	#define TALITOS_CDPR 0x40
ad42d5fc KP	88	#define TALITOS_CDPR_LO 0x44
9c4a7965 KP	89
9c4a7965 KP	90	/* descriptor buffer register */
ad42d5fc KP	91	#define TALITOS_DESCBUF 0x80
ad42d5fc KP	92	#define TALITOS_DESCBUF_LO 0x84
9c4a7965 KP	93
9c4a7965 KP	94	/* gather link table */
ad42d5fc KP	95	#define TALITOS_GATHER 0xc0
ad42d5fc KP	96	#define TALITOS_GATHER_LO 0xc4
9c4a7965 KP	97
9c4a7965 KP	98	/* scatter link table */
ad42d5fc KP	99	#define TALITOS_SCATTER 0xe0
ad42d5fc KP	100	#define TALITOS_SCATTER_LO 0xe4
9c4a7965 KP	101
	102	/* execution unit interrupt status registers */
	103	#define TALITOS_DEUISR 0x2030 /* DES unit */
	104	#define TALITOS_DEUISR_LO 0x2034
	105	#define TALITOS_AESUISR 0x4030 /* AES unit */
	106	#define TALITOS_AESUISR_LO 0x4034
	107	#define TALITOS_MDEUISR 0x6030 /* message digest unit */
	108	#define TALITOS_MDEUISR_LO 0x6034
fe5720e2 KP	109	#define TALITOS_MDEUICR 0x6038 /* interrupt control */
	110	#define TALITOS_MDEUICR_LO 0x603c
	111	#define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
9c4a7965 KP	112	#define TALITOS_AFEUISR 0x8030 /* arc4 unit */
	113	#define TALITOS_AFEUISR_LO 0x8034
	114	#define TALITOS_RNGUISR 0xa030 /* random number unit */
	115	#define TALITOS_RNGUISR_LO 0xa034
	116	#define TALITOS_RNGUSR 0xa028 /* rng status */
	117	#define TALITOS_RNGUSR_LO 0xa02c
	118	#define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
	119	#define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
	120	#define TALITOS_RNGUDSR 0xa010 /* data size */
	121	#define TALITOS_RNGUDSR_LO 0xa014
	122	#define TALITOS_RNGU_FIFO 0xa800 /* output FIFO */
	123	#define TALITOS_RNGU_FIFO_LO 0xa804 /* output FIFO */
	124	#define TALITOS_RNGURCR 0xa018 /* reset control */
	125	#define TALITOS_RNGURCR_LO 0xa01c
	126	#define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
	127	#define TALITOS_PKEUISR 0xc030 /* public key unit */
	128	#define TALITOS_PKEUISR_LO 0xc034
	129	#define TALITOS_KEUISR 0xe030 /* kasumi unit */
	130	#define TALITOS_KEUISR_LO 0xe034
	131	#define TALITOS_CRCUISR 0xf030 /* cyclic redundancy check unit*/
	132	#define TALITOS_CRCUISR_LO 0xf034
	133
497f2e6b LN	134	#define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
	135	#define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
	136
9c4a7965 KP	137	/*
	138	* talitos descriptor header (hdr) bits
	139	*/
	140
	141	/* written back when done */
dad3df20 HH	142	#define DESC_HDR_DONE cpu_to_be32(0xff000000)
	143	#define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
	144	#define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
	145	#define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
9c4a7965 KP	146
9c4a7965 KP	147	/* primary execution unit select */
dad3df20 HH	148	#define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
	149	#define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
	150	#define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
	151	#define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
	152	#define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
	153	#define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
	154	#define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
	155	#define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
	156	#define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
	157	#define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
9c4a7965 KP	158
9c4a7965 KP	159	/* primary execution unit mode (MODE0) and derivatives */
dad3df20 HH	160	#define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
	161	#define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
	162	#define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
	163	#define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
497f2e6b	164	#define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
dad3df20 HH	165	#define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
	166	#define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
	167	#define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
60f208d7	168	#define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
dad3df20 HH	169	#define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
	170	#define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
	171	#define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
497f2e6b LN	172	#define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
497f2e6b LN	173	#define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
9c4a7965 KP	174	#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 \| \
	175	DESC_HDR_MODE0_MDEU_HMAC)
	176	#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 \| \
	177	DESC_HDR_MODE0_MDEU_HMAC)
	178	#define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 \| \
	179	DESC_HDR_MODE0_MDEU_HMAC)
	180
	181	/* secondary execution unit select (SEL1) */
dad3df20 HH	182	#define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
	183	#define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
	184	#define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
	185	#define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
9c4a7965 KP	186
9c4a7965 KP	187	/* secondary execution unit mode (MODE1) and derivatives */
dad3df20 HH	188	#define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
	189	#define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
	190	#define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
	191	#define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
60f208d7	192	#define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
dad3df20 HH	193	#define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
	194	#define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
	195	#define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
497f2e6b LN	196	#define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
497f2e6b LN	197	#define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
9c4a7965 KP	198	#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 \| \
	199	DESC_HDR_MODE1_MDEU_HMAC)
	200	#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 \| \
	201	DESC_HDR_MODE1_MDEU_HMAC)
	202	#define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 \| \
	203	DESC_HDR_MODE1_MDEU_HMAC)
	204
	205	/* direction of overall data flow (DIR) */
dad3df20	206	#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
9c4a7965 KP	207
9c4a7965 KP	208	/* request done notification (DN) */
dad3df20	209	#define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
9c4a7965 KP	210
9c4a7965 KP	211	/* descriptor types */
dad3df20 HH	212	#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
	213	#define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
	214	#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
	215	#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
9c4a7965 KP	216
	217	/* link table extent field bits */
	218	#define DESC_PTR_LNKTBL_JUMP 0x80
	219	#define DESC_PTR_LNKTBL_RETURN 0x02
	220	#define DESC_PTR_LNKTBL_NEXT 0x01