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crypto: omap-sham - crypto_ahash_final() now not need to be called.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / crypto / omap-sham.c
CommitLineData
8628e7c8
DK		 1/*
2 * Cryptographic API.
3 *
4 * Support for OMAP SHA1/MD5 HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 * Some ideas are from old omap-sha1-md5.c driver.
14 */
15
16#define pr_fmt(fmt) "%s: " fmt, __func__
17
8628e7c8
DK		 18#include <linux/err.h>
19#include <linux/device.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/interrupt.h>
24#include <linux/kernel.h>
25#include <linux/clk.h>
26#include <linux/irq.h>
27#include <linux/io.h>
28#include <linux/platform_device.h>
29#include <linux/scatterlist.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
32#include <linux/crypto.h>
33#include <linux/cryptohash.h>
34#include <crypto/scatterwalk.h>
35#include <crypto/algapi.h>
36#include <crypto/sha.h>
37#include <crypto/hash.h>
38#include <crypto/internal/hash.h>
39
40#include <plat/cpu.h>
41#include <plat/dma.h>
42#include <mach/irqs.h>
43
44#define SHA_REG_DIGEST(x) (0x00 + ((x) * 0x04))
45#define SHA_REG_DIN(x) (0x1C + ((x) * 0x04))
46
47#define SHA1_MD5_BLOCK_SIZE SHA1_BLOCK_SIZE
48#define MD5_DIGEST_SIZE 16
49
50#define SHA_REG_DIGCNT 0x14
51
52#define SHA_REG_CTRL 0x18
53#define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
54#define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
55#define SHA_REG_CTRL_ALGO_CONST (1 << 3)
56#define SHA_REG_CTRL_ALGO (1 << 2)
57#define SHA_REG_CTRL_INPUT_READY (1 << 1)
58#define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
59
60#define SHA_REG_REV 0x5C
61#define SHA_REG_REV_MAJOR 0xF0
62#define SHA_REG_REV_MINOR 0x0F
63
64#define SHA_REG_MASK 0x60
65#define SHA_REG_MASK_DMA_EN (1 << 3)
66#define SHA_REG_MASK_IT_EN (1 << 2)
67#define SHA_REG_MASK_SOFTRESET (1 << 1)
68#define SHA_REG_AUTOIDLE (1 << 0)
69
70#define SHA_REG_SYSSTATUS 0x64
71#define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
72
73#define DEFAULT_TIMEOUT_INTERVAL HZ
74
75#define FLAGS_FIRST 0x0001
76#define FLAGS_FINUP 0x0002
77#define FLAGS_FINAL 0x0004
78#define FLAGS_FAST 0x0008
79#define FLAGS_SHA1 0x0010
80#define FLAGS_DMA_ACTIVE 0x0020
81#define FLAGS_OUTPUT_READY 0x0040
82#define FLAGS_CLEAN 0x0080
83#define FLAGS_INIT 0x0100
84#define FLAGS_CPU 0x0200
85#define FLAGS_HMAC 0x0400
3e133c8b 86#define FLAGS_ERROR 0x0800
a5d87237 87#define FLAGS_BUSY 0x1000
8628e7c8
DK		 88
89#define OP_UPDATE 1
90#define OP_FINAL 2
91
798eed5d
DK		 92#define OMAP_ALIGN_MASK (sizeof(u32)-1)
93#define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
94
95#define BUFLEN PAGE_SIZE
96
8628e7c8
DK		 97struct omap_sham_dev;
98
99struct omap_sham_reqctx {
100 struct omap_sham_dev *dd;
101 unsigned long flags;
102 unsigned long op;
103
798eed5d 104 u8 digest[SHA1_DIGEST_SIZE] OMAP_ALIGNED;
8628e7c8 105 size_t digcnt;
8628e7c8
DK		 106 size_t bufcnt;
107 size_t buflen;
108 dma_addr_t dma_addr;
109
110 /* walk state */
111 struct scatterlist *sg;
112 unsigned int offset; /* offset in current sg */
113 unsigned int total; /* total request */
798eed5d
DK		 114
115 u8 buffer[0] OMAP_ALIGNED;
8628e7c8
DK		 116};
117
118struct omap_sham_hmac_ctx {
119 struct crypto_shash *shash;
120 u8 ipad[SHA1_MD5_BLOCK_SIZE];
121 u8 opad[SHA1_MD5_BLOCK_SIZE];
122};
123
124struct omap_sham_ctx {
125 struct omap_sham_dev *dd;
126
127 unsigned long flags;
128
129 /* fallback stuff */
130 struct crypto_shash *fallback;
131
132 struct omap_sham_hmac_ctx base[0];
133};
134
135#define OMAP_SHAM_QUEUE_LENGTH 1
136
137struct omap_sham_dev {
138 struct list_head list;
139 unsigned long phys_base;
140 struct device *dev;
141 void __iomem *io_base;
142 int irq;
143 struct clk *iclk;
144 spinlock_t lock;
3e133c8b 145 int err;
8628e7c8
DK		 146 int dma;
147 int dma_lch;
148 struct tasklet_struct done_task;
149 struct tasklet_struct queue_task;
150
151 unsigned long flags;
152 struct crypto_queue queue;
153 struct ahash_request *req;
154};
155
156struct omap_sham_drv {
157 struct list_head dev_list;
158 spinlock_t lock;
159 unsigned long flags;
160};
161
162static struct omap_sham_drv sham = {
163 .dev_list = LIST_HEAD_INIT(sham.dev_list),
164 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
165};
166
167static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
168{
169 return __raw_readl(dd->io_base + offset);
170}
171
172static inline void omap_sham_write(struct omap_sham_dev *dd,
173 u32 offset, u32 value)
174{
175 __raw_writel(value, dd->io_base + offset);
176}
177
178static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
179 u32 value, u32 mask)
180{
181 u32 val;
182
183 val = omap_sham_read(dd, address);
184 val &= ~mask;
185 val |= value;
186 omap_sham_write(dd, address, val);
187}
188
189static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
190{
191 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
192
193 while (!(omap_sham_read(dd, offset) & bit)) {
194 if (time_is_before_jiffies(timeout))
195 return -ETIMEDOUT;
196 }
197
198 return 0;
199}
200
201static void omap_sham_copy_hash(struct ahash_request *req, int out)
202{
203 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
0c3cf4cc 204 u32 *hash = (u32 *)ctx->digest;
8628e7c8
DK		 205 int i;
206
207 if (likely(ctx->flags & FLAGS_SHA1)) {
208 /* SHA1 results are in big endian */
209 for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
210 if (out)
211 hash[i] = be32_to_cpu(omap_sham_read(ctx->dd,
212 SHA_REG_DIGEST(i)));
213 else
214 omap_sham_write(ctx->dd, SHA_REG_DIGEST(i),
215 cpu_to_be32(hash[i]));
216 } else {
217 /* MD5 results are in little endian */
218 for (i = 0; i < MD5_DIGEST_SIZE / sizeof(u32); i++)
219 if (out)
220 hash[i] = le32_to_cpu(omap_sham_read(ctx->dd,
221 SHA_REG_DIGEST(i)));
222 else
223 omap_sham_write(ctx->dd, SHA_REG_DIGEST(i),
224 cpu_to_le32(hash[i]));
225 }
226}
227
798eed5d 228static int omap_sham_hw_init(struct omap_sham_dev *dd)
8628e7c8 229{
798eed5d 230 clk_enable(dd->iclk);
8628e7c8 231
798eed5d
DK		 232 if (!(dd->flags & FLAGS_INIT)) {
233 omap_sham_write_mask(dd, SHA_REG_MASK,
234 SHA_REG_MASK_SOFTRESET, SHA_REG_MASK_SOFTRESET);
8628e7c8 235
798eed5d
DK		 236 if (omap_sham_wait(dd, SHA_REG_SYSSTATUS,
237 SHA_REG_SYSSTATUS_RESETDONE))
238 return -ETIMEDOUT;
8628e7c8 239
798eed5d
DK		 240 dd->flags |= FLAGS_INIT;
241 dd->err = 0;
242 }
8628e7c8 243
798eed5d
DK		 244 return 0;
245}
246
247static void omap_sham_write_ctrl(struct omap_sham_dev *dd, size_t length,
248 int final, int dma)
249{
250 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
251 u32 val = length << 5, mask;
252
253 if (likely(ctx->digcnt))
8628e7c8 254 omap_sham_write(dd, SHA_REG_DIGCNT, ctx->digcnt);
8628e7c8
DK		 255
256 omap_sham_write_mask(dd, SHA_REG_MASK,
257 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
258 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
259 /*
260 * Setting ALGO_CONST only for the first iteration
261 * and CLOSE_HASH only for the last one.
262 */
263 if (ctx->flags & FLAGS_SHA1)
264 val |= SHA_REG_CTRL_ALGO;
265 if (!ctx->digcnt)
266 val |= SHA_REG_CTRL_ALGO_CONST;
267 if (final)
268 val |= SHA_REG_CTRL_CLOSE_HASH;
269
270 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
271 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
272
273 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
8628e7c8
DK		 274}
275
276static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
277 size_t length, int final)
278{
279 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
798eed5d 280 int count, len32;
8628e7c8
DK		 281 const u32 *buffer = (const u32 *)buf;
282
283 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
284 ctx->digcnt, length, final);
285
798eed5d 286 omap_sham_write_ctrl(dd, length, final, 0);
8628e7c8 287
3e133c8b
DK		 288 /* should be non-zero before next lines to disable clocks later */
289 ctx->digcnt += length;
290
8628e7c8
DK		 291 if (omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY))
292 return -ETIMEDOUT;
293
8628e7c8
DK		 294 if (final)
295 ctx->flags |= FLAGS_FINAL; /* catch last interrupt */
296
297 len32 = DIV_ROUND_UP(length, sizeof(u32));
298
299 for (count = 0; count < len32; count++)
300 omap_sham_write(dd, SHA_REG_DIN(count), buffer[count]);
301
302 return -EINPROGRESS;
303}
304
305static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
306 size_t length, int final)
307{
308 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
798eed5d 309 int len32;
8628e7c8
DK		 310
311 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
312 ctx->digcnt, length, final);
8628e7c8
DK		 313
314 len32 = DIV_ROUND_UP(length, sizeof(u32));
315
316 omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
584db6a1
SO		 317 1, OMAP_DMA_SYNC_PACKET, dd->dma,
318 OMAP_DMA_DST_SYNC_PREFETCH);
8628e7c8
DK		 319
320 omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
321 dma_addr, 0, 0);
322
798eed5d 323 omap_sham_write_ctrl(dd, length, final, 1);
8628e7c8
DK		 324
325 ctx->digcnt += length;
326
327 if (final)
328 ctx->flags |= FLAGS_FINAL; /* catch last interrupt */
329
330 dd->flags |= FLAGS_DMA_ACTIVE;
331
332 omap_start_dma(dd->dma_lch);
333
334 return -EINPROGRESS;
335}
336
337static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
338 const u8 *data, size_t length)
339{
340 size_t count = min(length, ctx->buflen - ctx->bufcnt);
341
342 count = min(count, ctx->total);
343 if (count <= 0)
344 return 0;
345 memcpy(ctx->buffer + ctx->bufcnt, data, count);
346 ctx->bufcnt += count;
347
348 return count;
349}
350
351static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
352{
353 size_t count;
354
355 while (ctx->sg) {
356 count = omap_sham_append_buffer(ctx,
357 sg_virt(ctx->sg) + ctx->offset,
358 ctx->sg->length - ctx->offset);
359 if (!count)
360 break;
361 ctx->offset += count;
362 ctx->total -= count;
363 if (ctx->offset == ctx->sg->length) {
364 ctx->sg = sg_next(ctx->sg);
365 if (ctx->sg)
366 ctx->offset = 0;
367 else
368 ctx->total = 0;
369 }
370 }
371
372 return 0;
373}
374
798eed5d
DK		 375static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
376 struct omap_sham_reqctx *ctx,
377 size_t length, int final)
378{
379 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
380 DMA_TO_DEVICE);
381 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
382 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
383 return -EINVAL;
384 }
385
386 /* next call does not fail... so no unmap in the case of error */
387 return omap_sham_xmit_dma(dd, ctx->dma_addr, length, final);
388}
389
8628e7c8
DK		 390static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
391{
392 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
393 unsigned int final;
394 size_t count;
395
396 if (!ctx->total)
397 return 0;
398
399 omap_sham_append_sg(ctx);
400
401 final = (ctx->flags & FLAGS_FINUP) && !ctx->total;
402
403 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
404 ctx->bufcnt, ctx->digcnt, final);
405
406 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
407 count = ctx->bufcnt;
408 ctx->bufcnt = 0;
798eed5d 409 return omap_sham_xmit_dma_map(dd, ctx, count, final);
8628e7c8
DK		 410 }
411
412 return 0;
413}
414
415static int omap_sham_update_dma_fast(struct omap_sham_dev *dd)
416{
417 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
418 unsigned int length;
419
420 ctx->flags |= FLAGS_FAST;
421
422 length = min(ctx->total, sg_dma_len(ctx->sg));
423 ctx->total = length;
424
425 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
426 dev_err(dd->dev, "dma_map_sg error\n");
427 return -EINVAL;
428 }
429
430 ctx->total -= length;
431
798eed5d
DK		 432 /* next call does not fail... so no unmap in the case of error */
433 return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, 1);
8628e7c8
DK		 434}
435
436static int omap_sham_update_cpu(struct omap_sham_dev *dd)
437{
438 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
439 int bufcnt;
440
441 omap_sham_append_sg(ctx);
442 bufcnt = ctx->bufcnt;
443 ctx->bufcnt = 0;
444
445 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
446}
447
448static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
449{
450 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
451
452 omap_stop_dma(dd->dma_lch);
453 if (ctx->flags & FLAGS_FAST)
454 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
798eed5d
DK		 455 else
456 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
457 DMA_TO_DEVICE);
8628e7c8
DK		 458
459 return 0;
460}
461
462static void omap_sham_cleanup(struct ahash_request *req)
463{
464 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
465 struct omap_sham_dev *dd = ctx->dd;
466 unsigned long flags;
467
468 spin_lock_irqsave(&dd->lock, flags);
469 if (ctx->flags & FLAGS_CLEAN) {
470 spin_unlock_irqrestore(&dd->lock, flags);
471 return;
472 }
473 ctx->flags |= FLAGS_CLEAN;
474 spin_unlock_irqrestore(&dd->lock, flags);
475
798eed5d 476 if (ctx->digcnt)
0c3cf4cc
DK		 477 memcpy(req->result, ctx->digest, (ctx->flags & FLAGS_SHA1) ?
478 SHA1_DIGEST_SIZE : MD5_DIGEST_SIZE);
8628e7c8
DK		 479
480 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
481}
482
483static int omap_sham_init(struct ahash_request *req)
484{
485 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
486 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
487 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
488 struct omap_sham_dev *dd = NULL, *tmp;
489
490 spin_lock_bh(&sham.lock);
491 if (!tctx->dd) {
492 list_for_each_entry(tmp, &sham.dev_list, list) {
493 dd = tmp;
494 break;
495 }
496 tctx->dd = dd;
497 } else {
498 dd = tctx->dd;
499 }
500 spin_unlock_bh(&sham.lock);
501
502 ctx->dd = dd;
503
504 ctx->flags = 0;
505
506 ctx->flags |= FLAGS_FIRST;
507
508 dev_dbg(dd->dev, "init: digest size: %d\n",
509 crypto_ahash_digestsize(tfm));
510
511 if (crypto_ahash_digestsize(tfm) == SHA1_DIGEST_SIZE)
512 ctx->flags |= FLAGS_SHA1;
513
514 ctx->bufcnt = 0;
515 ctx->digcnt = 0;
798eed5d 516 ctx->buflen = BUFLEN;
8628e7c8
DK		 517
518 if (tctx->flags & FLAGS_HMAC) {
519 struct omap_sham_hmac_ctx *bctx = tctx->base;
520
521 memcpy(ctx->buffer, bctx->ipad, SHA1_MD5_BLOCK_SIZE);
522 ctx->bufcnt = SHA1_MD5_BLOCK_SIZE;
523 ctx->flags |= FLAGS_HMAC;
524 }
525
526 return 0;
527
528}
529
530static int omap_sham_update_req(struct omap_sham_dev *dd)
531{
532 struct ahash_request *req = dd->req;
533 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
534 int err;
535
536 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
537 ctx->total, ctx->digcnt, (ctx->flags & FLAGS_FINUP) != 0);
538
539 if (ctx->flags & FLAGS_CPU)
540 err = omap_sham_update_cpu(dd);
541 else if (ctx->flags & FLAGS_FAST)
542 err = omap_sham_update_dma_fast(dd);
543 else
544 err = omap_sham_update_dma_slow(dd);
545
546 /* wait for dma completion before can take more data */
547 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
548
549 return err;
550}
551
552static int omap_sham_final_req(struct omap_sham_dev *dd)
553{
554 struct ahash_request *req = dd->req;
555 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
556 int err = 0, use_dma = 1;
557
558 if (ctx->bufcnt <= 64)
559 /* faster to handle last block with cpu */
560 use_dma = 0;
561
562 if (use_dma)
798eed5d 563 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
8628e7c8
DK		 564 else
565 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
566
567 ctx->bufcnt = 0;
568
8628e7c8
DK		 569 dev_dbg(dd->dev, "final_req: err: %d\n", err);
570
571 return err;
572}
573
574static int omap_sham_finish_req_hmac(struct ahash_request *req)
575{
0c3cf4cc 576 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
8628e7c8
DK		 577 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
578 struct omap_sham_hmac_ctx *bctx = tctx->base;
579 int bs = crypto_shash_blocksize(bctx->shash);
580 int ds = crypto_shash_digestsize(bctx->shash);
581 struct {
582 struct shash_desc shash;
583 char ctx[crypto_shash_descsize(bctx->shash)];
584 } desc;
585
586 desc.shash.tfm = bctx->shash;
587 desc.shash.flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
588
589 return crypto_shash_init(&desc.shash) ?:
590 crypto_shash_update(&desc.shash, bctx->opad, bs) ?:
0c3cf4cc 591 crypto_shash_finup(&desc.shash, ctx->digest, ds, ctx->digest);
8628e7c8
DK		 592}
593
594static void omap_sham_finish_req(struct ahash_request *req, int err)
595{
596 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
798eed5d 597 struct omap_sham_dev *dd = ctx->dd;
8628e7c8
DK		 598
599 if (!err) {
600 omap_sham_copy_hash(ctx->dd->req, 1);
601 if (ctx->flags & FLAGS_HMAC)
602 err = omap_sham_finish_req_hmac(req);
3e133c8b
DK		 603 } else {
604 ctx->flags |= FLAGS_ERROR;
8628e7c8
DK		 605 }
606
3e133c8b 607 if ((ctx->flags & FLAGS_FINAL) || err)
8628e7c8
DK		 608 omap_sham_cleanup(req);
609
798eed5d
DK		 610 clk_disable(dd->iclk);
611 dd->flags &= ~FLAGS_BUSY;
8628e7c8
DK		 612
613 if (req->base.complete)
614 req->base.complete(&req->base, err);
615}
616
a5d87237
DK		 617static int omap_sham_handle_queue(struct omap_sham_dev *dd,
618 struct ahash_request *req)
8628e7c8 619{
798eed5d 620 struct crypto_async_request *async_req, *backlog = 0;
8628e7c8 621 struct omap_sham_reqctx *ctx;
a5d87237 622 struct ahash_request *prev_req;
8628e7c8 623 unsigned long flags;
a5d87237 624 int err = 0, ret = 0;
8628e7c8
DK		 625
626 spin_lock_irqsave(&dd->lock, flags);
a5d87237
DK		 627 if (req)
628 ret = ahash_enqueue_request(&dd->queue, req);
629 if (dd->flags & FLAGS_BUSY) {
630 spin_unlock_irqrestore(&dd->lock, flags);
631 return ret;
632 }
8628e7c8 633 async_req = crypto_dequeue_request(&dd->queue);
a5d87237
DK		 634 if (async_req) {
635 dd->flags |= FLAGS_BUSY;
636 backlog = crypto_get_backlog(&dd->queue);
637 }
8628e7c8
DK		 638 spin_unlock_irqrestore(&dd->lock, flags);
639
640 if (!async_req)
a5d87237 641 return ret;
8628e7c8
DK		 642
643 if (backlog)
644 backlog->complete(backlog, -EINPROGRESS);
645
646 req = ahash_request_cast(async_req);
647
648 prev_req = dd->req;
649 dd->req = req;
650
651 ctx = ahash_request_ctx(req);
652
653 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
654 ctx->op, req->nbytes);
655
798eed5d
DK		 656
657 err = omap_sham_hw_init(dd);
658 if (err)
659 goto err1;
660
661 omap_set_dma_dest_params(dd->dma_lch, 0,
662 OMAP_DMA_AMODE_CONSTANT,
663 dd->phys_base + SHA_REG_DIN(0), 0, 16);
664
665 omap_set_dma_dest_burst_mode(dd->dma_lch,
666 OMAP_DMA_DATA_BURST_16);
667
668 omap_set_dma_src_burst_mode(dd->dma_lch,
669 OMAP_DMA_DATA_BURST_4);
670
671 if (ctx->digcnt)
8628e7c8
DK		 672 /* request has changed - restore hash */
673 omap_sham_copy_hash(req, 0);
674
675 if (ctx->op == OP_UPDATE) {
676 err = omap_sham_update_req(dd);
677 if (err != -EINPROGRESS && (ctx->flags & FLAGS_FINUP))
678 /* no final() after finup() */
679 err = omap_sham_final_req(dd);
680 } else if (ctx->op == OP_FINAL) {
681 err = omap_sham_final_req(dd);
682 }
798eed5d 683err1:
8628e7c8
DK		 684 if (err != -EINPROGRESS) {
685 /* done_task will not finish it, so do it here */
686 omap_sham_finish_req(req, err);
687 tasklet_schedule(&dd->queue_task);
688 }
689
690 dev_dbg(dd->dev, "exit, err: %d\n", err);
691
a5d87237 692 return ret;
8628e7c8
DK		 693}
694
695static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
696{
697 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
698 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
699 struct omap_sham_dev *dd = tctx->dd;
8628e7c8
DK		 700
701 ctx->op = op;
702
a5d87237 703 return omap_sham_handle_queue(dd, req);
8628e7c8
DK		 704}
705
706static int omap_sham_update(struct ahash_request *req)
707{
708 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
709
710 if (!req->nbytes)
711 return 0;
712
713 ctx->total = req->nbytes;
714 ctx->sg = req->src;
715 ctx->offset = 0;
716
717 if (ctx->flags & FLAGS_FINUP) {
718 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
719 /*
720 * OMAP HW accel works only with buffers >= 9
721 * will switch to bypass in final()
722 * final has the same request and data
723 */
724 omap_sham_append_sg(ctx);
725 return 0;
726 } else if (ctx->bufcnt + ctx->total <= 64) {
727 ctx->flags |= FLAGS_CPU;
728 } else if (!ctx->bufcnt && sg_is_last(ctx->sg)) {
729 /* may be can use faster functions */
730 int aligned = IS_ALIGNED((u32)ctx->sg->offset,
731 sizeof(u32));
732
733 if (aligned && (ctx->flags & FLAGS_FIRST))
734 /* digest: first and final */
735 ctx->flags |= FLAGS_FAST;
736
737 ctx->flags &= ~FLAGS_FIRST;
738 }
739 } else if (ctx->bufcnt + ctx->total <= ctx->buflen) {
740 /* if not finaup -> not fast */
741 omap_sham_append_sg(ctx);
742 return 0;
743 }
744
745 return omap_sham_enqueue(req, OP_UPDATE);
746}
747
748static int omap_sham_shash_digest(struct crypto_shash *shash, u32 flags,
749 const u8 *data, unsigned int len, u8 *out)
750{
751 struct {
752 struct shash_desc shash;
753 char ctx[crypto_shash_descsize(shash)];
754 } desc;
755
756 desc.shash.tfm = shash;
757 desc.shash.flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
758
759 return crypto_shash_digest(&desc.shash, data, len, out);
760}
761
762static int omap_sham_final_shash(struct ahash_request *req)
763{
764 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
765 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
766
767 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
768 ctx->buffer, ctx->bufcnt, req->result);
769}
770
771static int omap_sham_final(struct ahash_request *req)
772{
773 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
774 int err = 0;
775
776 ctx->flags |= FLAGS_FINUP;
777
3e133c8b
DK		 778 if (!(ctx->flags & FLAGS_ERROR)) {
779 /* OMAP HW accel works only with buffers >= 9 */
780 /* HMAC is always >= 9 because of ipad */
781 if ((ctx->digcnt + ctx->bufcnt) < 9)
782 err = omap_sham_final_shash(req);
783 else if (ctx->bufcnt)
784 return omap_sham_enqueue(req, OP_FINAL);
785 }
8628e7c8
DK		 786
787 omap_sham_cleanup(req);
788
789 return err;
790}
791
792static int omap_sham_finup(struct ahash_request *req)
793{
794 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
795 int err1, err2;
796
797 ctx->flags |= FLAGS_FINUP;
798
799 err1 = omap_sham_update(req);
800 if (err1 == -EINPROGRESS)
801 return err1;
802 /*
803 * final() has to be always called to cleanup resources
804 * even if udpate() failed, except EINPROGRESS
805 */
806 err2 = omap_sham_final(req);
807
808 return err1 ?: err2;
809}
810
811static int omap_sham_digest(struct ahash_request *req)
812{
813 return omap_sham_init(req) ?: omap_sham_finup(req);
814}
815
816static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
817 unsigned int keylen)
818{
819 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
820 struct omap_sham_hmac_ctx *bctx = tctx->base;
821 int bs = crypto_shash_blocksize(bctx->shash);
822 int ds = crypto_shash_digestsize(bctx->shash);
823 int err, i;
824 err = crypto_shash_setkey(tctx->fallback, key, keylen);
825 if (err)
826 return err;
827
828 if (keylen > bs) {
829 err = omap_sham_shash_digest(bctx->shash,
830 crypto_shash_get_flags(bctx->shash),
831 key, keylen, bctx->ipad);
832 if (err)
833 return err;
834 keylen = ds;
835 } else {
836 memcpy(bctx->ipad, key, keylen);
837 }
838
839 memset(bctx->ipad + keylen, 0, bs - keylen);
840 memcpy(bctx->opad, bctx->ipad, bs);
841
842 for (i = 0; i < bs; i++) {
843 bctx->ipad[i] ^= 0x36;
844 bctx->opad[i] ^= 0x5c;
845 }
846
847 return err;
848}
849
850static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
851{
852 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
853 const char *alg_name = crypto_tfm_alg_name(tfm);
854
3e133c8b
DK		 855 pr_info("enter\n");
856
8628e7c8
DK		 857 /* Allocate a fallback and abort if it failed. */
858 tctx->fallback = crypto_alloc_shash(alg_name, 0,
859 CRYPTO_ALG_NEED_FALLBACK);
860 if (IS_ERR(tctx->fallback)) {
861 pr_err("omap-sham: fallback driver '%s' "
862 "could not be loaded.\n", alg_name);
863 return PTR_ERR(tctx->fallback);
864 }
865
866 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
798eed5d 867 sizeof(struct omap_sham_reqctx) + BUFLEN);
8628e7c8
DK		 868
869 if (alg_base) {
870 struct omap_sham_hmac_ctx *bctx = tctx->base;
871 tctx->flags |= FLAGS_HMAC;
872 bctx->shash = crypto_alloc_shash(alg_base, 0,
873 CRYPTO_ALG_NEED_FALLBACK);
874 if (IS_ERR(bctx->shash)) {
875 pr_err("omap-sham: base driver '%s' "
876 "could not be loaded.\n", alg_base);
877 crypto_free_shash(tctx->fallback);
878 return PTR_ERR(bctx->shash);
879 }
880
881 }
882
883 return 0;
884}
885
886static int omap_sham_cra_init(struct crypto_tfm *tfm)
887{
888 return omap_sham_cra_init_alg(tfm, NULL);
889}
890
891static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
892{
893 return omap_sham_cra_init_alg(tfm, "sha1");
894}
895
896static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
897{
898 return omap_sham_cra_init_alg(tfm, "md5");
899}
900
901static void omap_sham_cra_exit(struct crypto_tfm *tfm)
902{
903 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
904
905 crypto_free_shash(tctx->fallback);
906 tctx->fallback = NULL;
907
908 if (tctx->flags & FLAGS_HMAC) {
909 struct omap_sham_hmac_ctx *bctx = tctx->base;
910 crypto_free_shash(bctx->shash);
911 }
912}
913
914static struct ahash_alg algs[] = {
915{
916 .init = omap_sham_init,
917 .update = omap_sham_update,
918 .final = omap_sham_final,
919 .finup = omap_sham_finup,
920 .digest = omap_sham_digest,
921 .halg.digestsize = SHA1_DIGEST_SIZE,
922 .halg.base = {
923 .cra_name = "sha1",
924 .cra_driver_name = "omap-sha1",
925 .cra_priority = 100,
926 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
927 CRYPTO_ALG_ASYNC |
928 CRYPTO_ALG_NEED_FALLBACK,
929 .cra_blocksize = SHA1_BLOCK_SIZE,
930 .cra_ctxsize = sizeof(struct omap_sham_ctx),
931 .cra_alignmask = 0,
932 .cra_module = THIS_MODULE,
933 .cra_init = omap_sham_cra_init,
934 .cra_exit = omap_sham_cra_exit,
935 }
936},
937{
938 .init = omap_sham_init,
939 .update = omap_sham_update,
940 .final = omap_sham_final,
941 .finup = omap_sham_finup,
942 .digest = omap_sham_digest,
943 .halg.digestsize = MD5_DIGEST_SIZE,
944 .halg.base = {
945 .cra_name = "md5",
946 .cra_driver_name = "omap-md5",
947 .cra_priority = 100,
948 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
949 CRYPTO_ALG_ASYNC |
950 CRYPTO_ALG_NEED_FALLBACK,
951 .cra_blocksize = SHA1_BLOCK_SIZE,
952 .cra_ctxsize = sizeof(struct omap_sham_ctx),
798eed5d 953 .cra_alignmask = OMAP_ALIGN_MASK,
8628e7c8
DK		 954 .cra_module = THIS_MODULE,
955 .cra_init = omap_sham_cra_init,
956 .cra_exit = omap_sham_cra_exit,
957 }
958},
959{
960 .init = omap_sham_init,
961 .update = omap_sham_update,
962 .final = omap_sham_final,
963 .finup = omap_sham_finup,
964 .digest = omap_sham_digest,
965 .setkey = omap_sham_setkey,
966 .halg.digestsize = SHA1_DIGEST_SIZE,
967 .halg.base = {
968 .cra_name = "hmac(sha1)",
969 .cra_driver_name = "omap-hmac-sha1",
970 .cra_priority = 100,
971 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
972 CRYPTO_ALG_ASYNC |
973 CRYPTO_ALG_NEED_FALLBACK,
974 .cra_blocksize = SHA1_BLOCK_SIZE,
975 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
976 sizeof(struct omap_sham_hmac_ctx),
798eed5d 977 .cra_alignmask = OMAP_ALIGN_MASK,
8628e7c8
DK		 978 .cra_module = THIS_MODULE,
979 .cra_init = omap_sham_cra_sha1_init,
980 .cra_exit = omap_sham_cra_exit,
981 }
982},
983{
984 .init = omap_sham_init,
985 .update = omap_sham_update,
986 .final = omap_sham_final,
987 .finup = omap_sham_finup,
988 .digest = omap_sham_digest,
989 .setkey = omap_sham_setkey,
990 .halg.digestsize = MD5_DIGEST_SIZE,
991 .halg.base = {
992 .cra_name = "hmac(md5)",
993 .cra_driver_name = "omap-hmac-md5",
994 .cra_priority = 100,
995 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
996 CRYPTO_ALG_ASYNC |
997 CRYPTO_ALG_NEED_FALLBACK,
998 .cra_blocksize = SHA1_BLOCK_SIZE,
999 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1000 sizeof(struct omap_sham_hmac_ctx),
798eed5d 1001 .cra_alignmask = OMAP_ALIGN_MASK,
8628e7c8
DK		 1002 .cra_module = THIS_MODULE,
1003 .cra_init = omap_sham_cra_md5_init,
1004 .cra_exit = omap_sham_cra_exit,
1005 }
1006}
1007};
1008
1009static void omap_sham_done_task(unsigned long data)
1010{
1011 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1012 struct ahash_request *req = dd->req;
1013 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
3e133c8b 1014 int ready = 0, err = 0;
8628e7c8
DK		 1015
1016 if (ctx->flags & FLAGS_OUTPUT_READY) {
1017 ctx->flags &= ~FLAGS_OUTPUT_READY;
1018 ready = 1;
1019 }
1020
1021 if (dd->flags & FLAGS_DMA_ACTIVE) {
1022 dd->flags &= ~FLAGS_DMA_ACTIVE;
1023 omap_sham_update_dma_stop(dd);
3e133c8b
DK		 1024 if (!dd->err)
1025 err = omap_sham_update_dma_slow(dd);
8628e7c8
DK		 1026 }
1027
3e133c8b
DK		 1028 err = dd->err ? : err;
1029
1030 if (err != -EINPROGRESS && (ready || err)) {
1031 dev_dbg(dd->dev, "update done: err: %d\n", err);
8628e7c8 1032 /* finish curent request */
3e133c8b 1033 omap_sham_finish_req(req, err);
8628e7c8 1034 /* start new request */
a5d87237 1035 omap_sham_handle_queue(dd, NULL);
8628e7c8
DK		 1036 }
1037}
1038
1039static void omap_sham_queue_task(unsigned long data)
1040{
1041 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1042
a5d87237 1043 omap_sham_handle_queue(dd, NULL);
8628e7c8
DK		 1044}
1045
1046static irqreturn_t omap_sham_irq(int irq, void *dev_id)
1047{
1048 struct omap_sham_dev *dd = dev_id;
1049 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
1050
1051 if (!ctx) {
1052 dev_err(dd->dev, "unknown interrupt.\n");
1053 return IRQ_HANDLED;
1054 }
1055
1056 if (unlikely(ctx->flags & FLAGS_FINAL))
1057 /* final -> allow device to go to power-saving mode */
1058 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1059
1060 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1061 SHA_REG_CTRL_OUTPUT_READY);
1062 omap_sham_read(dd, SHA_REG_CTRL);
1063
1064 ctx->flags |= FLAGS_OUTPUT_READY;
3e133c8b 1065 dd->err = 0;
8628e7c8
DK		 1066 tasklet_schedule(&dd->done_task);
1067
1068 return IRQ_HANDLED;
1069}
1070
1071static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
1072{
1073 struct omap_sham_dev *dd = data;
1074
3e133c8b
DK		 1075 if (ch_status != OMAP_DMA_BLOCK_IRQ) {
1076 pr_err("omap-sham DMA error status: 0x%hx\n", ch_status);
1077 dd->err = -EIO;
1078 dd->flags &= ~FLAGS_INIT; /* request to re-initialize */
1079 }
1080
1081 tasklet_schedule(&dd->done_task);
8628e7c8
DK		 1082}
1083
1084static int omap_sham_dma_init(struct omap_sham_dev *dd)
1085{
1086 int err;
1087
1088 dd->dma_lch = -1;
1089
1090 err = omap_request_dma(dd->dma, dev_name(dd->dev),
1091 omap_sham_dma_callback, dd, &dd->dma_lch);
1092 if (err) {
1093 dev_err(dd->dev, "Unable to request DMA channel\n");
1094 return err;
1095 }
584db6a1 1096
8628e7c8
DK		 1097 return 0;
1098}
1099
1100static void omap_sham_dma_cleanup(struct omap_sham_dev *dd)
1101{
1102 if (dd->dma_lch >= 0) {
1103 omap_free_dma(dd->dma_lch);
1104 dd->dma_lch = -1;
1105 }
1106}
1107
1108static int __devinit omap_sham_probe(struct platform_device *pdev)
1109{
1110 struct omap_sham_dev *dd;
1111 struct device *dev = &pdev->dev;
1112 struct resource *res;
1113 int err, i, j;
1114
1115 dd = kzalloc(sizeof(struct omap_sham_dev), GFP_KERNEL);
1116 if (dd == NULL) {
1117 dev_err(dev, "unable to alloc data struct.\n");
1118 err = -ENOMEM;
1119 goto data_err;
1120 }
1121 dd->dev = dev;
1122 platform_set_drvdata(pdev, dd);
1123
1124 INIT_LIST_HEAD(&dd->list);
1125 spin_lock_init(&dd->lock);
1126 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1127 tasklet_init(&dd->queue_task, omap_sham_queue_task, (unsigned long)dd);
1128 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1129
1130 dd->irq = -1;
1131
1132 /* Get the base address */
1133 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1134 if (!res) {
1135 dev_err(dev, "no MEM resource info\n");
1136 err = -ENODEV;
1137 goto res_err;
1138 }
1139 dd->phys_base = res->start;
1140
1141 /* Get the DMA */
1142 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1143 if (!res) {
1144 dev_err(dev, "no DMA resource info\n");
1145 err = -ENODEV;
1146 goto res_err;
1147 }
1148 dd->dma = res->start;
1149
1150 /* Get the IRQ */
1151 dd->irq = platform_get_irq(pdev, 0);
1152 if (dd->irq < 0) {
1153 dev_err(dev, "no IRQ resource info\n");
1154 err = dd->irq;
1155 goto res_err;
1156 }
1157
1158 err = request_irq(dd->irq, omap_sham_irq,
1159 IRQF_TRIGGER_LOW, dev_name(dev), dd);
1160 if (err) {
1161 dev_err(dev, "unable to request irq.\n");
1162 goto res_err;
1163 }
1164
1165 err = omap_sham_dma_init(dd);
1166 if (err)
1167 goto dma_err;
1168
1169 /* Initializing the clock */
1170 dd->iclk = clk_get(dev, "ick");
1171 if (!dd->iclk) {
1172 dev_err(dev, "clock intialization failed.\n");
1173 err = -ENODEV;
1174 goto clk_err;
1175 }
1176
1177 dd->io_base = ioremap(dd->phys_base, SZ_4K);
1178 if (!dd->io_base) {
1179 dev_err(dev, "can't ioremap\n");
1180 err = -ENOMEM;
1181 goto io_err;
1182 }
1183
1184 clk_enable(dd->iclk);
1185 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1186 (omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MAJOR) >> 4,
1187 omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MINOR);
1188 clk_disable(dd->iclk);
1189
1190 spin_lock(&sham.lock);
1191 list_add_tail(&dd->list, &sham.dev_list);
1192 spin_unlock(&sham.lock);
1193
1194 for (i = 0; i < ARRAY_SIZE(algs); i++) {
1195 err = crypto_register_ahash(&algs[i]);
1196 if (err)
1197 goto err_algs;
1198 }
1199
1200 return 0;
1201
1202err_algs:
1203 for (j = 0; j < i; j++)
1204 crypto_unregister_ahash(&algs[j]);
1205 iounmap(dd->io_base);
1206io_err:
1207 clk_put(dd->iclk);
1208clk_err:
1209 omap_sham_dma_cleanup(dd);
1210dma_err:
1211 if (dd->irq >= 0)
1212 free_irq(dd->irq, dd);
1213res_err:
1214 kfree(dd);
1215 dd = NULL;
1216data_err:
1217 dev_err(dev, "initialization failed.\n");
1218
1219 return err;
1220}
1221
1222static int __devexit omap_sham_remove(struct platform_device *pdev)
1223{
1224 static struct omap_sham_dev *dd;
1225 int i;
1226
1227 dd = platform_get_drvdata(pdev);
1228 if (!dd)
1229 return -ENODEV;
1230 spin_lock(&sham.lock);
1231 list_del(&dd->list);
1232 spin_unlock(&sham.lock);
1233 for (i = 0; i < ARRAY_SIZE(algs); i++)
1234 crypto_unregister_ahash(&algs[i]);
1235 tasklet_kill(&dd->done_task);
1236 tasklet_kill(&dd->queue_task);
1237 iounmap(dd->io_base);
1238 clk_put(dd->iclk);
1239 omap_sham_dma_cleanup(dd);
1240 if (dd->irq >= 0)
1241 free_irq(dd->irq, dd);
1242 kfree(dd);
1243 dd = NULL;
1244
1245 return 0;
1246}
1247
1248static struct platform_driver omap_sham_driver = {
1249 .probe = omap_sham_probe,
1250 .remove = omap_sham_remove,
1251 .driver = {
1252 .name = "omap-sham",
1253 .owner = THIS_MODULE,
1254 },
1255};
1256
1257static int __init omap_sham_mod_init(void)
1258{
1259 pr_info("loading %s driver\n", "omap-sham");
1260
1261 if (!cpu_class_is_omap2() ||
1262 omap_type() != OMAP2_DEVICE_TYPE_SEC) {
1263 pr_err("Unsupported cpu\n");
1264 return -ENODEV;
1265 }
1266
1267 return platform_driver_register(&omap_sham_driver);
1268}
1269
1270static void __exit omap_sham_mod_exit(void)
1271{
1272 platform_driver_unregister(&omap_sham_driver);
1273}
1274
1275module_init(omap_sham_mod_init);
1276module_exit(omap_sham_mod_exit);
1277
1278MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
1279MODULE_LICENSE("GPL v2");
1280MODULE_AUTHOR("Dmitry Kasatkin");
kernel source for telekom puls (alcatel/mediatek)