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crypto: caam - fix printk recursion for long error texts
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / crypto / caam / caamalg.c
CommitLineData
8e8ec596
KP		 1/*
2 * caam - Freescale FSL CAAM support for crypto API
3 *
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 *
6 * Based on talitos crypto API driver.
7 *
8 * relationship of job descriptors to shared descriptors (SteveC Dec 10 2008):
9 *
10 * --------------- ---------------
11 * | JobDesc #1 |-------------------->| ShareDesc |
12 * | *(packet 1) | | (PDB) |
13 * --------------- |------------->| (hashKey) |
14 * . | | (cipherKey) |
15 * . | |-------->| (operation) |
16 * --------------- | | ---------------
17 * | JobDesc #2 |------| |
18 * | *(packet 2) | |
19 * --------------- |
20 * . |
21 * . |
22 * --------------- |
23 * | JobDesc #3 |------------
24 * | *(packet 3) |
25 * ---------------
26 *
27 * The SharedDesc never changes for a connection unless rekeyed, but
28 * each packet will likely be in a different place. So all we need
29 * to know to process the packet is where the input is, where the
30 * output goes, and what context we want to process with. Context is
31 * in the SharedDesc, packet references in the JobDesc.
32 *
33 * So, a job desc looks like:
34 *
35 * ---------------------
36 * | Header |
37 * | ShareDesc Pointer |
38 * | SEQ_OUT_PTR |
39 * | (output buffer) |
40 * | SEQ_IN_PTR |
41 * | (input buffer) |
42 * | LOAD (to DECO) |
43 * ---------------------
44 */
45
46#include "compat.h"
47
48#include "regs.h"
49#include "intern.h"
50#include "desc_constr.h"
51#include "jr.h"
52#include "error.h"
53
54/*
55 * crypto alg
56 */
57#define CAAM_CRA_PRIORITY 3000
58/* max key is sum of AES_MAX_KEY_SIZE, max split key size */
59#define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + \
60 SHA512_DIGEST_SIZE * 2)
61/* max IV is max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
62#define CAAM_MAX_IV_LENGTH 16
63
64#ifdef DEBUG
65/* for print_hex_dumps with line references */
66#define xstr(s) str(s)
67#define str(s) #s
68#define debug(format, arg...) printk(format, arg)
69#else
70#define debug(format, arg...)
71#endif
72
73/*
74 * per-session context
75 */
76struct caam_ctx {
77 struct device *jrdev;
78 u32 *sh_desc;
79 dma_addr_t shared_desc_phys;
80 u32 class1_alg_type;
81 u32 class2_alg_type;
82 u32 alg_op;
83 u8 *key;
84 dma_addr_t key_phys;
8e8ec596
KP		 85 unsigned int enckeylen;
86 unsigned int authkeylen;
87 unsigned int split_key_len;
88 unsigned int split_key_pad_len;
89 unsigned int authsize;
90};
91
92static int aead_authenc_setauthsize(struct crypto_aead *authenc,
93 unsigned int authsize)
94{
95 struct caam_ctx *ctx = crypto_aead_ctx(authenc);
96
97 ctx->authsize = authsize;
98
99 return 0;
100}
101
102struct split_key_result {
103 struct completion completion;
104 int err;
105};
106
107static void split_key_done(struct device *dev, u32 *desc, u32 err,
108 void *context)
109{
110 struct split_key_result *res = context;
111
112#ifdef DEBUG
113 dev_err(dev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
114#endif
115 if (err) {
de2954d6 116 char tmp[CAAM_ERROR_STR_MAX];
8e8ec596
KP		 117
118 dev_err(dev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
119 }
120
121 res->err = err;
122
123 complete(&res->completion);
124}
125
126/*
127get a split ipad/opad key
128
129Split key generation-----------------------------------------------
130
131[00] 0xb0810008 jobdesc: stidx=1 share=never len=8
132[01] 0x04000014 key: class2->keyreg len=20
133 @0xffe01000
134[03] 0x84410014 operation: cls2-op sha1 hmac init dec
135[04] 0x24940000 fifold: class2 msgdata-last2 len=0 imm
136[05] 0xa4000001 jump: class2 local all ->1 [06]
137[06] 0x64260028 fifostr: class2 mdsplit-jdk len=40
138 @0xffe04000
139*/
140static u32 gen_split_key(struct caam_ctx *ctx, const u8 *key_in, u32 authkeylen)
141{
142 struct device *jrdev = ctx->jrdev;
143 u32 *desc;
144 struct split_key_result result;
145 dma_addr_t dma_addr_in, dma_addr_out;
146 int ret = 0;
147
148 desc = kmalloc(CAAM_CMD_SZ * 6 + CAAM_PTR_SZ * 2, GFP_KERNEL | GFP_DMA);
149
150 init_job_desc(desc, 0);
151
152 dma_addr_in = dma_map_single(jrdev, (void *)key_in, authkeylen,
153 DMA_TO_DEVICE);
154 if (dma_mapping_error(jrdev, dma_addr_in)) {
155 dev_err(jrdev, "unable to map key input memory\n");
156 kfree(desc);
157 return -ENOMEM;
158 }
159 append_key(desc, dma_addr_in, authkeylen, CLASS_2 |
160 KEY_DEST_CLASS_REG);
161
162 /* Sets MDHA up into an HMAC-INIT */
163 append_operation(desc, ctx->alg_op | OP_ALG_DECRYPT |
164 OP_ALG_AS_INIT);
165
166 /*
167 * do a FIFO_LOAD of zero, this will trigger the internal key expansion
168 into both pads inside MDHA
169 */
170 append_fifo_load_as_imm(desc, NULL, 0, LDST_CLASS_2_CCB |
171 FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST2);
172
173 /*
174 * FIFO_STORE with the explicit split-key content store
175 * (0x26 output type)
176 */
177 dma_addr_out = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len,
178 DMA_FROM_DEVICE);
179 if (dma_mapping_error(jrdev, dma_addr_out)) {
180 dev_err(jrdev, "unable to map key output memory\n");
181 kfree(desc);
182 return -ENOMEM;
183 }
184 append_fifo_store(desc, dma_addr_out, ctx->split_key_len,
185 LDST_CLASS_2_CCB | FIFOST_TYPE_SPLIT_KEK);
186
187#ifdef DEBUG
188 print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ",
189 DUMP_PREFIX_ADDRESS, 16, 4, key_in, authkeylen, 1);
190 print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
191 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
192#endif
193
194 result.err = 0;
195 init_completion(&result.completion);
196
197 ret = caam_jr_enqueue(jrdev, desc, split_key_done, &result);
198 if (!ret) {
199 /* in progress */
200 wait_for_completion_interruptible(&result.completion);
201 ret = result.err;
202#ifdef DEBUG
203 print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ",
204 DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
205 ctx->split_key_pad_len, 1);
206#endif
207 }
208
209 dma_unmap_single(jrdev, dma_addr_out, ctx->split_key_pad_len,
210 DMA_FROM_DEVICE);
211 dma_unmap_single(jrdev, dma_addr_in, authkeylen, DMA_TO_DEVICE);
212
213 kfree(desc);
214
215 return ret;
216}
217
218static int build_sh_desc_ipsec(struct caam_ctx *ctx)
219{
220 struct device *jrdev = ctx->jrdev;
221 u32 *sh_desc;
222 u32 *jump_cmd;
223
224 /* build shared descriptor for this session */
225 sh_desc = kmalloc(CAAM_CMD_SZ * 4 + ctx->split_key_pad_len +
226 ctx->enckeylen, GFP_DMA | GFP_KERNEL);
227 if (!sh_desc) {
228 dev_err(jrdev, "could not allocate shared descriptor\n");
229 return -ENOMEM;
230 }
231
232 init_sh_desc(sh_desc, HDR_SAVECTX | HDR_SHARE_SERIAL);
233
234 jump_cmd = append_jump(sh_desc, CLASS_BOTH | JUMP_TEST_ALL |
235 JUMP_COND_SHRD | JUMP_COND_SELF);
236
237 /* process keys, starting with class 2/authentication */
238 append_key_as_imm(sh_desc, ctx->key, ctx->split_key_pad_len,
239 ctx->split_key_len,
240 CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC);
241
242 append_key_as_imm(sh_desc, (void *)ctx->key + ctx->split_key_pad_len,
243 ctx->enckeylen, ctx->enckeylen,
244 CLASS_1 | KEY_DEST_CLASS_REG);
245
246 /* update jump cmd now that we are at the jump target */
247 set_jump_tgt_here(sh_desc, jump_cmd);
248
249 ctx->shared_desc_phys = dma_map_single(jrdev, sh_desc,
250 desc_bytes(sh_desc),
251 DMA_TO_DEVICE);
252 if (dma_mapping_error(jrdev, ctx->shared_desc_phys)) {
253 dev_err(jrdev, "unable to map shared descriptor\n");
254 kfree(sh_desc);
255 return -ENOMEM;
256 }
257
258 ctx->sh_desc = sh_desc;
259
260 return 0;
261}
262
263static int aead_authenc_setkey(struct crypto_aead *aead,
264 const u8 *key, unsigned int keylen)
265{
266 /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
267 static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
268 struct caam_ctx *ctx = crypto_aead_ctx(aead);
269 struct device *jrdev = ctx->jrdev;
270 struct rtattr *rta = (void *)key;
271 struct crypto_authenc_key_param *param;
272 unsigned int authkeylen;
273 unsigned int enckeylen;
274 int ret = 0;
275
276 param = RTA_DATA(rta);
277 enckeylen = be32_to_cpu(param->enckeylen);
278
279 key += RTA_ALIGN(rta->rta_len);
280 keylen -= RTA_ALIGN(rta->rta_len);
281
282 if (keylen < enckeylen)
283 goto badkey;
284
285 authkeylen = keylen - enckeylen;
286
287 if (keylen > CAAM_MAX_KEY_SIZE)
288 goto badkey;
289
290 /* Pick class 2 key length from algorithm submask */
291 ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
292 OP_ALG_ALGSEL_SHIFT] * 2;
293 ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16);
294
295#ifdef DEBUG
296 printk(KERN_ERR "keylen %d enckeylen %d authkeylen %d\n",
297 keylen, enckeylen, authkeylen);
298 printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
299 ctx->split_key_len, ctx->split_key_pad_len);
300 print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ",
301 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
302#endif
303 ctx->key = kmalloc(ctx->split_key_pad_len + enckeylen,
304 GFP_KERNEL | GFP_DMA);
305 if (!ctx->key) {
306 dev_err(jrdev, "could not allocate key output memory\n");
307 return -ENOMEM;
308 }
309
310 ret = gen_split_key(ctx, key, authkeylen);
311 if (ret) {
312 kfree(ctx->key);
313 goto badkey;
314 }
315
316 /* postpend encryption key to auth split key */
317 memcpy(ctx->key + ctx->split_key_pad_len, key + authkeylen, enckeylen);
318
319 ctx->key_phys = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len +
320 enckeylen, DMA_TO_DEVICE);
321 if (dma_mapping_error(jrdev, ctx->key_phys)) {
322 dev_err(jrdev, "unable to map key i/o memory\n");
323 kfree(ctx->key);
324 return -ENOMEM;
325 }
326#ifdef DEBUG
327 print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ",
328 DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
329 ctx->split_key_pad_len + enckeylen, 1);
330#endif
331
8e8ec596
KP		 332 ctx->enckeylen = enckeylen;
333 ctx->authkeylen = authkeylen;
334
335 ret = build_sh_desc_ipsec(ctx);
336 if (ret) {
337 dma_unmap_single(jrdev, ctx->key_phys, ctx->split_key_pad_len +
338 enckeylen, DMA_TO_DEVICE);
339 kfree(ctx->key);
340 }
341
342 return ret;
343badkey:
344 crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
345 return -EINVAL;
346}
347
348struct link_tbl_entry {
349 u64 ptr;
350 u32 len;
351 u8 reserved;
352 u8 buf_pool_id;
353 u16 offset;
354};
355
356/*
357 * ipsec_esp_edesc - s/w-extended ipsec_esp descriptor
358 * @src_nents: number of segments in input scatterlist
359 * @dst_nents: number of segments in output scatterlist
360 * @assoc_nents: number of segments in associated data (SPI+Seq) scatterlist
361 * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE)
362 * @link_tbl_bytes: length of dma mapped link_tbl space
363 * @link_tbl_dma: bus physical mapped address of h/w link table
364 * @hw_desc: the h/w job descriptor followed by any referenced link tables
365 */
366struct ipsec_esp_edesc {
367 int assoc_nents;
368 int src_nents;
369 int dst_nents;
370 int link_tbl_bytes;
371 dma_addr_t link_tbl_dma;
372 struct link_tbl_entry *link_tbl;
373 u32 hw_desc[0];
374};
375
376static void ipsec_esp_unmap(struct device *dev,
377 struct ipsec_esp_edesc *edesc,
378 struct aead_request *areq)
379{
380 dma_unmap_sg(dev, areq->assoc, edesc->assoc_nents, DMA_TO_DEVICE);
381
382 if (unlikely(areq->dst != areq->src)) {
383 dma_unmap_sg(dev, areq->src, edesc->src_nents,
384 DMA_TO_DEVICE);
385 dma_unmap_sg(dev, areq->dst, edesc->dst_nents,
386 DMA_FROM_DEVICE);
387 } else {
388 dma_unmap_sg(dev, areq->src, edesc->src_nents,
389 DMA_BIDIRECTIONAL);
390 }
391
392 if (edesc->link_tbl_bytes)
393 dma_unmap_single(dev, edesc->link_tbl_dma,
394 edesc->link_tbl_bytes,
395 DMA_TO_DEVICE);
396}
397
398/*
399 * ipsec_esp descriptor callbacks
400 */
401static void ipsec_esp_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
402 void *context)
403{
404 struct aead_request *areq = context;
405 struct ipsec_esp_edesc *edesc;
406#ifdef DEBUG
407 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
408 int ivsize = crypto_aead_ivsize(aead);
409 struct caam_ctx *ctx = crypto_aead_ctx(aead);
410
411 dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
412#endif
413 edesc = (struct ipsec_esp_edesc *)((char *)desc -
414 offsetof(struct ipsec_esp_edesc, hw_desc));
415
416 if (err) {
de2954d6 417 char tmp[CAAM_ERROR_STR_MAX];
8e8ec596 418
8e8ec596
KP		 419 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
420 }
421
422 ipsec_esp_unmap(jrdev, edesc, areq);
423
424#ifdef DEBUG
425 print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ",
426 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->assoc),
427 areq->assoclen , 1);
428 print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ",
429 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src) - ivsize,
430 edesc->src_nents ? 100 : ivsize, 1);
431 print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ",
432 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src),
433 edesc->src_nents ? 100 : areq->cryptlen +
434 ctx->authsize + 4, 1);
435#endif
436
437 kfree(edesc);
438
439 aead_request_complete(areq, err);
440}
441
442static void ipsec_esp_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
443 void *context)
444{
445 struct aead_request *areq = context;
446 struct ipsec_esp_edesc *edesc;
447#ifdef DEBUG
448 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
449 struct caam_ctx *ctx = crypto_aead_ctx(aead);
450
451 dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
452#endif
453 edesc = (struct ipsec_esp_edesc *)((char *)desc -
454 offsetof(struct ipsec_esp_edesc, hw_desc));
455
456 if (err) {
de2954d6 457 char tmp[CAAM_ERROR_STR_MAX];
8e8ec596
KP		 458
459 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
460 }
461
462 ipsec_esp_unmap(jrdev, edesc, areq);
463
464 /*
465 * verify hw auth check passed else return -EBADMSG
466 */
467 if ((err & JRSTA_CCBERR_ERRID_MASK) == JRSTA_CCBERR_ERRID_ICVCHK)
468 err = -EBADMSG;
469
470#ifdef DEBUG
471 print_hex_dump(KERN_ERR, "iphdrout@"xstr(__LINE__)": ",
472 DUMP_PREFIX_ADDRESS, 16, 4,
473 ((char *)sg_virt(areq->assoc) - sizeof(struct iphdr)),
474 sizeof(struct iphdr) + areq->assoclen +
475 ((areq->cryptlen > 1500) ? 1500 : areq->cryptlen) +
476 ctx->authsize + 36, 1);
477 if (!err && edesc->link_tbl_bytes) {
478 struct scatterlist *sg = sg_last(areq->src, edesc->src_nents);
479 print_hex_dump(KERN_ERR, "sglastout@"xstr(__LINE__)": ",
480 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(sg),
481 sg->length + ctx->authsize + 16, 1);
482 }
483#endif
484 kfree(edesc);
485
486 aead_request_complete(areq, err);
487}
488
489/*
490 * convert scatterlist to h/w link table format
491 * scatterlist must have been previously dma mapped
492 */
493static void sg_to_link_tbl(struct scatterlist *sg, int sg_count,
494 struct link_tbl_entry *link_tbl_ptr, u32 offset)
495{
496 while (sg_count) {
497 link_tbl_ptr->ptr = sg_dma_address(sg);
498 link_tbl_ptr->len = sg_dma_len(sg);
499 link_tbl_ptr->reserved = 0;
500 link_tbl_ptr->buf_pool_id = 0;
501 link_tbl_ptr->offset = offset;
502 link_tbl_ptr++;
503 sg = sg_next(sg);
504 sg_count--;
505 }
506
507 /* set Final bit (marks end of link table) */
508 link_tbl_ptr--;
509 link_tbl_ptr->len |= 0x40000000;
510}
511
512/*
513 * fill in and submit ipsec_esp job descriptor
514 */
515static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
516 u32 encrypt,
517 void (*callback) (struct device *dev, u32 *desc,
518 u32 err, void *context))
519{
520 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
521 struct caam_ctx *ctx = crypto_aead_ctx(aead);
522 struct device *jrdev = ctx->jrdev;
523 u32 *desc = edesc->hw_desc, options;
524 int ret, sg_count, assoc_sg_count;
525 int ivsize = crypto_aead_ivsize(aead);
526 int authsize = ctx->authsize;
527 dma_addr_t ptr, dst_dma, src_dma;
528#ifdef DEBUG
529 u32 *sh_desc = ctx->sh_desc;
530
531 debug("assoclen %d cryptlen %d authsize %d\n",
532 areq->assoclen, areq->cryptlen, authsize);
533 print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ",
534 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->assoc),
535 areq->assoclen , 1);
536 print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ",
537 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src) - ivsize,
538 edesc->src_nents ? 100 : ivsize, 1);
539 print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ",
540 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src),
541 edesc->src_nents ? 100 : areq->cryptlen + authsize, 1);
542 print_hex_dump(KERN_ERR, "shrdesc@"xstr(__LINE__)": ",
543 DUMP_PREFIX_ADDRESS, 16, 4, sh_desc,
544 desc_bytes(sh_desc), 1);
545#endif
546 assoc_sg_count = dma_map_sg(jrdev, areq->assoc, edesc->assoc_nents ?: 1,
547 DMA_TO_DEVICE);
548 if (areq->src == areq->dst)
549 sg_count = dma_map_sg(jrdev, areq->src, edesc->src_nents ? : 1,
550 DMA_BIDIRECTIONAL);
551 else
552 sg_count = dma_map_sg(jrdev, areq->src, edesc->src_nents ? : 1,
553 DMA_TO_DEVICE);
554
555 /* start auth operation */
556 append_operation(desc, ctx->class2_alg_type | OP_ALG_AS_INITFINAL |
557 (encrypt ? : OP_ALG_ICV_ON));
558
559 /* Load FIFO with data for Class 2 CHA */
560 options = FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG;
561 if (!edesc->assoc_nents) {
562 ptr = sg_dma_address(areq->assoc);
563 } else {
564 sg_to_link_tbl(areq->assoc, edesc->assoc_nents,
565 edesc->link_tbl, 0);
566 ptr = edesc->link_tbl_dma;
567 options |= LDST_SGF;
568 }
569 append_fifo_load(desc, ptr, areq->assoclen, options);
570
571 /* copy iv from cipher/class1 input context to class2 infifo */
572 append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO | ivsize);
573
574 /* start class 1 (cipher) operation */
575 append_operation(desc, ctx->class1_alg_type | OP_ALG_AS_INITFINAL |
576 encrypt);
577
578 /* load payload & instruct to class2 to snoop class 1 if encrypting */
579 options = 0;
580 if (!edesc->src_nents) {
581 src_dma = sg_dma_address(areq->src);
582 } else {
583 sg_to_link_tbl(areq->src, edesc->src_nents, edesc->link_tbl +
584 edesc->assoc_nents, 0);
585 src_dma = edesc->link_tbl_dma + edesc->assoc_nents *
586 sizeof(struct link_tbl_entry);
587 options |= LDST_SGF;
588 }
589 append_seq_in_ptr(desc, src_dma, areq->cryptlen + authsize, options);
590 append_seq_fifo_load(desc, areq->cryptlen, FIFOLD_CLASS_BOTH |
591 FIFOLD_TYPE_LASTBOTH |
592 (encrypt ? FIFOLD_TYPE_MSG1OUT2
593 : FIFOLD_TYPE_MSG));
594
595 /* specify destination */
596 if (areq->src == areq->dst) {
597 dst_dma = src_dma;
598 } else {
599 sg_count = dma_map_sg(jrdev, areq->dst, edesc->dst_nents ? : 1,
600 DMA_FROM_DEVICE);
601 if (!edesc->dst_nents) {
602 dst_dma = sg_dma_address(areq->dst);
603 options = 0;
604 } else {
605 sg_to_link_tbl(areq->dst, edesc->dst_nents,
606 edesc->link_tbl + edesc->assoc_nents +
607 edesc->src_nents, 0);
608 dst_dma = edesc->link_tbl_dma + (edesc->assoc_nents +
609 edesc->src_nents) *
610 sizeof(struct link_tbl_entry);
611 options = LDST_SGF;
612 }
613 }
614 append_seq_out_ptr(desc, dst_dma, areq->cryptlen + authsize, options);
615 append_seq_fifo_store(desc, areq->cryptlen, FIFOST_TYPE_MESSAGE_DATA);
616
617 /* ICV */
618 if (encrypt)
619 append_seq_store(desc, authsize, LDST_CLASS_2_CCB |
620 LDST_SRCDST_BYTE_CONTEXT);
621 else
622 append_seq_fifo_load(desc, authsize, FIFOLD_CLASS_CLASS2 |
623 FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
624
625#ifdef DEBUG
626 debug("job_desc_len %d\n", desc_len(desc));
627 print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
628 DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc) , 1);
629 print_hex_dump(KERN_ERR, "jdlinkt@"xstr(__LINE__)": ",
630 DUMP_PREFIX_ADDRESS, 16, 4, edesc->link_tbl,
631 edesc->link_tbl_bytes, 1);
632#endif
633
634 ret = caam_jr_enqueue(jrdev, desc, callback, areq);
635 if (!ret)
636 ret = -EINPROGRESS;
637 else {
638 ipsec_esp_unmap(jrdev, edesc, areq);
639 kfree(edesc);
640 }
641
642 return ret;
643}
644
645/*
646 * derive number of elements in scatterlist
647 */
648static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
649{
650 struct scatterlist *sg = sg_list;
651 int sg_nents = 0;
652
653 *chained = 0;
654 while (nbytes > 0) {
655 sg_nents++;
656 nbytes -= sg->length;
657 if (!sg_is_last(sg) && (sg + 1)->length == 0)
658 *chained = 1;
659 sg = scatterwalk_sg_next(sg);
660 }
661
662 return sg_nents;
663}
664
665/*
666 * allocate and map the ipsec_esp extended descriptor
667 */
668static struct ipsec_esp_edesc *ipsec_esp_edesc_alloc(struct aead_request *areq,
669 int desc_bytes)
670{
671 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
672 struct caam_ctx *ctx = crypto_aead_ctx(aead);
673 struct device *jrdev = ctx->jrdev;
674 gfp_t flags = areq->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
675 GFP_ATOMIC;
676 int assoc_nents, src_nents, dst_nents = 0, chained, link_tbl_bytes;
677 struct ipsec_esp_edesc *edesc;
678
679 assoc_nents = sg_count(areq->assoc, areq->assoclen, &chained);
680 BUG_ON(chained);
681 if (likely(assoc_nents == 1))
682 assoc_nents = 0;
683
684 src_nents = sg_count(areq->src, areq->cryptlen + ctx->authsize,
685 &chained);
686 BUG_ON(chained);
687 if (src_nents == 1)
688 src_nents = 0;
689
690 if (unlikely(areq->dst != areq->src)) {
691 dst_nents = sg_count(areq->dst, areq->cryptlen + ctx->authsize,
692 &chained);
693 BUG_ON(chained);
694 if (dst_nents == 1)
695 dst_nents = 0;
696 }
697
698 link_tbl_bytes = (assoc_nents + src_nents + dst_nents) *
699 sizeof(struct link_tbl_entry);
700 debug("link_tbl_bytes %d\n", link_tbl_bytes);
701
702 /* allocate space for base edesc and hw desc commands, link tables */
703 edesc = kmalloc(sizeof(struct ipsec_esp_edesc) + desc_bytes +
704 link_tbl_bytes, GFP_DMA | flags);
705 if (!edesc) {
706 dev_err(jrdev, "could not allocate extended descriptor\n");
707 return ERR_PTR(-ENOMEM);
708 }
709
710 edesc->assoc_nents = assoc_nents;
711 edesc->src_nents = src_nents;
712 edesc->dst_nents = dst_nents;
713 edesc->link_tbl = (void *)edesc + sizeof(struct ipsec_esp_edesc) +
714 desc_bytes;
715 edesc->link_tbl_dma = dma_map_single(jrdev, edesc->link_tbl,
716 link_tbl_bytes, DMA_TO_DEVICE);
717 edesc->link_tbl_bytes = link_tbl_bytes;
718
719 return edesc;
720}
721
722static int aead_authenc_encrypt(struct aead_request *areq)
723{
724 struct ipsec_esp_edesc *edesc;
725 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
726 struct caam_ctx *ctx = crypto_aead_ctx(aead);
727 struct device *jrdev = ctx->jrdev;
728 int ivsize = crypto_aead_ivsize(aead);
729 u32 *desc;
730 dma_addr_t iv_dma;
731
732 /* allocate extended descriptor */
733 edesc = ipsec_esp_edesc_alloc(areq, 21 * sizeof(u32));
734 if (IS_ERR(edesc))
735 return PTR_ERR(edesc);
736
737 desc = edesc->hw_desc;
738
739 /* insert shared descriptor pointer */
740 init_job_desc_shared(desc, ctx->shared_desc_phys,
741 desc_len(ctx->sh_desc), HDR_SHARE_DEFER);
742
743 iv_dma = dma_map_single(jrdev, areq->iv, ivsize, DMA_TO_DEVICE);
744 /* check dma error */
745
746 append_load(desc, iv_dma, ivsize,
747 LDST_CLASS_1_CCB | LDST_SRCDST_BYTE_CONTEXT);
748
749 return ipsec_esp(edesc, areq, OP_ALG_ENCRYPT, ipsec_esp_encrypt_done);
750}
751
752static int aead_authenc_decrypt(struct aead_request *req)
753{
754 struct crypto_aead *aead = crypto_aead_reqtfm(req);
755 int ivsize = crypto_aead_ivsize(aead);
756 struct caam_ctx *ctx = crypto_aead_ctx(aead);
757 struct device *jrdev = ctx->jrdev;
758 struct ipsec_esp_edesc *edesc;
759 u32 *desc;
760 dma_addr_t iv_dma;
761
762 req->cryptlen -= ctx->authsize;
763
764 /* allocate extended descriptor */
765 edesc = ipsec_esp_edesc_alloc(req, 21 * sizeof(u32));
766 if (IS_ERR(edesc))
767 return PTR_ERR(edesc);
768
769 desc = edesc->hw_desc;
770
771 /* insert shared descriptor pointer */
772 init_job_desc_shared(desc, ctx->shared_desc_phys,
773 desc_len(ctx->sh_desc), HDR_SHARE_DEFER);
774
775 iv_dma = dma_map_single(jrdev, req->iv, ivsize, DMA_TO_DEVICE);
776 /* check dma error */
777
778 append_load(desc, iv_dma, ivsize,
779 LDST_CLASS_1_CCB | LDST_SRCDST_BYTE_CONTEXT);
780
781 return ipsec_esp(edesc, req, !OP_ALG_ENCRYPT, ipsec_esp_decrypt_done);
782}
783
784static int aead_authenc_givencrypt(struct aead_givcrypt_request *req)
785{
786 struct aead_request *areq = &req->areq;
787 struct ipsec_esp_edesc *edesc;
788 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
789 struct caam_ctx *ctx = crypto_aead_ctx(aead);
790 struct device *jrdev = ctx->jrdev;
791 int ivsize = crypto_aead_ivsize(aead);
792 dma_addr_t iv_dma;
793 u32 *desc;
794
795 iv_dma = dma_map_single(jrdev, req->giv, ivsize, DMA_FROM_DEVICE);
796
797 debug("%s: giv %p\n", __func__, req->giv);
798
799 /* allocate extended descriptor */
800 edesc = ipsec_esp_edesc_alloc(areq, 27 * sizeof(u32));
801 if (IS_ERR(edesc))
802 return PTR_ERR(edesc);
803
804 desc = edesc->hw_desc;
805
806 /* insert shared descriptor pointer */
807 init_job_desc_shared(desc, ctx->shared_desc_phys,
808 desc_len(ctx->sh_desc), HDR_SHARE_DEFER);
809
810 /*
811 * LOAD IMM Info FIFO
812 * to DECO, Last, Padding, Random, Message, 16 bytes
813 */
814 append_load_imm_u32(desc, NFIFOENTRY_DEST_DECO | NFIFOENTRY_LC1 |
815 NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DTYPE_MSG |
816 NFIFOENTRY_PTYPE_RND | ivsize,
817 LDST_SRCDST_WORD_INFO_FIFO);
818
819 /*
820 * disable info fifo entries since the above serves as the entry
821 * this way, the MOVE command won't generate an entry.
822 * Note that this isn't required in more recent versions of
823 * SEC as a MOVE that doesn't do info FIFO entries is available.
824 */
825 append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
826
827 /* MOVE DECO Alignment -> C1 Context 16 bytes */
d37d36e3 828 append_move(desc, MOVE_SRC_INFIFO | MOVE_DEST_CLASS1CTX | ivsize);
8e8ec596
KP		 829
830 /* re-enable info fifo entries */
831 append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
832
833 /* MOVE C1 Context -> OFIFO 16 bytes */
d37d36e3 834 append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_OUTFIFO | ivsize);
8e8ec596
KP		 835
836 append_fifo_store(desc, iv_dma, ivsize, FIFOST_TYPE_MESSAGE_DATA);
837
838 return ipsec_esp(edesc, areq, OP_ALG_ENCRYPT, ipsec_esp_encrypt_done);
839}
840
841struct caam_alg_template {
842 char name[CRYPTO_MAX_ALG_NAME];
843 char driver_name[CRYPTO_MAX_ALG_NAME];
844 unsigned int blocksize;
845 struct aead_alg aead;
846 u32 class1_alg_type;
847 u32 class2_alg_type;
848 u32 alg_op;
849};
850
851static struct caam_alg_template driver_algs[] = {
852 /* single-pass ipsec_esp descriptor */
853 {
854 .name = "authenc(hmac(sha1),cbc(aes))",
855 .driver_name = "authenc-hmac-sha1-cbc-aes-caam",
856 .blocksize = AES_BLOCK_SIZE,
857 .aead = {
858 .setkey = aead_authenc_setkey,
859 .setauthsize = aead_authenc_setauthsize,
860 .encrypt = aead_authenc_encrypt,
861 .decrypt = aead_authenc_decrypt,
862 .givencrypt = aead_authenc_givencrypt,
863 .geniv = "<built-in>",
864 .ivsize = AES_BLOCK_SIZE,
865 .maxauthsize = SHA1_DIGEST_SIZE,
866 },
867 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
868 .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
869 .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
870 },
871 {
872 .name = "authenc(hmac(sha256),cbc(aes))",
873 .driver_name = "authenc-hmac-sha256-cbc-aes-caam",
874 .blocksize = AES_BLOCK_SIZE,
875 .aead = {
876 .setkey = aead_authenc_setkey,
877 .setauthsize = aead_authenc_setauthsize,
878 .encrypt = aead_authenc_encrypt,
879 .decrypt = aead_authenc_decrypt,
880 .givencrypt = aead_authenc_givencrypt,
881 .geniv = "<built-in>",
882 .ivsize = AES_BLOCK_SIZE,
883 .maxauthsize = SHA256_DIGEST_SIZE,
884 },
885 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
886 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
887 OP_ALG_AAI_HMAC_PRECOMP,
888 .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
889 },
890 {
891 .name = "authenc(hmac(sha1),cbc(des3_ede))",
892 .driver_name = "authenc-hmac-sha1-cbc-des3_ede-caam",
893 .blocksize = DES3_EDE_BLOCK_SIZE,
894 .aead = {
895 .setkey = aead_authenc_setkey,
896 .setauthsize = aead_authenc_setauthsize,
897 .encrypt = aead_authenc_encrypt,
898 .decrypt = aead_authenc_decrypt,
899 .givencrypt = aead_authenc_givencrypt,
900 .geniv = "<built-in>",
901 .ivsize = DES3_EDE_BLOCK_SIZE,
902 .maxauthsize = SHA1_DIGEST_SIZE,
903 },
904 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
905 .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
906 .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
907 },
908 {
909 .name = "authenc(hmac(sha256),cbc(des3_ede))",
910 .driver_name = "authenc-hmac-sha256-cbc-des3_ede-caam",
911 .blocksize = DES3_EDE_BLOCK_SIZE,
912 .aead = {
913 .setkey = aead_authenc_setkey,
914 .setauthsize = aead_authenc_setauthsize,
915 .encrypt = aead_authenc_encrypt,
916 .decrypt = aead_authenc_decrypt,
917 .givencrypt = aead_authenc_givencrypt,
918 .geniv = "<built-in>",
919 .ivsize = DES3_EDE_BLOCK_SIZE,
920 .maxauthsize = SHA256_DIGEST_SIZE,
921 },
922 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
923 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
924 OP_ALG_AAI_HMAC_PRECOMP,
925 .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
926 },
927 {
928 .name = "authenc(hmac(sha1),cbc(des))",
929 .driver_name = "authenc-hmac-sha1-cbc-des-caam",
930 .blocksize = DES_BLOCK_SIZE,
931 .aead = {
932 .setkey = aead_authenc_setkey,
933 .setauthsize = aead_authenc_setauthsize,
934 .encrypt = aead_authenc_encrypt,
935 .decrypt = aead_authenc_decrypt,
936 .givencrypt = aead_authenc_givencrypt,
937 .geniv = "<built-in>",
938 .ivsize = DES_BLOCK_SIZE,
939 .maxauthsize = SHA1_DIGEST_SIZE,
940 },
941 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
942 .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
943 .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
944 },
945 {
946 .name = "authenc(hmac(sha256),cbc(des))",
947 .driver_name = "authenc-hmac-sha256-cbc-des-caam",
948 .blocksize = DES_BLOCK_SIZE,
949 .aead = {
950 .setkey = aead_authenc_setkey,
951 .setauthsize = aead_authenc_setauthsize,
952 .encrypt = aead_authenc_encrypt,
953 .decrypt = aead_authenc_decrypt,
954 .givencrypt = aead_authenc_givencrypt,
955 .geniv = "<built-in>",
956 .ivsize = DES_BLOCK_SIZE,
957 .maxauthsize = SHA256_DIGEST_SIZE,
958 },
959 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
960 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
961 OP_ALG_AAI_HMAC_PRECOMP,
962 .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
963 },
964};
965
966struct caam_crypto_alg {
967 struct list_head entry;
968 struct device *ctrldev;
969 int class1_alg_type;
970 int class2_alg_type;
971 int alg_op;
972 struct crypto_alg crypto_alg;
973};
974
975static int caam_cra_init(struct crypto_tfm *tfm)
976{
977 struct crypto_alg *alg = tfm->__crt_alg;
978 struct caam_crypto_alg *caam_alg =
979 container_of(alg, struct caam_crypto_alg, crypto_alg);
980 struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
981 struct caam_drv_private *priv = dev_get_drvdata(caam_alg->ctrldev);
982 int tgt_jr = atomic_inc_return(&priv->tfm_count);
983
984 /*
985 * distribute tfms across job rings to ensure in-order
986 * crypto request processing per tfm
987 */
988 ctx->jrdev = priv->algapi_jr[(tgt_jr / 2) % priv->num_jrs_for_algapi];
989
990 /* copy descriptor header template value */
991 ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam_alg->class1_alg_type;
992 ctx->class2_alg_type = OP_TYPE_CLASS2_ALG | caam_alg->class2_alg_type;
993 ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_alg->alg_op;
994
995 return 0;
996}
997
998static void caam_cra_exit(struct crypto_tfm *tfm)
999{
1000 struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
1001
1002 if (!dma_mapping_error(ctx->jrdev, ctx->shared_desc_phys))
1003 dma_unmap_single(ctx->jrdev, ctx->shared_desc_phys,
1004 desc_bytes(ctx->sh_desc), DMA_TO_DEVICE);
1005 kfree(ctx->sh_desc);
1006}
1007
1008static void __exit caam_algapi_exit(void)
1009{
1010
1011 struct device_node *dev_node;
1012 struct platform_device *pdev;
1013 struct device *ctrldev;
1014 struct caam_drv_private *priv;
1015 struct caam_crypto_alg *t_alg, *n;
1016 int i, err;
1017
54e198d4 1018 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
8e8ec596
KP		 1019 if (!dev_node)
1020 return;
1021
1022 pdev = of_find_device_by_node(dev_node);
1023 if (!pdev)
1024 return;
1025
1026 ctrldev = &pdev->dev;
1027 of_node_put(dev_node);
1028 priv = dev_get_drvdata(ctrldev);
1029
1030 if (!priv->alg_list.next)
1031 return;
1032
1033 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
1034 crypto_unregister_alg(&t_alg->crypto_alg);
1035 list_del(&t_alg->entry);
1036 kfree(t_alg);
1037 }
1038
1039 for (i = 0; i < priv->total_jobrs; i++) {
1040 err = caam_jr_deregister(priv->algapi_jr[i]);
1041 if (err < 0)
1042 break;
1043 }
1044 kfree(priv->algapi_jr);
1045}
1046
1047static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev,
1048 struct caam_alg_template
1049 *template)
1050{
1051 struct caam_crypto_alg *t_alg;
1052 struct crypto_alg *alg;
1053
1054 t_alg = kzalloc(sizeof(struct caam_crypto_alg), GFP_KERNEL);
1055 if (!t_alg) {
1056 dev_err(ctrldev, "failed to allocate t_alg\n");
1057 return ERR_PTR(-ENOMEM);
1058 }
1059
1060 alg = &t_alg->crypto_alg;
1061
1062 snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name);
1063 snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1064 template->driver_name);
1065 alg->cra_module = THIS_MODULE;
1066 alg->cra_init = caam_cra_init;
1067 alg->cra_exit = caam_cra_exit;
1068 alg->cra_priority = CAAM_CRA_PRIORITY;
1069 alg->cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC;
1070 alg->cra_blocksize = template->blocksize;
1071 alg->cra_alignmask = 0;
1072 alg->cra_type = &crypto_aead_type;
1073 alg->cra_ctxsize = sizeof(struct caam_ctx);
1074 alg->cra_u.aead = template->aead;
1075
1076 t_alg->class1_alg_type = template->class1_alg_type;
1077 t_alg->class2_alg_type = template->class2_alg_type;
1078 t_alg->alg_op = template->alg_op;
1079 t_alg->ctrldev = ctrldev;
1080
1081 return t_alg;
1082}
1083
1084static int __init caam_algapi_init(void)
1085{
1086 struct device_node *dev_node;
1087 struct platform_device *pdev;
1088 struct device *ctrldev, **jrdev;
1089 struct caam_drv_private *priv;
1090 int i = 0, err = 0;
1091
54e198d4 1092 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
8e8ec596
KP		 1093 if (!dev_node)
1094 return -ENODEV;
1095
1096 pdev = of_find_device_by_node(dev_node);
1097 if (!pdev)
1098 return -ENODEV;
1099
1100 ctrldev = &pdev->dev;
1101 priv = dev_get_drvdata(ctrldev);
1102 of_node_put(dev_node);
1103
1104 INIT_LIST_HEAD(&priv->alg_list);
1105
1106 jrdev = kmalloc(sizeof(*jrdev) * priv->total_jobrs, GFP_KERNEL);
1107 if (!jrdev)
1108 return -ENOMEM;
1109
1110 for (i = 0; i < priv->total_jobrs; i++) {
1111 err = caam_jr_register(ctrldev, &jrdev[i]);
1112 if (err < 0)
1113 break;
1114 }
1115 if (err < 0 && i == 0) {
1116 dev_err(ctrldev, "algapi error in job ring registration: %d\n",
1117 err);
b3b7f055 1118 kfree(jrdev);
8e8ec596
KP		 1119 return err;
1120 }
1121
1122 priv->num_jrs_for_algapi = i;
1123 priv->algapi_jr = jrdev;
1124 atomic_set(&priv->tfm_count, -1);
1125
1126 /* register crypto algorithms the device supports */
1127 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
1128 /* TODO: check if h/w supports alg */
1129 struct caam_crypto_alg *t_alg;
1130
1131 t_alg = caam_alg_alloc(ctrldev, &driver_algs[i]);
1132 if (IS_ERR(t_alg)) {
1133 err = PTR_ERR(t_alg);
1134 dev_warn(ctrldev, "%s alg allocation failed\n",
cdc712d8 1135 driver_algs[i].driver_name);
8e8ec596
KP		 1136 continue;
1137 }
1138
1139 err = crypto_register_alg(&t_alg->crypto_alg);
1140 if (err) {
1141 dev_warn(ctrldev, "%s alg registration failed\n",
1142 t_alg->crypto_alg.cra_driver_name);
1143 kfree(t_alg);
1144 } else {
1145 list_add_tail(&t_alg->entry, &priv->alg_list);
1146 dev_info(ctrldev, "%s\n",
1147 t_alg->crypto_alg.cra_driver_name);
1148 }
1149 }
1150
1151 return err;
1152}
1153
1154module_init(caam_algapi_init);
1155module_exit(caam_algapi_exit);
1156
1157MODULE_LICENSE("GPL");
1158MODULE_DESCRIPTION("FSL CAAM support for crypto API");
1159MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
kernel source for telekom puls (alcatel/mediatek)