[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / cpufreq / exynos5250-cpufreq.c

/*
 * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS5250 - CPU frequency scaling support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/cpufreq.h>

#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/cpufreq.h>

static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;

static unsigned int exynos5250_volt_table[] = {
	1300000, 1250000, 1225000, 1200000, 1150000,
	1125000, 1100000, 1075000, 1050000, 1025000,
	1012500, 1000000,  975000,  950000,  937500,
	925000
};

static struct cpufreq_frequency_table exynos5250_freq_table[] = {
	{L0, 1700 * 1000},
	{L1, 1600 * 1000},
	{L2, 1500 * 1000},
	{L3, 1400 * 1000},
	{L4, 1300 * 1000},
	{L5, 1200 * 1000},
	{L6, 1100 * 1000},
	{L7, 1000 * 1000},
	{L8,  900 * 1000},
	{L9,  800 * 1000},
	{L10, 700 * 1000},
	{L11, 600 * 1000},
	{L12, 500 * 1000},
	{L13, 400 * 1000},
	{L14, 300 * 1000},
	{L15, 200 * 1000},
	{0, CPUFREQ_TABLE_END},
};

static struct apll_freq apll_freq_5250[] = {
	/*
	 * values:
	 * freq
	 * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2
	 * clock divider for COPY, HPM, RESERVED
	 * PLL M, P, S
	 */
	APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
	APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
	APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
	APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
	APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
	APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
	APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
	APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
	APLL_FREQ(900,  0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
	APLL_FREQ(800,  0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
	APLL_FREQ(700,  0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
	APLL_FREQ(600,  0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
	APLL_FREQ(500,  0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
	APLL_FREQ(400,  0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
	APLL_FREQ(300,  0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
	APLL_FREQ(200,  0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
};

static void set_clkdiv(unsigned int div_index)
{
	unsigned int tmp;

	/* Change Divider - CPU0 */

	tmp = apll_freq_5250[div_index].clk_div_cpu0;

	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);

	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
		cpu_relax();

	/* Change Divider - CPU1 */
	tmp = apll_freq_5250[div_index].clk_div_cpu1;

	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);

	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
		cpu_relax();
}

static void set_apll(unsigned int new_index,
			     unsigned int old_index)
{
	unsigned int tmp, pdiv;

	/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
	clk_set_parent(moutcore, mout_mpll);

	do {
		cpu_relax();
		tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
		tmp &= 0x7;
	} while (tmp != 0x2);

	/* 2. Set APLL Lock time */
	pdiv = ((apll_freq_5250[new_index].mps >> 8) & 0x3f);

	__raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK);

	/* 3. Change PLL PMS values */
	tmp = __raw_readl(EXYNOS5_APLL_CON0);
	tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
	tmp |= apll_freq_5250[new_index].mps;
	__raw_writel(tmp, EXYNOS5_APLL_CON0);

	/* 4. wait_lock_time */
	do {
		cpu_relax();
		tmp = __raw_readl(EXYNOS5_APLL_CON0);
	} while (!(tmp & (0x1 << 29)));

	/* 5. MUX_CORE_SEL = APLL */
	clk_set_parent(moutcore, mout_apll);

	do {
		cpu_relax();
		tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
		tmp &= (0x7 << 16);
	} while (tmp != (0x1 << 16));

}

static bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index)
{
	unsigned int old_pm = apll_freq_5250[old_index].mps >> 8;
	unsigned int new_pm = apll_freq_5250[new_index].mps >> 8;

	return (old_pm == new_pm) ? 0 : 1;
}

static void exynos5250_set_frequency(unsigned int old_index,
				  unsigned int new_index)
{
	unsigned int tmp;

	if (old_index > new_index) {
		if (!exynos5250_pms_change(old_index, new_index)) {
			/* 1. Change the system clock divider values */
			set_clkdiv(new_index);
			/* 2. Change just s value in apll m,p,s value */
			tmp = __raw_readl(EXYNOS5_APLL_CON0);
			tmp &= ~(0x7 << 0);
			tmp |= apll_freq_5250[new_index].mps & 0x7;
			__raw_writel(tmp, EXYNOS5_APLL_CON0);

		} else {
			/* Clock Configuration Procedure */
			/* 1. Change the system clock divider values */
			set_clkdiv(new_index);
			/* 2. Change the apll m,p,s value */
			set_apll(new_index, old_index);
		}
	} else if (old_index < new_index) {
		if (!exynos5250_pms_change(old_index, new_index)) {
			/* 1. Change just s value in apll m,p,s value */
			tmp = __raw_readl(EXYNOS5_APLL_CON0);
			tmp &= ~(0x7 << 0);
			tmp |= apll_freq_5250[new_index].mps & 0x7;
			__raw_writel(tmp, EXYNOS5_APLL_CON0);
			/* 2. Change the system clock divider values */
			set_clkdiv(new_index);
		} else {
			/* Clock Configuration Procedure */
			/* 1. Change the apll m,p,s value */
			set_apll(new_index, old_index);
			/* 2. Change the system clock divider values */
			set_clkdiv(new_index);
		}
	}
}

int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
{
	unsigned long rate;

	cpu_clk = clk_get(NULL, "armclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	moutcore = clk_get(NULL, "mout_cpu");
	if (IS_ERR(moutcore))
		goto err_moutcore;

	mout_mpll = clk_get(NULL, "mout_mpll");
	if (IS_ERR(mout_mpll))
		goto err_mout_mpll;

	rate = clk_get_rate(mout_mpll) / 1000;

	mout_apll = clk_get(NULL, "mout_apll");
	if (IS_ERR(mout_apll))
		goto err_mout_apll;

	info->mpll_freq_khz = rate;
	/* 800Mhz */
	info->pll_safe_idx = L9;
	info->cpu_clk = cpu_clk;
	info->volt_table = exynos5250_volt_table;
	info->freq_table = exynos5250_freq_table;
	info->set_freq = exynos5250_set_frequency;
	info->need_apll_change = exynos5250_pms_change;

	return 0;

err_mout_apll:
	clk_put(mout_mpll);
err_mout_mpll:
	clk_put(moutcore);
err_moutcore:
	clk_put(cpu_clk);

	pr_err("%s: failed initialization\n", __func__);
	return -EINVAL;
}
EXPORT_SYMBOL(exynos5250_cpufreq_init);
Commit	Line	Data
562a6cbe JL	1	/*
	2	* Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* EXYNOS5250 - CPU frequency scaling support
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
	16	#include <linux/io.h>
	17	#include <linux/slab.h>
	18	#include <linux/cpufreq.h>
	19
	20	#include <mach/map.h>
	21	#include <mach/regs-clock.h>
3c2a0909	22	#include <mach/cpufreq.h>
562a6cbe	23
562a6cbe JL	24	static struct clk *cpu_clk;
	25	static struct clk *moutcore;
	26	static struct clk *mout_mpll;
	27	static struct clk *mout_apll;
	28
9d0554ff JC	29	static unsigned int exynos5250_volt_table[] = {
	30	1300000, 1250000, 1225000, 1200000, 1150000,
	31	1125000, 1100000, 1075000, 1050000, 1025000,
	32	1012500, 1000000, 975000, 950000, 937500,
	33	925000
562a6cbe JL	34	};
562a6cbe JL	35
562a6cbe JL	36	static struct cpufreq_frequency_table exynos5250_freq_table[] = {
	37	{L0, 1700 * 1000},
	38	{L1, 1600 * 1000},
	39	{L2, 1500 * 1000},
	40	{L3, 1400 * 1000},
	41	{L4, 1300 * 1000},
	42	{L5, 1200 * 1000},
	43	{L6, 1100 * 1000},
	44	{L7, 1000 * 1000},
9d0554ff JC	45	{L8, 900 * 1000},
9d0554ff JC	46	{L9, 800 * 1000},
562a6cbe JL	47	{L10, 700 * 1000},
	48	{L11, 600 * 1000},
	49	{L12, 500 * 1000},
	50	{L13, 400 * 1000},
	51	{L14, 300 * 1000},
	52	{L15, 200 * 1000},
	53	{0, CPUFREQ_TABLE_END},
	54	};
	55
9d0554ff	56	static struct apll_freq apll_freq_5250[] = {
562a6cbe	57	/*
9d0554ff JC	58	* values:
	59	* freq
	60	* clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2
	61	* clock divider for COPY, HPM, RESERVED
	62	* PLL M, P, S
562a6cbe	63	*/
9d0554ff JC	64	APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
	65	APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
	66	APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
	67	APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
	68	APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
	69	APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
	70	APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
	71	APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
	72	APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
	73	APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
	74	APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
	75	APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
	76	APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
	77	APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
	78	APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
	79	APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
562a6cbe JL	80	};
	81
	82	static void set_clkdiv(unsigned int div_index)
	83	{
	84	unsigned int tmp;
	85
	86	/* Change Divider - CPU0 */
	87
9d0554ff	88	tmp = apll_freq_5250[div_index].clk_div_cpu0;
562a6cbe JL	89
	90	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
	91
	92	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
	93	cpu_relax();
	94
	95	/* Change Divider - CPU1 */
9d0554ff	96	tmp = apll_freq_5250[div_index].clk_div_cpu1;
562a6cbe JL	97
	98	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
	99
	100	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
	101	cpu_relax();
	102	}
	103
	104	static void set_apll(unsigned int new_index,
	105	unsigned int old_index)
	106	{
	107	unsigned int tmp, pdiv;
	108
	109	/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
	110	clk_set_parent(moutcore, mout_mpll);
	111
	112	do {
	113	cpu_relax();
	114	tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
	115	tmp &= 0x7;
	116	} while (tmp != 0x2);
	117
	118	/* 2. Set APLL Lock time */
9d0554ff	119	pdiv = ((apll_freq_5250[new_index].mps >> 8) & 0x3f);
562a6cbe JL	120
	121	__raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK);
	122
	123	/* 3. Change PLL PMS values */
	124	tmp = __raw_readl(EXYNOS5_APLL_CON0);
	125	tmp &= ~((0x3ff << 16) \| (0x3f << 8) \| (0x7 << 0));
9d0554ff	126	tmp \|= apll_freq_5250[new_index].mps;
562a6cbe JL	127	__raw_writel(tmp, EXYNOS5_APLL_CON0);
	128
	129	/* 4. wait_lock_time */
	130	do {
	131	cpu_relax();
	132	tmp = __raw_readl(EXYNOS5_APLL_CON0);
	133	} while (!(tmp & (0x1 << 29)));
	134
	135	/* 5. MUX_CORE_SEL = APLL */
	136	clk_set_parent(moutcore, mout_apll);
	137
	138	do {
	139	cpu_relax();
	140	tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
	141	tmp &= (0x7 << 16);
	142	} while (tmp != (0x1 << 16));
	143
	144	}
	145
94aa4409	146	static bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index)
562a6cbe	147	{
9d0554ff JC	148	unsigned int old_pm = apll_freq_5250[old_index].mps >> 8;
9d0554ff JC	149	unsigned int new_pm = apll_freq_5250[new_index].mps >> 8;
562a6cbe JL	150
	151	return (old_pm == new_pm) ? 0 : 1;
	152	}
	153
	154	static void exynos5250_set_frequency(unsigned int old_index,
	155	unsigned int new_index)
	156	{
	157	unsigned int tmp;
	158
	159	if (old_index > new_index) {
	160	if (!exynos5250_pms_change(old_index, new_index)) {
	161	/* 1. Change the system clock divider values */
	162	set_clkdiv(new_index);
	163	/* 2. Change just s value in apll m,p,s value */
	164	tmp = __raw_readl(EXYNOS5_APLL_CON0);
	165	tmp &= ~(0x7 << 0);
9d0554ff	166	tmp \|= apll_freq_5250[new_index].mps & 0x7;
562a6cbe JL	167	__raw_writel(tmp, EXYNOS5_APLL_CON0);
	168
	169	} else {
	170	/* Clock Configuration Procedure */
	171	/* 1. Change the system clock divider values */
	172	set_clkdiv(new_index);
	173	/* 2. Change the apll m,p,s value */
	174	set_apll(new_index, old_index);
	175	}
	176	} else if (old_index < new_index) {
	177	if (!exynos5250_pms_change(old_index, new_index)) {
	178	/* 1. Change just s value in apll m,p,s value */
	179	tmp = __raw_readl(EXYNOS5_APLL_CON0);
	180	tmp &= ~(0x7 << 0);
9d0554ff	181	tmp \|= apll_freq_5250[new_index].mps & 0x7;
562a6cbe JL	182	__raw_writel(tmp, EXYNOS5_APLL_CON0);
	183	/* 2. Change the system clock divider values */
	184	set_clkdiv(new_index);
	185	} else {
	186	/* Clock Configuration Procedure */
	187	/* 1. Change the apll m,p,s value */
	188	set_apll(new_index, old_index);
	189	/* 2. Change the system clock divider values */
	190	set_clkdiv(new_index);
	191	}
	192	}
	193	}
	194
562a6cbe JL	195	int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
562a6cbe JL	196	{
562a6cbe JL	197	unsigned long rate;
562a6cbe JL	198
562a6cbe JL	199	cpu_clk = clk_get(NULL, "armclk");
	200	if (IS_ERR(cpu_clk))
	201	return PTR_ERR(cpu_clk);
	202
	203	moutcore = clk_get(NULL, "mout_cpu");
	204	if (IS_ERR(moutcore))
	205	goto err_moutcore;
	206
	207	mout_mpll = clk_get(NULL, "mout_mpll");
	208	if (IS_ERR(mout_mpll))
	209	goto err_mout_mpll;
	210
	211	rate = clk_get_rate(mout_mpll) / 1000;
	212
	213	mout_apll = clk_get(NULL, "mout_apll");
	214	if (IS_ERR(mout_apll))
	215	goto err_mout_apll;
	216
562a6cbe	217	info->mpll_freq_khz = rate;
562a6cbe JL	218	/* 800Mhz */
562a6cbe JL	219	info->pll_safe_idx = L9;
562a6cbe JL	220	info->cpu_clk = cpu_clk;
	221	info->volt_table = exynos5250_volt_table;
	222	info->freq_table = exynos5250_freq_table;
	223	info->set_freq = exynos5250_set_frequency;
	224	info->need_apll_change = exynos5250_pms_change;
	225
	226	return 0;
	227
	228	err_mout_apll:
	229	clk_put(mout_mpll);
	230	err_mout_mpll:
	231	clk_put(moutcore);
	232	err_moutcore:
	233	clk_put(cpu_clk);
	234
	235	pr_err("%s: failed initialization\n", __func__);
	236	return -EINVAL;
	237	}
	238	EXPORT_SYMBOL(exynos5250_cpufreq_init);