[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / cpufreq / exynos4210-cpufreq.c

/*
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4 - CPU frequency scaling support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
#include <linux/cpufreq.h>
#include <linux/notifier.h>
#include <linux/suspend.h>

#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/regs-mem.h>

#include <plat/clock.h>
#include <plat/pm.h>

static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;

static struct regulator *arm_regulator;

static struct cpufreq_freqs freqs;

static unsigned int locking_frequency;
static bool frequency_locked;
static DEFINE_MUTEX(cpufreq_lock);

enum cpufreq_level_index {
	L0, L1, L2, L3, L4, CPUFREQ_LEVEL_END,
};

static struct cpufreq_frequency_table exynos4_freq_table[] = {
	{L0, 1200*1000},
	{L1, 1000*1000},
	{L2, 800*1000},
	{L3, 500*1000},
	{L4, 200*1000},
	{0, CPUFREQ_TABLE_END},
};

static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
	/*
	 * Clock divider value for following
	 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
	 *		DIVATB, DIVPCLK_DBG, DIVAPLL }
	 */

	/* ARM L0: 1200MHz */
	{ 0, 3, 7, 3, 4, 1, 7 },

	/* ARM L1: 1000MHz */
	{ 0, 3, 7, 3, 4, 1, 7 },

	/* ARM L2: 800MHz */
	{ 0, 3, 7, 3, 3, 1, 7 },

	/* ARM L3: 500MHz */
	{ 0, 3, 7, 3, 3, 1, 7 },

	/* ARM L4: 200MHz */
	{ 0, 1, 3, 1, 3, 1, 0 },
};

static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
	/*
	 * Clock divider value for following
	 * { DIVCOPY, DIVHPM }
	 */

	/* ARM L0: 1200MHz */
	{ 5, 0 },

	/* ARM L1: 1000MHz */
	{ 4, 0 },

	/* ARM L2: 800MHz */
	{ 3, 0 },

	/* ARM L3: 500MHz */
	{ 3, 0 },

	/* ARM L4: 200MHz */
	{ 3, 0 },
};

struct cpufreq_voltage_table {
	unsigned int	index;		/* any */
	unsigned int	arm_volt;	/* uV */
};

static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
	{
		.index		= L0,
		.arm_volt	= 1350000,
	}, {
		.index		= L1,
		.arm_volt	= 1300000,
	}, {
		.index		= L2,
		.arm_volt	= 1200000,
	}, {
		.index		= L3,
		.arm_volt	= 1100000,
	}, {
		.index		= L4,
		.arm_volt	= 1050000,
	},
};

static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
	/* APLL FOUT L0: 1200MHz */
	((150 << 16) | (3 << 8) | 1),

	/* APLL FOUT L1: 1000MHz */
	((250 << 16) | (6 << 8) | 1),

	/* APLL FOUT L2: 800MHz */
	((200 << 16) | (6 << 8) | 1),

	/* APLL FOUT L3: 500MHz */
	((250 << 16) | (6 << 8) | 2),

	/* APLL FOUT L4: 200MHz */
	((200 << 16) | (6 << 8) | 3),
};

static int exynos4_verify_speed(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
}

static unsigned int exynos4_getspeed(unsigned int cpu)
{
	return clk_get_rate(cpu_clk) / 1000;
}

static void exynos4_set_clkdiv(unsigned int div_index)
{
	unsigned int tmp;

	/* Change Divider - CPU0 */

	tmp = __raw_readl(S5P_CLKDIV_CPU);

	tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
		S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
		S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
		S5P_CLKDIV_CPU0_APLL_MASK);

	tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
		(clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
		(clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
		(clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
		(clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
		(clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
		(clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));

	__raw_writel(tmp, S5P_CLKDIV_CPU);

	do {
		tmp = __raw_readl(S5P_CLKDIV_STATCPU);
	} while (tmp & 0x1111111);

	/* Change Divider - CPU1 */

	tmp = __raw_readl(S5P_CLKDIV_CPU1);

	tmp &= ~((0x7 << 4) | 0x7);

	tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
		(clkdiv_cpu1[div_index][1] << 0));

	__raw_writel(tmp, S5P_CLKDIV_CPU1);

	do {
		tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
	} while (tmp & 0x11);
}

static void exynos4_set_apll(unsigned int index)
{
	unsigned int tmp;

	/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
	clk_set_parent(moutcore, mout_mpll);

	do {
		tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
			>> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
		tmp &= 0x7;
	} while (tmp != 0x2);

	/* 2. Set APLL Lock time */
	__raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);

	/* 3. Change PLL PMS values */
	tmp = __raw_readl(S5P_APLL_CON0);
	tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
	tmp |= exynos4_apll_pms_table[index];
	__raw_writel(tmp, S5P_APLL_CON0);

	/* 4. wait_lock_time */
	do {
		tmp = __raw_readl(S5P_APLL_CON0);
	} while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));

	/* 5. MUX_CORE_SEL = APLL */
	clk_set_parent(moutcore, mout_apll);

	do {
		tmp = __raw_readl(S5P_CLKMUX_STATCPU);
		tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
	} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
}

static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
{
	unsigned int tmp;

	if (old_index > new_index) {
		/* The frequency changing to L0 needs to change apll */
		if (freqs.new == exynos4_freq_table[L0].frequency) {
			/* 1. Change the system clock divider values */
			exynos4_set_clkdiv(new_index);

			/* 2. Change the apll m,p,s value */
			exynos4_set_apll(new_index);
		} else {
			/* 1. Change the system clock divider values */
			exynos4_set_clkdiv(new_index);

			/* 2. Change just s value in apll m,p,s value */
			tmp = __raw_readl(S5P_APLL_CON0);
			tmp &= ~(0x7 << 0);
			tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
			__raw_writel(tmp, S5P_APLL_CON0);
		}
	}

	else if (old_index < new_index) {
		/* The frequency changing from L0 needs to change apll */
		if (freqs.old == exynos4_freq_table[L0].frequency) {
			/* 1. Change the apll m,p,s value */
			exynos4_set_apll(new_index);

			/* 2. Change the system clock divider values */
			exynos4_set_clkdiv(new_index);
		} else {
			/* 1. Change just s value in apll m,p,s value */
			tmp = __raw_readl(S5P_APLL_CON0);
			tmp &= ~(0x7 << 0);
			tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
			__raw_writel(tmp, S5P_APLL_CON0);

			/* 2. Change the system clock divider values */
			exynos4_set_clkdiv(new_index);
		}
	}
}

static int exynos4_target(struct cpufreq_policy *policy,
			  unsigned int target_freq,
			  unsigned int relation)
{
	unsigned int index, old_index;
	unsigned int arm_volt;
	int err = -EINVAL;

	freqs.old = exynos4_getspeed(policy->cpu);

	mutex_lock(&cpufreq_lock);

	if (frequency_locked && target_freq != locking_frequency) {
		err = -EAGAIN;
		goto out;
	}

	if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
					   freqs.old, relation, &old_index))
		goto out;

	if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
					   target_freq, relation, &index))
		goto out;

	err = 0;

	freqs.new = exynos4_freq_table[index].frequency;
	freqs.cpu = policy->cpu;

	if (freqs.new == freqs.old)
		goto out;

	/* get the voltage value */
	arm_volt = exynos4_volt_table[index].arm_volt;

	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);

	/* control regulator */
	if (freqs.new > freqs.old) {
		/* Voltage up */
		regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
	}

	/* Clock Configuration Procedure */
	exynos4_set_frequency(old_index, index);

	/* control regulator */
	if (freqs.new < freqs.old) {
		/* Voltage down */
		regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
	}

	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);

out:
	mutex_unlock(&cpufreq_lock);
	return err;
}

#ifdef CONFIG_PM
/*
 * These suspend/resume are used as syscore_ops, it is already too
 * late to set regulator voltages at this stage.
 */
static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
{
	return 0;
}

static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
{
	return 0;
}
#endif

/**
 * exynos4_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
 *			context
 * @notifier
 * @pm_event
 * @v
 *
 * While frequency_locked == true, target() ignores every frequency but
 * locking_frequency. The locking_frequency value is the initial frequency,
 * which is set by the bootloader. In order to eliminate possible
 * inconsistency in clock values, we save and restore frequencies during
 * suspend and resume and block CPUFREQ activities. Note that the standard
 * suspend/resume cannot be used as they are too deep (syscore_ops) for
 * regulator actions.
 */
static int exynos4_cpufreq_pm_notifier(struct notifier_block *notifier,
				       unsigned long pm_event, void *v)
{
	struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */
	static unsigned int saved_frequency;
	unsigned int temp;

	mutex_lock(&cpufreq_lock);
	switch (pm_event) {
	case PM_SUSPEND_PREPARE:
		if (frequency_locked)
			goto out;
		frequency_locked = true;

		if (locking_frequency) {
			saved_frequency = exynos4_getspeed(0);

			mutex_unlock(&cpufreq_lock);
			exynos4_target(policy, locking_frequency,
				       CPUFREQ_RELATION_H);
			mutex_lock(&cpufreq_lock);
		}

		break;
	case PM_POST_SUSPEND:

		if (saved_frequency) {
			/*
			 * While frequency_locked, only locking_frequency
			 * is valid for target(). In order to use
			 * saved_frequency while keeping frequency_locked,
			 * we temporarly overwrite locking_frequency.
			 */
			temp = locking_frequency;
			locking_frequency = saved_frequency;

			mutex_unlock(&cpufreq_lock);
			exynos4_target(policy, locking_frequency,
				       CPUFREQ_RELATION_H);
			mutex_lock(&cpufreq_lock);

			locking_frequency = temp;
		}

		frequency_locked = false;
		break;
	}
out:
	mutex_unlock(&cpufreq_lock);

	return NOTIFY_OK;
}

static struct notifier_block exynos4_cpufreq_nb = {
	.notifier_call = exynos4_cpufreq_pm_notifier,
};

static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
	int ret;

	policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);

	cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);

	/* set the transition latency value */
	policy->cpuinfo.transition_latency = 100000;

	/*
	 * EXYNOS4 multi-core processors has 2 cores
	 * that the frequency cannot be set independently.
	 * Each cpu is bound to the same speed.
	 * So the affected cpu is all of the cpus.
	 */
	cpumask_setall(policy->cpus);

	ret = cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
	if (ret)
		return ret;

	cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);

	return 0;
}

static int exynos4_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_put_attr(policy->cpu);
	return 0;
}

static struct freq_attr *exynos4_cpufreq_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver exynos4_driver = {
	.flags		= CPUFREQ_STICKY,
	.verify		= exynos4_verify_speed,
	.target		= exynos4_target,
	.get		= exynos4_getspeed,
	.init		= exynos4_cpufreq_cpu_init,
	.exit		= exynos4_cpufreq_cpu_exit,
	.name		= "exynos4_cpufreq",
	.attr		= exynos4_cpufreq_attr,
#ifdef CONFIG_PM
	.suspend	= exynos4_cpufreq_suspend,
	.resume		= exynos4_cpufreq_resume,
#endif
};

static int __init exynos4_cpufreq_init(void)
{
	cpu_clk = clk_get(NULL, "armclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	locking_frequency = exynos4_getspeed(0);

	moutcore = clk_get(NULL, "moutcore");
	if (IS_ERR(moutcore))
		goto out;

	mout_mpll = clk_get(NULL, "mout_mpll");
	if (IS_ERR(mout_mpll))
		goto out;

	mout_apll = clk_get(NULL, "mout_apll");
	if (IS_ERR(mout_apll))
		goto out;

	arm_regulator = regulator_get(NULL, "vdd_arm");
	if (IS_ERR(arm_regulator)) {
		printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
		goto out;
	}

	register_pm_notifier(&exynos4_cpufreq_nb);

	return cpufreq_register_driver(&exynos4_driver);

out:
	if (!IS_ERR(cpu_clk))
		clk_put(cpu_clk);

	if (!IS_ERR(moutcore))
		clk_put(moutcore);

	if (!IS_ERR(mout_mpll))
		clk_put(mout_mpll);

	if (!IS_ERR(mout_apll))
		clk_put(mout_apll);

	if (!IS_ERR(arm_regulator))
		regulator_put(arm_regulator);

	printk(KERN_ERR "%s: failed initialization\n", __func__);

	return -EINVAL;
}
late_initcall(exynos4_cpufreq_init);
Commit	Line	Data
f7d77079	1	/*
7d30e8b3	2	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
f40f91fe SK	3	* http://www.samsung.com
f40f91fe SK	4	*
7d30e8b3	5	* EXYNOS4 - CPU frequency scaling support
f40f91fe SK	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/types.h>
	13	#include <linux/kernel.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
	16	#include <linux/io.h>
	17	#include <linux/slab.h>
	18	#include <linux/regulator/consumer.h>
	19	#include <linux/cpufreq.h>
0073f538 MH	20	#include <linux/notifier.h>
0073f538 MH	21	#include <linux/suspend.h>
f40f91fe SK	22
	23	#include <mach/map.h>
	24	#include <mach/regs-clock.h>
	25	#include <mach/regs-mem.h>
	26
	27	#include <plat/clock.h>
bf5ce054	28	#include <plat/pm.h>
f40f91fe SK	29
	30	static struct clk *cpu_clk;
	31	static struct clk *moutcore;
	32	static struct clk *mout_mpll;
	33	static struct clk *mout_apll;
	34
f40f91fe	35	static struct regulator *arm_regulator;
f40f91fe SK	36
f40f91fe SK	37	static struct cpufreq_freqs freqs;
f40f91fe	38
0073f538 MH	39	static unsigned int locking_frequency;
	40	static bool frequency_locked;
	41	static DEFINE_MUTEX(cpufreq_lock);
	42
f40f91fe	43	enum cpufreq_level_index {
ba9d7803	44	L0, L1, L2, L3, L4, CPUFREQ_LEVEL_END,
f40f91fe SK	45	};
f40f91fe SK	46
7d30e8b3	47	static struct cpufreq_frequency_table exynos4_freq_table[] = {
ba9d7803 JL	48	{L0, 1200*1000},
	49	{L1, 1000*1000},
	50	{L2, 800*1000},
	51	{L3, 500*1000},
	52	{L4, 200*1000},
f40f91fe SK	53	{0, CPUFREQ_TABLE_END},
	54	};
	55
bf5ce054	56	static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
f40f91fe SK	57	/*
	58	* Clock divider value for following
	59	* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
	60	* DIVATB, DIVPCLK_DBG, DIVAPLL }
	61	*/
	62
ba9d7803 JL	63	/* ARM L0: 1200MHz */
ba9d7803 JL	64	{ 0, 3, 7, 3, 4, 1, 7 },
f40f91fe	65
ba9d7803 JL	66	/* ARM L1: 1000MHz */
ba9d7803 JL	67	{ 0, 3, 7, 3, 4, 1, 7 },
f40f91fe	68
ba9d7803 JL	69	/* ARM L2: 800MHz */
ba9d7803 JL	70	{ 0, 3, 7, 3, 3, 1, 7 },
f40f91fe	71
ba9d7803 JL	72	/* ARM L3: 500MHz */
	73	{ 0, 3, 7, 3, 3, 1, 7 },
	74
	75	/* ARM L4: 200MHz */
	76	{ 0, 1, 3, 1, 3, 1, 0 },
bf5ce054	77	};
f40f91fe	78
bf5ce054 SJ	79	static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
	80	/*
	81	* Clock divider value for following
	82	* { DIVCOPY, DIVHPM }
	83	*/
	84
ba9d7803 JL	85	/* ARM L0: 1200MHz */
	86	{ 5, 0 },
	87
	88	/* ARM L1: 1000MHz */
	89	{ 4, 0 },
bf5ce054	90
ba9d7803	91	/* ARM L2: 800MHz */
bf5ce054	92	{ 3, 0 },
f40f91fe	93
ba9d7803	94	/* ARM L3: 500MHz */
bf5ce054 SJ	95	{ 3, 0 },
bf5ce054 SJ	96
ba9d7803	97	/* ARM L4: 200MHz */
bf5ce054	98	{ 3, 0 },
f40f91fe SK	99	};
f40f91fe SK	100
f40f91fe SK	101	struct cpufreq_voltage_table {
	102	unsigned int index; /* any */
	103	unsigned int arm_volt; /* uV */
f40f91fe SK	104	};
f40f91fe SK	105
7d30e8b3	106	static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
f40f91fe SK	107	{
f40f91fe SK	108	.index = L0,
ba9d7803	109	.arm_volt = 1350000,
f40f91fe SK	110	}, {
f40f91fe SK	111	.index = L1,
ba9d7803	112	.arm_volt = 1300000,
f40f91fe SK	113	}, {
f40f91fe SK	114	.index = L2,
ba9d7803	115	.arm_volt = 1200000,
f40f91fe SK	116	}, {
f40f91fe SK	117	.index = L3,
ba9d7803 JL	118	.arm_volt = 1100000,
	119	}, {
	120	.index = L4,
	121	.arm_volt = 1050000,
f40f91fe SK	122	},
	123	};
	124
7d30e8b3	125	static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
ba9d7803 JL	126	/* APLL FOUT L0: 1200MHz */
	127	((150 << 16) \| (3 << 8) \| 1),
	128
	129	/* APLL FOUT L1: 1000MHz */
bf5ce054 SJ	130	((250 << 16) \| (6 << 8) \| 1),
bf5ce054 SJ	131
ba9d7803	132	/* APLL FOUT L2: 800MHz */
bf5ce054 SJ	133	((200 << 16) \| (6 << 8) \| 1),
bf5ce054 SJ	134
ba9d7803 JL	135	/* APLL FOUT L3: 500MHz */
ba9d7803 JL	136	((250 << 16) \| (6 << 8) \| 2),
bf5ce054	137
ba9d7803 JL	138	/* APLL FOUT L4: 200MHz */
ba9d7803 JL	139	((200 << 16) \| (6 << 8) \| 3),
bf5ce054 SJ	140	};
bf5ce054 SJ	141
2f0d6f20	142	static int exynos4_verify_speed(struct cpufreq_policy *policy)
f40f91fe	143	{
7d30e8b3	144	return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
f40f91fe SK	145	}
f40f91fe SK	146
2f0d6f20	147	static unsigned int exynos4_getspeed(unsigned int cpu)
f40f91fe SK	148	{
	149	return clk_get_rate(cpu_clk) / 1000;
	150	}
	151
2f0d6f20	152	static void exynos4_set_clkdiv(unsigned int div_index)
f40f91fe SK	153	{
	154	unsigned int tmp;
	155
	156	/* Change Divider - CPU0 */
	157
	158	tmp = __raw_readl(S5P_CLKDIV_CPU);
	159
	160	tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK \| S5P_CLKDIV_CPU0_COREM0_MASK \|
	161	S5P_CLKDIV_CPU0_COREM1_MASK \| S5P_CLKDIV_CPU0_PERIPH_MASK \|
	162	S5P_CLKDIV_CPU0_ATB_MASK \| S5P_CLKDIV_CPU0_PCLKDBG_MASK \|
	163	S5P_CLKDIV_CPU0_APLL_MASK);
	164
	165	tmp \|= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) \|
	166	(clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) \|
	167	(clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) \|
	168	(clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) \|
	169	(clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) \|
	170	(clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) \|
	171	(clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
	172
	173	__raw_writel(tmp, S5P_CLKDIV_CPU);
	174
	175	do {
	176	tmp = __raw_readl(S5P_CLKDIV_STATCPU);
	177	} while (tmp & 0x1111111);
	178
bf5ce054 SJ	179	/* Change Divider - CPU1 */
	180
	181	tmp = __raw_readl(S5P_CLKDIV_CPU1);
	182
	183	tmp &= ~((0x7 << 4) \| 0x7);
	184
	185	tmp \|= ((clkdiv_cpu1[div_index][0] << 4) \|
	186	(clkdiv_cpu1[div_index][1] << 0));
	187
	188	__raw_writel(tmp, S5P_CLKDIV_CPU1);
	189
	190	do {
	191	tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
	192	} while (tmp & 0x11);
f40f91fe SK	193	}
f40f91fe SK	194
7d30e8b3	195	static void exynos4_set_apll(unsigned int index)
bf5ce054 SJ	196	{
	197	unsigned int tmp;
	198
	199	/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
	200	clk_set_parent(moutcore, mout_mpll);
	201
	202	do {
	203	tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
	204	>> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
	205	tmp &= 0x7;
	206	} while (tmp != 0x2);
	207
	208	/* 2. Set APLL Lock time */
	209	__raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
	210
	211	/* 3. Change PLL PMS values */
	212	tmp = __raw_readl(S5P_APLL_CON0);
	213	tmp &= ~((0x3ff << 16) \| (0x3f << 8) \| (0x7 << 0));
7d30e8b3	214	tmp \|= exynos4_apll_pms_table[index];
bf5ce054 SJ	215	__raw_writel(tmp, S5P_APLL_CON0);
	216
	217	/* 4. wait_lock_time */
	218	do {
	219	tmp = __raw_readl(S5P_APLL_CON0);
	220	} while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
	221
	222	/* 5. MUX_CORE_SEL = APLL */
	223	clk_set_parent(moutcore, mout_apll);
	224
	225	do {
	226	tmp = __raw_readl(S5P_CLKMUX_STATCPU);
	227	tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
	228	} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
	229	}
	230
7d30e8b3	231	static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
bf5ce054 SJ	232	{
	233	unsigned int tmp;
	234
	235	if (old_index > new_index) {
	236	/* The frequency changing to L0 needs to change apll */
7d30e8b3	237	if (freqs.new == exynos4_freq_table[L0].frequency) {
bf5ce054	238	/* 1. Change the system clock divider values */
7d30e8b3	239	exynos4_set_clkdiv(new_index);
bf5ce054 SJ	240
bf5ce054 SJ	241	/* 2. Change the apll m,p,s value */
7d30e8b3	242	exynos4_set_apll(new_index);
bf5ce054 SJ	243	} else {
bf5ce054 SJ	244	/* 1. Change the system clock divider values */
7d30e8b3	245	exynos4_set_clkdiv(new_index);
bf5ce054 SJ	246
	247	/* 2. Change just s value in apll m,p,s value */
	248	tmp = __raw_readl(S5P_APLL_CON0);
	249	tmp &= ~(0x7 << 0);
7d30e8b3	250	tmp \|= (exynos4_apll_pms_table[new_index] & 0x7);
bf5ce054 SJ	251	__raw_writel(tmp, S5P_APLL_CON0);
	252	}
	253	}
	254
	255	else if (old_index < new_index) {
	256	/* The frequency changing from L0 needs to change apll */
7d30e8b3	257	if (freqs.old == exynos4_freq_table[L0].frequency) {
bf5ce054	258	/* 1. Change the apll m,p,s value */
7d30e8b3	259	exynos4_set_apll(new_index);
bf5ce054 SJ	260
bf5ce054 SJ	261	/* 2. Change the system clock divider values */
7d30e8b3	262	exynos4_set_clkdiv(new_index);
bf5ce054 SJ	263	} else {
	264	/* 1. Change just s value in apll m,p,s value */
	265	tmp = __raw_readl(S5P_APLL_CON0);
	266	tmp &= ~(0x7 << 0);
7d30e8b3	267	tmp \|= (exynos4_apll_pms_table[new_index] & 0x7);
bf5ce054 SJ	268	__raw_writel(tmp, S5P_APLL_CON0);
	269
	270	/* 2. Change the system clock divider values */
7d30e8b3	271	exynos4_set_clkdiv(new_index);
bf5ce054 SJ	272	}
	273	}
	274	}
	275
7d30e8b3	276	static int exynos4_target(struct cpufreq_policy *policy,
f40f91fe SK	277	unsigned int target_freq,
	278	unsigned int relation)
	279	{
bf5ce054	280	unsigned int index, old_index;
c8c430e2	281	unsigned int arm_volt;
0073f538	282	int err = -EINVAL;
f40f91fe	283
7d30e8b3	284	freqs.old = exynos4_getspeed(policy->cpu);
f40f91fe	285
0073f538 MH	286	mutex_lock(&cpufreq_lock);
	287
	288	if (frequency_locked && target_freq != locking_frequency) {
	289	err = -EAGAIN;
	290	goto out;
	291	}
	292
7d30e8b3	293	if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
bf5ce054	294	freqs.old, relation, &old_index))
0073f538	295	goto out;
bf5ce054	296
7d30e8b3	297	if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
f40f91fe	298	target_freq, relation, &index))
0073f538 MH	299	goto out;
	300
	301	err = 0;
f40f91fe	302
7d30e8b3	303	freqs.new = exynos4_freq_table[index].frequency;
f40f91fe SK	304	freqs.cpu = policy->cpu;
	305
	306	if (freqs.new == freqs.old)
0073f538	307	goto out;
f40f91fe	308
f40f91fe	309	/* get the voltage value */
7d30e8b3	310	arm_volt = exynos4_volt_table[index].arm_volt;
f40f91fe SK	311
	312	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	313
	314	/* control regulator */
	315	if (freqs.new > freqs.old) {
	316	/* Voltage up */
f40f91fe	317	regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
f40f91fe SK	318	}
	319
	320	/* Clock Configuration Procedure */
7d30e8b3	321	exynos4_set_frequency(old_index, index);
f40f91fe SK	322
	323	/* control regulator */
	324	if (freqs.new < freqs.old) {
	325	/* Voltage down */
f40f91fe	326	regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
f40f91fe SK	327	}
	328
	329	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	330
0073f538 MH	331	out:
	332	mutex_unlock(&cpufreq_lock);
	333	return err;
f40f91fe SK	334	}
	335
	336	#ifdef CONFIG_PM
0073f538 MH	337	/*
	338	* These suspend/resume are used as syscore_ops, it is already too
	339	* late to set regulator voltages at this stage.
	340	*/
411f5c7a	341	static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
f40f91fe SK	342	{
	343	return 0;
	344	}
	345
7d30e8b3	346	static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
f40f91fe SK	347	{
	348	return 0;
	349	}
	350	#endif
	351
0073f538 MH	352	/**
	353	* exynos4_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
	354	* context
	355	* @notifier
	356	* @pm_event
	357	* @v
	358	*
	359	* While frequency_locked == true, target() ignores every frequency but
	360	* locking_frequency. The locking_frequency value is the initial frequency,
	361	* which is set by the bootloader. In order to eliminate possible
	362	* inconsistency in clock values, we save and restore frequencies during
	363	* suspend and resume and block CPUFREQ activities. Note that the standard
	364	* suspend/resume cannot be used as they are too deep (syscore_ops) for
	365	* regulator actions.
	366	*/
	367	static int exynos4_cpufreq_pm_notifier(struct notifier_block *notifier,
	368	unsigned long pm_event, void *v)
	369	{
	370	struct cpufreq_policy policy = cpufreq_cpu_get(0); / boot CPU */
	371	static unsigned int saved_frequency;
	372	unsigned int temp;
	373
	374	mutex_lock(&cpufreq_lock);
	375	switch (pm_event) {
	376	case PM_SUSPEND_PREPARE:
	377	if (frequency_locked)
	378	goto out;
	379	frequency_locked = true;
	380
	381	if (locking_frequency) {
	382	saved_frequency = exynos4_getspeed(0);
	383
	384	mutex_unlock(&cpufreq_lock);
	385	exynos4_target(policy, locking_frequency,
	386	CPUFREQ_RELATION_H);
	387	mutex_lock(&cpufreq_lock);
	388	}
	389
	390	break;
	391	case PM_POST_SUSPEND:
	392
	393	if (saved_frequency) {
	394	/*
	395	* While frequency_locked, only locking_frequency
	396	* is valid for target(). In order to use
	397	* saved_frequency while keeping frequency_locked,
	398	* we temporarly overwrite locking_frequency.
	399	*/
	400	temp = locking_frequency;
	401	locking_frequency = saved_frequency;
	402
	403	mutex_unlock(&cpufreq_lock);
	404	exynos4_target(policy, locking_frequency,
	405	CPUFREQ_RELATION_H);
	406	mutex_lock(&cpufreq_lock);
	407
	408	locking_frequency = temp;
	409	}
	410
	411	frequency_locked = false;
	412	break;
	413	}
	414	out:
	415	mutex_unlock(&cpufreq_lock);
416
417	return NOTIFY_OK;
418	}
419
420	static struct notifier_block exynos4_cpufreq_nb = {
421	.notifier_call = exynos4_cpufreq_pm_notifier,
422	};
423
7d30e8b3	424	static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
f40f91fe	425	{
5beae3b9 DK	426	int ret;
5beae3b9 DK	427
7d30e8b3	428	policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
f40f91fe	429
7d30e8b3	430	cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
f40f91fe SK	431
	432	/* set the transition latency value */
	433	policy->cpuinfo.transition_latency = 100000;
	434
	435	/*
7d30e8b3	436	* EXYNOS4 multi-core processors has 2 cores
f40f91fe SK	437	* that the frequency cannot be set independently.
	438	* Each cpu is bound to the same speed.
	439	* So the affected cpu is all of the cpus.
	440	*/
	441	cpumask_setall(policy->cpus);
	442
5beae3b9 DK	443	ret = cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
	444	if (ret)
	445	return ret;
	446
	447	cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
	448
	449	return 0;
f40f91fe SK	450	}
f40f91fe SK	451
5beae3b9 DK	452	static int exynos4_cpufreq_cpu_exit(struct cpufreq_policy *policy)
	453	{
	454	cpufreq_frequency_table_put_attr(policy->cpu);
	455	return 0;
	456	}
	457
	458	static struct freq_attr *exynos4_cpufreq_attr[] = {
	459	&cpufreq_freq_attr_scaling_available_freqs,
	460	NULL,
	461	};
	462
7d30e8b3	463	static struct cpufreq_driver exynos4_driver = {
f40f91fe	464	.flags = CPUFREQ_STICKY,
7d30e8b3 KK	465	.verify = exynos4_verify_speed,
	466	.target = exynos4_target,
	467	.get = exynos4_getspeed,
	468	.init = exynos4_cpufreq_cpu_init,
5beae3b9	469	.exit = exynos4_cpufreq_cpu_exit,
7d30e8b3	470	.name = "exynos4_cpufreq",
5beae3b9	471	.attr = exynos4_cpufreq_attr,
f40f91fe	472	#ifdef CONFIG_PM
7d30e8b3 KK	473	.suspend = exynos4_cpufreq_suspend,
7d30e8b3 KK	474	.resume = exynos4_cpufreq_resume,
f40f91fe SK	475	#endif
	476	};
	477
7d30e8b3	478	static int __init exynos4_cpufreq_init(void)
f40f91fe	479	{
f40f91fe SK	480	cpu_clk = clk_get(NULL, "armclk");
	481	if (IS_ERR(cpu_clk))
	482	return PTR_ERR(cpu_clk);
	483
0073f538 MH	484	locking_frequency = exynos4_getspeed(0);
0073f538 MH	485
f40f91fe SK	486	moutcore = clk_get(NULL, "moutcore");
	487	if (IS_ERR(moutcore))
	488	goto out;
	489
	490	mout_mpll = clk_get(NULL, "mout_mpll");
	491	if (IS_ERR(mout_mpll))
	492	goto out;
	493
	494	mout_apll = clk_get(NULL, "mout_apll");
	495	if (IS_ERR(mout_apll))
	496	goto out;
	497
f40f91fe SK	498	arm_regulator = regulator_get(NULL, "vdd_arm");
	499	if (IS_ERR(arm_regulator)) {
	500	printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
	501	goto out;
	502	}
	503
0073f538 MH	504	register_pm_notifier(&exynos4_cpufreq_nb);
0073f538 MH	505
7d30e8b3	506	return cpufreq_register_driver(&exynos4_driver);
f40f91fe SK	507
	508	out:
	509	if (!IS_ERR(cpu_clk))
	510	clk_put(cpu_clk);
	511
	512	if (!IS_ERR(moutcore))
	513	clk_put(moutcore);
	514
	515	if (!IS_ERR(mout_mpll))
	516	clk_put(mout_mpll);
	517
	518	if (!IS_ERR(mout_apll))
	519	clk_put(mout_apll);
	520
f40f91fe SK	521	if (!IS_ERR(arm_regulator))
	522	regulator_put(arm_regulator);
	523
f40f91fe SK	524	printk(KERN_ERR "%s: failed initialization\n", __func__);
	525
	526	return -EINVAL;
	527	}
7d30e8b3	528	late_initcall(exynos4_cpufreq_init);