[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / cpufreq / exynos-cpufreq.c

/*
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS - CPU frequency scaling support for EXYNOS series
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
#include <linux/cpufreq.h>
#include <linux/suspend.h>

#include <plat/cpu.h>

#include "exynos-cpufreq.h"

static struct exynos_dvfs_info *exynos_info;

static struct regulator *arm_regulator;
static struct cpufreq_freqs freqs;

static unsigned int locking_frequency;
static bool frequency_locked;
static DEFINE_MUTEX(cpufreq_lock);

static int exynos_verify_speed(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy,
					      exynos_info->freq_table);
}

static unsigned int exynos_getspeed(unsigned int cpu)
{
	return clk_get_rate(exynos_info->cpu_clk) / 1000;
}

static int exynos_cpufreq_get_index(unsigned int freq)
{
	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
	int index;

	for (index = 0;
		freq_table[index].frequency != CPUFREQ_TABLE_END; index++)
		if (freq_table[index].frequency == freq)
			break;

	if (freq_table[index].frequency == CPUFREQ_TABLE_END)
		return -EINVAL;

	return index;
}

static int exynos_cpufreq_scale(unsigned int target_freq)
{
	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
	unsigned int *volt_table = exynos_info->volt_table;
	struct cpufreq_policy *policy = cpufreq_cpu_get(0);
	unsigned int arm_volt, safe_arm_volt = 0;
	unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
	int index, old_index;
	int ret = 0;

	freqs.old = policy->cur;
	freqs.new = target_freq;
	freqs.cpu = policy->cpu;

	if (freqs.new == freqs.old)
		goto out;

	/*
	 * The policy max have been changed so that we cannot get proper
	 * old_index with cpufreq_frequency_table_target(). Thus, ignore
	 * policy and get the index from the raw freqeuncy table.
	 */
	old_index = exynos_cpufreq_get_index(freqs.old);
	if (old_index < 0) {
		ret = old_index;
		goto out;
	}

	index = exynos_cpufreq_get_index(target_freq);
	if (index < 0) {
		ret = index;
		goto out;
	}

	/*
	 * ARM clock source will be changed APLL to MPLL temporary
	 * To support this level, need to control regulator for
	 * required voltage level
	 */
	if (exynos_info->need_apll_change != NULL) {
		if (exynos_info->need_apll_change(old_index, index) &&
		   (freq_table[index].frequency < mpll_freq_khz) &&
		   (freq_table[old_index].frequency < mpll_freq_khz))
			safe_arm_volt = volt_table[exynos_info->pll_safe_idx];
	}
	arm_volt = volt_table[index];

	for_each_cpu(freqs.cpu, policy->cpus)
		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);

	/* When the new frequency is higher than current frequency */
	if ((freqs.new > freqs.old) && !safe_arm_volt) {
		/* Firstly, voltage up to increase frequency */
		ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
		if (ret) {
			pr_err("%s: failed to set cpu voltage to %d\n",
				__func__, arm_volt);
			goto out;
		}
	}

	if (safe_arm_volt) {
		ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
				      safe_arm_volt);
		if (ret) {
			pr_err("%s: failed to set cpu voltage to %d\n",
				__func__, safe_arm_volt);
			goto out;
		}
	}

	exynos_info->set_freq(old_index, index);

	for_each_cpu(freqs.cpu, policy->cpus)
		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);

	/* When the new frequency is lower than current frequency */
	if ((freqs.new < freqs.old) ||
	   ((freqs.new > freqs.old) && safe_arm_volt)) {
		/* down the voltage after frequency change */
		regulator_set_voltage(arm_regulator, arm_volt,
				arm_volt);
		if (ret) {
			pr_err("%s: failed to set cpu voltage to %d\n",
				__func__, arm_volt);
			goto out;
		}
	}

out:

	cpufreq_cpu_put(policy);

	return ret;
}

static int exynos_target(struct cpufreq_policy *policy,
			  unsigned int target_freq,
			  unsigned int relation)
{
	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
	unsigned int index;
	unsigned int new_freq;
	int ret = 0;

	mutex_lock(&cpufreq_lock);

	if (frequency_locked)
		goto out;

	if (cpufreq_frequency_table_target(policy, freq_table,
					   target_freq, relation, &index)) {
		ret = -EINVAL;
		goto out;
	}

	new_freq = freq_table[index].frequency;

	ret = exynos_cpufreq_scale(new_freq);

out:
	mutex_unlock(&cpufreq_lock);

	return ret;
}

#ifdef CONFIG_PM
static int exynos_cpufreq_suspend(struct cpufreq_policy *policy)
{
	return 0;
}

static int exynos_cpufreq_resume(struct cpufreq_policy *policy)
{
	return 0;
}
#endif

/**
 * exynos_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
 *			context
 * @notifier
 * @pm_event
 * @v
 *
 * While frequency_locked == true, target() ignores every frequency but
 * locking_frequency. The locking_frequency value is the initial frequency,
 * which is set by the bootloader. In order to eliminate possible
 * inconsistency in clock values, we save and restore frequencies during
 * suspend and resume and block CPUFREQ activities. Note that the standard
 * suspend/resume cannot be used as they are too deep (syscore_ops) for
 * regulator actions.
 */
static int exynos_cpufreq_pm_notifier(struct notifier_block *notifier,
				       unsigned long pm_event, void *v)
{
	int ret;

	switch (pm_event) {
	case PM_SUSPEND_PREPARE:
		mutex_lock(&cpufreq_lock);
		frequency_locked = true;
		mutex_unlock(&cpufreq_lock);

		ret = exynos_cpufreq_scale(locking_frequency);
		if (ret < 0)
			return NOTIFY_BAD;

		break;

	case PM_POST_SUSPEND:
		mutex_lock(&cpufreq_lock);
		frequency_locked = false;
		mutex_unlock(&cpufreq_lock);
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block exynos_cpufreq_nb = {
	.notifier_call = exynos_cpufreq_pm_notifier,
};

static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
	policy->cur = policy->min = policy->max = exynos_getspeed(policy->cpu);

	cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu);

	/* set the transition latency value */
	policy->cpuinfo.transition_latency = 100000;

	cpumask_setall(policy->cpus);

	return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);
}

static int exynos_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_put_attr(policy->cpu);
	return 0;
}

static struct freq_attr *exynos_cpufreq_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver exynos_driver = {
	.flags		= CPUFREQ_STICKY,
	.verify		= exynos_verify_speed,
	.target		= exynos_target,
	.get		= exynos_getspeed,
	.init		= exynos_cpufreq_cpu_init,
	.exit		= exynos_cpufreq_cpu_exit,
	.name		= "exynos_cpufreq",
	.attr		= exynos_cpufreq_attr,
#ifdef CONFIG_PM
	.suspend	= exynos_cpufreq_suspend,
	.resume		= exynos_cpufreq_resume,
#endif
};

static int __init exynos_cpufreq_init(void)
{
	int ret = -EINVAL;

	exynos_info = kzalloc(sizeof(struct exynos_dvfs_info), GFP_KERNEL);
	if (!exynos_info)
		return -ENOMEM;

	if (soc_is_exynos4210())
		ret = exynos4210_cpufreq_init(exynos_info);
	else if (soc_is_exynos4212() || soc_is_exynos4412())
		ret = exynos4x12_cpufreq_init(exynos_info);
	else if (soc_is_exynos5250())
		ret = exynos5250_cpufreq_init(exynos_info);
	else
		pr_err("%s: CPU type not found\n", __func__);

	if (ret)
		goto err_vdd_arm;

	if (exynos_info->set_freq == NULL) {
		pr_err("%s: No set_freq function (ERR)\n", __func__);
		goto err_vdd_arm;
	}

	arm_regulator = regulator_get(NULL, "vdd_arm");
	if (IS_ERR(arm_regulator)) {
		pr_err("%s: failed to get resource vdd_arm\n", __func__);
		goto err_vdd_arm;
	}

	locking_frequency = exynos_getspeed(0);

	register_pm_notifier(&exynos_cpufreq_nb);

	if (cpufreq_register_driver(&exynos_driver)) {
		pr_err("%s: failed to register cpufreq driver\n", __func__);
		goto err_cpufreq;
	}

	return 0;
err_cpufreq:
	unregister_pm_notifier(&exynos_cpufreq_nb);

	regulator_put(arm_regulator);
err_vdd_arm:
	kfree(exynos_info);
	pr_debug("%s: failed initialization\n", __func__);
	return -EINVAL;
}
late_initcall(exynos_cpufreq_init);
Commit	Line	Data
a125a17f JL	1	/*
	2	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* EXYNOS - CPU frequency scaling support for EXYNOS series
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
a125a17f JL	12	#include <linux/kernel.h>
	13	#include <linux/err.h>
	14	#include <linux/clk.h>
	15	#include <linux/io.h>
	16	#include <linux/slab.h>
	17	#include <linux/regulator/consumer.h>
	18	#include <linux/cpufreq.h>
	19	#include <linux/suspend.h>
a125a17f	20
6c523c61	21	#include <plat/cpu.h>
a125a17f	22
c4aaa295 KK	23	#include "exynos-cpufreq.h"
c4aaa295 KK	24
a125a17f JL	25	static struct exynos_dvfs_info *exynos_info;
	26
	27	static struct regulator *arm_regulator;
	28	static struct cpufreq_freqs freqs;
	29
	30	static unsigned int locking_frequency;
	31	static bool frequency_locked;
	32	static DEFINE_MUTEX(cpufreq_lock);
	33
5542721a	34	static int exynos_verify_speed(struct cpufreq_policy *policy)
a125a17f JL	35	{
	36	return cpufreq_frequency_table_verify(policy,
	37	exynos_info->freq_table);
	38	}
	39
5542721a	40	static unsigned int exynos_getspeed(unsigned int cpu)
a125a17f JL	41	{
	42	return clk_get_rate(exynos_info->cpu_clk) / 1000;
	43	}
	44
0e0e425f JC	45	static int exynos_cpufreq_get_index(unsigned int freq)
	46	{
	47	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
	48	int index;
	49
	50	for (index = 0;
	51	freq_table[index].frequency != CPUFREQ_TABLE_END; index++)
	52	if (freq_table[index].frequency == freq)
	53	break;
	54
	55	if (freq_table[index].frequency == CPUFREQ_TABLE_END)
	56	return -EINVAL;
	57
	58	return index;
	59	}
	60
	61	static int exynos_cpufreq_scale(unsigned int target_freq)
a125a17f	62	{
a125a17f JL	63	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
a125a17f JL	64	unsigned int *volt_table = exynos_info->volt_table;
0e0e425f JC	65	struct cpufreq_policy *policy = cpufreq_cpu_get(0);
0e0e425f JC	66	unsigned int arm_volt, safe_arm_volt = 0;
a125a17f	67	unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
d271d077	68	int index, old_index;
0e0e425f	69	int ret = 0;
a125a17f JL	70
a125a17f JL	71	freqs.old = policy->cur;
c098ea74	72	freqs.new = target_freq;
0e0e425f	73	freqs.cpu = policy->cpu;
a125a17f	74
c098ea74	75	if (freqs.new == freqs.old)
a125a17f	76	goto out;
a125a17f	77
53df1ad5 JL	78	/*
	79	* The policy max have been changed so that we cannot get proper
	80	* old_index with cpufreq_frequency_table_target(). Thus, ignore
	81	* policy and get the index from the raw freqeuncy table.
	82	*/
0e0e425f JC	83	old_index = exynos_cpufreq_get_index(freqs.old);
	84	if (old_index < 0) {
	85	ret = old_index;
a125a17f JL	86	goto out;
	87	}
	88
0e0e425f JC	89	index = exynos_cpufreq_get_index(target_freq);
	90	if (index < 0) {
	91	ret = index;
a125a17f JL	92	goto out;
	93	}
	94
a125a17f JL	95	/*
	96	* ARM clock source will be changed APLL to MPLL temporary
	97	* To support this level, need to control regulator for
	98	* required voltage level
	99	*/
	100	if (exynos_info->need_apll_change != NULL) {
	101	if (exynos_info->need_apll_change(old_index, index) &&
	102	(freq_table[index].frequency < mpll_freq_khz) &&
	103	(freq_table[old_index].frequency < mpll_freq_khz))
	104	safe_arm_volt = volt_table[exynos_info->pll_safe_idx];
	105	}
	106	arm_volt = volt_table[index];
	107
fd06a208 TF	108	for_each_cpu(freqs.cpu, policy->cpus)
fd06a208 TF	109	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
a125a17f JL	110
	111	/* When the new frequency is higher than current frequency */
	112	if ((freqs.new > freqs.old) && !safe_arm_volt) {
	113	/* Firstly, voltage up to increase frequency */
0e0e425f JC	114	ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
	115	if (ret) {
	116	pr_err("%s: failed to set cpu voltage to %d\n",
	117	__func__, arm_volt);
	118	goto out;
	119	}
a125a17f JL	120	}
a125a17f JL	121
0e0e425f JC	122	if (safe_arm_volt) {
0e0e425f JC	123	ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
a125a17f	124	safe_arm_volt);
0e0e425f JC	125	if (ret) {
	126	pr_err("%s: failed to set cpu voltage to %d\n",
	127	__func__, safe_arm_volt);
	128	goto out;
	129	}
	130	}
857d90f7 JC	131
857d90f7 JC	132	exynos_info->set_freq(old_index, index);
a125a17f	133
fd06a208 TF	134	for_each_cpu(freqs.cpu, policy->cpus)
fd06a208 TF	135	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
a125a17f JL	136
	137	/* When the new frequency is lower than current frequency */
	138	if ((freqs.new < freqs.old) \|\|
	139	((freqs.new > freqs.old) && safe_arm_volt)) {
	140	/* down the voltage after frequency change */
	141	regulator_set_voltage(arm_regulator, arm_volt,
	142	arm_volt);
0e0e425f JC	143	if (ret) {
	144	pr_err("%s: failed to set cpu voltage to %d\n",
	145	__func__, arm_volt);
	146	goto out;
	147	}
a125a17f JL	148	}
a125a17f JL	149
0e0e425f JC	150	out:
	151
	152	cpufreq_cpu_put(policy);
	153
	154	return ret;
	155	}
	156
	157	static int exynos_target(struct cpufreq_policy *policy,
	158	unsigned int target_freq,
	159	unsigned int relation)
	160	{
	161	struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
	162	unsigned int index;
c098ea74	163	unsigned int new_freq;
229b21e2	164	int ret = 0;
0e0e425f JC	165
	166	mutex_lock(&cpufreq_lock);
	167
	168	if (frequency_locked)
	169	goto out;
	170
	171	if (cpufreq_frequency_table_target(policy, freq_table,
	172	target_freq, relation, &index)) {
	173	ret = -EINVAL;
	174	goto out;
a125a17f JL	175	}
a125a17f JL	176
c098ea74	177	new_freq = freq_table[index].frequency;
0e0e425f	178
c098ea74	179	ret = exynos_cpufreq_scale(new_freq);
0e0e425f	180
a125a17f JL	181	out:
	182	mutex_unlock(&cpufreq_lock);
	183
	184	return ret;
	185	}
	186
	187	#ifdef CONFIG_PM
	188	static int exynos_cpufreq_suspend(struct cpufreq_policy *policy)
	189	{
	190	return 0;
	191	}
	192
	193	static int exynos_cpufreq_resume(struct cpufreq_policy *policy)
	194	{
	195	return 0;
	196	}
	197	#endif
	198
	199	/**
	200	* exynos_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
	201	* context
	202	* @notifier
	203	* @pm_event
	204	* @v
	205	*
	206	* While frequency_locked == true, target() ignores every frequency but
	207	* locking_frequency. The locking_frequency value is the initial frequency,
	208	* which is set by the bootloader. In order to eliminate possible
	209	* inconsistency in clock values, we save and restore frequencies during
	210	* suspend and resume and block CPUFREQ activities. Note that the standard
	211	* suspend/resume cannot be used as they are too deep (syscore_ops) for
	212	* regulator actions.
	213	*/
	214	static int exynos_cpufreq_pm_notifier(struct notifier_block *notifier,
	215	unsigned long pm_event, void *v)
	216	{
0e0e425f	217	int ret;
a125a17f	218
a125a17f JL	219	switch (pm_event) {
a125a17f JL	220	case PM_SUSPEND_PREPARE:
0e0e425f	221	mutex_lock(&cpufreq_lock);
a125a17f	222	frequency_locked = true;
0e0e425f	223	mutex_unlock(&cpufreq_lock);
a125a17f	224
0e0e425f JC	225	ret = exynos_cpufreq_scale(locking_frequency);
	226	if (ret < 0)
	227	return NOTIFY_BAD;
a125a17f	228
a125a17f JL	229	break;
	230
	231	case PM_POST_SUSPEND:
0e0e425f	232	mutex_lock(&cpufreq_lock);
a125a17f	233	frequency_locked = false;
0e0e425f	234	mutex_unlock(&cpufreq_lock);
a125a17f JL	235	break;
a125a17f JL	236	}
a125a17f JL	237
	238	return NOTIFY_OK;
	239	}
	240
	241	static struct notifier_block exynos_cpufreq_nb = {
	242	.notifier_call = exynos_cpufreq_pm_notifier,
	243	};
	244
	245	static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
	246	{
	247	policy->cur = policy->min = policy->max = exynos_getspeed(policy->cpu);
	248
	249	cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu);
	250
	251	/* set the transition latency value */
	252	policy->cpuinfo.transition_latency = 100000;
	253
6ca939b3	254	cpumask_setall(policy->cpus);
a125a17f JL	255
	256	return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);
	257	}
	258
1298271b IS	259	static int exynos_cpufreq_cpu_exit(struct cpufreq_policy *policy)
	260	{
	261	cpufreq_frequency_table_put_attr(policy->cpu);
	262	return 0;
	263	}
	264
	265	static struct freq_attr *exynos_cpufreq_attr[] = {
	266	&cpufreq_freq_attr_scaling_available_freqs,
	267	NULL,
	268	};
	269
a125a17f JL	270	static struct cpufreq_driver exynos_driver = {
	271	.flags = CPUFREQ_STICKY,
	272	.verify = exynos_verify_speed,
	273	.target = exynos_target,
	274	.get = exynos_getspeed,
	275	.init = exynos_cpufreq_cpu_init,
1298271b	276	.exit = exynos_cpufreq_cpu_exit,
a125a17f	277	.name = "exynos_cpufreq",
1298271b	278	.attr = exynos_cpufreq_attr,
a125a17f JL	279	#ifdef CONFIG_PM
	280	.suspend = exynos_cpufreq_suspend,
	281	.resume = exynos_cpufreq_resume,
	282	#endif
	283	};
	284
	285	static int __init exynos_cpufreq_init(void)
	286	{
	287	int ret = -EINVAL;
	288
	289	exynos_info = kzalloc(sizeof(struct exynos_dvfs_info), GFP_KERNEL);
	290	if (!exynos_info)
	291	return -ENOMEM;
	292
	293	if (soc_is_exynos4210())
	294	ret = exynos4210_cpufreq_init(exynos_info);
a35c5051 JL	295	else if (soc_is_exynos4212() \|\| soc_is_exynos4412())
a35c5051 JL	296	ret = exynos4x12_cpufreq_init(exynos_info);
562a6cbe JL	297	else if (soc_is_exynos5250())
562a6cbe JL	298	ret = exynos5250_cpufreq_init(exynos_info);
a125a17f JL	299	else
	300	pr_err("%s: CPU type not found\n", __func__);
	301
	302	if (ret)
	303	goto err_vdd_arm;
	304
	305	if (exynos_info->set_freq == NULL) {
	306	pr_err("%s: No set_freq function (ERR)\n", __func__);
	307	goto err_vdd_arm;
	308	}
	309
	310	arm_regulator = regulator_get(NULL, "vdd_arm");
	311	if (IS_ERR(arm_regulator)) {
	312	pr_err("%s: failed to get resource vdd_arm\n", __func__);
	313	goto err_vdd_arm;
	314	}
	315
6e45eb12 JC	316	locking_frequency = exynos_getspeed(0);
6e45eb12 JC	317
a125a17f JL	318	register_pm_notifier(&exynos_cpufreq_nb);
	319
	320	if (cpufreq_register_driver(&exynos_driver)) {
	321	pr_err("%s: failed to register cpufreq driver\n", __func__);
	322	goto err_cpufreq;
	323	}
	324
	325	return 0;
	326	err_cpufreq:
	327	unregister_pm_notifier(&exynos_cpufreq_nb);
	328
184cddd1	329	regulator_put(arm_regulator);
a125a17f JL	330	err_vdd_arm:
	331	kfree(exynos_info);
	332	pr_debug("%s: failed initialization\n", __func__);
	333	return -EINVAL;
	334	}
	335	late_initcall(exynos_cpufreq_init);