ARM: Fix build after memfd_create syscall
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / cpufreq / dbx500-cpufreq.c
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7c1a70e9 1/*
7c1a70e9 2 * Copyright (C) STMicroelectronics 2009
0baf066f 3 * Copyright (C) ST-Ericsson SA 2010-2012
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4 *
5 * License Terms: GNU General Public License v2
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6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
7 * Author: Martin Persson <martin.persson@stericsson.com>
8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
7c1a70e9 9 */
0baf066f 10
b4689444 11#include <linux/module.h>
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12#include <linux/kernel.h>
13#include <linux/cpufreq.h>
14#include <linux/delay.h>
72b2fd5c 15#include <linux/slab.h>
b4689444 16#include <linux/platform_device.h>
78e30d12 17#include <linux/clk.h>
7c1a70e9 18
fdb44464 19static struct cpufreq_frequency_table *freq_table;
78e30d12 20static struct clk *armss_clk;
72b2fd5c 21
edb10c11 22static struct freq_attr *dbx500_cpufreq_attr[] = {
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23 &cpufreq_freq_attr_scaling_available_freqs,
24 NULL,
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25};
26
edb10c11 27static int dbx500_cpufreq_verify_speed(struct cpufreq_policy *policy)
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28{
29 return cpufreq_frequency_table_verify(policy, freq_table);
30}
31
edb10c11 32static int dbx500_cpufreq_target(struct cpufreq_policy *policy,
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33 unsigned int target_freq,
34 unsigned int relation)
35{
36 struct cpufreq_freqs freqs;
72b2fd5c 37 unsigned int idx;
9291cf9d 38 int ret;
7c1a70e9 39
72b2fd5c 40 /* Lookup the next frequency */
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41 if (cpufreq_frequency_table_target(policy, freq_table, target_freq,
42 relation, &idx))
72b2fd5c 43 return -EINVAL;
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44
45 freqs.old = policy->cur;
72b2fd5c 46 freqs.new = freq_table[idx].frequency;
7c1a70e9 47
72b2fd5c 48 if (freqs.old == freqs.new)
7c1a70e9 49 return 0;
7c1a70e9 50
72b2fd5c 51 /* pre-change notification */
b43a7ffb 52 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
7c1a70e9 53
78e30d12 54 /* update armss clk frequency */
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55 ret = clk_set_rate(armss_clk, freqs.new * 1000);
56
57 if (ret) {
58 pr_err("dbx500-cpufreq: Failed to set armss_clk to %d Hz: error %d\n",
59 freqs.new * 1000, ret);
60 return ret;
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61 }
62
72b2fd5c 63 /* post change notification */
b43a7ffb 64 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
7c1a70e9 65
72b2fd5c 66 return 0;
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67}
68
edb10c11 69static unsigned int dbx500_cpufreq_getspeed(unsigned int cpu)
7c1a70e9 70{
fdb44464 71 int i = 0;
78e30d12 72 unsigned long freq = clk_get_rate(armss_clk) / 1000;
fdb44464 73
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74 /* The value is rounded to closest frequency in the defined table. */
75 while (freq_table[i + 1].frequency != CPUFREQ_TABLE_END) {
76 if (freq < freq_table[i].frequency +
77 (freq_table[i + 1].frequency - freq_table[i].frequency) / 2)
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78 return freq_table[i].frequency;
79 i++;
80 }
81
c7789669 82 return freq_table[i].frequency;
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83}
84
edb10c11 85static int __cpuinit dbx500_cpufreq_init(struct cpufreq_policy *policy)
7c1a70e9 86{
fdb44464 87 int res;
c72fe851 88
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89 /* get policy fields based on the table */
90 res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
91 if (!res)
92 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
93 else {
9291cf9d 94 pr_err("dbx500-cpufreq: Failed to read policy table\n");
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95 return res;
96 }
97
98 policy->min = policy->cpuinfo.min_freq;
99 policy->max = policy->cpuinfo.max_freq;
edb10c11 100 policy->cur = dbx500_cpufreq_getspeed(policy->cpu);
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101 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
102
103 /*
104 * FIXME : Need to take time measurement across the target()
105 * function with no/some/all drivers in the notification
106 * list.
107 */
72b2fd5c 108 policy->cpuinfo.transition_latency = 20 * 1000; /* in ns */
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109
110 /* policy sharing between dual CPUs */
4c738d00 111 cpumask_setall(policy->cpus);
7c1a70e9 112
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113 return 0;
114}
115
edb10c11 116static struct cpufreq_driver dbx500_cpufreq_driver = {
ec669123 117 .flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS,
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118 .verify = dbx500_cpufreq_verify_speed,
119 .target = dbx500_cpufreq_target,
120 .get = dbx500_cpufreq_getspeed,
121 .init = dbx500_cpufreq_init,
122 .name = "DBX500",
123 .attr = dbx500_cpufreq_attr,
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124};
125
edb10c11 126static int dbx500_cpufreq_probe(struct platform_device *pdev)
b4689444 127{
3e27996c 128 int i = 0;
fdb44464 129
3e27996c 130 freq_table = dev_get_platdata(&pdev->dev);
fdb44464 131 if (!freq_table) {
edb10c11 132 pr_err("dbx500-cpufreq: Failed to fetch cpufreq table\n");
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133 return -ENODEV;
134 }
135
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136 armss_clk = clk_get(&pdev->dev, "armss");
137 if (IS_ERR(armss_clk)) {
9291cf9d 138 pr_err("dbx500-cpufreq: Failed to get armss clk\n");
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139 return PTR_ERR(armss_clk);
140 }
141
9291cf9d 142 pr_info("dbx500-cpufreq: Available frequencies:\n");
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143 while (freq_table[i].frequency != CPUFREQ_TABLE_END) {
144 pr_info(" %d Mhz\n", freq_table[i].frequency/1000);
145 i++;
146 }
147
edb10c11 148 return cpufreq_register_driver(&dbx500_cpufreq_driver);
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149}
150
edb10c11 151static struct platform_driver dbx500_cpufreq_plat_driver = {
b4689444 152 .driver = {
edb10c11 153 .name = "cpufreq-ux500",
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154 .owner = THIS_MODULE,
155 },
edb10c11 156 .probe = dbx500_cpufreq_probe,
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157};
158
edb10c11 159static int __init dbx500_cpufreq_register(void)
7c1a70e9 160{
edb10c11 161 return platform_driver_register(&dbx500_cpufreq_plat_driver);
7c1a70e9 162}
edb10c11 163device_initcall(dbx500_cpufreq_register);
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164
165MODULE_LICENSE("GPL v2");
edb10c11 166MODULE_DESCRIPTION("cpufreq driver for DBX500");