[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / clocksource / sh_tmu.c

/*
 * SuperH Timer Support - TMU
 *
 *  Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/sh_timer.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pm_domain.h>

struct sh_tmu_priv {
	void __iomem *mapbase;
	struct clk *clk;
	struct irqaction irqaction;
	struct platform_device *pdev;
	unsigned long rate;
	unsigned long periodic;
	struct clock_event_device ced;
	struct clocksource cs;
};

static DEFINE_SPINLOCK(sh_tmu_lock);

#define TSTR -1 /* shared register */
#define TCOR  0 /* channel register */
#define TCNT 1 /* channel register */
#define TCR 2 /* channel register */

static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == TSTR)
		return ioread8(base - cfg->channel_offset);

	offs = reg_nr << 2;

	if (reg_nr == TCR)
		return ioread16(base + offs);
	else
		return ioread32(base + offs);
}

static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
				unsigned long value)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == TSTR) {
		iowrite8(value, base - cfg->channel_offset);
		return;
	}

	offs = reg_nr << 2;

	if (reg_nr == TCR)
		iowrite16(value, base + offs);
	else
		iowrite32(value, base + offs);
}

static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	unsigned long flags, value;

	/* start stop register shared by multiple timer channels */
	spin_lock_irqsave(&sh_tmu_lock, flags);
	value = sh_tmu_read(p, TSTR);

	if (start)
		value |= 1 << cfg->timer_bit;
	else
		value &= ~(1 << cfg->timer_bit);

	sh_tmu_write(p, TSTR, value);
	spin_unlock_irqrestore(&sh_tmu_lock, flags);
}

static int sh_tmu_enable(struct sh_tmu_priv *p)
{
	int ret;

	/* enable clock */
	ret = clk_enable(p->clk);
	if (ret) {
		dev_err(&p->pdev->dev, "cannot enable clock\n");
		return ret;
	}

	/* make sure channel is disabled */
	sh_tmu_start_stop_ch(p, 0);

	/* maximum timeout */
	sh_tmu_write(p, TCOR, 0xffffffff);
	sh_tmu_write(p, TCNT, 0xffffffff);

	/* configure channel to parent clock / 4, irq off */
	p->rate = clk_get_rate(p->clk) / 4;
	sh_tmu_write(p, TCR, 0x0000);

	/* enable channel */
	sh_tmu_start_stop_ch(p, 1);

	return 0;
}

static void sh_tmu_disable(struct sh_tmu_priv *p)
{
	/* disable channel */
	sh_tmu_start_stop_ch(p, 0);

	/* disable interrupts in TMU block */
	sh_tmu_write(p, TCR, 0x0000);

	/* stop clock */
	clk_disable(p->clk);
}

static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
			    int periodic)
{
	/* stop timer */
	sh_tmu_start_stop_ch(p, 0);

	/* acknowledge interrupt */
	sh_tmu_read(p, TCR);

	/* enable interrupt */
	sh_tmu_write(p, TCR, 0x0020);

	/* reload delta value in case of periodic timer */
	if (periodic)
		sh_tmu_write(p, TCOR, delta);
	else
		sh_tmu_write(p, TCOR, 0xffffffff);

	sh_tmu_write(p, TCNT, delta);

	/* start timer */
	sh_tmu_start_stop_ch(p, 1);
}

static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
{
	struct sh_tmu_priv *p = dev_id;

	/* disable or acknowledge interrupt */
	if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
		sh_tmu_write(p, TCR, 0x0000);
	else
		sh_tmu_write(p, TCR, 0x0020);

	/* notify clockevent layer */
	p->ced.event_handler(&p->ced);
	return IRQ_HANDLED;
}

static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
{
	return container_of(cs, struct sh_tmu_priv, cs);
}

static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);

	return sh_tmu_read(p, TCNT) ^ 0xffffffff;
}

static int sh_tmu_clocksource_enable(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
	int ret;

	ret = sh_tmu_enable(p);
	if (!ret)
		__clocksource_updatefreq_hz(cs, p->rate);
	return ret;
}

static void sh_tmu_clocksource_disable(struct clocksource *cs)
{
	sh_tmu_disable(cs_to_sh_tmu(cs));
}

static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
				       char *name, unsigned long rating)
{
	struct clocksource *cs = &p->cs;

	cs->name = name;
	cs->rating = rating;
	cs->read = sh_tmu_clocksource_read;
	cs->enable = sh_tmu_clocksource_enable;
	cs->disable = sh_tmu_clocksource_disable;
	cs->mask = CLOCKSOURCE_MASK(32);
	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;

	dev_info(&p->pdev->dev, "used as clock source\n");

	/* Register with dummy 1 Hz value, gets updated in ->enable() */
	clocksource_register_hz(cs, 1);
	return 0;
}

static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
{
	return container_of(ced, struct sh_tmu_priv, ced);
}

static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
{
	struct clock_event_device *ced = &p->ced;

	sh_tmu_enable(p);

	/* TODO: calculate good shift from rate and counter bit width */

	ced->shift = 32;
	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
	ced->min_delta_ns = 5000;

	if (periodic) {
		p->periodic = (p->rate + HZ/2) / HZ;
		sh_tmu_set_next(p, p->periodic, 1);
	}
}

static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
				    struct clock_event_device *ced)
{
	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
	int disabled = 0;

	/* deal with old setting first */
	switch (ced->mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
		sh_tmu_disable(p);
		disabled = 1;
		break;
	default:
		break;
	}

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		dev_info(&p->pdev->dev, "used for periodic clock events\n");
		sh_tmu_clock_event_start(p, 1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		dev_info(&p->pdev->dev, "used for oneshot clock events\n");
		sh_tmu_clock_event_start(p, 0);
		break;
	case CLOCK_EVT_MODE_UNUSED:
		if (!disabled)
			sh_tmu_disable(p);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		break;
	}
}

static int sh_tmu_clock_event_next(unsigned long delta,
				   struct clock_event_device *ced)
{
	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);

	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);

	/* program new delta value */
	sh_tmu_set_next(p, delta, 0);
	return 0;
}

static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
				       char *name, unsigned long rating)
{
	struct clock_event_device *ced = &p->ced;
	int ret;

	memset(ced, 0, sizeof(*ced));

	ced->name = name;
	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	ced->features |= CLOCK_EVT_FEAT_ONESHOT;
	ced->rating = rating;
	ced->cpumask = cpumask_of(0);
	ced->set_next_event = sh_tmu_clock_event_next;
	ced->set_mode = sh_tmu_clock_event_mode;

	dev_info(&p->pdev->dev, "used for clock events\n");
	clockevents_register_device(ced);

	ret = setup_irq(p->irqaction.irq, &p->irqaction);
	if (ret) {
		dev_err(&p->pdev->dev, "failed to request irq %d\n",
			p->irqaction.irq);
		return;
	}
}

static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
		    unsigned long clockevent_rating,
		    unsigned long clocksource_rating)
{
	if (clockevent_rating)
		sh_tmu_register_clockevent(p, name, clockevent_rating);
	else if (clocksource_rating)
		sh_tmu_register_clocksource(p, name, clocksource_rating);

	return 0;
}

static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
{
	struct sh_timer_config *cfg = pdev->dev.platform_data;
	struct resource *res;
	int irq, ret;
	ret = -ENXIO;

	memset(p, 0, sizeof(*p));
	p->pdev = pdev;

	if (!cfg) {
		dev_err(&p->pdev->dev, "missing platform data\n");
		goto err0;
	}

	platform_set_drvdata(pdev, p);

	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&p->pdev->dev, "failed to get I/O memory\n");
		goto err0;
	}

	irq = platform_get_irq(p->pdev, 0);
	if (irq < 0) {
		dev_err(&p->pdev->dev, "failed to get irq\n");
		goto err0;
	}

	/* map memory, let mapbase point to our channel */
	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	if (p->mapbase == NULL) {
		dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
		goto err0;
	}

	/* setup data for setup_irq() (too early for request_irq()) */
	p->irqaction.name = dev_name(&p->pdev->dev);
	p->irqaction.handler = sh_tmu_interrupt;
	p->irqaction.dev_id = p;
	p->irqaction.irq = irq;
	p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
			     IRQF_IRQPOLL  | IRQF_NOBALANCING;

	/* get hold of clock */
	p->clk = clk_get(&p->pdev->dev, "tmu_fck");
	if (IS_ERR(p->clk)) {
		dev_err(&p->pdev->dev, "cannot get clock\n");
		ret = PTR_ERR(p->clk);
		goto err1;
	}

	return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
			       cfg->clockevent_rating,
			       cfg->clocksource_rating);
 err1:
	iounmap(p->mapbase);
 err0:
	return ret;
}

static int __devinit sh_tmu_probe(struct platform_device *pdev)
{
	struct sh_tmu_priv *p = platform_get_drvdata(pdev);
	int ret;

	if (!is_early_platform_device(pdev))
		pm_genpd_dev_always_on(&pdev->dev, true);

	if (p) {
		dev_info(&pdev->dev, "kept as earlytimer\n");
		return 0;
	}

	p = kmalloc(sizeof(*p), GFP_KERNEL);
	if (p == NULL) {
		dev_err(&pdev->dev, "failed to allocate driver data\n");
		return -ENOMEM;
	}

	ret = sh_tmu_setup(p, pdev);
	if (ret) {
		kfree(p);
		platform_set_drvdata(pdev, NULL);
	}
	return ret;
}

static int __devexit sh_tmu_remove(struct platform_device *pdev)
{
	return -EBUSY; /* cannot unregister clockevent and clocksource */
}

static struct platform_driver sh_tmu_device_driver = {
	.probe		= sh_tmu_probe,
	.remove		= __devexit_p(sh_tmu_remove),
	.driver		= {
		.name	= "sh_tmu",
	}
};

static int __init sh_tmu_init(void)
{
	return platform_driver_register(&sh_tmu_device_driver);
}

static void __exit sh_tmu_exit(void)
{
	platform_driver_unregister(&sh_tmu_device_driver);
}

early_platform_init("earlytimer", &sh_tmu_device_driver);
module_init(sh_tmu_init);
module_exit(sh_tmu_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("SuperH TMU Timer Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9570ef20 MD	1	/*
	2	* SuperH Timer Support - TMU
	3	*
	4	* Copyright (C) 2009 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
	25	#include <linux/delay.h>
	26	#include <linux/io.h>
	27	#include <linux/clk.h>
	28	#include <linux/irq.h>
	29	#include <linux/err.h>
	30	#include <linux/clocksource.h>
	31	#include <linux/clockchips.h>
46a12f74	32	#include <linux/sh_timer.h>
5a0e3ad6	33	#include <linux/slab.h>
7deeab5d	34	#include <linux/module.h>
2ee619f9	35	#include <linux/pm_domain.h>
9570ef20 MD	36
	37	struct sh_tmu_priv {
	38	void __iomem *mapbase;
	39	struct clk *clk;
	40	struct irqaction irqaction;
	41	struct platform_device *pdev;
	42	unsigned long rate;
	43	unsigned long periodic;
	44	struct clock_event_device ced;
	45	struct clocksource cs;
	46	};
	47
	48	static DEFINE_SPINLOCK(sh_tmu_lock);
	49
	50	#define TSTR -1 /* shared register */
	51	#define TCOR 0 /* channel register */
	52	#define TCNT 1 /* channel register */
	53	#define TCR 2 /* channel register */
	54
	55	static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
	56	{
46a12f74	57	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
9570ef20 MD	58	void __iomem *base = p->mapbase;
	59	unsigned long offs;
	60
	61	if (reg_nr == TSTR)
	62	return ioread8(base - cfg->channel_offset);
	63
	64	offs = reg_nr << 2;
	65
	66	if (reg_nr == TCR)
	67	return ioread16(base + offs);
	68	else
	69	return ioread32(base + offs);
	70	}
	71
	72	static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
	73	unsigned long value)
	74	{
46a12f74	75	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
9570ef20 MD	76	void __iomem *base = p->mapbase;
	77	unsigned long offs;
	78
	79	if (reg_nr == TSTR) {
	80	iowrite8(value, base - cfg->channel_offset);
	81	return;
	82	}
	83
	84	offs = reg_nr << 2;
	85
	86	if (reg_nr == TCR)
	87	iowrite16(value, base + offs);
	88	else
	89	iowrite32(value, base + offs);
	90	}
	91
	92	static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
	93	{
46a12f74	94	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
9570ef20 MD	95	unsigned long flags, value;
	96
	97	/* start stop register shared by multiple timer channels */
	98	spin_lock_irqsave(&sh_tmu_lock, flags);
	99	value = sh_tmu_read(p, TSTR);
	100
	101	if (start)
	102	value \|= 1 << cfg->timer_bit;
	103	else
	104	value &= ~(1 << cfg->timer_bit);
	105
	106	sh_tmu_write(p, TSTR, value);
	107	spin_unlock_irqrestore(&sh_tmu_lock, flags);
	108	}
	109
	110	static int sh_tmu_enable(struct sh_tmu_priv *p)
	111	{
9570ef20 MD	112	int ret;
9570ef20 MD	113
d4905ce3	114	/* enable clock */
9570ef20 MD	115	ret = clk_enable(p->clk);
9570ef20 MD	116	if (ret) {
214a607a	117	dev_err(&p->pdev->dev, "cannot enable clock\n");
9570ef20 MD	118	return ret;
	119	}
	120
	121	/* make sure channel is disabled */
	122	sh_tmu_start_stop_ch(p, 0);
	123
	124	/* maximum timeout */
	125	sh_tmu_write(p, TCOR, 0xffffffff);
	126	sh_tmu_write(p, TCNT, 0xffffffff);
	127
	128	/* configure channel to parent clock / 4, irq off */
	129	p->rate = clk_get_rate(p->clk) / 4;
	130	sh_tmu_write(p, TCR, 0x0000);
	131
	132	/* enable channel */
	133	sh_tmu_start_stop_ch(p, 1);
	134
	135	return 0;
	136	}
	137
	138	static void sh_tmu_disable(struct sh_tmu_priv *p)
	139	{
	140	/* disable channel */
	141	sh_tmu_start_stop_ch(p, 0);
	142
be890a1a MD	143	/* disable interrupts in TMU block */
	144	sh_tmu_write(p, TCR, 0x0000);
	145
d4905ce3	146	/* stop clock */
9570ef20 MD	147	clk_disable(p->clk);
	148	}
	149
	150	static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
	151	int periodic)
	152	{
	153	/* stop timer */
	154	sh_tmu_start_stop_ch(p, 0);
	155
	156	/* acknowledge interrupt */
	157	sh_tmu_read(p, TCR);
	158
	159	/* enable interrupt */
	160	sh_tmu_write(p, TCR, 0x0020);
	161
	162	/* reload delta value in case of periodic timer */
	163	if (periodic)
	164	sh_tmu_write(p, TCOR, delta);
	165	else
6f4b67b8	166	sh_tmu_write(p, TCOR, 0xffffffff);
9570ef20 MD	167
	168	sh_tmu_write(p, TCNT, delta);
	169
	170	/* start timer */
	171	sh_tmu_start_stop_ch(p, 1);
	172	}
	173
	174	static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
	175	{
	176	struct sh_tmu_priv *p = dev_id;
	177
	178	/* disable or acknowledge interrupt */
	179	if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
	180	sh_tmu_write(p, TCR, 0x0000);
	181	else
	182	sh_tmu_write(p, TCR, 0x0020);
	183
	184	/* notify clockevent layer */
	185	p->ced.event_handler(&p->ced);
	186	return IRQ_HANDLED;
	187	}
	188
	189	static struct sh_tmu_priv cs_to_sh_tmu(struct clocksource cs)
	190	{
	191	return container_of(cs, struct sh_tmu_priv, cs);
	192	}
	193
	194	static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
	195	{
	196	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
	197
	198	return sh_tmu_read(p, TCNT) ^ 0xffffffff;
	199	}
	200
	201	static int sh_tmu_clocksource_enable(struct clocksource *cs)
	202	{
	203	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
0aeac458	204	int ret;
9570ef20	205
0aeac458 MD	206	ret = sh_tmu_enable(p);
	207	if (!ret)
	208	__clocksource_updatefreq_hz(cs, p->rate);
	209	return ret;
9570ef20 MD	210	}
	211
	212	static void sh_tmu_clocksource_disable(struct clocksource *cs)
	213	{
	214	sh_tmu_disable(cs_to_sh_tmu(cs));
	215	}
	216
	217	static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
	218	char *name, unsigned long rating)
	219	{
	220	struct clocksource *cs = &p->cs;
	221
	222	cs->name = name;
	223	cs->rating = rating;
	224	cs->read = sh_tmu_clocksource_read;
	225	cs->enable = sh_tmu_clocksource_enable;
	226	cs->disable = sh_tmu_clocksource_disable;
	227	cs->mask = CLOCKSOURCE_MASK(32);
	228	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
66f49121	229
214a607a	230	dev_info(&p->pdev->dev, "used as clock source\n");
0aeac458 MD	231
	232	/* Register with dummy 1 Hz value, gets updated in ->enable() */
	233	clocksource_register_hz(cs, 1);
9570ef20 MD	234	return 0;
	235	}
	236
	237	static struct sh_tmu_priv ced_to_sh_tmu(struct clock_event_device ced)
	238	{
	239	return container_of(ced, struct sh_tmu_priv, ced);
	240	}
	241
	242	static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
	243	{
	244	struct clock_event_device *ced = &p->ced;
	245
	246	sh_tmu_enable(p);
	247
	248	/* TODO: calculate good shift from rate and counter bit width */
	249
	250	ced->shift = 32;
	251	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	252	ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
	253	ced->min_delta_ns = 5000;
	254
	255	if (periodic) {
	256	p->periodic = (p->rate + HZ/2) / HZ;
	257	sh_tmu_set_next(p, p->periodic, 1);
	258	}
	259	}
	260
	261	static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
	262	struct clock_event_device *ced)
	263	{
	264	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
	265	int disabled = 0;
	266
	267	/* deal with old setting first */
	268	switch (ced->mode) {
	269	case CLOCK_EVT_MODE_PERIODIC:
	270	case CLOCK_EVT_MODE_ONESHOT:
	271	sh_tmu_disable(p);
	272	disabled = 1;
	273	break;
	274	default:
	275	break;
	276	}
	277
	278	switch (mode) {
	279	case CLOCK_EVT_MODE_PERIODIC:
214a607a	280	dev_info(&p->pdev->dev, "used for periodic clock events\n");
9570ef20 MD	281	sh_tmu_clock_event_start(p, 1);
	282	break;
	283	case CLOCK_EVT_MODE_ONESHOT:
214a607a	284	dev_info(&p->pdev->dev, "used for oneshot clock events\n");
9570ef20 MD	285	sh_tmu_clock_event_start(p, 0);
	286	break;
	287	case CLOCK_EVT_MODE_UNUSED:
	288	if (!disabled)
	289	sh_tmu_disable(p);
	290	break;
	291	case CLOCK_EVT_MODE_SHUTDOWN:
	292	default:
	293	break;
	294	}
	295	}
	296
	297	static int sh_tmu_clock_event_next(unsigned long delta,
	298	struct clock_event_device *ced)
	299	{
	300	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
	301
	302	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
	303
	304	/* program new delta value */
	305	sh_tmu_set_next(p, delta, 0);
	306	return 0;
	307	}
	308
	309	static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
	310	char *name, unsigned long rating)
	311	{
	312	struct clock_event_device *ced = &p->ced;
	313	int ret;
	314
	315	memset(ced, 0, sizeof(*ced));
	316
	317	ced->name = name;
	318	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	319	ced->features \|= CLOCK_EVT_FEAT_ONESHOT;
	320	ced->rating = rating;
	321	ced->cpumask = cpumask_of(0);
	322	ced->set_next_event = sh_tmu_clock_event_next;
	323	ced->set_mode = sh_tmu_clock_event_mode;
	324
214a607a	325	dev_info(&p->pdev->dev, "used for clock events\n");
da64c2a8 PM	326	clockevents_register_device(ced);
da64c2a8 PM	327
9570ef20 MD	328	ret = setup_irq(p->irqaction.irq, &p->irqaction);
9570ef20 MD	329	if (ret) {
214a607a PM	330	dev_err(&p->pdev->dev, "failed to request irq %d\n",
214a607a PM	331	p->irqaction.irq);
9570ef20 MD	332	return;
9570ef20 MD	333	}
9570ef20 MD	334	}
	335
	336	static int sh_tmu_register(struct sh_tmu_priv p, char name,
	337	unsigned long clockevent_rating,
	338	unsigned long clocksource_rating)
	339	{
	340	if (clockevent_rating)
	341	sh_tmu_register_clockevent(p, name, clockevent_rating);
	342	else if (clocksource_rating)
	343	sh_tmu_register_clocksource(p, name, clocksource_rating);
	344
	345	return 0;
	346	}
	347
	348	static int sh_tmu_setup(struct sh_tmu_priv p, struct platform_device pdev)
	349	{
46a12f74	350	struct sh_timer_config *cfg = pdev->dev.platform_data;
9570ef20 MD	351	struct resource *res;
	352	int irq, ret;
	353	ret = -ENXIO;
	354
	355	memset(p, 0, sizeof(*p));
	356	p->pdev = pdev;
	357
	358	if (!cfg) {
	359	dev_err(&p->pdev->dev, "missing platform data\n");
	360	goto err0;
	361	}
	362
	363	platform_set_drvdata(pdev, p);
	364
	365	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	366	if (!res) {
	367	dev_err(&p->pdev->dev, "failed to get I/O memory\n");
	368	goto err0;
	369	}
	370
	371	irq = platform_get_irq(p->pdev, 0);
	372	if (irq < 0) {
	373	dev_err(&p->pdev->dev, "failed to get irq\n");
	374	goto err0;
	375	}
	376
	377	/* map memory, let mapbase point to our channel */
	378	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	379	if (p->mapbase == NULL) {
214a607a	380	dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
9570ef20 MD	381	goto err0;
	382	}
	383
	384	/* setup data for setup_irq() (too early for request_irq()) */
214a607a	385	p->irqaction.name = dev_name(&p->pdev->dev);
9570ef20 MD	386	p->irqaction.handler = sh_tmu_interrupt;
	387	p->irqaction.dev_id = p;
	388	p->irqaction.irq = irq;
fecf066c PM	389	p->irqaction.flags = IRQF_DISABLED \| IRQF_TIMER \| \
fecf066c PM	390	IRQF_IRQPOLL \| IRQF_NOBALANCING;
9570ef20 MD	391
9570ef20 MD	392	/* get hold of clock */
c2a25e81	393	p->clk = clk_get(&p->pdev->dev, "tmu_fck");
9570ef20	394	if (IS_ERR(p->clk)) {
03ff858c MD	395	dev_err(&p->pdev->dev, "cannot get clock\n");
	396	ret = PTR_ERR(p->clk);
	397	goto err1;
9570ef20 MD	398	}
9570ef20 MD	399
214a607a	400	return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
9570ef20 MD	401	cfg->clockevent_rating,
	402	cfg->clocksource_rating);
	403	err1:
	404	iounmap(p->mapbase);
	405	err0:
	406	return ret;
	407	}
	408
	409	static int __devinit sh_tmu_probe(struct platform_device *pdev)
	410	{
	411	struct sh_tmu_priv *p = platform_get_drvdata(pdev);
9570ef20 MD	412	int ret;
9570ef20 MD	413
2ee619f9 RW	414	if (!is_early_platform_device(pdev))
	415	pm_genpd_dev_always_on(&pdev->dev, true);
	416
9570ef20	417	if (p) {
214a607a	418	dev_info(&pdev->dev, "kept as earlytimer\n");
9570ef20 MD	419	return 0;
	420	}
	421
	422	p = kmalloc(sizeof(*p), GFP_KERNEL);
	423	if (p == NULL) {
	424	dev_err(&pdev->dev, "failed to allocate driver data\n");
	425	return -ENOMEM;
	426	}
	427
	428	ret = sh_tmu_setup(p, pdev);
	429	if (ret) {
	430	kfree(p);
	431	platform_set_drvdata(pdev, NULL);
	432	}
	433	return ret;
	434	}
	435
	436	static int __devexit sh_tmu_remove(struct platform_device *pdev)
	437	{
	438	return -EBUSY; /* cannot unregister clockevent and clocksource */
	439	}
	440
	441	static struct platform_driver sh_tmu_device_driver = {
	442	.probe = sh_tmu_probe,
	443	.remove = __devexit_p(sh_tmu_remove),
	444	.driver = {
	445	.name = "sh_tmu",
	446	}
	447	};
	448
	449	static int __init sh_tmu_init(void)
	450	{
	451	return platform_driver_register(&sh_tmu_device_driver);
	452	}
	453
	454	static void __exit sh_tmu_exit(void)
	455	{
	456	platform_driver_unregister(&sh_tmu_device_driver);
	457	}
	458
	459	early_platform_init("earlytimer", &sh_tmu_device_driver);
	460	module_init(sh_tmu_init);
	461	module_exit(sh_tmu_exit);
	462
	463	MODULE_AUTHOR("Magnus Damm");
	464	MODULE_DESCRIPTION("SuperH TMU Timer Driver");
	465	MODULE_LICENSE("GPL v2");