[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / clocksource / sh_cmt.c

/*
 * SuperH Timer Support - CMT
 *
 *  Copyright (C) 2008 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/sh_timer.h>
#include <linux/slab.h>

struct sh_cmt_priv {
	void __iomem *mapbase;
	struct clk *clk;
	unsigned long width; /* 16 or 32 bit version of hardware block */
	unsigned long overflow_bit;
	unsigned long clear_bits;
	struct irqaction irqaction;
	struct platform_device *pdev;

	unsigned long flags;
	unsigned long match_value;
	unsigned long next_match_value;
	unsigned long max_match_value;
	unsigned long rate;
	spinlock_t lock;
	struct clock_event_device ced;
	struct clocksource cs;
	unsigned long total_cycles;
};

static DEFINE_SPINLOCK(sh_cmt_lock);

#define CMSTR -1 /* shared register */
#define CMCSR 0 /* channel register */
#define CMCNT 1 /* channel register */
#define CMCOR 2 /* channel register */

static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == CMSTR) {
		offs = 0;
		base -= cfg->channel_offset;
	} else
		offs = reg_nr;

	if (p->width == 16)
		offs <<= 1;
	else {
		offs <<= 2;
		if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
			return ioread32(base + offs);
	}

	return ioread16(base + offs);
}

static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
				unsigned long value)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == CMSTR) {
		offs = 0;
		base -= cfg->channel_offset;
	} else
		offs = reg_nr;

	if (p->width == 16)
		offs <<= 1;
	else {
		offs <<= 2;
		if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
			iowrite32(value, base + offs);
			return;
		}
	}

	iowrite16(value, base + offs);
}

static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
					int *has_wrapped)
{
	unsigned long v1, v2, v3;
	int o1, o2;

	o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;

	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	do {
		o2 = o1;
		v1 = sh_cmt_read(p, CMCNT);
		v2 = sh_cmt_read(p, CMCNT);
		v3 = sh_cmt_read(p, CMCNT);
		o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
	} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
			  || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));

	*has_wrapped = o1;
	return v2;
}


static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	unsigned long flags, value;

	/* start stop register shared by multiple timer channels */
	spin_lock_irqsave(&sh_cmt_lock, flags);
	value = sh_cmt_read(p, CMSTR);

	if (start)
		value |= 1 << cfg->timer_bit;
	else
		value &= ~(1 << cfg->timer_bit);

	sh_cmt_write(p, CMSTR, value);
	spin_unlock_irqrestore(&sh_cmt_lock, flags);
}

static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	int ret;

	/* enable clock */
	ret = clk_enable(p->clk);
	if (ret) {
		pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk);
		return ret;
	}

	/* make sure channel is disabled */
	sh_cmt_start_stop_ch(p, 0);

	/* configure channel, periodic mode and maximum timeout */
	if (p->width == 16) {
		*rate = clk_get_rate(p->clk) / 512;
		sh_cmt_write(p, CMCSR, 0x43);
	} else {
		*rate = clk_get_rate(p->clk) / 8;
		sh_cmt_write(p, CMCSR, 0x01a4);
	}

	sh_cmt_write(p, CMCOR, 0xffffffff);
	sh_cmt_write(p, CMCNT, 0);

	/* enable channel */
	sh_cmt_start_stop_ch(p, 1);
	return 0;
}

static void sh_cmt_disable(struct sh_cmt_priv *p)
{
	/* disable channel */
	sh_cmt_start_stop_ch(p, 0);

	/* disable interrupts in CMT block */
	sh_cmt_write(p, CMCSR, 0);

	/* stop clock */
	clk_disable(p->clk);
}

/* private flags */
#define FLAG_CLOCKEVENT (1 << 0)
#define FLAG_CLOCKSOURCE (1 << 1)
#define FLAG_REPROGRAM (1 << 2)
#define FLAG_SKIPEVENT (1 << 3)
#define FLAG_IRQCONTEXT (1 << 4)

static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
					      int absolute)
{
	unsigned long new_match;
	unsigned long value = p->next_match_value;
	unsigned long delay = 0;
	unsigned long now = 0;
	int has_wrapped;

	now = sh_cmt_get_counter(p, &has_wrapped);
	p->flags |= FLAG_REPROGRAM; /* force reprogram */

	if (has_wrapped) {
		/* we're competing with the interrupt handler.
		 *  -> let the interrupt handler reprogram the timer.
		 *  -> interrupt number two handles the event.
		 */
		p->flags |= FLAG_SKIPEVENT;
		return;
	}

	if (absolute)
		now = 0;

	do {
		/* reprogram the timer hardware,
		 * but don't save the new match value yet.
		 */
		new_match = now + value + delay;
		if (new_match > p->max_match_value)
			new_match = p->max_match_value;

		sh_cmt_write(p, CMCOR, new_match);

		now = sh_cmt_get_counter(p, &has_wrapped);
		if (has_wrapped && (new_match > p->match_value)) {
			/* we are changing to a greater match value,
			 * so this wrap must be caused by the counter
			 * matching the old value.
			 * -> first interrupt reprograms the timer.
			 * -> interrupt number two handles the event.
			 */
			p->flags |= FLAG_SKIPEVENT;
			break;
		}

		if (has_wrapped) {
			/* we are changing to a smaller match value,
			 * so the wrap must be caused by the counter
			 * matching the new value.
			 * -> save programmed match value.
			 * -> let isr handle the event.
			 */
			p->match_value = new_match;
			break;
		}

		/* be safe: verify hardware settings */
		if (now < new_match) {
			/* timer value is below match value, all good.
			 * this makes sure we won't miss any match events.
			 * -> save programmed match value.
			 * -> let isr handle the event.
			 */
			p->match_value = new_match;
			break;
		}

		/* the counter has reached a value greater
		 * than our new match value. and since the
		 * has_wrapped flag isn't set we must have
		 * programmed a too close event.
		 * -> increase delay and retry.
		 */
		if (delay)
			delay <<= 1;
		else
			delay = 1;

		if (!delay)
			pr_warning("sh_cmt: too long delay\n");

	} while (delay);
}

static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
{
	unsigned long flags;

	if (delta > p->max_match_value)
		pr_warning("sh_cmt: delta out of range\n");

	spin_lock_irqsave(&p->lock, flags);
	p->next_match_value = delta;
	sh_cmt_clock_event_program_verify(p, 0);
	spin_unlock_irqrestore(&p->lock, flags);
}

static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
{
	struct sh_cmt_priv *p = dev_id;

	/* clear flags */
	sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);

	/* update clock source counter to begin with if enabled
	 * the wrap flag should be cleared by the timer specific
	 * isr before we end up here.
	 */
	if (p->flags & FLAG_CLOCKSOURCE)
		p->total_cycles += p->match_value;

	if (!(p->flags & FLAG_REPROGRAM))
		p->next_match_value = p->max_match_value;

	p->flags |= FLAG_IRQCONTEXT;

	if (p->flags & FLAG_CLOCKEVENT) {
		if (!(p->flags & FLAG_SKIPEVENT)) {
			if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
				p->next_match_value = p->max_match_value;
				p->flags |= FLAG_REPROGRAM;
			}

			p->ced.event_handler(&p->ced);
		}
	}

	p->flags &= ~FLAG_SKIPEVENT;

	if (p->flags & FLAG_REPROGRAM) {
		p->flags &= ~FLAG_REPROGRAM;
		sh_cmt_clock_event_program_verify(p, 1);

		if (p->flags & FLAG_CLOCKEVENT)
			if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
			    || (p->match_value == p->next_match_value))
				p->flags &= ~FLAG_REPROGRAM;
	}

	p->flags &= ~FLAG_IRQCONTEXT;

	return IRQ_HANDLED;
}

static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
{
	int ret = 0;
	unsigned long flags;

	spin_lock_irqsave(&p->lock, flags);

	if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
		ret = sh_cmt_enable(p, &p->rate);

	if (ret)
		goto out;
	p->flags |= flag;

	/* setup timeout if no clockevent */
	if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
		sh_cmt_set_next(p, p->max_match_value);
 out:
	spin_unlock_irqrestore(&p->lock, flags);

	return ret;
}

static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
{
	unsigned long flags;
	unsigned long f;

	spin_lock_irqsave(&p->lock, flags);

	f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
	p->flags &= ~flag;

	if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
		sh_cmt_disable(p);

	/* adjust the timeout to maximum if only clocksource left */
	if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
		sh_cmt_set_next(p, p->max_match_value);

	spin_unlock_irqrestore(&p->lock, flags);
}

static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
{
	return container_of(cs, struct sh_cmt_priv, cs);
}

static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
{
	struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
	unsigned long flags, raw;
	unsigned long value;
	int has_wrapped;

	spin_lock_irqsave(&p->lock, flags);
	value = p->total_cycles;
	raw = sh_cmt_get_counter(p, &has_wrapped);

	if (unlikely(has_wrapped))
		raw += p->match_value;
	spin_unlock_irqrestore(&p->lock, flags);

	return value + raw;
}

static int sh_cmt_clocksource_enable(struct clocksource *cs)
{
	struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
	int ret;

	p->total_cycles = 0;

	ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
	if (ret)
		return ret;

	/* TODO: calculate good shift from rate and counter bit width */
	cs->shift = 0;
	cs->mult = clocksource_hz2mult(p->rate, cs->shift);
	return 0;
}

static void sh_cmt_clocksource_disable(struct clocksource *cs)
{
	sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
}

static void sh_cmt_clocksource_resume(struct clocksource *cs)
{
	sh_cmt_start(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
}

static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
				       char *name, unsigned long rating)
{
	struct clocksource *cs = &p->cs;

	cs->name = name;
	cs->rating = rating;
	cs->read = sh_cmt_clocksource_read;
	cs->enable = sh_cmt_clocksource_enable;
	cs->disable = sh_cmt_clocksource_disable;
	cs->suspend = sh_cmt_clocksource_disable;
	cs->resume = sh_cmt_clocksource_resume;
	cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
	pr_info("sh_cmt: %s used as clock source\n", cs->name);
	clocksource_register(cs);
	return 0;
}

static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
{
	return container_of(ced, struct sh_cmt_priv, ced);
}

static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
{
	struct clock_event_device *ced = &p->ced;

	sh_cmt_start(p, FLAG_CLOCKEVENT);

	/* TODO: calculate good shift from rate and counter bit width */

	ced->shift = 32;
	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
	ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);

	if (periodic)
		sh_cmt_set_next(p, (p->rate + HZ/2) / HZ);
	else
		sh_cmt_set_next(p, p->max_match_value);
}

static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
				    struct clock_event_device *ced)
{
	struct sh_cmt_priv *p = ced_to_sh_cmt(ced);

	/* deal with old setting first */
	switch (ced->mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
		sh_cmt_stop(p, FLAG_CLOCKEVENT);
		break;
	default:
		break;
	}

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		pr_info("sh_cmt: %s used for periodic clock events\n",
			ced->name);
		sh_cmt_clock_event_start(p, 1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		pr_info("sh_cmt: %s used for oneshot clock events\n",
			ced->name);
		sh_cmt_clock_event_start(p, 0);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
		sh_cmt_stop(p, FLAG_CLOCKEVENT);
		break;
	default:
		break;
	}
}

static int sh_cmt_clock_event_next(unsigned long delta,
				   struct clock_event_device *ced)
{
	struct sh_cmt_priv *p = ced_to_sh_cmt(ced);

	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
	if (likely(p->flags & FLAG_IRQCONTEXT))
		p->next_match_value = delta;
	else
		sh_cmt_set_next(p, delta);

	return 0;
}

static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
				       char *name, unsigned long rating)
{
	struct clock_event_device *ced = &p->ced;

	memset(ced, 0, sizeof(*ced));

	ced->name = name;
	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	ced->features |= CLOCK_EVT_FEAT_ONESHOT;
	ced->rating = rating;
	ced->cpumask = cpumask_of(0);
	ced->set_next_event = sh_cmt_clock_event_next;
	ced->set_mode = sh_cmt_clock_event_mode;

	pr_info("sh_cmt: %s used for clock events\n", ced->name);
	clockevents_register_device(ced);
}

static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
			   unsigned long clockevent_rating,
			   unsigned long clocksource_rating)
{
	if (p->width == (sizeof(p->max_match_value) * 8))
		p->max_match_value = ~0;
	else
		p->max_match_value = (1 << p->width) - 1;

	p->match_value = p->max_match_value;
	spin_lock_init(&p->lock);

	if (clockevent_rating)
		sh_cmt_register_clockevent(p, name, clockevent_rating);

	if (clocksource_rating)
		sh_cmt_register_clocksource(p, name, clocksource_rating);

	return 0;
}

static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
{
	struct sh_timer_config *cfg = pdev->dev.platform_data;
	struct resource *res;
	int irq, ret;
	ret = -ENXIO;

	memset(p, 0, sizeof(*p));
	p->pdev = pdev;

	if (!cfg) {
		dev_err(&p->pdev->dev, "missing platform data\n");
		goto err0;
	}

	platform_set_drvdata(pdev, p);

	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&p->pdev->dev, "failed to get I/O memory\n");
		goto err0;
	}

	irq = platform_get_irq(p->pdev, 0);
	if (irq < 0) {
		dev_err(&p->pdev->dev, "failed to get irq\n");
		goto err0;
	}

	/* map memory, let mapbase point to our channel */
	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	if (p->mapbase == NULL) {
		pr_err("sh_cmt: failed to remap I/O memory\n");
		goto err0;
	}

	/* request irq using setup_irq() (too early for request_irq()) */
	p->irqaction.name = cfg->name;
	p->irqaction.handler = sh_cmt_interrupt;
	p->irqaction.dev_id = p;
	p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;

	/* get hold of clock */
	p->clk = clk_get(&p->pdev->dev, cfg->clk);
	if (IS_ERR(p->clk)) {
		pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk);
		ret = PTR_ERR(p->clk);
		goto err1;
	}

	if (resource_size(res) == 6) {
		p->width = 16;
		p->overflow_bit = 0x80;
		p->clear_bits = ~0x80;
	} else {
		p->width = 32;
		p->overflow_bit = 0x8000;
		p->clear_bits = ~0xc000;
	}

	ret = sh_cmt_register(p, cfg->name,
			      cfg->clockevent_rating,
			      cfg->clocksource_rating);
	if (ret) {
		pr_err("sh_cmt: registration failed\n");
		goto err1;
	}

	ret = setup_irq(irq, &p->irqaction);
	if (ret) {
		pr_err("sh_cmt: failed to request irq %d\n", irq);
		goto err1;
	}

	return 0;

err1:
	iounmap(p->mapbase);
err0:
	return ret;
}

static int __devinit sh_cmt_probe(struct platform_device *pdev)
{
	struct sh_cmt_priv *p = platform_get_drvdata(pdev);
	struct sh_timer_config *cfg = pdev->dev.platform_data;
	int ret;

	if (p) {
		pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name);
		return 0;
	}

	p = kmalloc(sizeof(*p), GFP_KERNEL);
	if (p == NULL) {
		dev_err(&pdev->dev, "failed to allocate driver data\n");
		return -ENOMEM;
	}

	ret = sh_cmt_setup(p, pdev);
	if (ret) {
		kfree(p);
		platform_set_drvdata(pdev, NULL);
	}
	return ret;
}

static int __devexit sh_cmt_remove(struct platform_device *pdev)
{
	return -EBUSY; /* cannot unregister clockevent and clocksource */
}

static struct platform_driver sh_cmt_device_driver = {
	.probe		= sh_cmt_probe,
	.remove		= __devexit_p(sh_cmt_remove),
	.driver		= {
		.name	= "sh_cmt",
	}
};

static int __init sh_cmt_init(void)
{
	return platform_driver_register(&sh_cmt_device_driver);
}

static void __exit sh_cmt_exit(void)
{
	platform_driver_unregister(&sh_cmt_device_driver);
}

early_platform_init("earlytimer", &sh_cmt_device_driver);
module_init(sh_cmt_init);
module_exit(sh_cmt_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("SuperH CMT Timer Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
3fb1b6ad MD	1	/*
	2	* SuperH Timer Support - CMT
	3	*
	4	* Copyright (C) 2008 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/init.h>
3fb1b6ad MD	21	#include <linux/platform_device.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
	25	#include <linux/io.h>
	26	#include <linux/clk.h>
	27	#include <linux/irq.h>
	28	#include <linux/err.h>
	29	#include <linux/clocksource.h>
	30	#include <linux/clockchips.h>
46a12f74	31	#include <linux/sh_timer.h>
5a0e3ad6	32	#include <linux/slab.h>
3fb1b6ad MD	33
	34	struct sh_cmt_priv {
	35	void __iomem *mapbase;
	36	struct clk *clk;
	37	unsigned long width; /* 16 or 32 bit version of hardware block */
	38	unsigned long overflow_bit;
	39	unsigned long clear_bits;
	40	struct irqaction irqaction;
	41	struct platform_device *pdev;
	42
	43	unsigned long flags;
	44	unsigned long match_value;
	45	unsigned long next_match_value;
	46	unsigned long max_match_value;
	47	unsigned long rate;
	48	spinlock_t lock;
	49	struct clock_event_device ced;
19bdc9d0	50	struct clocksource cs;
3fb1b6ad MD	51	unsigned long total_cycles;
	52	};
	53
	54	static DEFINE_SPINLOCK(sh_cmt_lock);
	55
	56	#define CMSTR -1 /* shared register */
	57	#define CMCSR 0 /* channel register */
	58	#define CMCNT 1 /* channel register */
	59	#define CMCOR 2 /* channel register */
	60
	61	static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
	62	{
46a12f74	63	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
3fb1b6ad MD	64	void __iomem *base = p->mapbase;
	65	unsigned long offs;
	66
	67	if (reg_nr == CMSTR) {
	68	offs = 0;
	69	base -= cfg->channel_offset;
	70	} else
	71	offs = reg_nr;
	72
	73	if (p->width == 16)
	74	offs <<= 1;
	75	else {
	76	offs <<= 2;
	77	if ((reg_nr == CMCNT) \|\| (reg_nr == CMCOR))
	78	return ioread32(base + offs);
	79	}
	80
	81	return ioread16(base + offs);
	82	}
	83
	84	static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
	85	unsigned long value)
	86	{
46a12f74	87	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
3fb1b6ad MD	88	void __iomem *base = p->mapbase;
	89	unsigned long offs;
	90
	91	if (reg_nr == CMSTR) {
	92	offs = 0;
	93	base -= cfg->channel_offset;
	94	} else
	95	offs = reg_nr;
	96
	97	if (p->width == 16)
	98	offs <<= 1;
	99	else {
	100	offs <<= 2;
	101	if ((reg_nr == CMCNT) \|\| (reg_nr == CMCOR)) {
	102	iowrite32(value, base + offs);
	103	return;
	104	}
	105	}
	106
	107	iowrite16(value, base + offs);
	108	}
	109
	110	static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
	111	int *has_wrapped)
	112	{
	113	unsigned long v1, v2, v3;
5b644c7a MD	114	int o1, o2;
	115
	116	o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
3fb1b6ad MD	117
	118	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	119	do {
5b644c7a	120	o2 = o1;
3fb1b6ad MD	121	v1 = sh_cmt_read(p, CMCNT);
	122	v2 = sh_cmt_read(p, CMCNT);
	123	v3 = sh_cmt_read(p, CMCNT);
5b644c7a MD	124	o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
	125	} while (unlikely((o1 != o2) \|\| (v1 > v2 && v1 < v3)
	126	\|\| (v2 > v3 && v2 < v1) \|\| (v3 > v1 && v3 < v2)));
3fb1b6ad	127
5b644c7a	128	*has_wrapped = o1;
3fb1b6ad MD	129	return v2;
	130	}
	131
	132
	133	static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
	134	{
46a12f74	135	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
3fb1b6ad MD	136	unsigned long flags, value;
	137
	138	/* start stop register shared by multiple timer channels */
	139	spin_lock_irqsave(&sh_cmt_lock, flags);
	140	value = sh_cmt_read(p, CMSTR);
	141
	142	if (start)
	143	value \|= 1 << cfg->timer_bit;
	144	else
	145	value &= ~(1 << cfg->timer_bit);
	146
	147	sh_cmt_write(p, CMSTR, value);
	148	spin_unlock_irqrestore(&sh_cmt_lock, flags);
	149	}
	150
	151	static int sh_cmt_enable(struct sh_cmt_priv p, unsigned long rate)
	152	{
46a12f74	153	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
3fb1b6ad MD	154	int ret;
	155
	156	/* enable clock */
	157	ret = clk_enable(p->clk);
	158	if (ret) {
	159	pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk);
	160	return ret;
	161	}
3fb1b6ad MD	162
	163	/* make sure channel is disabled */
	164	sh_cmt_start_stop_ch(p, 0);
	165
	166	/* configure channel, periodic mode and maximum timeout */
3014f474 MD	167	if (p->width == 16) {
	168	*rate = clk_get_rate(p->clk) / 512;
	169	sh_cmt_write(p, CMCSR, 0x43);
	170	} else {
	171	*rate = clk_get_rate(p->clk) / 8;
3fb1b6ad	172	sh_cmt_write(p, CMCSR, 0x01a4);
3014f474	173	}
3fb1b6ad MD	174
	175	sh_cmt_write(p, CMCOR, 0xffffffff);
	176	sh_cmt_write(p, CMCNT, 0);
	177
	178	/* enable channel */
	179	sh_cmt_start_stop_ch(p, 1);
	180	return 0;
	181	}
	182
	183	static void sh_cmt_disable(struct sh_cmt_priv *p)
	184	{
	185	/* disable channel */
	186	sh_cmt_start_stop_ch(p, 0);
	187
be890a1a MD	188	/* disable interrupts in CMT block */
	189	sh_cmt_write(p, CMCSR, 0);
	190
3fb1b6ad MD	191	/* stop clock */
	192	clk_disable(p->clk);
	193	}
	194
	195	/* private flags */
	196	#define FLAG_CLOCKEVENT (1 << 0)
	197	#define FLAG_CLOCKSOURCE (1 << 1)
	198	#define FLAG_REPROGRAM (1 << 2)
	199	#define FLAG_SKIPEVENT (1 << 3)
	200	#define FLAG_IRQCONTEXT (1 << 4)
	201
	202	static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
	203	int absolute)
	204	{
	205	unsigned long new_match;
	206	unsigned long value = p->next_match_value;
	207	unsigned long delay = 0;
	208	unsigned long now = 0;
	209	int has_wrapped;
	210
	211	now = sh_cmt_get_counter(p, &has_wrapped);
	212	p->flags \|= FLAG_REPROGRAM; /* force reprogram */
	213
	214	if (has_wrapped) {
	215	/* we're competing with the interrupt handler.
	216	* -> let the interrupt handler reprogram the timer.
	217	* -> interrupt number two handles the event.
	218	*/
	219	p->flags \|= FLAG_SKIPEVENT;
	220	return;
	221	}
	222
	223	if (absolute)
	224	now = 0;
	225
	226	do {
	227	/* reprogram the timer hardware,
	228	* but don't save the new match value yet.
	229	*/
	230	new_match = now + value + delay;
	231	if (new_match > p->max_match_value)
	232	new_match = p->max_match_value;
	233
	234	sh_cmt_write(p, CMCOR, new_match);
	235
	236	now = sh_cmt_get_counter(p, &has_wrapped);
	237	if (has_wrapped && (new_match > p->match_value)) {
	238	/* we are changing to a greater match value,
	239	* so this wrap must be caused by the counter
	240	* matching the old value.
	241	* -> first interrupt reprograms the timer.
	242	* -> interrupt number two handles the event.
	243	*/
	244	p->flags \|= FLAG_SKIPEVENT;
	245	break;
	246	}
	247
	248	if (has_wrapped) {
	249	/* we are changing to a smaller match value,
	250	* so the wrap must be caused by the counter
	251	* matching the new value.
	252	* -> save programmed match value.
	253	* -> let isr handle the event.
	254	*/
255	p->match_value = new_match;
256	break;
257	}
258
259	/* be safe: verify hardware settings */
260	if (now < new_match) {
261	/* timer value is below match value, all good.
262	* this makes sure we won't miss any match events.
263	* -> save programmed match value.
264	* -> let isr handle the event.
265	*/
266	p->match_value = new_match;
267	break;
268	}
269
270	/* the counter has reached a value greater
271	* than our new match value. and since the
272	* has_wrapped flag isn't set we must have
273	* programmed a too close event.
274	* -> increase delay and retry.
275	*/
276	if (delay)
277	delay <<= 1;
278	else
279	delay = 1;
280
281	if (!delay)
282	pr_warning("sh_cmt: too long delay\n");
283
284	} while (delay);
285	}
286
287	static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
288	{
289	unsigned long flags;
290
291	if (delta > p->max_match_value)
292	pr_warning("sh_cmt: delta out of range\n");
293
294	spin_lock_irqsave(&p->lock, flags);
295	p->next_match_value = delta;
296	sh_cmt_clock_event_program_verify(p, 0);
297	spin_unlock_irqrestore(&p->lock, flags);
298	}
299
300	static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
301	{
302	struct sh_cmt_priv *p = dev_id;
303
304	/* clear flags */
305	sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
306
307	/* update clock source counter to begin with if enabled
308	* the wrap flag should be cleared by the timer specific
309	* isr before we end up here.
310	*/
311	if (p->flags & FLAG_CLOCKSOURCE)
312	p->total_cycles += p->match_value;
313
314	if (!(p->flags & FLAG_REPROGRAM))
315	p->next_match_value = p->max_match_value;
316
317	p->flags \|= FLAG_IRQCONTEXT;
318
319	if (p->flags & FLAG_CLOCKEVENT) {
320	if (!(p->flags & FLAG_SKIPEVENT)) {
321	if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
322	p->next_match_value = p->max_match_value;
323	p->flags \|= FLAG_REPROGRAM;
324	}
325
326	p->ced.event_handler(&p->ced);
327	}
328	}
329
330	p->flags &= ~FLAG_SKIPEVENT;
331
332	if (p->flags & FLAG_REPROGRAM) {
333	p->flags &= ~FLAG_REPROGRAM;
334	sh_cmt_clock_event_program_verify(p, 1);
335
336	if (p->flags & FLAG_CLOCKEVENT)
337	if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
338	\|\| (p->match_value == p->next_match_value))
339	p->flags &= ~FLAG_REPROGRAM;
340	}
341
342	p->flags &= ~FLAG_IRQCONTEXT;
343
344	return IRQ_HANDLED;
345	}
346
347	static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
348	{
349	int ret = 0;
350	unsigned long flags;
351
352	spin_lock_irqsave(&p->lock, flags);
353
354	if (!(p->flags & (FLAG_CLOCKEVENT \| FLAG_CLOCKSOURCE)))
355	ret = sh_cmt_enable(p, &p->rate);
356
357	if (ret)
358	goto out;
359	p->flags \|= flag;
360
361	/* setup timeout if no clockevent */
362	if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
363	sh_cmt_set_next(p, p->max_match_value);
364	out:
365	spin_unlock_irqrestore(&p->lock, flags);
366
367	return ret;
368	}
369
370	static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
371	{
372	unsigned long flags;
373	unsigned long f;
374
375	spin_lock_irqsave(&p->lock, flags);
376
377	f = p->flags & (FLAG_CLOCKEVENT \| FLAG_CLOCKSOURCE);
378	p->flags &= ~flag;
379
380	if (f && !(p->flags & (FLAG_CLOCKEVENT \| FLAG_CLOCKSOURCE)))
381	sh_cmt_disable(p);
382
383	/* adjust the timeout to maximum if only clocksource left */
384	if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
385	sh_cmt_set_next(p, p->max_match_value);
386
387	spin_unlock_irqrestore(&p->lock, flags);
388	}
389
19bdc9d0 MD	390	static struct sh_cmt_priv cs_to_sh_cmt(struct clocksource cs)
	391	{
	392	return container_of(cs, struct sh_cmt_priv, cs);
	393	}
	394
	395	static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
	396	{
	397	struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
	398	unsigned long flags, raw;
	399	unsigned long value;
	400	int has_wrapped;
	401
	402	spin_lock_irqsave(&p->lock, flags);
	403	value = p->total_cycles;
	404	raw = sh_cmt_get_counter(p, &has_wrapped);
	405
	406	if (unlikely(has_wrapped))
5b644c7a	407	raw += p->match_value;
19bdc9d0 MD	408	spin_unlock_irqrestore(&p->lock, flags);
	409
	410	return value + raw;
	411	}
	412
	413	static int sh_cmt_clocksource_enable(struct clocksource *cs)
	414	{
	415	struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
	416	int ret;
	417
	418	p->total_cycles = 0;
	419
	420	ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
	421	if (ret)
	422	return ret;
	423
	424	/* TODO: calculate good shift from rate and counter bit width */
	425	cs->shift = 0;
	426	cs->mult = clocksource_hz2mult(p->rate, cs->shift);
	427	return 0;
	428	}
	429
	430	static void sh_cmt_clocksource_disable(struct clocksource *cs)
	431	{
	432	sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
	433	}
	434
c8162884 MD	435	static void sh_cmt_clocksource_resume(struct clocksource *cs)
	436	{
	437	sh_cmt_start(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
	438	}
	439
19bdc9d0 MD	440	static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
	441	char *name, unsigned long rating)
	442	{
	443	struct clocksource *cs = &p->cs;
	444
	445	cs->name = name;
	446	cs->rating = rating;
	447	cs->read = sh_cmt_clocksource_read;
	448	cs->enable = sh_cmt_clocksource_enable;
	449	cs->disable = sh_cmt_clocksource_disable;
c8162884 MD	450	cs->suspend = sh_cmt_clocksource_disable;
c8162884 MD	451	cs->resume = sh_cmt_clocksource_resume;
19bdc9d0 MD	452	cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
	453	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
	454	pr_info("sh_cmt: %s used as clock source\n", cs->name);
	455	clocksource_register(cs);
	456	return 0;
	457	}
	458
3fb1b6ad MD	459	static struct sh_cmt_priv ced_to_sh_cmt(struct clock_event_device ced)
	460	{
	461	return container_of(ced, struct sh_cmt_priv, ced);
	462	}
	463
	464	static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
	465	{
	466	struct clock_event_device *ced = &p->ced;
	467
	468	sh_cmt_start(p, FLAG_CLOCKEVENT);
	469
	470	/* TODO: calculate good shift from rate and counter bit width */
	471
	472	ced->shift = 32;
	473	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	474	ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
	475	ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
	476
	477	if (periodic)
	478	sh_cmt_set_next(p, (p->rate + HZ/2) / HZ);
	479	else
	480	sh_cmt_set_next(p, p->max_match_value);
	481	}
	482
	483	static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
	484	struct clock_event_device *ced)
	485	{
	486	struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
	487
	488	/* deal with old setting first */
	489	switch (ced->mode) {
	490	case CLOCK_EVT_MODE_PERIODIC:
	491	case CLOCK_EVT_MODE_ONESHOT:
	492	sh_cmt_stop(p, FLAG_CLOCKEVENT);
	493	break;
	494	default:
	495	break;
	496	}
	497
	498	switch (mode) {
	499	case CLOCK_EVT_MODE_PERIODIC:
	500	pr_info("sh_cmt: %s used for periodic clock events\n",
	501	ced->name);
	502	sh_cmt_clock_event_start(p, 1);
	503	break;
	504	case CLOCK_EVT_MODE_ONESHOT:
	505	pr_info("sh_cmt: %s used for oneshot clock events\n",
	506	ced->name);
	507	sh_cmt_clock_event_start(p, 0);
	508	break;
	509	case CLOCK_EVT_MODE_SHUTDOWN:
	510	case CLOCK_EVT_MODE_UNUSED:
	511	sh_cmt_stop(p, FLAG_CLOCKEVENT);
	512	break;
	513	default:
	514	break;
	515	}
	516	}
	517
	518	static int sh_cmt_clock_event_next(unsigned long delta,
	519	struct clock_event_device *ced)
	520	{
	521	struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
	522
523	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
524	if (likely(p->flags & FLAG_IRQCONTEXT))
525	p->next_match_value = delta;
526	else
527	sh_cmt_set_next(p, delta);
528
529	return 0;
530	}
531
532	static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
533	char *name, unsigned long rating)
534	{
535	struct clock_event_device *ced = &p->ced;
536
537	memset(ced, 0, sizeof(*ced));
538
539	ced->name = name;
540	ced->features = CLOCK_EVT_FEAT_PERIODIC;
541	ced->features \|= CLOCK_EVT_FEAT_ONESHOT;
542	ced->rating = rating;
543	ced->cpumask = cpumask_of(0);
544	ced->set_next_event = sh_cmt_clock_event_next;
545	ced->set_mode = sh_cmt_clock_event_mode;
546
547	pr_info("sh_cmt: %s used for clock events\n", ced->name);
3fb1b6ad MD	548	clockevents_register_device(ced);
	549	}
	550
d1fcc0a8 PM	551	static int sh_cmt_register(struct sh_cmt_priv p, char name,
	552	unsigned long clockevent_rating,
	553	unsigned long clocksource_rating)
3fb1b6ad MD	554	{
	555	if (p->width == (sizeof(p->max_match_value) * 8))
	556	p->max_match_value = ~0;
	557	else
	558	p->max_match_value = (1 << p->width) - 1;
	559
	560	p->match_value = p->max_match_value;
	561	spin_lock_init(&p->lock);
	562
	563	if (clockevent_rating)
	564	sh_cmt_register_clockevent(p, name, clockevent_rating);
	565
19bdc9d0 MD	566	if (clocksource_rating)
	567	sh_cmt_register_clocksource(p, name, clocksource_rating);
	568
3fb1b6ad MD	569	return 0;
	570	}
	571
	572	static int sh_cmt_setup(struct sh_cmt_priv p, struct platform_device pdev)
	573	{
46a12f74	574	struct sh_timer_config *cfg = pdev->dev.platform_data;
3fb1b6ad MD	575	struct resource *res;
	576	int irq, ret;
	577	ret = -ENXIO;
	578
	579	memset(p, 0, sizeof(*p));
	580	p->pdev = pdev;
	581
	582	if (!cfg) {
	583	dev_err(&p->pdev->dev, "missing platform data\n");
	584	goto err0;
	585	}
	586
	587	platform_set_drvdata(pdev, p);
	588
	589	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	590	if (!res) {
	591	dev_err(&p->pdev->dev, "failed to get I/O memory\n");
	592	goto err0;
	593	}
	594
	595	irq = platform_get_irq(p->pdev, 0);
	596	if (irq < 0) {
	597	dev_err(&p->pdev->dev, "failed to get irq\n");
	598	goto err0;
	599	}
	600
	601	/* map memory, let mapbase point to our channel */
	602	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	603	if (p->mapbase == NULL) {
	604	pr_err("sh_cmt: failed to remap I/O memory\n");
	605	goto err0;
	606	}
	607
	608	/* request irq using setup_irq() (too early for request_irq()) */
	609	p->irqaction.name = cfg->name;
	610	p->irqaction.handler = sh_cmt_interrupt;
	611	p->irqaction.dev_id = p;
	612	p->irqaction.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL;
3fb1b6ad MD	613
	614	/* get hold of clock */
	615	p->clk = clk_get(&p->pdev->dev, cfg->clk);
	616	if (IS_ERR(p->clk)) {
	617	pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk);
	618	ret = PTR_ERR(p->clk);
da64c2a8	619	goto err1;
3fb1b6ad MD	620	}
	621
	622	if (resource_size(res) == 6) {
	623	p->width = 16;
	624	p->overflow_bit = 0x80;
3014f474	625	p->clear_bits = ~0x80;
3fb1b6ad MD	626	} else {
	627	p->width = 32;
	628	p->overflow_bit = 0x8000;
	629	p->clear_bits = ~0xc000;
	630	}
	631
da64c2a8 PM	632	ret = sh_cmt_register(p, cfg->name,
	633	cfg->clockevent_rating,
	634	cfg->clocksource_rating);
	635	if (ret) {
	636	pr_err("sh_cmt: registration failed\n");
	637	goto err1;
	638	}
	639
	640	ret = setup_irq(irq, &p->irqaction);
	641	if (ret) {
	642	pr_err("sh_cmt: failed to request irq %d\n", irq);
	643	goto err1;
	644	}
	645
	646	return 0;
	647
	648	err1:
3fb1b6ad	649	iounmap(p->mapbase);
da64c2a8	650	err0:
3fb1b6ad MD	651	return ret;
	652	}
	653
	654	static int __devinit sh_cmt_probe(struct platform_device *pdev)
	655	{
	656	struct sh_cmt_priv *p = platform_get_drvdata(pdev);
46a12f74	657	struct sh_timer_config *cfg = pdev->dev.platform_data;
3fb1b6ad MD	658	int ret;
3fb1b6ad MD	659
e475eedb MD	660	if (p) {
	661	pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name);
	662	return 0;
	663	}
	664
8e0b8429	665	p = kmalloc(sizeof(*p), GFP_KERNEL);
3fb1b6ad MD	666	if (p == NULL) {
	667	dev_err(&pdev->dev, "failed to allocate driver data\n");
	668	return -ENOMEM;
	669	}
	670
	671	ret = sh_cmt_setup(p, pdev);
	672	if (ret) {
8e0b8429	673	kfree(p);
3fb1b6ad MD	674	platform_set_drvdata(pdev, NULL);
	675	}
	676	return ret;
	677	}
	678
	679	static int __devexit sh_cmt_remove(struct platform_device *pdev)
	680	{
	681	return -EBUSY; /* cannot unregister clockevent and clocksource */
	682	}
	683
	684	static struct platform_driver sh_cmt_device_driver = {
	685	.probe = sh_cmt_probe,
	686	.remove = __devexit_p(sh_cmt_remove),
	687	.driver = {
	688	.name = "sh_cmt",
	689	}
	690	};
	691
	692	static int __init sh_cmt_init(void)
	693	{
	694	return platform_driver_register(&sh_cmt_device_driver);
	695	}
	696
	697	static void __exit sh_cmt_exit(void)
	698	{
	699	platform_driver_unregister(&sh_cmt_device_driver);
	700	}
	701
e475eedb	702	early_platform_init("earlytimer", &sh_cmt_device_driver);
3fb1b6ad MD	703	module_init(sh_cmt_init);
	704	module_exit(sh_cmt_exit);
	705
	706	MODULE_AUTHOR("Magnus Damm");
	707	MODULE_DESCRIPTION("SuperH CMT Timer Driver");
	708	MODULE_LICENSE("GPL v2");