[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / clocksource / exynos_mct.c

/* linux/arch/arm/mach-exynos4/mct.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4 MCT(Multi-Core Timer) support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/clocksource.h>

#include <asm/arch_timer.h>
#include <asm/localtimer.h>

#include <plat/cpu.h>

#include <mach/map.h>
#include <mach/irqs.h>
#include <asm/mach/time.h>

#define EXYNOS4_MCTREG(x)		(x)
#define EXYNOS4_MCT_G_CNT_L		EXYNOS4_MCTREG(0x100)
#define EXYNOS4_MCT_G_CNT_U		EXYNOS4_MCTREG(0x104)
#define EXYNOS4_MCT_G_CNT_WSTAT		EXYNOS4_MCTREG(0x110)
#define EXYNOS4_MCT_G_COMP0_L		EXYNOS4_MCTREG(0x200)
#define EXYNOS4_MCT_G_COMP0_U		EXYNOS4_MCTREG(0x204)
#define EXYNOS4_MCT_G_COMP0_ADD_INCR	EXYNOS4_MCTREG(0x208)
#define EXYNOS4_MCT_G_TCON		EXYNOS4_MCTREG(0x240)
#define EXYNOS4_MCT_G_INT_CSTAT		EXYNOS4_MCTREG(0x244)
#define EXYNOS4_MCT_G_INT_ENB		EXYNOS4_MCTREG(0x248)
#define EXYNOS4_MCT_G_WSTAT		EXYNOS4_MCTREG(0x24C)
#define _EXYNOS4_MCT_L_BASE		EXYNOS4_MCTREG(0x300)
#define EXYNOS4_MCT_L_BASE(x)		(_EXYNOS4_MCT_L_BASE + (0x100 * x))
#define EXYNOS4_MCT_L_MASK		(0xffffff00)

#define MCT_L_TCNTB_OFFSET		(0x00)
#define MCT_L_ICNTB_OFFSET		(0x08)
#define MCT_L_TCON_OFFSET		(0x20)
#define MCT_L_INT_CSTAT_OFFSET		(0x30)
#define MCT_L_INT_ENB_OFFSET		(0x34)
#define MCT_L_WSTAT_OFFSET		(0x40)
#define MCT_G_TCON_START		(1 << 8)
#define MCT_G_TCON_COMP0_AUTO_INC	(1 << 1)
#define MCT_G_TCON_COMP0_ENABLE		(1 << 0)
#define MCT_L_TCON_INTERVAL_MODE	(1 << 2)
#define MCT_L_TCON_INT_START		(1 << 1)
#define MCT_L_TCON_TIMER_START		(1 << 0)

#define TICK_BASE_CNT	1

enum {
	MCT_INT_SPI,
	MCT_INT_PPI
};

enum {
	MCT_G0_IRQ,
	MCT_G1_IRQ,
	MCT_G2_IRQ,
	MCT_G3_IRQ,
	MCT_L0_IRQ,
	MCT_L1_IRQ,
	MCT_L2_IRQ,
	MCT_L3_IRQ,
	MCT_NR_IRQS,
};

static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
static int mct_irqs[MCT_NR_IRQS];

struct mct_clock_event_device {
	struct clock_event_device *evt;
	unsigned long base;
	char name[10];
};

static void exynos4_mct_write(unsigned int value, unsigned long offset)
{
	unsigned long stat_addr;
	u32 mask;
	u32 i;

	__raw_writel(value, reg_base + offset);

	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
		stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
		switch (offset & EXYNOS4_MCT_L_MASK) {
		case MCT_L_TCON_OFFSET:
			mask = 1 << 3;		/* L_TCON write status */
			break;
		case MCT_L_ICNTB_OFFSET:
			mask = 1 << 1;		/* L_ICNTB write status */
			break;
		case MCT_L_TCNTB_OFFSET:
			mask = 1 << 0;		/* L_TCNTB write status */
			break;
		default:
			return;
		}
	} else {
		switch (offset) {
		case EXYNOS4_MCT_G_TCON:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 16;		/* G_TCON write status */
			break;
		case EXYNOS4_MCT_G_COMP0_L:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 0;		/* G_COMP0_L write status */
			break;
		case EXYNOS4_MCT_G_COMP0_U:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 1;		/* G_COMP0_U write status */
			break;
		case EXYNOS4_MCT_G_COMP0_ADD_INCR:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 2;		/* G_COMP0_ADD_INCR w status */
			break;
		case EXYNOS4_MCT_G_CNT_L:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 0;		/* G_CNT_L write status */
			break;
		case EXYNOS4_MCT_G_CNT_U:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 1;		/* G_CNT_U write status */
			break;
		default:
			return;
		}
	}

	/* Wait maximum 1 ms until written values are applied */
	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
		if (__raw_readl(reg_base + stat_addr) & mask) {
			__raw_writel(mask, reg_base + stat_addr);
			return;
		}

	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
}

/* Clocksource handling */
static void exynos4_mct_frc_start(u32 hi, u32 lo)
{
	u32 reg;

	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);

	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	reg |= MCT_G_TCON_START;
	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}

static cycle_t exynos4_frc_read(struct clocksource *cs)
{
	unsigned int lo, hi;
	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);

	do {
		hi = hi2;
		lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
		hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
	} while (hi != hi2);

	return ((cycle_t)hi << 32) | lo;
}

static void exynos4_frc_resume(struct clocksource *cs)
{
	exynos4_mct_frc_start(0, 0);
}

struct clocksource mct_frc = {
	.name		= "mct-frc",
	.rating		= 400,
	.read		= exynos4_frc_read,
	.mask		= CLOCKSOURCE_MASK(64),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= exynos4_frc_resume,
};

static void __init exynos4_clocksource_init(void)
{
	exynos4_mct_frc_start(0, 0);

	if (clocksource_register_hz(&mct_frc, clk_rate))
		panic("%s: can't register clocksource\n", mct_frc.name);
}

static void exynos4_mct_comp0_stop(void)
{
	unsigned int tcon;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
	tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);

	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
}

static void exynos4_mct_comp0_start(enum clock_event_mode mode,
				    unsigned long cycles)
{
	unsigned int tcon;
	cycle_t comp_cycle;

	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);

	if (mode == CLOCK_EVT_MODE_PERIODIC) {
		tcon |= MCT_G_TCON_COMP0_AUTO_INC;
		exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	}

	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);

	tcon |= MCT_G_TCON_COMP0_ENABLE;
	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
}

static int exynos4_comp_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	exynos4_mct_comp0_start(evt->mode, cycles);

	return 0;
}

static void exynos4_comp_set_mode(enum clock_event_mode mode,
				  struct clock_event_device *evt)
{
	unsigned long cycles_per_jiffy;
	exynos4_mct_comp0_stop();

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_comp0_start(mode, cycles_per_jiffy);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device mct_comp_device = {
	.name		= "mct-comp",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 250,
	.set_next_event	= exynos4_comp_set_next_event,
	.set_mode	= exynos4_comp_set_mode,
};

static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mct_comp_event_irq = {
	.name		= "mct_comp_irq",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= exynos4_mct_comp_isr,
	.dev_id		= &mct_comp_device,
};

static void exynos4_clockevent_init(void)
{
	mct_comp_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&mct_comp_device, clk_rate,
					0xf, 0xffffffff);
	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
}

#ifdef CONFIG_LOCAL_TIMERS

static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);

/* Clock event handling */
static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
{
	unsigned long tmp;
	unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;

	tmp = __raw_readl(reg_base + offset);
	if (tmp & mask) {
		tmp &= ~mask;
		exynos4_mct_write(tmp, offset);
	}
}

static void exynos4_mct_tick_start(unsigned long cycles,
				   struct mct_clock_event_device *mevt)
{
	unsigned long tmp;

	exynos4_mct_tick_stop(mevt);

	tmp = (1 << 31) | cycles;	/* MCT_L_UPDATE_ICNTB */

	/* update interrupt count buffer */
	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);

	/* enable MCT tick interrupt */
	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);

	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
	tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
	       MCT_L_TCON_INTERVAL_MODE;
	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
}

static int exynos4_tick_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);

	exynos4_mct_tick_start(cycles, mevt);

	return 0;
}

static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
					 struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	unsigned long cycles_per_jiffy;

	exynos4_mct_tick_stop(mevt);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_tick_start(cycles_per_jiffy, mevt);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
	struct clock_event_device *evt = mevt->evt;

	/*
	 * This is for supporting oneshot mode.
	 * Mct would generate interrupt periodically
	 * without explicit stopping.
	 */
	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
		exynos4_mct_tick_stop(mevt);

	/* Clear the MCT tick interrupt */
	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
		return 1;
	} else {
		return 0;
	}
}

static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
{
	struct mct_clock_event_device *mevt = dev_id;
	struct clock_event_device *evt = mevt->evt;

	exynos4_mct_tick_clear(mevt);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mct_tick0_event_irq = {
	.name		= "mct_tick0_irq",
	.flags		= IRQF_TIMER | IRQF_NOBALANCING,
	.handler	= exynos4_mct_tick_isr,
};

static struct irqaction mct_tick1_event_irq = {
	.name		= "mct_tick1_irq",
	.flags		= IRQF_TIMER | IRQF_NOBALANCING,
	.handler	= exynos4_mct_tick_isr,
};

static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt;
	unsigned int cpu = smp_processor_id();

	mevt = this_cpu_ptr(&percpu_mct_tick);
	mevt->evt = evt;

	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
	sprintf(mevt->name, "mct_tick%d", cpu);

	evt->name = mevt->name;
	evt->cpumask = cpumask_of(cpu);
	evt->set_next_event = exynos4_tick_set_next_event;
	evt->set_mode = exynos4_tick_set_mode;
	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 450;
	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
					0xf, 0x7fffffff);

	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);

	if (mct_int_type == MCT_INT_SPI) {
		if (cpu == 0) {
			mct_tick0_event_irq.dev_id = mevt;
			evt->irq = mct_irqs[MCT_L0_IRQ];
			setup_irq(evt->irq, &mct_tick0_event_irq);
		} else {
			mct_tick1_event_irq.dev_id = mevt;
			evt->irq = mct_irqs[MCT_L1_IRQ];
			setup_irq(evt->irq, &mct_tick1_event_irq);
			irq_set_affinity(evt->irq, cpumask_of(1));
		}
	} else {
		enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
	}

	return 0;
}

static void exynos4_local_timer_stop(struct clock_event_device *evt)
{
	unsigned int cpu = smp_processor_id();
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	if (mct_int_type == MCT_INT_SPI)
		if (cpu == 0)
			remove_irq(evt->irq, &mct_tick0_event_irq);
		else
			remove_irq(evt->irq, &mct_tick1_event_irq);
	else
		disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
}

static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
	.setup	= exynos4_local_timer_setup,
	.stop	= exynos4_local_timer_stop,
};
#endif /* CONFIG_LOCAL_TIMERS */

static void __init exynos4_timer_resources(struct device_node *np)
{
	struct clk *mct_clk;
	mct_clk = clk_get(NULL, "xtal");

	clk_rate = clk_get_rate(mct_clk);

	reg_base = np ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
	if (!reg_base)
		panic("%s: unable to ioremap mct address space\n", __func__);

#ifdef CONFIG_LOCAL_TIMERS
	if (mct_int_type == MCT_INT_PPI) {
		int err;

		err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
					 exynos4_mct_tick_isr, "MCT",
					 &percpu_mct_tick);
		WARN(err, "MCT: can't request IRQ %d (%d)\n",
		     mct_irqs[MCT_L0_IRQ], err);
	}

	local_timer_register(&exynos4_mct_tick_ops);
#endif /* CONFIG_LOCAL_TIMERS */
}

static const struct of_device_id exynos_mct_ids[] = {
	{ .compatible = "samsung,exynos4210-mct", .data = (void *)MCT_INT_SPI },
	{ .compatible = "samsung,exynos4412-mct", .data = (void *)MCT_INT_PPI },
};

void __init mct_init(void)
{
	struct device_node *np = NULL;
	const struct of_device_id *match;
	u32 nr_irqs, i;

#ifdef CONFIG_OF
	np = of_find_matching_node_and_match(NULL, exynos_mct_ids, &match);
#endif
	if (np) {
		mct_int_type = (u32)(match->data);

		/* This driver uses only one global timer interrupt */
		mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);

		/*
		 * Find out the number of local irqs specified. The local
		 * timer irqs are specified after the four global timer
		 * irqs are specified.
		 */
#ifdef CONFIG_OF
		nr_irqs = of_irq_count(np);
#endif
		for (i = MCT_L0_IRQ; i < nr_irqs; i++)
			mct_irqs[i] = irq_of_parse_and_map(np, i);
	} else if (soc_is_exynos4210()) {
		mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
		mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
		mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
		mct_int_type = MCT_INT_SPI;
	} else {
		panic("unable to determine mct controller type\n");
	}

	exynos4_timer_resources(np);
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}
CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init)
CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init)
Commit	Line	Data
30d8bead CY	1	/* linux/arch/arm/mach-exynos4/mct.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* EXYNOS4 MCT(Multi-Core Timer) support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/delay.h>
	21	#include <linux/percpu.h>
2edb36c4	22	#include <linux/of.h>
36ba5d52 TA	23	#include <linux/of_irq.h>
36ba5d52 TA	24	#include <linux/of_address.h>
9fbf0c85	25	#include <linux/clocksource.h>
30d8bead	26
2edb36c4	27	#include <asm/arch_timer.h>
a8cb6041	28	#include <asm/localtimer.h>
3a062281 CY	29
	30	#include <plat/cpu.h>
	31
30d8bead	32	#include <mach/map.h>
3a062281	33	#include <mach/irqs.h>
30d8bead CY	34	#include <asm/mach/time.h>
30d8bead CY	35
a1ba7a7a TA	36	#define EXYNOS4_MCTREG(x) (x)
	37	#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
	38	#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
	39	#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
	40	#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
	41	#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
	42	#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
	43	#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
	44	#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
	45	#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
	46	#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
	47	#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
	48	#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
	49	#define EXYNOS4_MCT_L_MASK (0xffffff00)
	50
	51	#define MCT_L_TCNTB_OFFSET (0x00)
	52	#define MCT_L_ICNTB_OFFSET (0x08)
	53	#define MCT_L_TCON_OFFSET (0x20)
	54	#define MCT_L_INT_CSTAT_OFFSET (0x30)
	55	#define MCT_L_INT_ENB_OFFSET (0x34)
	56	#define MCT_L_WSTAT_OFFSET (0x40)
	57	#define MCT_G_TCON_START (1 << 8)
	58	#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
	59	#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
	60	#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
	61	#define MCT_L_TCON_INT_START (1 << 1)
	62	#define MCT_L_TCON_TIMER_START (1 << 0)
	63
4d2e4d7f CY	64	#define TICK_BASE_CNT 1
4d2e4d7f CY	65
3a062281 CY	66	enum {
	67	MCT_INT_SPI,
	68	MCT_INT_PPI
	69	};
	70
c371dc60 TA	71	enum {
	72	MCT_G0_IRQ,
	73	MCT_G1_IRQ,
	74	MCT_G2_IRQ,
	75	MCT_G3_IRQ,
	76	MCT_L0_IRQ,
	77	MCT_L1_IRQ,
	78	MCT_L2_IRQ,
	79	MCT_L3_IRQ,
	80	MCT_NR_IRQS,
	81	};
	82
a1ba7a7a	83	static void __iomem *reg_base;
30d8bead	84	static unsigned long clk_rate;
3a062281	85	static unsigned int mct_int_type;
c371dc60	86	static int mct_irqs[MCT_NR_IRQS];
30d8bead CY	87
	88	struct mct_clock_event_device {
	89	struct clock_event_device *evt;
a1ba7a7a	90	unsigned long base;
c8987470	91	char name[10];
30d8bead CY	92	};
30d8bead CY	93
a1ba7a7a	94	static void exynos4_mct_write(unsigned int value, unsigned long offset)
30d8bead	95	{
a1ba7a7a	96	unsigned long stat_addr;
30d8bead CY	97	u32 mask;
	98	u32 i;
	99
a1ba7a7a	100	__raw_writel(value, reg_base + offset);
30d8bead	101
a1ba7a7a TA	102	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
	103	stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
	104	switch (offset & EXYNOS4_MCT_L_MASK) {
	105	case MCT_L_TCON_OFFSET:
c8987470 CY	106	mask = 1 << 3; /* L_TCON write status */
c8987470 CY	107	break;
a1ba7a7a	108	case MCT_L_ICNTB_OFFSET:
c8987470 CY	109	mask = 1 << 1; /* L_ICNTB write status */
c8987470 CY	110	break;
a1ba7a7a	111	case MCT_L_TCNTB_OFFSET:
c8987470 CY	112	mask = 1 << 0; /* L_TCNTB write status */
	113	break;
	114	default:
	115	return;
	116	}
	117	} else {
a1ba7a7a TA	118	switch (offset) {
a1ba7a7a TA	119	case EXYNOS4_MCT_G_TCON:
c8987470 CY	120	stat_addr = EXYNOS4_MCT_G_WSTAT;
	121	mask = 1 << 16; /* G_TCON write status */
	122	break;
a1ba7a7a	123	case EXYNOS4_MCT_G_COMP0_L:
c8987470 CY	124	stat_addr = EXYNOS4_MCT_G_WSTAT;
	125	mask = 1 << 0; /* G_COMP0_L write status */
	126	break;
a1ba7a7a	127	case EXYNOS4_MCT_G_COMP0_U:
c8987470 CY	128	stat_addr = EXYNOS4_MCT_G_WSTAT;
	129	mask = 1 << 1; /* G_COMP0_U write status */
	130	break;
a1ba7a7a	131	case EXYNOS4_MCT_G_COMP0_ADD_INCR:
c8987470 CY	132	stat_addr = EXYNOS4_MCT_G_WSTAT;
	133	mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
	134	break;
a1ba7a7a	135	case EXYNOS4_MCT_G_CNT_L:
c8987470 CY	136	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	137	mask = 1 << 0; /* G_CNT_L write status */
	138	break;
a1ba7a7a	139	case EXYNOS4_MCT_G_CNT_U:
c8987470 CY	140	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	141	mask = 1 << 1; /* G_CNT_U write status */
	142	break;
	143	default:
	144	return;
	145	}
30d8bead CY	146	}
	147
	148	/* Wait maximum 1 ms until written values are applied */
	149	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
a1ba7a7a TA	150	if (__raw_readl(reg_base + stat_addr) & mask) {
a1ba7a7a TA	151	__raw_writel(mask, reg_base + stat_addr);
30d8bead CY	152	return;
	153	}
	154
a1ba7a7a	155	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
30d8bead CY	156	}
	157
	158	/* Clocksource handling */
	159	static void exynos4_mct_frc_start(u32 hi, u32 lo)
	160	{
	161	u32 reg;
	162
	163	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	164	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
	165
a1ba7a7a	166	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	167	reg \|= MCT_G_TCON_START;
	168	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
	169	}
	170
	171	static cycle_t exynos4_frc_read(struct clocksource *cs)
	172	{
	173	unsigned int lo, hi;
a1ba7a7a	174	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	175
	176	do {
	177	hi = hi2;
a1ba7a7a TA	178	lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
a1ba7a7a TA	179	hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
30d8bead CY	180	} while (hi != hi2);
	181
	182	return ((cycle_t)hi << 32) \| lo;
	183	}
	184
aa421c13 CY	185	static void exynos4_frc_resume(struct clocksource *cs)
	186	{
	187	exynos4_mct_frc_start(0, 0);
	188	}
	189
30d8bead CY	190	struct clocksource mct_frc = {
	191	.name = "mct-frc",
	192	.rating = 400,
	193	.read = exynos4_frc_read,
	194	.mask = CLOCKSOURCE_MASK(64),
	195	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
aa421c13	196	.resume = exynos4_frc_resume,
30d8bead CY	197	};
	198
	199	static void __init exynos4_clocksource_init(void)
	200	{
	201	exynos4_mct_frc_start(0, 0);
	202
	203	if (clocksource_register_hz(&mct_frc, clk_rate))
	204	panic("%s: can't register clocksource\n", mct_frc.name);
	205	}
	206
	207	static void exynos4_mct_comp0_stop(void)
	208	{
	209	unsigned int tcon;
	210
a1ba7a7a	211	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	212	tcon &= ~(MCT_G_TCON_COMP0_ENABLE \| MCT_G_TCON_COMP0_AUTO_INC);
	213
	214	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	215	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
	216	}
	217
	218	static void exynos4_mct_comp0_start(enum clock_event_mode mode,
	219	unsigned long cycles)
	220	{
	221	unsigned int tcon;
	222	cycle_t comp_cycle;
	223
a1ba7a7a	224	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
30d8bead CY	225
	226	if (mode == CLOCK_EVT_MODE_PERIODIC) {
	227	tcon \|= MCT_G_TCON_COMP0_AUTO_INC;
	228	exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	229	}
	230
	231	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	232	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	233	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
	234
	235	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
	236
	237	tcon \|= MCT_G_TCON_COMP0_ENABLE;
	238	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
	239	}
	240
	241	static int exynos4_comp_set_next_event(unsigned long cycles,
	242	struct clock_event_device *evt)
	243	{
	244	exynos4_mct_comp0_start(evt->mode, cycles);
	245
	246	return 0;
	247	}
	248
	249	static void exynos4_comp_set_mode(enum clock_event_mode mode,
	250	struct clock_event_device *evt)
	251	{
4d2e4d7f	252	unsigned long cycles_per_jiffy;
30d8bead CY	253	exynos4_mct_comp0_stop();
	254
	255	switch (mode) {
	256	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	257	cycles_per_jiffy =
	258	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	259	exynos4_mct_comp0_start(mode, cycles_per_jiffy);
30d8bead CY	260	break;
	261
	262	case CLOCK_EVT_MODE_ONESHOT:
	263	case CLOCK_EVT_MODE_UNUSED:
	264	case CLOCK_EVT_MODE_SHUTDOWN:
	265	case CLOCK_EVT_MODE_RESUME:
	266	break;
	267	}
	268	}
	269
	270	static struct clock_event_device mct_comp_device = {
	271	.name = "mct-comp",
	272	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	273	.rating = 250,
	274	.set_next_event = exynos4_comp_set_next_event,
	275	.set_mode = exynos4_comp_set_mode,
	276	};
	277
	278	static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
	279	{
	280	struct clock_event_device *evt = dev_id;
	281
	282	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
	283
	284	evt->event_handler(evt);
	285
	286	return IRQ_HANDLED;
	287	}
	288
	289	static struct irqaction mct_comp_event_irq = {
	290	.name = "mct_comp_irq",
	291	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	292	.handler = exynos4_mct_comp_isr,
	293	.dev_id = &mct_comp_device,
	294	};
	295
	296	static void exynos4_clockevent_init(void)
	297	{
30d8bead	298	mct_comp_device.cpumask = cpumask_of(0);
838a2ae8 SG	299	clockevents_config_and_register(&mct_comp_device, clk_rate,
838a2ae8 SG	300	0xf, 0xffffffff);
c371dc60	301	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
30d8bead CY	302	}
	303
	304	#ifdef CONFIG_LOCAL_TIMERS
991a6c7d KK	305
	306	static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
	307
30d8bead CY	308	/* Clock event handling */
	309	static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
	310	{
	311	unsigned long tmp;
	312	unsigned long mask = MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START;
a1ba7a7a	313	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
30d8bead	314
a1ba7a7a	315	tmp = __raw_readl(reg_base + offset);
30d8bead CY	316	if (tmp & mask) {
30d8bead CY	317	tmp &= ~mask;
a1ba7a7a	318	exynos4_mct_write(tmp, offset);
30d8bead CY	319	}
	320	}
	321
	322	static void exynos4_mct_tick_start(unsigned long cycles,
	323	struct mct_clock_event_device *mevt)
	324	{
	325	unsigned long tmp;
	326
	327	exynos4_mct_tick_stop(mevt);
	328
	329	tmp = (1 << 31) \| cycles; /* MCT_L_UPDATE_ICNTB */
	330
	331	/* update interrupt count buffer */
	332	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
	333
25985edc	334	/* enable MCT tick interrupt */
30d8bead CY	335	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
30d8bead CY	336
a1ba7a7a	337	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
30d8bead CY	338	tmp \|= MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START \|
	339	MCT_L_TCON_INTERVAL_MODE;
	340	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
	341	}
	342
	343	static int exynos4_tick_set_next_event(unsigned long cycles,
	344	struct clock_event_device *evt)
	345	{
e700e41d	346	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
30d8bead CY	347
	348	exynos4_mct_tick_start(cycles, mevt);
	349
	350	return 0;
	351	}
	352
	353	static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
	354	struct clock_event_device *evt)
	355	{
e700e41d	356	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
4d2e4d7f	357	unsigned long cycles_per_jiffy;
30d8bead CY	358
	359	exynos4_mct_tick_stop(mevt);
	360
	361	switch (mode) {
	362	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	363	cycles_per_jiffy =
	364	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	365	exynos4_mct_tick_start(cycles_per_jiffy, mevt);
30d8bead CY	366	break;
	367
	368	case CLOCK_EVT_MODE_ONESHOT:
	369	case CLOCK_EVT_MODE_UNUSED:
	370	case CLOCK_EVT_MODE_SHUTDOWN:
	371	case CLOCK_EVT_MODE_RESUME:
	372	break;
	373	}
	374	}
	375
c8987470	376	static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
30d8bead	377	{
30d8bead CY	378	struct clock_event_device *evt = mevt->evt;
	379
	380	/*
	381	* This is for supporting oneshot mode.
	382	* Mct would generate interrupt periodically
	383	* without explicit stopping.
	384	*/
	385	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
	386	exynos4_mct_tick_stop(mevt);
	387
	388	/* Clear the MCT tick interrupt */
a1ba7a7a	389	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
3a062281 CY	390	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
	391	return 1;
	392	} else {
	393	return 0;
	394	}
	395	}
	396
	397	static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
	398	{
	399	struct mct_clock_event_device *mevt = dev_id;
	400	struct clock_event_device *evt = mevt->evt;
	401
	402	exynos4_mct_tick_clear(mevt);
30d8bead CY	403
	404	evt->event_handler(evt);
	405
	406	return IRQ_HANDLED;
	407	}
	408
	409	static struct irqaction mct_tick0_event_irq = {
	410	.name = "mct_tick0_irq",
	411	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	412	.handler = exynos4_mct_tick_isr,
	413	};
	414
	415	static struct irqaction mct_tick1_event_irq = {
	416	.name = "mct_tick1_irq",
	417	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	418	.handler = exynos4_mct_tick_isr,
	419	};
	420
a8cb6041	421	static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
30d8bead	422	{
e700e41d	423	struct mct_clock_event_device *mevt;
30d8bead CY	424	unsigned int cpu = smp_processor_id();
30d8bead CY	425
e700e41d MZ	426	mevt = this_cpu_ptr(&percpu_mct_tick);
e700e41d MZ	427	mevt->evt = evt;
30d8bead	428
e700e41d MZ	429	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
e700e41d MZ	430	sprintf(mevt->name, "mct_tick%d", cpu);
30d8bead	431
e700e41d	432	evt->name = mevt->name;
30d8bead CY	433	evt->cpumask = cpumask_of(cpu);
	434	evt->set_next_event = exynos4_tick_set_next_event;
	435	evt->set_mode = exynos4_tick_set_mode;
	436	evt->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	437	evt->rating = 450;
838a2ae8 SG	438	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
838a2ae8 SG	439	0xf, 0x7fffffff);
30d8bead	440
4d2e4d7f	441	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
30d8bead	442
3a062281 CY	443	if (mct_int_type == MCT_INT_SPI) {
3a062281 CY	444	if (cpu == 0) {
e700e41d	445	mct_tick0_event_irq.dev_id = mevt;
c371dc60 TA	446	evt->irq = mct_irqs[MCT_L0_IRQ];
c371dc60 TA	447	setup_irq(evt->irq, &mct_tick0_event_irq);
3a062281	448	} else {
e700e41d	449	mct_tick1_event_irq.dev_id = mevt;
c371dc60 TA	450	evt->irq = mct_irqs[MCT_L1_IRQ];
	451	setup_irq(evt->irq, &mct_tick1_event_irq);
	452	irq_set_affinity(evt->irq, cpumask_of(1));
3a062281	453	}
30d8bead	454	} else {
c371dc60	455	enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
30d8bead	456	}
4d487d7e KK	457
4d487d7e KK	458	return 0;
30d8bead CY	459	}
30d8bead CY	460
a8cb6041	461	static void exynos4_local_timer_stop(struct clock_event_device *evt)
30d8bead	462	{
e248cd5d	463	unsigned int cpu = smp_processor_id();
28af690a	464	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
e700e41d	465	if (mct_int_type == MCT_INT_SPI)
e248cd5d ADK	466	if (cpu == 0)
	467	remove_irq(evt->irq, &mct_tick0_event_irq);
	468	else
	469	remove_irq(evt->irq, &mct_tick1_event_irq);
e700e41d	470	else
c371dc60	471	disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
30d8bead	472	}
a8cb6041 MZ	473
	474	static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
	475	.setup = exynos4_local_timer_setup,
	476	.stop = exynos4_local_timer_stop,
	477	};
30d8bead CY	478	#endif /* CONFIG_LOCAL_TIMERS */
30d8bead CY	479
36ba5d52	480	static void __init exynos4_timer_resources(struct device_node *np)
30d8bead CY	481	{
	482	struct clk *mct_clk;
	483	mct_clk = clk_get(NULL, "xtal");
	484
	485	clk_rate = clk_get_rate(mct_clk);
e700e41d	486
36ba5d52 TA	487	reg_base = np ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
	488	if (!reg_base)
	489	panic("%s: unable to ioremap mct address space\n", __func__);
a1ba7a7a	490
991a6c7d	491	#ifdef CONFIG_LOCAL_TIMERS
e700e41d MZ	492	if (mct_int_type == MCT_INT_PPI) {
	493	int err;
	494
c371dc60	495	err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
e700e41d MZ	496	exynos4_mct_tick_isr, "MCT",
	497	&percpu_mct_tick);
	498	WARN(err, "MCT: can't request IRQ %d (%d)\n",
c371dc60	499	mct_irqs[MCT_L0_IRQ], err);
e700e41d	500	}
a8cb6041 MZ	501
a8cb6041 MZ	502	local_timer_register(&exynos4_mct_tick_ops);
991a6c7d	503	#endif /* CONFIG_LOCAL_TIMERS */
30d8bead CY	504	}
30d8bead CY	505
36ba5d52 TA	506	static const struct of_device_id exynos_mct_ids[] = {
	507	{ .compatible = "samsung,exynos4210-mct", .data = (void *)MCT_INT_SPI },
	508	{ .compatible = "samsung,exynos4412-mct", .data = (void *)MCT_INT_PPI },
	509	};
	510
9fbf0c85	511	void __init mct_init(void)
30d8bead	512	{
36ba5d52 TA	513	struct device_node *np = NULL;
	514	const struct of_device_id *match;
	515	u32 nr_irqs, i;
	516
36ba5d52 TA	517	#ifdef CONFIG_OF
	518	np = of_find_matching_node_and_match(NULL, exynos_mct_ids, &match);
	519	#endif
	520	if (np) {
	521	mct_int_type = (u32)(match->data);
	522
	523	/* This driver uses only one global timer interrupt */
	524	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
	525
	526	/*
	527	* Find out the number of local irqs specified. The local
	528	* timer irqs are specified after the four global timer
	529	* irqs are specified.
	530	*/
	531	#ifdef CONFIG_OF
	532	nr_irqs = of_irq_count(np);
	533	#endif
	534	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
	535	mct_irqs[i] = irq_of_parse_and_map(np, i);
	536	} else if (soc_is_exynos4210()) {
c371dc60 TA	537	mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
	538	mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
	539	mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
3a062281	540	mct_int_type = MCT_INT_SPI;
c371dc60	541	} else {
36ba5d52	542	panic("unable to determine mct controller type\n");
c371dc60	543	}
3a062281	544
36ba5d52	545	exynos4_timer_resources(np);
30d8bead CY	546	exynos4_clocksource_init();
	547	exynos4_clockevent_init();
	548	}
9fbf0c85 TA	549	CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init)
9fbf0c85 TA	550	CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init)