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e062b571 TA |
1 | /* |
2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
3 | * Copyright (c) 2013 Linaro Ltd. | |
4 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Common Clock Framework support for all Exynos4 SoCs. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/clkdev.h> | |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_address.h> | |
18 | ||
19 | #include <plat/cpu.h> | |
20 | #include "clk.h" | |
21 | #include "clk-pll.h" | |
22 | ||
23 | /* Exynos4 clock controller register offsets */ | |
24 | #define SRC_LEFTBUS 0x4200 | |
25 | #define E4X12_GATE_IP_IMAGE 0x4930 | |
26 | #define GATE_IP_RIGHTBUS 0x8800 | |
27 | #define E4X12_GATE_IP_PERIR 0x8960 | |
6d7190f8 TF |
28 | #define EPLL_LOCK 0xc010 |
29 | #define VPLL_LOCK 0xc020 | |
30 | #define EPLL_CON0 0xc110 | |
31 | #define EPLL_CON1 0xc114 | |
32 | #define EPLL_CON2 0xc118 | |
33 | #define VPLL_CON0 0xc120 | |
34 | #define VPLL_CON1 0xc124 | |
35 | #define VPLL_CON2 0xc128 | |
e062b571 TA |
36 | #define SRC_TOP0 0xc210 |
37 | #define SRC_TOP1 0xc214 | |
38 | #define SRC_CAM 0xc220 | |
39 | #define SRC_TV 0xc224 | |
40 | #define SRC_MFC 0xcc28 | |
41 | #define SRC_G3D 0xc22c | |
42 | #define E4210_SRC_IMAGE 0xc230 | |
43 | #define SRC_LCD0 0xc234 | |
44 | #define SRC_LCD1 0xc238 | |
15547015 | 45 | #define E4X12_SRC_ISP 0xc238 |
e062b571 TA |
46 | #define SRC_MAUDIO 0xc23c |
47 | #define SRC_FSYS 0xc240 | |
48 | #define SRC_PERIL0 0xc250 | |
49 | #define SRC_PERIL1 0xc254 | |
50 | #define E4X12_SRC_CAM1 0xc258 | |
51 | #define SRC_MASK_CAM 0xc320 | |
52 | #define SRC_MASK_TV 0xc324 | |
53 | #define SRC_MASK_LCD0 0xc334 | |
54 | #define SRC_MASK_LCD1 0xc338 | |
15547015 | 55 | #define E4X12_SRC_MASK_ISP 0xc338 |
e062b571 TA |
56 | #define SRC_MASK_MAUDIO 0xc33c |
57 | #define SRC_MASK_FSYS 0xc340 | |
58 | #define SRC_MASK_PERIL0 0xc350 | |
59 | #define SRC_MASK_PERIL1 0xc354 | |
60 | #define DIV_TOP 0xc510 | |
61 | #define DIV_CAM 0xc520 | |
62 | #define DIV_TV 0xc524 | |
63 | #define DIV_MFC 0xc528 | |
64 | #define DIV_G3D 0xc52c | |
65 | #define DIV_IMAGE 0xc530 | |
66 | #define DIV_LCD0 0xc534 | |
67 | #define E4210_DIV_LCD1 0xc538 | |
68 | #define E4X12_DIV_ISP 0xc538 | |
69 | #define DIV_MAUDIO 0xc53c | |
70 | #define DIV_FSYS0 0xc540 | |
71 | #define DIV_FSYS1 0xc544 | |
72 | #define DIV_FSYS2 0xc548 | |
73 | #define DIV_FSYS3 0xc54c | |
74 | #define DIV_PERIL0 0xc550 | |
75 | #define DIV_PERIL1 0xc554 | |
76 | #define DIV_PERIL2 0xc558 | |
77 | #define DIV_PERIL3 0xc55c | |
78 | #define DIV_PERIL4 0xc560 | |
79 | #define DIV_PERIL5 0xc564 | |
80 | #define E4X12_DIV_CAM1 0xc568 | |
81 | #define GATE_SCLK_CAM 0xc820 | |
82 | #define GATE_IP_CAM 0xc920 | |
83 | #define GATE_IP_TV 0xc924 | |
84 | #define GATE_IP_MFC 0xc928 | |
85 | #define GATE_IP_G3D 0xc92c | |
86 | #define E4210_GATE_IP_IMAGE 0xc930 | |
87 | #define GATE_IP_LCD0 0xc934 | |
88 | #define GATE_IP_LCD1 0xc938 | |
15547015 | 89 | #define E4X12_GATE_IP_ISP 0xc938 |
e062b571 TA |
90 | #define E4X12_GATE_IP_MAUDIO 0xc93c |
91 | #define GATE_IP_FSYS 0xc940 | |
92 | #define GATE_IP_GPS 0xc94c | |
93 | #define GATE_IP_PERIL 0xc950 | |
94 | #define GATE_IP_PERIR 0xc960 | |
95 | #define E4X12_MPLL_CON0 0x10108 | |
96 | #define E4X12_SRC_DMC 0x10200 | |
97 | #define APLL_CON0 0x14100 | |
98 | #define E4210_MPLL_CON0 0x14108 | |
99 | #define SRC_CPU 0x14200 | |
100 | #define DIV_CPU0 0x14500 | |
15547015 AH |
101 | #define E4X12_DIV_ISP0 0x18300 |
102 | #define E4X12_DIV_ISP1 0x18304 | |
1e25810b | 103 | #define E4X12_GATE_ISP0 0x18800 |
15547015 | 104 | #define E4X12_GATE_ISP1 0x18804 |
e062b571 TA |
105 | |
106 | /* the exynos4 soc type */ | |
107 | enum exynos4_soc { | |
108 | EXYNOS4210, | |
109 | EXYNOS4X12, | |
110 | }; | |
111 | ||
112 | /* | |
113 | * Let each supported clock get a unique id. This id is used to lookup the clock | |
114 | * for device tree based platforms. The clocks are categorized into three | |
115 | * sections: core, sclk gate and bus interface gate clocks. | |
116 | * | |
117 | * When adding a new clock to this list, it is advised to choose a clock | |
118 | * category and add it to the end of that category. That is because the the | |
119 | * device tree source file is referring to these ids and any change in the | |
120 | * sequence number of existing clocks will require corresponding change in the | |
121 | * device tree files. This limitation would go away when pre-processor support | |
122 | * for dtc would be available. | |
123 | */ | |
124 | enum exynos4_clks { | |
125 | none, | |
126 | ||
127 | /* core clocks */ | |
128 | xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll, | |
129 | sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100, | |
e77ba804 LM |
130 | aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core, |
131 | mout_apll, /* 20 */ | |
e062b571 TA |
132 | |
133 | /* gate for special clocks (sclk) */ | |
134 | sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0, | |
135 | sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac, | |
136 | sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0, | |
137 | sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4, | |
138 | sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4, | |
139 | sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, | |
140 | sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, | |
15547015 AH |
141 | sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp, |
142 | sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, | |
e062b571 TA |
143 | |
144 | /* gate clocks */ | |
145 | fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, | |
146 | smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi, | |
147 | smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d, | |
148 | smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1, | |
149 | mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0, | |
150 | sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie, | |
151 | onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3, | |
152 | uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, | |
153 | spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus, | |
154 | spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif, | |
1e25810b | 155 | audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0, |
15547015 AH |
156 | fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp, |
157 | gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp, | |
158 | mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp, | |
159 | asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk, | |
160 | spi1_isp_sclk, uart_isp_sclk, | |
1e25810b SN |
161 | |
162 | /* mux clocks */ | |
163 | mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0, | |
8e1ce839 | 164 | mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d, |
e062b571 TA |
165 | |
166 | nr_clks, | |
167 | }; | |
168 | ||
169 | /* | |
170 | * list of controller registers to be saved and restored during a | |
171 | * suspend/resume cycle. | |
172 | */ | |
173 | static __initdata unsigned long exynos4_clk_regs[] = { | |
174 | SRC_LEFTBUS, | |
175 | E4X12_GATE_IP_IMAGE, | |
176 | GATE_IP_RIGHTBUS, | |
177 | E4X12_GATE_IP_PERIR, | |
178 | SRC_TOP0, | |
179 | SRC_TOP1, | |
180 | SRC_CAM, | |
181 | SRC_TV, | |
182 | SRC_MFC, | |
183 | SRC_G3D, | |
184 | E4210_SRC_IMAGE, | |
185 | SRC_LCD0, | |
186 | SRC_LCD1, | |
187 | SRC_MAUDIO, | |
188 | SRC_FSYS, | |
189 | SRC_PERIL0, | |
190 | SRC_PERIL1, | |
191 | E4X12_SRC_CAM1, | |
192 | SRC_MASK_CAM, | |
193 | SRC_MASK_TV, | |
194 | SRC_MASK_LCD0, | |
195 | SRC_MASK_LCD1, | |
196 | SRC_MASK_MAUDIO, | |
197 | SRC_MASK_FSYS, | |
198 | SRC_MASK_PERIL0, | |
199 | SRC_MASK_PERIL1, | |
200 | DIV_TOP, | |
201 | DIV_CAM, | |
202 | DIV_TV, | |
203 | DIV_MFC, | |
204 | DIV_G3D, | |
205 | DIV_IMAGE, | |
206 | DIV_LCD0, | |
207 | E4210_DIV_LCD1, | |
208 | E4X12_DIV_ISP, | |
209 | DIV_MAUDIO, | |
210 | DIV_FSYS0, | |
211 | DIV_FSYS1, | |
212 | DIV_FSYS2, | |
213 | DIV_FSYS3, | |
214 | DIV_PERIL0, | |
215 | DIV_PERIL1, | |
216 | DIV_PERIL2, | |
217 | DIV_PERIL3, | |
218 | DIV_PERIL4, | |
219 | DIV_PERIL5, | |
220 | E4X12_DIV_CAM1, | |
221 | GATE_SCLK_CAM, | |
222 | GATE_IP_CAM, | |
223 | GATE_IP_TV, | |
224 | GATE_IP_MFC, | |
225 | GATE_IP_G3D, | |
226 | E4210_GATE_IP_IMAGE, | |
227 | GATE_IP_LCD0, | |
228 | GATE_IP_LCD1, | |
229 | E4X12_GATE_IP_MAUDIO, | |
230 | GATE_IP_FSYS, | |
231 | GATE_IP_GPS, | |
232 | GATE_IP_PERIL, | |
233 | GATE_IP_PERIR, | |
234 | E4X12_MPLL_CON0, | |
235 | E4X12_SRC_DMC, | |
236 | APLL_CON0, | |
237 | E4210_MPLL_CON0, | |
238 | SRC_CPU, | |
239 | DIV_CPU0, | |
240 | }; | |
241 | ||
242 | /* list of all parent clock list */ | |
243 | PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; | |
244 | PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; | |
245 | PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; | |
246 | PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", }; | |
e062b571 | 247 | PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; |
e062b571 TA |
248 | PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", }; |
249 | PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", }; | |
250 | PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", }; | |
251 | PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", }; | |
e062b571 TA |
252 | PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", }; |
253 | PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", }; | |
e062b571 TA |
254 | PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", |
255 | "spdif_extclk", }; | |
15547015 AH |
256 | PNAME(mout_onenand_p) = {"aclk133", "aclk160", }; |
257 | PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", }; | |
e062b571 | 258 | |
74f7f8ba TF |
259 | /* Exynos 4210-specific parent groups */ |
260 | PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", }; | |
261 | PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", }; | |
262 | PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", }; | |
263 | PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", | |
264 | "sclk_usbphy0", "none", "sclk_hdmiphy", | |
265 | "sclk_mpll", "sclk_epll", "sclk_vpll", }; | |
266 | PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m", | |
267 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
268 | "sclk_epll", "sclk_vpll" }; | |
269 | PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m", | |
270 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
271 | "sclk_epll", "sclk_vpll", }; | |
272 | PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m", | |
273 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
274 | "sclk_epll", "sclk_vpll", }; | |
275 | PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", }; | |
276 | PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", }; | |
277 | ||
278 | /* Exynos 4x12-specific parent groups */ | |
279 | PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", }; | |
280 | PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", }; | |
281 | PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", }; | |
282 | PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", | |
283 | "none", "sclk_hdmiphy", "mout_mpll_user_t", | |
284 | "sclk_epll", "sclk_vpll", }; | |
285 | PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m", | |
286 | "sclk_usbphy0", "xxti", "xusbxti", | |
287 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll" }; | |
288 | PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m", | |
289 | "sclk_usbphy0", "xxti", "xusbxti", | |
290 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; | |
291 | PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m", | |
292 | "sclk_usbphy0", "xxti", "xusbxti", | |
293 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; | |
294 | PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", }; | |
15547015 AH |
295 | PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; |
296 | PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; | |
297 | PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; | |
74f7f8ba | 298 | |
e062b571 TA |
299 | /* fixed rate clocks generated outside the soc */ |
300 | struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { | |
301 | FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0), | |
302 | FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0), | |
303 | }; | |
304 | ||
305 | /* fixed rate clocks generated inside the soc */ | |
306 | struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { | |
307 | FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), | |
308 | FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), | |
309 | FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), | |
310 | }; | |
311 | ||
312 | struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { | |
313 | FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), | |
314 | }; | |
315 | ||
316 | /* list of mux clocks supported in all exynos4 soc's */ | |
317 | struct samsung_mux_clock exynos4_mux_clks[] __initdata = { | |
e77ba804 LM |
318 | MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, |
319 | CLK_SET_RATE_PARENT, 0), | |
e062b571 | 320 | MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), |
e062b571 TA |
321 | MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), |
322 | MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), | |
8e1ce839 TF |
323 | MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, |
324 | CLK_SET_RATE_PARENT, 0), | |
325 | MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, | |
326 | CLK_SET_RATE_PARENT, 0), | |
e062b571 | 327 | MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), |
15547015 | 328 | MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), |
e062b571 | 329 | MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"), |
15547015 | 330 | MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), |
e062b571 TA |
331 | }; |
332 | ||
333 | /* list of mux clocks supported in exynos4210 soc */ | |
334 | struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { | |
74f7f8ba TF |
335 | MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), |
336 | MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), | |
337 | MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), | |
338 | MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), | |
e062b571 TA |
339 | MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), |
340 | MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), | |
341 | MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), | |
74f7f8ba | 342 | MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), |
e062b571 TA |
343 | MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), |
344 | MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), | |
74f7f8ba TF |
345 | MUX(none, "mout_fimd1", group1_p4210, SRC_LCD1, 0, 4), |
346 | MUX(none, "mout_mipi1", group1_p4210, SRC_LCD1, 12, 4), | |
e062b571 | 347 | MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"), |
fba79e32 TF |
348 | MUX_A(mout_core, "mout_core", mout_core_p4210, |
349 | SRC_CPU, 16, 1, "mout_core"), | |
e062b571 TA |
350 | MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, |
351 | SRC_TOP0, 8, 1, "sclk_vpll"), | |
1e25810b SN |
352 | MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), |
353 | MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), | |
354 | MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), | |
355 | MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), | |
356 | MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), | |
357 | MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), | |
358 | MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), | |
359 | MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), | |
74f7f8ba | 360 | MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), |
8e1ce839 TF |
361 | MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, |
362 | CLK_SET_RATE_PARENT, 0), | |
74f7f8ba TF |
363 | MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), |
364 | MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), | |
365 | MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), | |
366 | MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), | |
367 | MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), | |
368 | MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), | |
369 | MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), | |
370 | MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), | |
8e79561c | 371 | MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), |
74f7f8ba TF |
372 | MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), |
373 | MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), | |
374 | MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), | |
375 | MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), | |
376 | MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), | |
377 | MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), | |
378 | MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), | |
379 | MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), | |
380 | MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), | |
381 | MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), | |
e062b571 TA |
382 | }; |
383 | ||
384 | /* list of mux clocks supported in exynos4x12 soc */ | |
385 | struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { | |
74f7f8ba TF |
386 | MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, |
387 | SRC_CPU, 24, 1), | |
15547015 AH |
388 | MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), |
389 | MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), | |
74f7f8ba TF |
390 | MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12, |
391 | SRC_TOP1, 12, 1), | |
15547015 AH |
392 | MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, |
393 | SRC_TOP1, 16, 1), | |
394 | MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), | |
395 | MUX(none, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12, | |
396 | SRC_TOP1, 24, 1), | |
e062b571 TA |
397 | MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), |
398 | MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), | |
399 | MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), | |
400 | MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), | |
74f7f8ba TF |
401 | MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), |
402 | MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), | |
403 | MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), | |
404 | MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), | |
e062b571 TA |
405 | MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), |
406 | MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), | |
407 | MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, | |
408 | E4X12_SRC_DMC, 12, 1, "sclk_mpll"), | |
409 | MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p, | |
410 | SRC_TOP0, 8, 1, "sclk_vpll"), | |
e77ba804 | 411 | MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), |
1e25810b SN |
412 | MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), |
413 | MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), | |
414 | MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), | |
415 | MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), | |
416 | MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), | |
417 | MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), | |
418 | MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), | |
419 | MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), | |
74f7f8ba | 420 | MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), |
8e1ce839 TF |
421 | MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, |
422 | CLK_SET_RATE_PARENT, 0), | |
74f7f8ba TF |
423 | MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), |
424 | MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), | |
425 | MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), | |
426 | MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), | |
427 | MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), | |
428 | MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), | |
429 | MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), | |
430 | MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), | |
4c3cc72c | 431 | MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), |
74f7f8ba TF |
432 | MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), |
433 | MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), | |
434 | MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), | |
435 | MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), | |
436 | MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), | |
437 | MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), | |
438 | MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), | |
439 | MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), | |
440 | MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), | |
441 | MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), | |
15547015 AH |
442 | MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), |
443 | MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), | |
444 | MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), | |
445 | MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), | |
e062b571 TA |
446 | }; |
447 | ||
448 | /* list of divider clocks supported in all exynos4 soc's */ | |
449 | struct samsung_div_clock exynos4_div_clks[] __initdata = { | |
450 | DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3), | |
451 | DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3), | |
452 | DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), | |
453 | DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), | |
454 | DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), | |
455 | DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), | |
456 | DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), | |
457 | DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), | |
458 | DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), | |
459 | DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), | |
36fc0972 | 460 | DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), |
8e1ce839 TF |
461 | DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4, |
462 | CLK_SET_RATE_PARENT, 0), | |
e062b571 TA |
463 | DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), |
464 | DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), | |
465 | DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), | |
6976d274 | 466 | DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), |
e062b571 TA |
467 | DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), |
468 | DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), | |
469 | DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), | |
470 | DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), | |
471 | DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), | |
e062b571 TA |
472 | DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), |
473 | DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), | |
474 | DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), | |
15547015 | 475 | DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), |
e062b571 TA |
476 | DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), |
477 | DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), | |
478 | DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), | |
479 | DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), | |
480 | DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), | |
481 | DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), | |
482 | DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), | |
483 | DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), | |
484 | DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), | |
485 | DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), | |
486 | DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), | |
487 | DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), | |
488 | DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), | |
489 | DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), | |
490 | DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), | |
491 | DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), | |
492 | DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), | |
493 | DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), | |
494 | DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), | |
495 | DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), | |
496 | DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"), | |
497 | DIV_A(sclk_apll, "sclk_apll", "mout_apll", | |
498 | DIV_CPU0, 24, 3, "sclk_apll"), | |
499 | DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, | |
500 | CLK_SET_RATE_PARENT, 0), | |
501 | DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, | |
502 | CLK_SET_RATE_PARENT, 0), | |
503 | DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, | |
504 | CLK_SET_RATE_PARENT, 0), | |
505 | DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, | |
506 | CLK_SET_RATE_PARENT, 0), | |
507 | DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, | |
508 | CLK_SET_RATE_PARENT, 0), | |
509 | }; | |
510 | ||
511 | /* list of divider clocks supported in exynos4210 soc */ | |
512 | struct samsung_div_clock exynos4210_div_clks[] __initdata = { | |
15547015 | 513 | DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), |
e062b571 TA |
514 | DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4), |
515 | DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), | |
516 | DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), | |
517 | DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), | |
518 | DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, | |
519 | CLK_SET_RATE_PARENT, 0), | |
520 | }; | |
521 | ||
522 | /* list of divider clocks supported in exynos4x12 soc */ | |
523 | struct samsung_div_clock exynos4x12_div_clks[] __initdata = { | |
524 | DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), | |
525 | DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), | |
526 | DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), | |
527 | DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), | |
528 | DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), | |
15547015 AH |
529 | DIV(none, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), |
530 | DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), | |
531 | DIV(none, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", DIV_TOP, 24, 3), | |
532 | DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), | |
533 | DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), | |
534 | DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), | |
535 | DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), | |
536 | DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), | |
537 | DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), | |
538 | DIV(none, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3), | |
539 | DIV(none, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3), | |
540 | DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), | |
541 | DIV(none, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3), | |
542 | DIV(none, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3), | |
e062b571 TA |
543 | }; |
544 | ||
545 | /* list of gate clocks supported in all exynos4 soc's */ | |
546 | struct samsung_gate_clock exynos4_gate_clks[] __initdata = { | |
547 | /* | |
548 | * After all Exynos4 based platforms are migrated to use device tree, | |
549 | * the device name and clock alias names specified below for some | |
550 | * of the clocks can be removed. | |
551 | */ | |
552 | GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), | |
e062b571 TA |
553 | GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 0xc354, 8, 0, 0), |
554 | GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), | |
555 | GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), | |
556 | GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), | |
557 | GATE(fimd1, "fimd1", "aclk160", GATE_IP_LCD1, 0, 0, 0), | |
558 | GATE(mie1, "mie1", "aclk160", GATE_IP_LCD1, 1, 0, 0), | |
559 | GATE(dsim1, "dsim1", "aclk160", GATE_IP_LCD1, 3, 0, 0), | |
560 | GATE(smmu_fimd1, "smmu_fimd1", "aclk160", GATE_IP_LCD1, 4, 0, 0), | |
561 | GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), | |
562 | GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), | |
8e1ce839 TF |
563 | GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, |
564 | CLK_SET_RATE_PARENT, 0), | |
e062b571 TA |
565 | GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), |
566 | GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), | |
567 | GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), | |
568 | GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), | |
569 | GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), | |
570 | GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), | |
571 | GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, | |
572 | CLK_SET_RATE_PARENT, 0), | |
573 | GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, | |
574 | CLK_SET_RATE_PARENT, 0), | |
575 | GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0", | |
576 | SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), | |
69aff2fd TF |
577 | GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, |
578 | CLK_SET_RATE_PARENT, 0), | |
e062b571 TA |
579 | GATE(sclk_audio1, "sclk_audio1", "div_audio1", 0xc354, 0, |
580 | CLK_SET_RATE_PARENT, 0), | |
581 | GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0), | |
582 | GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), | |
583 | GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), | |
584 | GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"), | |
585 | GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"), | |
586 | GATE_A(usb_host, "usb_host", "aclk133", | |
587 | GATE_IP_FSYS, 12, 0, 0, "usbhost"), | |
588 | GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0", | |
589 | SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), | |
590 | GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1", | |
591 | SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), | |
592 | GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2", | |
593 | SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), | |
594 | GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3", | |
595 | SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), | |
596 | GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0", | |
597 | SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"), | |
598 | GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1", | |
599 | SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"), | |
600 | GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0", | |
601 | SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), | |
602 | GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0", | |
603 | SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0, | |
604 | "mmc_busclk.2"), | |
605 | GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1", | |
606 | SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0, | |
607 | "mmc_busclk.2"), | |
608 | GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2", | |
609 | SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0, | |
610 | "mmc_busclk.2"), | |
611 | GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3", | |
612 | SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0, | |
613 | "mmc_busclk.2"), | |
614 | GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4", | |
615 | SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"), | |
616 | GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0", | |
617 | 0xc350, 0, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), | |
618 | GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1", | |
619 | 0xc350, 4, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), | |
620 | GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2", | |
621 | 0xc350, 8, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), | |
622 | GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3", | |
623 | 0xc350, 12, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), | |
624 | GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4", | |
625 | 0xc350, 16, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), | |
626 | GATE(sclk_audio2, "sclk_audio2", "div_audio2", 0xc354, 4, | |
627 | CLK_SET_RATE_PARENT, 0), | |
628 | GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0", | |
629 | 0xc354, 16, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), | |
630 | GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1", | |
631 | 0xc354, 20, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), | |
632 | GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2", | |
633 | 0xc354, 24, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), | |
634 | GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160", | |
635 | GATE_IP_CAM, 0, 0, 0, "fimc"), | |
636 | GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160", | |
637 | GATE_IP_CAM, 1, 0, 0, "fimc"), | |
638 | GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160", | |
639 | GATE_IP_CAM, 2, 0, 0, "fimc"), | |
640 | GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160", | |
641 | GATE_IP_CAM, 3, 0, 0, "fimc"), | |
642 | GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160", | |
643 | GATE_IP_CAM, 4, 0, 0, "fimc"), | |
644 | GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160", | |
645 | GATE_IP_CAM, 5, 0, 0, "fimc"), | |
646 | GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160", | |
647 | GATE_IP_CAM, 7, 0, 0, "sysmmu"), | |
648 | GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160", | |
649 | GATE_IP_CAM, 8, 0, 0, "sysmmu"), | |
650 | GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160", | |
651 | GATE_IP_CAM, 9, 0, 0, "sysmmu"), | |
652 | GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160", | |
653 | GATE_IP_CAM, 10, 0, 0, "sysmmu"), | |
654 | GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160", | |
655 | GATE_IP_CAM, 11, 0, 0, "sysmmu"), | |
1e25810b SN |
656 | GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), |
657 | GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), | |
e062b571 TA |
658 | GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160", |
659 | GATE_IP_TV, 4, 0, 0, "sysmmu"), | |
660 | GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"), | |
661 | GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100", | |
662 | GATE_IP_MFC, 1, 0, 0, "sysmmu"), | |
663 | GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100", | |
664 | GATE_IP_MFC, 2, 0, 0, "sysmmu"), | |
665 | GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160", | |
666 | GATE_IP_LCD0, 0, 0, 0, "fimd"), | |
667 | GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160", | |
668 | GATE_IP_LCD0, 4, 0, 0, "sysmmu"), | |
669 | GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133", | |
670 | GATE_IP_FSYS, 0, 0, 0, "dma"), | |
671 | GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133", | |
672 | GATE_IP_FSYS, 1, 0, 0, "dma"), | |
673 | GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133", | |
674 | GATE_IP_FSYS, 5, 0, 0, "hsmmc"), | |
675 | GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133", | |
676 | GATE_IP_FSYS, 6, 0, 0, "hsmmc"), | |
677 | GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133", | |
678 | GATE_IP_FSYS, 7, 0, 0, "hsmmc"), | |
679 | GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133", | |
680 | GATE_IP_FSYS, 8, 0, 0, "hsmmc"), | |
681 | GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100", | |
682 | GATE_IP_PERIL, 0, 0, 0, "uart"), | |
683 | GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100", | |
684 | GATE_IP_PERIL, 1, 0, 0, "uart"), | |
685 | GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100", | |
686 | GATE_IP_PERIL, 2, 0, 0, "uart"), | |
687 | GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100", | |
688 | GATE_IP_PERIL, 3, 0, 0, "uart"), | |
689 | GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100", | |
690 | GATE_IP_PERIL, 4, 0, 0, "uart"), | |
691 | GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100", | |
692 | GATE_IP_PERIL, 6, 0, 0, "i2c"), | |
693 | GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100", | |
694 | GATE_IP_PERIL, 7, 0, 0, "i2c"), | |
695 | GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100", | |
696 | GATE_IP_PERIL, 8, 0, 0, "i2c"), | |
697 | GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100", | |
698 | GATE_IP_PERIL, 9, 0, 0, "i2c"), | |
699 | GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100", | |
700 | GATE_IP_PERIL, 10, 0, 0, "i2c"), | |
701 | GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100", | |
702 | GATE_IP_PERIL, 11, 0, 0, "i2c"), | |
703 | GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100", | |
704 | GATE_IP_PERIL, 12, 0, 0, "i2c"), | |
705 | GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100", | |
706 | GATE_IP_PERIL, 13, 0, 0, "i2c"), | |
707 | GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100", | |
708 | GATE_IP_PERIL, 14, 0, 0, "i2c"), | |
709 | GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100", | |
710 | GATE_IP_PERIL, 16, 0, 0, "spi"), | |
711 | GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100", | |
712 | GATE_IP_PERIL, 17, 0, 0, "spi"), | |
713 | GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100", | |
714 | GATE_IP_PERIL, 18, 0, 0, "spi"), | |
715 | GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100", | |
716 | GATE_IP_PERIL, 20, 0, 0, "iis"), | |
717 | GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100", | |
718 | GATE_IP_PERIL, 21, 0, 0, "iis"), | |
719 | GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100", | |
720 | GATE_IP_PERIL, 22, 0, 0, "pcm"), | |
721 | GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100", | |
722 | GATE_IP_PERIL, 23, 0, 0, "pcm"), | |
723 | GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100", | |
724 | GATE_IP_PERIL, 26, 0, 0, "spdif"), | |
725 | GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100", | |
726 | GATE_IP_PERIL, 27, 0, 0, "ac97"), | |
727 | }; | |
728 | ||
729 | /* list of gate clocks supported in exynos4210 soc */ | |
730 | struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { | |
731 | GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), | |
732 | GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), | |
733 | GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), | |
734 | GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), | |
735 | GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), | |
736 | GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0), | |
737 | GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), | |
738 | GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), | |
739 | GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), | |
740 | GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), | |
741 | GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), | |
742 | GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), | |
743 | GATE(chipid, "chipid", "aclk100", GATE_IP_PERIR, 0, 0, 0), | |
744 | GATE(sysreg, "sysreg", "aclk100", GATE_IP_PERIR, 0, 0, 0), | |
745 | GATE(hdmi_cec, "hdmi_cec", "aclk100", GATE_IP_PERIR, 11, 0, 0), | |
746 | GATE(smmu_rotator, "smmu_rotator", "aclk200", | |
747 | E4210_GATE_IP_IMAGE, 4, 0, 0), | |
748 | GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", | |
749 | SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), | |
750 | GATE(sclk_sata, "sclk_sata", "div_sata", | |
751 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), | |
7bc1d2da TF |
752 | GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), |
753 | GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), | |
e062b571 TA |
754 | GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"), |
755 | GATE_A(mct, "mct", "aclk100", GATE_IP_PERIR, 13, 0, 0, "mct"), | |
756 | GATE_A(wdt, "watchdog", "aclk100", GATE_IP_PERIR, 14, 0, 0, "watchdog"), | |
757 | GATE_A(rtc, "rtc", "aclk100", GATE_IP_PERIR, 15, 0, 0, "rtc"), | |
758 | GATE_A(keyif, "keyif", "aclk100", GATE_IP_PERIR, 16, 0, 0, "keypad"), | |
759 | GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", | |
760 | SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), | |
761 | }; | |
762 | ||
763 | /* list of gate clocks supported in exynos4x12 soc */ | |
764 | struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { | |
765 | GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), | |
766 | GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), | |
767 | GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), | |
768 | GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), | |
769 | GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0), | |
770 | GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), | |
771 | GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), | |
772 | GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0), | |
773 | GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0), | |
774 | GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0", | |
775 | SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), | |
776 | GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", | |
777 | SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), | |
778 | GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi", | |
779 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), | |
780 | GATE(smmu_rotator, "smmu_rotator", "aclk200", | |
781 | E4X12_GATE_IP_IMAGE, 4, 0, 0), | |
782 | GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"), | |
783 | GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"), | |
784 | GATE_A(keyif, "keyif", "aclk100", | |
785 | E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"), | |
15547015 AH |
786 | GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp", |
787 | E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), | |
788 | GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre", | |
789 | E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0), | |
790 | GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre", | |
791 | E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0), | |
792 | GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp", | |
793 | E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0), | |
794 | GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp", | |
795 | E4X12_GATE_IP_ISP, 0, 0, 0), | |
796 | GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp", | |
797 | E4X12_GATE_IP_ISP, 1, 0, 0), | |
798 | GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp", | |
799 | E4X12_GATE_IP_ISP, 2, 0, 0), | |
800 | GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp", | |
801 | E4X12_GATE_IP_ISP, 3, 0, 0), | |
e062b571 TA |
802 | GATE_A(wdt, "watchdog", "aclk100", |
803 | E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"), | |
804 | GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100", | |
805 | E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"), | |
806 | GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100", | |
807 | E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"), | |
15547015 AH |
808 | GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0, |
809 | CLK_IGNORE_UNUSED, 0), | |
810 | GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1, | |
811 | CLK_IGNORE_UNUSED, 0), | |
812 | GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2, | |
813 | CLK_IGNORE_UNUSED, 0), | |
1e25810b SN |
814 | GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, |
815 | CLK_IGNORE_UNUSED, 0), | |
816 | GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, | |
817 | CLK_IGNORE_UNUSED, 0), | |
15547015 AH |
818 | GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, |
819 | CLK_IGNORE_UNUSED, 0), | |
820 | GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, | |
821 | CLK_IGNORE_UNUSED, 0), | |
822 | GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, | |
823 | CLK_IGNORE_UNUSED, 0), | |
824 | GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, | |
825 | CLK_IGNORE_UNUSED, 0), | |
826 | GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, | |
827 | CLK_IGNORE_UNUSED, 0), | |
828 | GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, | |
829 | CLK_IGNORE_UNUSED, 0), | |
830 | GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, | |
831 | CLK_IGNORE_UNUSED, 0), | |
1e25810b SN |
832 | GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, |
833 | CLK_IGNORE_UNUSED, 0), | |
834 | GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, | |
835 | CLK_IGNORE_UNUSED, 0), | |
15547015 AH |
836 | GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, |
837 | CLK_IGNORE_UNUSED, 0), | |
838 | GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, | |
839 | CLK_IGNORE_UNUSED, 0), | |
840 | GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, | |
841 | CLK_IGNORE_UNUSED, 0), | |
842 | GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, | |
843 | CLK_IGNORE_UNUSED, 0), | |
844 | GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, | |
845 | CLK_IGNORE_UNUSED, 0), | |
846 | GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, | |
847 | CLK_IGNORE_UNUSED, 0), | |
848 | GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, | |
849 | CLK_IGNORE_UNUSED, 0), | |
850 | GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, | |
851 | CLK_IGNORE_UNUSED, 0), | |
852 | GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, | |
853 | CLK_IGNORE_UNUSED, 0), | |
854 | GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, | |
855 | CLK_IGNORE_UNUSED, 0), | |
856 | GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, | |
857 | CLK_IGNORE_UNUSED, 0), | |
858 | GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, | |
859 | CLK_IGNORE_UNUSED, 0), | |
e062b571 TA |
860 | }; |
861 | ||
862 | #ifdef CONFIG_OF | |
863 | static struct of_device_id exynos4_clk_ids[] __initdata = { | |
864 | { .compatible = "samsung,exynos4210-clock", | |
865 | .data = (void *)EXYNOS4210, }, | |
866 | { .compatible = "samsung,exynos4412-clock", | |
867 | .data = (void *)EXYNOS4X12, }, | |
868 | { }, | |
869 | }; | |
870 | #endif | |
871 | ||
872 | /* | |
873 | * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit | |
874 | * resides in chipid register space, outside of the clock controller memory | |
875 | * mapped space. So to determine the parent of fin_pll clock, the chipid | |
876 | * controller is first remapped and the value of XOM[0] bit is read to | |
877 | * determine the parent clock. | |
878 | */ | |
879 | static void __init exynos4_clk_register_finpll(void) | |
880 | { | |
881 | struct samsung_fixed_rate_clock fclk; | |
882 | struct device_node *np; | |
883 | struct clk *clk; | |
884 | void __iomem *chipid_base = S5P_VA_CHIPID; | |
885 | unsigned long xom, finpll_f = 24000000; | |
886 | char *parent_name; | |
887 | ||
888 | np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid"); | |
889 | if (np) | |
890 | chipid_base = of_iomap(np, 0); | |
891 | ||
892 | if (chipid_base) { | |
893 | xom = readl(chipid_base + 8); | |
894 | parent_name = xom & 1 ? "xusbxti" : "xxti"; | |
895 | clk = clk_get(NULL, parent_name); | |
896 | if (IS_ERR(clk)) { | |
897 | pr_err("%s: failed to lookup parent clock %s, assuming " | |
898 | "fin_pll clock frequency is 24MHz\n", __func__, | |
899 | parent_name); | |
900 | } else { | |
901 | finpll_f = clk_get_rate(clk); | |
902 | } | |
903 | } else { | |
904 | pr_err("%s: failed to map chipid registers, assuming " | |
905 | "fin_pll clock frequency is 24MHz\n", __func__); | |
906 | } | |
907 | ||
908 | fclk.id = fin_pll; | |
909 | fclk.name = "fin_pll"; | |
910 | fclk.parent_name = NULL; | |
911 | fclk.flags = CLK_IS_ROOT; | |
912 | fclk.fixed_rate = finpll_f; | |
913 | samsung_clk_register_fixed_rate(&fclk, 1); | |
914 | ||
915 | if (np) | |
916 | iounmap(chipid_base); | |
917 | } | |
918 | ||
919 | /* | |
920 | * This function allows non-dt platforms to specify the clock speed of the | |
921 | * xxti and xusbxti clocks. These clocks are then registered with the specified | |
922 | * clock speed. | |
923 | */ | |
924 | void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f, | |
925 | unsigned long xusbxti_f) | |
926 | { | |
927 | exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f; | |
928 | exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f; | |
929 | samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks, | |
930 | ARRAY_SIZE(exynos4_fixed_rate_ext_clks)); | |
931 | } | |
932 | ||
933 | static __initdata struct of_device_id ext_clk_match[] = { | |
934 | { .compatible = "samsung,clock-xxti", .data = (void *)0, }, | |
935 | { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, | |
936 | {}, | |
937 | }; | |
938 | ||
939 | /* register exynos4 clocks */ | |
940 | void __init exynos4_clk_init(struct device_node *np) | |
941 | { | |
942 | void __iomem *reg_base; | |
943 | struct clk *apll, *mpll, *epll, *vpll; | |
944 | u32 exynos4_soc; | |
945 | ||
946 | if (np) { | |
947 | const struct of_device_id *match; | |
948 | match = of_match_node(exynos4_clk_ids, np); | |
949 | exynos4_soc = (u32)match->data; | |
950 | ||
951 | reg_base = of_iomap(np, 0); | |
952 | if (!reg_base) | |
953 | panic("%s: failed to map registers\n", __func__); | |
954 | } else { | |
955 | reg_base = S5P_VA_CMU; | |
956 | if (soc_is_exynos4210()) | |
957 | exynos4_soc = EXYNOS4210; | |
958 | else if (soc_is_exynos4212() || soc_is_exynos4412()) | |
959 | exynos4_soc = EXYNOS4X12; | |
960 | else | |
961 | panic("%s: unable to determine soc\n", __func__); | |
962 | } | |
963 | ||
964 | samsung_clk_init(np, reg_base, nr_clks, | |
965 | exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs)); | |
966 | ||
967 | if (np) | |
968 | samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks, | |
969 | ARRAY_SIZE(exynos4_fixed_rate_ext_clks), | |
970 | ext_clk_match); | |
971 | ||
972 | exynos4_clk_register_finpll(); | |
973 | ||
974 | if (exynos4_soc == EXYNOS4210) { | |
975 | apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll", | |
976 | reg_base + APLL_CON0, pll_4508); | |
977 | mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll", | |
978 | reg_base + E4210_MPLL_CON0, pll_4508); | |
979 | epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll", | |
6d7190f8 | 980 | reg_base + EPLL_CON0, pll_4600); |
e062b571 | 981 | vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc", |
6d7190f8 | 982 | reg_base + VPLL_CON0, pll_4650c); |
e062b571 TA |
983 | } else { |
984 | apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", | |
985 | reg_base + APLL_CON0); | |
986 | mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", | |
987 | reg_base + E4X12_MPLL_CON0); | |
988 | epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", | |
6d7190f8 | 989 | reg_base + EPLL_CON0); |
e062b571 | 990 | vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll", |
6d7190f8 | 991 | reg_base + VPLL_CON0); |
e062b571 TA |
992 | } |
993 | ||
994 | samsung_clk_add_lookup(apll, fout_apll); | |
995 | samsung_clk_add_lookup(mpll, fout_mpll); | |
996 | samsung_clk_add_lookup(epll, fout_epll); | |
997 | samsung_clk_add_lookup(vpll, fout_vpll); | |
998 | ||
999 | samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, | |
1000 | ARRAY_SIZE(exynos4_fixed_rate_clks)); | |
1001 | samsung_clk_register_mux(exynos4_mux_clks, | |
1002 | ARRAY_SIZE(exynos4_mux_clks)); | |
1003 | samsung_clk_register_div(exynos4_div_clks, | |
1004 | ARRAY_SIZE(exynos4_div_clks)); | |
1005 | samsung_clk_register_gate(exynos4_gate_clks, | |
1006 | ARRAY_SIZE(exynos4_gate_clks)); | |
1007 | ||
1008 | if (exynos4_soc == EXYNOS4210) { | |
1009 | samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks, | |
1010 | ARRAY_SIZE(exynos4210_fixed_rate_clks)); | |
1011 | samsung_clk_register_mux(exynos4210_mux_clks, | |
1012 | ARRAY_SIZE(exynos4210_mux_clks)); | |
1013 | samsung_clk_register_div(exynos4210_div_clks, | |
1014 | ARRAY_SIZE(exynos4210_div_clks)); | |
1015 | samsung_clk_register_gate(exynos4210_gate_clks, | |
1016 | ARRAY_SIZE(exynos4210_gate_clks)); | |
1017 | } else { | |
1018 | samsung_clk_register_mux(exynos4x12_mux_clks, | |
1019 | ARRAY_SIZE(exynos4x12_mux_clks)); | |
1020 | samsung_clk_register_div(exynos4x12_div_clks, | |
1021 | ARRAY_SIZE(exynos4x12_div_clks)); | |
1022 | samsung_clk_register_gate(exynos4x12_gate_clks, | |
1023 | ARRAY_SIZE(exynos4x12_gate_clks)); | |
1024 | } | |
1025 | ||
1026 | pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" | |
1027 | "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", | |
1028 | exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", | |
1029 | _get_rate("sclk_apll"), _get_rate("sclk_mpll"), | |
1030 | _get_rate("sclk_epll"), _get_rate("sclk_vpll"), | |
1031 | _get_rate("arm_clk")); | |
1032 | } | |
1033 | CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init); | |
1034 | CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init); |